2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
44 #include "brw_vec4_gs_visitor.h"
46 #include "main/uniforms.h"
47 #include "glsl/nir/glsl_types.h"
48 #include "glsl/ir_optimization.h"
49 #include "program/sampler.h"
54 fs_visitor::emit_vs_system_value(int location
)
56 fs_reg
*reg
= new(this->mem_ctx
)
57 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
59 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
62 case SYSTEM_VALUE_BASE_VERTEX
:
64 vs_prog_data
->uses_vertexid
= true;
66 case SYSTEM_VALUE_VERTEX_ID
:
67 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
69 vs_prog_data
->uses_vertexid
= true;
71 case SYSTEM_VALUE_INSTANCE_ID
:
73 vs_prog_data
->uses_instanceid
= true;
76 unreachable("not reached");
82 /* Sample from the MCS surface attached to this multisample texture. */
84 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
85 const fs_reg
&sampler
)
87 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
88 const fs_reg srcs
[] = {
89 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
90 sampler
, fs_reg(), brw_imm_ud(components
), brw_imm_d(0)
92 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
95 /* We only care about one or two regs of response, but the sampler always
98 inst
->regs_written
= 4 * dispatch_width
/ 8;
104 fs_visitor::emit_texture(ir_texture_opcode op
,
105 const glsl_type
*dest_type
,
106 fs_reg coordinate
, int coord_components
,
108 fs_reg lod
, fs_reg lod2
, int grad_components
,
112 int gather_component
,
117 fs_inst
*inst
= NULL
;
119 if (op
== ir_query_levels
) {
120 /* textureQueryLevels() is implemented in terms of TXS so we need to
121 * pass a valid LOD argument.
123 assert(lod
.file
== BAD_FILE
);
124 lod
= brw_imm_ud(0u);
127 if (op
== ir_samples_identical
) {
128 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
130 /* If mcs is an immediate value, it means there is no MCS. In that case
133 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
134 bld
.MOV(dst
, brw_imm_ud(0u));
135 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
136 fs_reg tmp
= vgrf(glsl_type::uint_type
);
137 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
138 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
140 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
147 /* Writemasking doesn't eliminate channels on SIMD8 texture
148 * samples, so don't worry about them.
150 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
151 const fs_reg srcs
[] = {
152 coordinate
, shadow_c
, lod
, lod2
,
153 sample_index
, mcs
, sampler_reg
, offset_value
,
154 brw_imm_d(coord_components
), brw_imm_d(grad_components
)
160 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
163 opcode
= FS_OPCODE_TXB_LOGICAL
;
166 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
169 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
172 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
175 if ((key_tex
->msaa_16
& (1 << sampler
)))
176 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
178 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
181 case ir_query_levels
:
182 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
185 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
188 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
189 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
192 unreachable("Invalid texture opcode.");
195 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
196 inst
->regs_written
= 4 * dispatch_width
/ 8;
198 if (shadow_c
.file
!= BAD_FILE
)
199 inst
->shadow_compare
= true;
201 if (offset_value
.file
== IMM
)
202 inst
->offset
= offset_value
.ud
;
205 if (gather_component
== 1 &&
206 key_tex
->gather_channel_quirk_mask
& (1 << sampler
)) {
207 /* gather4 sampler is broken for green channel on RG32F --
208 * we must ask for blue instead.
210 inst
->offset
|= 2 << 16;
212 inst
->offset
|= gather_component
<< 16;
215 if (devinfo
->gen
== 6)
216 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
219 /* fixup #layers for cube map arrays */
220 if (op
== ir_txs
&& is_cube_array
) {
221 fs_reg depth
= offset(dst
, bld
, 2);
222 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
223 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
225 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
226 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
227 for (int i
= 0; i
< components
; i
++) {
229 fixed_payload
[i
] = fixed_depth
;
231 fixed_payload
[i
] = offset(dst
, bld
, i
);
234 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
237 if (op
== ir_query_levels
) {
238 /* # levels is in .w */
239 dst
= offset(dst
, bld
, 3);
246 * Apply workarounds for Gen6 gather with UINT/SINT
249 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
254 int width
= (wa
& WA_8BIT
) ? 8 : 16;
256 for (int i
= 0; i
< 4; i
++) {
257 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
258 /* Convert from UNORM to UINT */
259 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
263 /* Reinterpret the UINT value as a signed INT value by
264 * shifting the sign bit into place, then shifting back
267 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
268 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
271 dst
= offset(dst
, bld
, 1);
275 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
277 fs_visitor::emit_dummy_fs()
279 int reg_width
= dispatch_width
/ 8;
281 /* Everyone's favorite color. */
282 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
283 for (int i
= 0; i
< 4; i
++) {
284 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
285 brw_imm_f(color
[i
]));
289 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
291 if (devinfo
->gen
>= 6) {
293 write
->mlen
= 4 * reg_width
;
295 write
->header_size
= 2;
297 write
->mlen
= 2 + 4 * reg_width
;
300 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
301 * varying to avoid GPU hangs, so set that.
303 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
304 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
305 memset(wm_prog_data
->urb_setup
, -1,
306 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
308 /* We don't have any uniforms. */
309 stage_prog_data
->nr_params
= 0;
310 stage_prog_data
->nr_pull_params
= 0;
311 stage_prog_data
->curb_read_length
= 0;
312 stage_prog_data
->dispatch_grf_start_reg
= 2;
313 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
314 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
319 /* The register location here is relative to the start of the URB
320 * data. It will get adjusted to be a real location before
321 * generate_code() time.
324 fs_visitor::interp_reg(int location
, int channel
)
326 assert(stage
== MESA_SHADER_FRAGMENT
);
327 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
328 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
329 int stride
= (channel
& 1) * 4;
331 assert(prog_data
->urb_setup
[location
] != -1);
333 return brw_vec1_grf(regnr
, stride
);
336 /** Emits the interpolation for the varying inputs. */
338 fs_visitor::emit_interpolation_setup_gen4()
340 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
342 fs_builder abld
= bld
.annotate("compute pixel centers");
343 this->pixel_x
= vgrf(glsl_type::uint_type
);
344 this->pixel_y
= vgrf(glsl_type::uint_type
);
345 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
346 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
347 abld
.ADD(this->pixel_x
,
348 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
349 fs_reg(brw_imm_v(0x10101010)));
350 abld
.ADD(this->pixel_y
,
351 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
352 fs_reg(brw_imm_v(0x11001100)));
354 abld
= bld
.annotate("compute pixel deltas from v0");
356 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
357 vgrf(glsl_type::vec2_type
);
358 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
359 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
360 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
362 if (devinfo
->has_pln
&& dispatch_width
== 16) {
363 for (unsigned i
= 0; i
< 2; i
++) {
364 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
365 half(this->pixel_x
, i
), xstart
);
366 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
367 half(this->pixel_y
, i
), ystart
);
370 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
371 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
374 abld
= bld
.annotate("compute pos.w and 1/pos.w");
375 /* Compute wpos.w. It's always in our setup, since it's needed to
376 * interpolate the other attributes.
378 this->wpos_w
= vgrf(glsl_type::float_type
);
379 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
380 interp_reg(VARYING_SLOT_POS
, 3));
381 /* Compute the pixel 1/W value from wpos.w. */
382 this->pixel_w
= vgrf(glsl_type::float_type
);
383 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
386 /** Emits the interpolation for the varying inputs. */
388 fs_visitor::emit_interpolation_setup_gen6()
390 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
392 fs_builder abld
= bld
.annotate("compute pixel centers");
393 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
394 /* The "Register Region Restrictions" page says for BDW (and newer,
397 * "When destination spans two registers, the source may be one or
398 * two registers. The destination elements must be evenly split
399 * between the two registers."
401 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
402 * compute our pixel centers.
404 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
405 BRW_REGISTER_TYPE_UW
);
407 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
408 dbld
.ADD(int_pixel_xy
,
409 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
410 fs_reg(brw_imm_v(0x11001010)));
412 this->pixel_x
= vgrf(glsl_type::float_type
);
413 this->pixel_y
= vgrf(glsl_type::float_type
);
414 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
415 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
417 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
419 * "When destination spans two registers, the source MUST span two
422 * Since the GRF source of the ADD will only read a single register, we
423 * must do two separate ADDs in SIMD16.
425 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
426 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
427 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
428 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
429 abld
.ADD(int_pixel_x
,
430 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
431 fs_reg(brw_imm_v(0x10101010)));
432 abld
.ADD(int_pixel_y
,
433 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
434 fs_reg(brw_imm_v(0x11001100)));
436 /* As of gen6, we can no longer mix float and int sources. We have
437 * to turn the integer pixel centers into floats for their actual
440 this->pixel_x
= vgrf(glsl_type::float_type
);
441 this->pixel_y
= vgrf(glsl_type::float_type
);
442 abld
.MOV(this->pixel_x
, int_pixel_x
);
443 abld
.MOV(this->pixel_y
, int_pixel_y
);
446 abld
= bld
.annotate("compute pos.w");
447 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
448 this->wpos_w
= vgrf(glsl_type::float_type
);
449 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
451 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
452 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
453 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
457 static enum brw_conditional_mod
458 cond_for_alpha_func(GLenum func
)
462 return BRW_CONDITIONAL_G
;
464 return BRW_CONDITIONAL_GE
;
466 return BRW_CONDITIONAL_L
;
468 return BRW_CONDITIONAL_LE
;
470 return BRW_CONDITIONAL_EQ
;
472 return BRW_CONDITIONAL_NEQ
;
474 unreachable("Not reached");
479 * Alpha test support for when we compile it into the shader instead
480 * of using the normal fixed-function alpha test.
483 fs_visitor::emit_alpha_test()
485 assert(stage
== MESA_SHADER_FRAGMENT
);
486 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
487 const fs_builder abld
= bld
.annotate("Alpha test");
490 if (key
->alpha_test_func
== GL_ALWAYS
)
493 if (key
->alpha_test_func
== GL_NEVER
) {
495 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
496 BRW_REGISTER_TYPE_UW
));
497 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
498 BRW_CONDITIONAL_NEQ
);
501 fs_reg color
= offset(outputs
[0], bld
, 3);
503 /* f0.1 &= func(color, ref) */
504 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
505 cond_for_alpha_func(key
->alpha_test_func
));
507 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
508 cmp
->flag_subreg
= 1;
512 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
513 fs_reg color0
, fs_reg color1
,
514 fs_reg src0_alpha
, unsigned components
)
516 assert(stage
== MESA_SHADER_FRAGMENT
);
517 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
519 /* Hand over gl_FragDepth or the payload depth. */
520 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
521 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
523 fs_reg src_depth
, src_stencil
;
525 if (source_depth_to_render_target
) {
526 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
527 src_depth
= frag_depth
;
529 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
532 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
533 src_stencil
= frag_stencil
;
535 const fs_reg sources
[] = {
536 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
537 sample_mask
, brw_imm_ud(components
)
539 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
540 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
541 sources
, ARRAY_SIZE(sources
));
543 if (prog_data
->uses_kill
) {
544 write
->predicate
= BRW_PREDICATE_NORMAL
;
545 write
->flag_subreg
= 1;
552 fs_visitor::emit_fb_writes()
554 assert(stage
== MESA_SHADER_FRAGMENT
);
555 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
556 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
558 fs_inst
*inst
= NULL
;
560 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
561 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
562 * would require SIMD8 moves of each half to message regs, e.g. by using
563 * the SIMD lowering pass. Unfortunately this is more difficult than it
564 * sounds because the SIMD8 single-source message lacks channel selects
565 * for the second and third subspans.
567 no16("Missing support for simd16 depth writes on gen6\n");
570 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
571 /* From the 'Render Target Write message' section of the docs:
572 * "Output Stencil is not supported with SIMD16 Render Target Write
575 * FINISHME: split 16 into 2 8s
577 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
581 const fs_builder abld
= bld
.annotate("FB dual-source write");
583 inst
= emit_single_fb_write(abld
, this->outputs
[0],
584 this->dual_src_output
, reg_undef
, 4);
587 prog_data
->dual_src_blend
= true;
589 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
590 /* Skip over outputs that weren't written. */
591 if (this->outputs
[target
].file
== BAD_FILE
)
594 const fs_builder abld
= bld
.annotate(
595 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
598 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
599 src0_alpha
= offset(outputs
[0], bld
, 3);
601 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
603 this->output_components
[target
]);
604 inst
->target
= target
;
609 /* Even if there's no color buffers enabled, we still need to send
610 * alpha out the pipeline to our null renderbuffer to support
611 * alpha-testing, alpha-to-coverage, and so on.
613 /* FINISHME: Factor out this frequently recurring pattern into a
616 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
617 reg_undef
, offset(this->outputs
[0], bld
, 3) };
618 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
619 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
621 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
629 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
631 const struct brw_vs_prog_key
*key
=
632 (const struct brw_vs_prog_key
*) this->key
;
634 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
635 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
636 for (int j
= 0; j
< 4; ++j
) {
637 stage_prog_data
->param
[uniforms
+ j
] =
638 (gl_constant_value
*) &clip_planes
[i
][j
];
645 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
647 * This does nothing if the shader uses gl_ClipDistance or user clipping is
648 * disabled altogether.
650 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
652 struct brw_vue_prog_data
*vue_prog_data
=
653 (struct brw_vue_prog_data
*) prog_data
;
654 const struct brw_vs_prog_key
*key
=
655 (const struct brw_vs_prog_key
*) this->key
;
657 /* Bail unless some sort of legacy clipping is enabled */
658 if (key
->nr_userclip_plane_consts
== 0)
661 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
663 * "If a linked set of shaders forming the vertex stage contains no
664 * static write to gl_ClipVertex or gl_ClipDistance, but the
665 * application has requested clipping against user clip planes through
666 * the API, then the coordinate written to gl_Position is used for
667 * comparison against the user clip planes."
669 * This function is only called if the shader didn't write to
670 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
671 * if the user wrote to it; otherwise we use gl_Position.
674 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
675 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
676 clip_vertex
= VARYING_SLOT_POS
;
678 /* If the clip vertex isn't written, skip this. Typically this means
679 * the GS will set up clipping. */
680 if (outputs
[clip_vertex
].file
== BAD_FILE
)
683 setup_uniform_clipplane_values(clip_planes
);
685 const fs_builder abld
= bld
.annotate("user clip distances");
687 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
688 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
689 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
690 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
692 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
693 fs_reg u
= userplane
[i
];
694 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
695 output
.reg_offset
= i
& 3;
697 abld
.MUL(output
, outputs
[clip_vertex
], u
);
698 for (int j
= 1; j
< 4; j
++) {
699 u
.nr
= userplane
[i
].nr
+ j
;
700 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
706 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
708 int slot
, urb_offset
, length
;
709 int starting_urb_offset
= 0;
710 const struct brw_vue_prog_data
*vue_prog_data
=
711 (const struct brw_vue_prog_data
*) this->prog_data
;
712 const struct brw_vs_prog_key
*vs_key
=
713 (const struct brw_vs_prog_key
*) this->key
;
714 const GLbitfield64 psiz_mask
=
715 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
716 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
720 /* If we don't have any valid slots to write, just do a minimal urb write
721 * send to terminate the shader. This includes 1 slot of undefined data,
722 * because it's invalid to write 0 data:
724 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
725 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
726 * Write Data Payload:
728 * "The write data payload can be between 1 and 8 message phases long."
730 if (vue_map
->slots_valid
== 0) {
731 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
732 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
733 BRW_REGISTER_TYPE_UD
)));
735 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
742 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
744 fs_reg per_slot_offsets
;
746 if (stage
== MESA_SHADER_GEOMETRY
) {
747 const struct brw_gs_prog_data
*gs_prog_data
=
748 (const struct brw_gs_prog_data
*) this->prog_data
;
750 /* We need to increment the Global Offset to skip over the control data
751 * header and the extra "Vertex Count" field (1 HWord) at the beginning
752 * of the VUE. We're counting in OWords, so the units are doubled.
754 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
755 if (gs_prog_data
->static_vertex_count
== -1)
756 starting_urb_offset
+= 2;
758 /* We also need to use per-slot offsets. The per-slot offset is the
759 * Vertex Count. SIMD8 mode processes 8 different primitives at a
760 * time; each may output a different number of vertices.
762 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
765 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
766 const int output_vertex_size_owords
=
767 gs_prog_data
->output_vertex_size_hwords
* 2;
770 if (gs_vertex_count
.file
== IMM
) {
771 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
774 per_slot_offsets
= vgrf(glsl_type::int_type
);
775 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
776 brw_imm_ud(output_vertex_size_owords
));
781 urb_offset
= starting_urb_offset
;
783 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
784 int varying
= vue_map
->slot_to_varying
[slot
];
786 case VARYING_SLOT_PSIZ
: {
787 /* The point size varying slot is the vue header and is always in the
788 * vue map. But often none of the special varyings that live there
789 * are written and in that case we can skip writing to the vue
790 * header, provided the corresponding state properly clamps the
791 * values further down the pipeline. */
792 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
798 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
799 bld
.MOV(zero
, brw_imm_ud(0u));
801 sources
[length
++] = zero
;
802 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
803 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
805 sources
[length
++] = zero
;
807 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
808 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
810 sources
[length
++] = zero
;
812 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
813 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
815 sources
[length
++] = zero
;
818 case BRW_VARYING_SLOT_NDC
:
819 case VARYING_SLOT_EDGE
:
820 unreachable("unexpected scalar vs output");
824 /* gl_Position is always in the vue map, but isn't always written by
825 * the shader. Other varyings (clip distances) get added to the vue
826 * map but don't always get written. In those cases, the
827 * corresponding this->output[] slot will be invalid we and can skip
828 * the urb write for the varying. If we've already queued up a vue
829 * slot for writing we flush a mlen 5 urb write, otherwise we just
830 * advance the urb_offset.
832 if (varying
== BRW_VARYING_SLOT_PAD
||
833 this->outputs
[varying
].file
== BAD_FILE
) {
841 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
842 (varying
== VARYING_SLOT_COL0
||
843 varying
== VARYING_SLOT_COL1
||
844 varying
== VARYING_SLOT_BFC0
||
845 varying
== VARYING_SLOT_BFC1
)) {
846 /* We need to clamp these guys, so do a saturating MOV into a
847 * temp register and use that for the payload.
849 for (int i
= 0; i
< 4; i
++) {
850 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
851 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
852 set_saturate(true, bld
.MOV(reg
, src
));
853 sources
[length
++] = reg
;
856 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
857 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
858 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
859 sources
[length
++] = brw_imm_d(0);
864 const fs_builder abld
= bld
.annotate("URB write");
866 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
867 * the last slot or if we need to flush (see BAD_FILE varying case
868 * above), emit a URB write send now to flush out the data.
870 int last
= slot
== vue_map
->num_slots
- 1;
871 if (length
== 8 || last
)
874 fs_reg
*payload_sources
=
875 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
876 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
877 BRW_REGISTER_TYPE_F
);
879 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
881 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
882 payload_sources
[1] = per_slot_offsets
;
884 memcpy(&payload_sources
[header_size
], sources
,
885 length
* sizeof sources
[0]);
887 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
890 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
891 inst
->eot
= last
&& stage
== MESA_SHADER_VERTEX
;
892 inst
->mlen
= length
+ header_size
;
893 inst
->offset
= urb_offset
;
894 urb_offset
= starting_urb_offset
+ slot
+ 1;
902 fs_visitor::emit_cs_terminate()
904 assert(devinfo
->gen
>= 7);
906 /* We are getting the thread ID from the compute shader header */
907 assert(stage
== MESA_SHADER_COMPUTE
);
909 /* We can't directly send from g0, since sends with EOT have to use
910 * g112-127. So, copy it to a virtual register, The register allocator will
911 * make sure it uses the appropriate register range.
913 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
914 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
915 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
917 /* Send a message to the thread spawner to terminate the thread. */
918 fs_inst
*inst
= bld
.exec_all()
919 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
924 fs_visitor::emit_barrier()
926 assert(devinfo
->gen
>= 7);
928 /* We are getting the barrier ID from the compute shader header */
929 assert(stage
== MESA_SHADER_COMPUTE
);
931 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
933 const fs_builder pbld
= bld
.exec_all().group(8, 0);
935 /* Clear the message payload */
936 pbld
.MOV(payload
, brw_imm_ud(0u));
938 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
939 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
940 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(0x0f000000u
));
942 /* Emit a gateway "barrier" message using the payload we set up, followed
943 * by a wait instruction.
945 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
948 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
951 struct brw_stage_prog_data
*prog_data
,
952 struct gl_program
*prog
,
953 const nir_shader
*shader
,
954 unsigned dispatch_width
,
955 int shader_time_index
)
956 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
957 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
958 dispatch_width(dispatch_width
),
959 shader_time_index(shader_time_index
),
960 bld(fs_builder(this, dispatch_width
).at_end())
965 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
967 struct brw_gs_compile
*c
,
968 struct brw_gs_prog_data
*prog_data
,
969 const nir_shader
*shader
,
970 int shader_time_index
)
971 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
972 &prog_data
->base
.base
),
973 key(&c
->key
), gs_compile(c
),
974 prog_data(&prog_data
->base
.base
), prog(NULL
),
976 shader_time_index(shader_time_index
),
977 bld(fs_builder(this, dispatch_width
).at_end())
987 case MESA_SHADER_FRAGMENT
:
988 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
990 case MESA_SHADER_VERTEX
:
991 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
993 case MESA_SHADER_GEOMETRY
:
994 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
996 case MESA_SHADER_COMPUTE
:
997 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1000 unreachable("unhandled shader stage");
1003 this->prog_data
= this->stage_prog_data
;
1005 this->failed
= false;
1006 this->simd16_unsupported
= false;
1007 this->no16_msg
= NULL
;
1009 this->nir_locals
= NULL
;
1010 this->nir_ssa_values
= NULL
;
1012 memset(&this->payload
, 0, sizeof(this->payload
));
1013 memset(this->output_components
, 0, sizeof(this->output_components
));
1014 this->source_depth_to_render_target
= false;
1015 this->runtime_check_aads_emit
= false;
1016 this->first_non_payload_grf
= 0;
1017 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1019 this->virtual_grf_start
= NULL
;
1020 this->virtual_grf_end
= NULL
;
1021 this->live_intervals
= NULL
;
1022 this->regs_live_at_ip
= NULL
;
1025 this->last_scratch
= 0;
1026 this->pull_constant_loc
= NULL
;
1027 this->push_constant_loc
= NULL
;
1029 this->promoted_constants
= 0,
1031 this->spilled_any_registers
= false;
1032 this->do_dual_src
= false;
1034 if (dispatch_width
== 8)
1035 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1038 fs_visitor::~fs_visitor()