2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation(ir
);
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
74 assert(ir
->location
== FRAG_RESULT_DATA0
);
75 assert(ir
->index
== 1);
76 this->dual_src_output
= *reg
;
77 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
80 this->outputs
[i
] = *reg
;
81 this->output_components
[i
] = 4;
83 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
84 this->frag_depth
= *reg
;
86 /* gl_FragData or a user-defined FS output */
87 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
88 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
91 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
92 : ir
->type
->vector_elements
;
94 /* General color output. */
95 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
96 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
97 this->outputs
[output
] = *reg
;
98 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
99 this->output_components
[output
] = vector_elements
;
102 } else if (ir
->mode
== ir_var_uniform
) {
103 int param_index
= c
->prog_data
.nr_params
;
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
109 if (ir
->is_in_uniform_block())
112 if (dispatch_width
== 16) {
113 if (!variable_storage(ir
)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
119 param_size
[param_index
] = type_size(ir
->type
);
120 if (!strncmp(ir
->name
, "gl_", 3)) {
121 setup_builtin_uniform_values(ir
);
123 setup_uniform_values(ir
);
126 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
127 reg
->type
= brw_type_for_base_type(ir
->type
);
131 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
133 hash_table_insert(this->variable_ht
, reg
, ir
);
137 fs_visitor::visit(ir_dereference_variable
*ir
)
139 fs_reg
*reg
= variable_storage(ir
->var
);
144 fs_visitor::visit(ir_dereference_record
*ir
)
146 const glsl_type
*struct_type
= ir
->record
->type
;
148 ir
->record
->accept(this);
150 unsigned int offset
= 0;
151 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
152 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
154 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
156 this->result
.reg_offset
+= offset
;
157 this->result
.type
= brw_type_for_base_type(ir
->type
);
161 fs_visitor::visit(ir_dereference_array
*ir
)
163 ir_constant
*constant_index
;
165 int element_size
= type_size(ir
->type
);
167 constant_index
= ir
->array_index
->as_constant();
169 ir
->array
->accept(this);
171 src
.type
= brw_type_for_base_type(ir
->type
);
173 if (constant_index
) {
174 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
175 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
184 ir
->array_index
->accept(this);
187 index_reg
= fs_reg(this, glsl_type::int_type
);
188 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
191 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
194 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
195 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
201 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
203 if (intel
->gen
< 6 ||
204 !x
.is_valid_3src() ||
205 !y
.is_valid_3src() ||
206 !a
.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
209 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
210 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
212 emit(MUL(y_times_a
, y
, a
));
214 a
.negate
= !a
.negate
;
215 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
216 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
218 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
223 emit(LRP(dst
, a
, y
, x
));
228 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
229 fs_reg src0
, fs_reg src1
)
233 if (intel
->gen
>= 6) {
234 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
235 inst
->conditional_mod
= conditionalmod
;
237 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
239 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
240 inst
->predicate
= BRW_PREDICATE_NORMAL
;
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
248 fs_visitor::try_emit_saturate(ir_expression
*ir
)
250 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
255 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
257 sat_val
->accept(this);
258 fs_reg src
= this->result
;
260 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
265 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
266 if (!modify
|| modify
->regs_written
!= 1) {
267 this->result
= fs_reg(this, ir
->type
);
268 fs_inst
*inst
= emit(MOV(this->result
, src
));
269 inst
->saturate
= true;
271 modify
->saturate
= true;
280 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
282 /* 3-src instructions were introduced in gen6. */
286 /* MAD can only handle floating-point data. */
287 if (ir
->type
!= glsl_type::float_type
)
290 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
291 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
293 if (!mul
|| mul
->operation
!= ir_binop_mul
)
296 if (nonmul
->as_constant() ||
297 mul
->operands
[0]->as_constant() ||
298 mul
->operands
[1]->as_constant())
301 nonmul
->accept(this);
302 fs_reg src0
= this->result
;
304 mul
->operands
[0]->accept(this);
305 fs_reg src1
= this->result
;
307 mul
->operands
[1]->accept(this);
308 fs_reg src2
= this->result
;
310 this->result
= fs_reg(this, ir
->type
);
311 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
317 fs_visitor::visit(ir_expression
*ir
)
319 unsigned int operand
;
323 assert(ir
->get_num_operands() <= 3);
325 if (try_emit_saturate(ir
))
327 if (ir
->operation
== ir_binop_add
) {
328 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
332 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
333 ir
->operands
[operand
]->accept(this);
334 if (this->result
.file
== BAD_FILE
) {
335 fail("Failed to get tree for expression operand:\n");
336 ir
->operands
[operand
]->print();
339 op
[operand
] = this->result
;
341 /* Matrix expression operands should have been broken down to vector
342 * operations already.
344 assert(!ir
->operands
[operand
]->type
->is_matrix());
345 /* And then those vector operands should have been broken down to scalar.
347 assert(!ir
->operands
[operand
]->type
->is_vector());
350 /* Storage for our result. If our result goes into an assignment, it will
351 * just get copy-propagated out, so no worries.
353 this->result
= fs_reg(this, ir
->type
);
355 switch (ir
->operation
) {
356 case ir_unop_logic_not
:
357 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
358 * ones complement of the whole register, not just bit 0.
360 emit(XOR(this->result
, op
[0], fs_reg(1)));
363 op
[0].negate
= !op
[0].negate
;
364 this->result
= op
[0];
368 op
[0].negate
= false;
369 this->result
= op
[0];
372 temp
= fs_reg(this, ir
->type
);
374 emit(MOV(this->result
, fs_reg(0.0f
)));
376 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
377 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
378 inst
->predicate
= BRW_PREDICATE_NORMAL
;
380 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
381 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
382 inst
->predicate
= BRW_PREDICATE_NORMAL
;
386 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
390 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
393 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
397 assert(!"not reached: should be handled by ir_explog_to_explog2");
400 case ir_unop_sin_reduced
:
401 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
404 case ir_unop_cos_reduced
:
405 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
409 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
412 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
416 emit(ADD(this->result
, op
[0], op
[1]));
419 assert(!"not reached: should be handled by ir_sub_to_add_neg");
423 if (ir
->type
->is_integer()) {
424 /* For integer multiplication, the MUL uses the low 16 bits
425 * of one of the operands (src0 on gen6, src1 on gen7). The
426 * MACH accumulates in the contribution of the upper 16 bits
429 * FINISHME: Emit just the MUL if we know an operand is small
432 if (intel
->gen
>= 7 && dispatch_width
== 16)
433 fail("16-wide explicit accumulator operands unsupported\n");
435 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
437 emit(MUL(acc
, op
[0], op
[1]));
438 emit(MACH(reg_null_d
, op
[0], op
[1]));
439 emit(MOV(this->result
, fs_reg(acc
)));
441 emit(MUL(this->result
, op
[0], op
[1]));
445 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
446 assert(ir
->type
->is_integer());
447 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
450 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
451 assert(ir
->type
->is_integer());
452 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
456 case ir_binop_greater
:
457 case ir_binop_lequal
:
458 case ir_binop_gequal
:
460 case ir_binop_all_equal
:
461 case ir_binop_nequal
:
462 case ir_binop_any_nequal
:
463 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
464 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
466 emit(CMP(this->result
, op
[0], op
[1],
467 brw_conditional_for_comparison(ir
->operation
)));
470 case ir_binop_logic_xor
:
471 emit(XOR(this->result
, op
[0], op
[1]));
474 case ir_binop_logic_or
:
475 emit(OR(this->result
, op
[0], op
[1]));
478 case ir_binop_logic_and
:
479 emit(AND(this->result
, op
[0], op
[1]));
484 assert(!"not reached: should be handled by brw_fs_channel_expressions");
488 assert(!"not reached: should be handled by lower_noise");
491 case ir_quadop_vector
:
492 assert(!"not reached: should be handled by lower_quadop_vector");
495 case ir_binop_vector_extract
:
496 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
499 case ir_triop_vector_insert
:
500 assert(!"not reached: should be handled by lower_vector_insert()");
504 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
508 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
511 case ir_unop_bitcast_i2f
:
512 case ir_unop_bitcast_u2f
:
513 op
[0].type
= BRW_REGISTER_TYPE_F
;
514 this->result
= op
[0];
517 case ir_unop_bitcast_f2u
:
518 op
[0].type
= BRW_REGISTER_TYPE_UD
;
519 this->result
= op
[0];
522 case ir_unop_bitcast_f2i
:
523 op
[0].type
= BRW_REGISTER_TYPE_D
;
524 this->result
= op
[0];
530 emit(MOV(this->result
, op
[0]));
534 emit(AND(this->result
, op
[0], fs_reg(1)));
537 temp
= fs_reg(this, glsl_type::int_type
);
538 emit(AND(temp
, op
[0], fs_reg(1)));
539 emit(MOV(this->result
, temp
));
543 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
546 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
550 emit(RNDZ(this->result
, op
[0]));
553 op
[0].negate
= !op
[0].negate
;
554 emit(RNDD(this->result
, op
[0]));
555 this->result
.negate
= true;
558 emit(RNDD(this->result
, op
[0]));
561 emit(FRC(this->result
, op
[0]));
563 case ir_unop_round_even
:
564 emit(RNDE(this->result
, op
[0]));
569 resolve_ud_negate(&op
[0]);
570 resolve_ud_negate(&op
[1]);
571 emit_minmax(ir
->operation
== ir_binop_min
?
572 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
573 this->result
, op
[0], op
[1]);
575 case ir_unop_pack_snorm_2x16
:
576 case ir_unop_pack_snorm_4x8
:
577 case ir_unop_pack_unorm_2x16
:
578 case ir_unop_pack_unorm_4x8
:
579 case ir_unop_unpack_snorm_2x16
:
580 case ir_unop_unpack_snorm_4x8
:
581 case ir_unop_unpack_unorm_2x16
:
582 case ir_unop_unpack_unorm_4x8
:
583 case ir_unop_unpack_half_2x16
:
584 case ir_unop_pack_half_2x16
:
585 assert(!"not reached: should be handled by lower_packing_builtins");
587 case ir_unop_unpack_half_2x16_split_x
:
588 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
590 case ir_unop_unpack_half_2x16_split_y
:
591 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
594 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
597 case ir_unop_bitfield_reverse
:
598 emit(BFREV(this->result
, op
[0]));
600 case ir_unop_bit_count
:
601 emit(CBIT(this->result
, op
[0]));
603 case ir_unop_find_msb
:
604 temp
= fs_reg(this, glsl_type::uint_type
);
605 emit(FBH(temp
, op
[0]));
607 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
608 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
609 * subtract the result from 31 to convert the MSB count into an LSB count.
612 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
613 emit(MOV(this->result
, temp
));
614 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
617 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
618 inst
->predicate
= BRW_PREDICATE_NORMAL
;
620 case ir_unop_find_lsb
:
621 emit(FBL(this->result
, op
[0]));
623 case ir_triop_bitfield_extract
:
624 /* Note that the instruction's argument order is reversed from GLSL
627 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
630 emit(BFI1(this->result
, op
[0], op
[1]));
633 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
635 case ir_quadop_bitfield_insert
:
636 assert(!"not reached: should be handled by "
637 "lower_instructions::bitfield_insert_to_bfm_bfi");
640 case ir_unop_bit_not
:
641 emit(NOT(this->result
, op
[0]));
643 case ir_binop_bit_and
:
644 emit(AND(this->result
, op
[0], op
[1]));
646 case ir_binop_bit_xor
:
647 emit(XOR(this->result
, op
[0], op
[1]));
649 case ir_binop_bit_or
:
650 emit(OR(this->result
, op
[0], op
[1]));
653 case ir_binop_lshift
:
654 emit(SHL(this->result
, op
[0], op
[1]));
657 case ir_binop_rshift
:
658 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
659 emit(ASR(this->result
, op
[0], op
[1]));
661 emit(SHR(this->result
, op
[0], op
[1]));
663 case ir_binop_pack_half_2x16_split
:
664 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
666 case ir_binop_ubo_load
: {
667 /* This IR node takes a constant uniform block and a constant or
668 * variable byte offset within the block and loads a vector from that.
670 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
671 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
672 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
674 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
675 packed_consts
.type
= result
.type
;
677 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
678 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
679 packed_consts
, surf_index
, const_offset_reg
));
681 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
682 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
683 /* UBO bools are any nonzero value. We consider bools to be
684 * values with the low bit set to 1. Convert them using CMP.
686 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
687 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
689 emit(MOV(result
, packed_consts
));
692 packed_consts
.smear
++;
695 /* The std140 packing rules don't allow vectors to cross 16-byte
696 * boundaries, and a reg is 32 bytes.
698 assert(packed_consts
.smear
< 8);
701 /* Turn the byte offset into a dword offset. */
702 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
703 emit(SHR(base_offset
, op
[1], fs_reg(2)));
705 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
706 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
709 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
710 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
716 result
.reg_offset
= 0;
721 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
727 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
728 const glsl_type
*type
, bool predicated
)
730 switch (type
->base_type
) {
731 case GLSL_TYPE_FLOAT
:
735 for (unsigned int i
= 0; i
< type
->components(); i
++) {
736 l
.type
= brw_type_for_base_type(type
);
737 r
.type
= brw_type_for_base_type(type
);
739 if (predicated
|| !l
.equals(r
)) {
740 fs_inst
*inst
= emit(MOV(l
, r
));
741 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
748 case GLSL_TYPE_ARRAY
:
749 for (unsigned int i
= 0; i
< type
->length
; i
++) {
750 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
754 case GLSL_TYPE_STRUCT
:
755 for (unsigned int i
= 0; i
< type
->length
; i
++) {
756 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
761 case GLSL_TYPE_SAMPLER
:
765 case GLSL_TYPE_ERROR
:
766 case GLSL_TYPE_INTERFACE
:
767 assert(!"not reached");
772 /* If the RHS processing resulted in an instruction generating a
773 * temporary value, and it would be easy to rewrite the instruction to
774 * generate its result right into the LHS instead, do so. This ends
775 * up reliably removing instructions where it can be tricky to do so
776 * later without real UD chain information.
779 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
782 fs_inst
*pre_rhs_inst
,
783 fs_inst
*last_rhs_inst
)
785 /* Only attempt if we're doing a direct assignment. */
787 !(ir
->lhs
->type
->is_scalar() ||
788 (ir
->lhs
->type
->is_vector() &&
789 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
792 /* Make sure the last instruction generated our source reg. */
793 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
799 /* If last_rhs_inst wrote a different number of components than our LHS,
800 * we can't safely rewrite it.
802 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
805 /* Success! Rewrite the instruction. */
812 fs_visitor::visit(ir_assignment
*ir
)
817 /* FINISHME: arrays on the lhs */
818 ir
->lhs
->accept(this);
821 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
823 ir
->rhs
->accept(this);
826 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
828 assert(l
.file
!= BAD_FILE
);
829 assert(r
.file
!= BAD_FILE
);
831 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
835 emit_bool_to_cond_code(ir
->condition
);
838 if (ir
->lhs
->type
->is_scalar() ||
839 ir
->lhs
->type
->is_vector()) {
840 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
841 if (ir
->write_mask
& (1 << i
)) {
842 inst
= emit(MOV(l
, r
));
844 inst
->predicate
= BRW_PREDICATE_NORMAL
;
850 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
855 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
856 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
866 if (ir
->shadow_comparitor
) {
867 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
868 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
869 coordinate
.reg_offset
++;
871 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
874 if (ir
->op
== ir_tex
) {
875 /* There's no plain shadow compare message, so we use shadow
876 * compare with a bias of 0.0.
878 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
880 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
881 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
884 assert(!"Should not get here.");
887 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
889 } else if (ir
->op
== ir_tex
) {
890 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
891 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
892 coordinate
.reg_offset
++;
894 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
896 } else if (ir
->op
== ir_txd
) {
899 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
900 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
901 coordinate
.reg_offset
++;
903 /* the slots for u and v are always present, but r is optional */
904 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
907 * dPdx = dudx, dvdx, drdx
908 * dPdy = dudy, dvdy, drdy
910 * 1-arg: Does not exist.
912 * 2-arg: dudx dvdx dudy dvdy
913 * dPdx.x dPdx.y dPdy.x dPdy.y
916 * 3-arg: dudx dvdx drdx dudy dvdy drdy
917 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
920 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
921 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
924 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
926 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
927 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
930 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
931 } else if (ir
->op
== ir_txs
) {
932 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
934 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
937 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
938 * instructions. We'll need to do SIMD16 here.
941 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
943 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
944 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
946 coordinate
.reg_offset
++;
949 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
950 * be necessary for TXF (ld), but seems wise to do for all messages.
952 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
953 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
956 /* lod/bias appears after u/v/r. */
959 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
962 /* The unused upper half. */
967 /* Now, since we're doing simd16, the return is 2 interleaved
968 * vec4s where the odd-indexed ones are junk. We'll need to move
969 * this weirdness around to the expected layout.
972 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
974 brw_type_for_base_type(ir
->type
) :
975 BRW_REGISTER_TYPE_F
));
978 fs_inst
*inst
= NULL
;
981 inst
= emit(SHADER_OPCODE_TEX
, dst
);
984 inst
= emit(FS_OPCODE_TXB
, dst
);
987 inst
= emit(SHADER_OPCODE_TXL
, dst
);
990 inst
= emit(SHADER_OPCODE_TXD
, dst
);
993 inst
= emit(SHADER_OPCODE_TXS
, dst
);
996 inst
= emit(SHADER_OPCODE_TXF
, dst
);
999 fail("unrecognized texture opcode");
1001 inst
->base_mrf
= base_mrf
;
1003 inst
->header_present
= true;
1004 inst
->regs_written
= simd16
? 8 : 4;
1007 for (int i
= 0; i
< 4; i
++) {
1008 emit(MOV(orig_dst
, dst
));
1009 orig_dst
.reg_offset
++;
1010 dst
.reg_offset
+= 2;
1017 /* gen5's sampler has slots for u, v, r, array index, then optional
1018 * parameters like shadow comparitor or LOD bias. If optional
1019 * parameters aren't present, those base slots are optional and don't
1020 * need to be included in the message.
1022 * We don't fill in the unnecessary slots regardless, which may look
1023 * surprising in the disassembly.
1026 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1027 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1028 fs_reg sample_index
)
1032 int reg_width
= dispatch_width
/ 8;
1033 bool header_present
= false;
1034 const int vector_elements
=
1035 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1037 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
1038 /* It appears that the ld instruction used for txf does its
1039 * address bounds check before adding in the offset. To work
1040 * around this, just add the integer offset to the integer texel
1041 * coordinate, and don't put the offset in the header.
1043 ir_constant
*offset
= ir
->offset
->as_constant();
1044 for (int i
= 0; i
< vector_elements
; i
++) {
1045 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1047 offset
->value
.i
[i
]));
1048 coordinate
.reg_offset
++;
1052 /* The offsets set up by the ir_texture visitor are in the
1053 * m1 header, so we can't go headerless.
1055 header_present
= true;
1060 for (int i
= 0; i
< vector_elements
; i
++) {
1061 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1063 coordinate
.reg_offset
++;
1066 mlen
+= vector_elements
* reg_width
;
1068 if (ir
->shadow_comparitor
) {
1069 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1071 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1075 fs_inst
*inst
= NULL
;
1078 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1081 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1082 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1085 inst
= emit(FS_OPCODE_TXB
, dst
);
1088 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1089 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1092 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1095 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1099 * dPdx = dudx, dvdx, drdx
1100 * dPdy = dudy, dvdy, drdy
1102 * Load up these values:
1103 * - dudx dudy dvdx dvdy drdx drdy
1104 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1106 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1107 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1111 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1116 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1120 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1122 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1125 mlen
= header_present
+ 4 * reg_width
;
1126 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1127 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1130 mlen
= header_present
+ 4 * reg_width
;
1133 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1135 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1137 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1140 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1143 inst
->base_mrf
= base_mrf
;
1145 inst
->header_present
= header_present
;
1146 inst
->regs_written
= 4;
1149 fail("Message length >11 disallowed by hardware\n");
1156 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1157 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1158 fs_reg sample_index
)
1162 int reg_width
= dispatch_width
/ 8;
1163 bool header_present
= false;
1166 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1167 /* The offsets set up by the ir_texture visitor are in the
1168 * m1 header, so we can't go headerless.
1170 header_present
= true;
1175 if (ir
->shadow_comparitor
) {
1176 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1180 /* Set up the LOD info */
1186 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1190 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1194 if (dispatch_width
== 16)
1195 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1197 /* Load dPdx and the coordinate together:
1198 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1200 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1201 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1202 coordinate
.reg_offset
++;
1205 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1206 * only derivatives for (u, v, r).
1208 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1209 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1213 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1221 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1225 /* It appears that the ld instruction used for txf does its
1226 * address bounds check before adding in the offset. To work
1227 * around this, just add the integer offset to the integer texel
1228 * coordinate, and don't put the offset in the header.
1231 ir_constant
*offset
= ir
->offset
->as_constant();
1232 offsets
[0] = offset
->value
.i
[0];
1233 offsets
[1] = offset
->value
.i
[1];
1234 offsets
[2] = offset
->value
.i
[2];
1236 memset(offsets
, 0, sizeof(offsets
));
1239 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1240 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1241 coordinate
, offsets
[0]));
1242 coordinate
.reg_offset
++;
1245 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1248 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1249 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1250 coordinate
, offsets
[i
]));
1251 coordinate
.reg_offset
++;
1256 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1259 /* constant zero MCS; we arrange to never actually have a compressed
1260 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1261 * if we ever support texturing from compressed multisample surfaces
1263 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1266 /* there is no offsetting for this message; just copy in the integer
1267 * texture coordinates
1269 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1270 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1272 coordinate
.reg_offset
++;
1278 /* Set up the coordinate (except for cases where it was done above) */
1279 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
&& ir
->op
!= ir_txf_ms
) {
1280 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1281 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1282 coordinate
.reg_offset
++;
1287 /* Generate the SEND */
1288 fs_inst
*inst
= NULL
;
1290 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1291 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1292 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1293 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1294 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1295 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
); break;
1296 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1297 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
); break;
1299 inst
->base_mrf
= base_mrf
;
1301 inst
->header_present
= header_present
;
1302 inst
->regs_written
= 4;
1305 fail("Message length >11 disallowed by hardware\n");
1312 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1313 bool is_rect
, int sampler
, int texunit
)
1315 fs_inst
*inst
= NULL
;
1316 bool needs_gl_clamp
= true;
1317 fs_reg scale_x
, scale_y
;
1319 /* The 965 requires the EU to do the normalization of GL rectangle
1320 * texture coordinates. We use the program parameter state
1321 * tracking to get the scaling factor.
1325 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1326 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1327 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1328 int tokens
[STATE_LENGTH
] = {
1330 STATE_TEXRECT_SCALE
,
1336 if (dispatch_width
== 16) {
1337 fail("rectangle scale uniform setup not supported on 16-wide\n");
1341 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1342 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1344 GLuint index
= _mesa_add_state_reference(params
,
1345 (gl_state_index
*)tokens
);
1346 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1347 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1348 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1349 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1352 /* The 965 requires the EU to do the normalization of GL rectangle
1353 * texture coordinates. We use the program parameter state
1354 * tracking to get the scaling factor.
1356 if (intel
->gen
< 6 && is_rect
) {
1357 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1358 fs_reg src
= coordinate
;
1361 emit(MUL(dst
, src
, scale_x
));
1364 emit(MUL(dst
, src
, scale_y
));
1365 } else if (is_rect
) {
1366 /* On gen6+, the sampler handles the rectangle coordinates
1367 * natively, without needing rescaling. But that means we have
1368 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1369 * not [0, 1] like the default case below.
1371 needs_gl_clamp
= false;
1373 for (int i
= 0; i
< 2; i
++) {
1374 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1375 fs_reg chan
= coordinate
;
1376 chan
.reg_offset
+= i
;
1378 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1379 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1381 /* Our parameter comes in as 1.0/width or 1.0/height,
1382 * because that's what people normally want for doing
1383 * texture rectangle handling. We need width or height
1384 * for clamping, but we don't care enough to make a new
1385 * parameter type, so just invert back.
1387 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1388 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1389 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1391 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1392 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1397 if (ir
->coordinate
&& needs_gl_clamp
) {
1398 for (unsigned int i
= 0;
1399 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1400 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1401 fs_reg chan
= coordinate
;
1402 chan
.reg_offset
+= i
;
1404 fs_inst
*inst
= emit(MOV(chan
, chan
));
1405 inst
->saturate
= true;
1413 fs_visitor::visit(ir_texture
*ir
)
1415 fs_inst
*inst
= NULL
;
1418 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, &fp
->Base
);
1419 /* FINISHME: We're failing to recompile our programs when the sampler is
1420 * updated. This only matters for the texture rectangle scale parameters
1421 * (pre-gen6, or gen6+ with GL_CLAMP).
1423 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1425 /* Should be lowered by do_lower_texture_projection */
1426 assert(!ir
->projector
);
1428 /* Generate code to compute all the subexpression trees. This has to be
1429 * done before loading any values into MRFs for the sampler message since
1430 * generating these values may involve SEND messages that need the MRFs.
1433 if (ir
->coordinate
) {
1434 ir
->coordinate
->accept(this);
1436 coordinate
= rescale_texcoord(ir
, this->result
,
1437 ir
->sampler
->type
->sampler_dimensionality
==
1438 GLSL_SAMPLER_DIM_RECT
,
1442 fs_reg shadow_comparitor
;
1443 if (ir
->shadow_comparitor
) {
1444 ir
->shadow_comparitor
->accept(this);
1445 shadow_comparitor
= this->result
;
1448 fs_reg lod
, lod2
, sample_index
;
1454 ir
->lod_info
.bias
->accept(this);
1458 ir
->lod_info
.grad
.dPdx
->accept(this);
1461 ir
->lod_info
.grad
.dPdy
->accept(this);
1462 lod2
= this->result
;
1467 ir
->lod_info
.lod
->accept(this);
1471 ir
->lod_info
.sample_index
->accept(this);
1472 sample_index
= this->result
;
1476 /* Writemasking doesn't eliminate channels on SIMD8 texture
1477 * samples, so don't worry about them.
1479 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1481 if (intel
->gen
>= 7) {
1482 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1483 lod
, lod2
, sample_index
);
1484 } else if (intel
->gen
>= 5) {
1485 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1486 lod
, lod2
, sample_index
);
1488 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1492 /* The header is set up by generate_tex() when necessary. */
1493 inst
->src
[0] = reg_undef
;
1495 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1496 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1498 inst
->sampler
= sampler
;
1500 if (ir
->shadow_comparitor
)
1501 inst
->shadow_compare
= true;
1503 /* fixup #layers for cube map arrays */
1504 if (ir
->op
== ir_txs
) {
1505 glsl_type
const *type
= ir
->sampler
->type
;
1506 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1507 type
->sampler_array
) {
1509 depth
.reg_offset
= 2;
1510 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1514 swizzle_result(ir
, dst
, sampler
);
1518 * Swizzle the result of a texture result. This is necessary for
1519 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1522 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1524 this->result
= orig_val
;
1526 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
)
1529 if (ir
->type
== glsl_type::float_type
) {
1530 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1531 assert(ir
->sampler
->type
->sampler_shadow
);
1532 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1533 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1535 for (int i
= 0; i
< 4; i
++) {
1536 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1537 fs_reg l
= swizzled_result
;
1540 if (swiz
== SWIZZLE_ZERO
) {
1541 emit(MOV(l
, fs_reg(0.0f
)));
1542 } else if (swiz
== SWIZZLE_ONE
) {
1543 emit(MOV(l
, fs_reg(1.0f
)));
1545 fs_reg r
= orig_val
;
1546 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1550 this->result
= swizzled_result
;
1555 fs_visitor::visit(ir_swizzle
*ir
)
1557 ir
->val
->accept(this);
1558 fs_reg val
= this->result
;
1560 if (ir
->type
->vector_elements
== 1) {
1561 this->result
.reg_offset
+= ir
->mask
.x
;
1565 fs_reg result
= fs_reg(this, ir
->type
);
1566 this->result
= result
;
1568 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1569 fs_reg channel
= val
;
1587 channel
.reg_offset
+= swiz
;
1588 emit(MOV(result
, channel
));
1589 result
.reg_offset
++;
1594 fs_visitor::visit(ir_discard
*ir
)
1596 assert(ir
->condition
== NULL
); /* FINISHME */
1598 /* We track our discarded pixels in f0.1. By predicating on it, we can
1599 * update just the flag bits that aren't yet discarded. By emitting a
1600 * CMP of g0 != g0, all our currently executing channels will get turned
1603 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1604 BRW_REGISTER_TYPE_UW
));
1605 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1606 BRW_CONDITIONAL_NZ
));
1607 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1608 cmp
->flag_subreg
= 1;
1610 if (intel
->gen
>= 6) {
1611 /* For performance, after a discard, jump to the end of the shader.
1612 * However, many people will do foliage by discarding based on a
1613 * texture's alpha mask, and then continue on to texture with the
1614 * remaining pixels. To avoid trashing the derivatives for those
1615 * texture samples, we'll only jump if all of the pixels in the subspan
1616 * have been discarded.
1618 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1619 discard_jump
->flag_subreg
= 1;
1620 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1621 discard_jump
->predicate_inverse
= true;
1626 fs_visitor::visit(ir_constant
*ir
)
1628 /* Set this->result to reg at the bottom of the function because some code
1629 * paths will cause this visitor to be applied to other fields. This will
1630 * cause the value stored in this->result to be modified.
1632 * Make reg constant so that it doesn't get accidentally modified along the
1633 * way. Yes, I actually had this problem. :(
1635 const fs_reg
reg(this, ir
->type
);
1636 fs_reg dst_reg
= reg
;
1638 if (ir
->type
->is_array()) {
1639 const unsigned size
= type_size(ir
->type
->fields
.array
);
1641 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1642 ir
->array_elements
[i
]->accept(this);
1643 fs_reg src_reg
= this->result
;
1645 dst_reg
.type
= src_reg
.type
;
1646 for (unsigned j
= 0; j
< size
; j
++) {
1647 emit(MOV(dst_reg
, src_reg
));
1648 src_reg
.reg_offset
++;
1649 dst_reg
.reg_offset
++;
1652 } else if (ir
->type
->is_record()) {
1653 foreach_list(node
, &ir
->components
) {
1654 ir_constant
*const field
= (ir_constant
*) node
;
1655 const unsigned size
= type_size(field
->type
);
1657 field
->accept(this);
1658 fs_reg src_reg
= this->result
;
1660 dst_reg
.type
= src_reg
.type
;
1661 for (unsigned j
= 0; j
< size
; j
++) {
1662 emit(MOV(dst_reg
, src_reg
));
1663 src_reg
.reg_offset
++;
1664 dst_reg
.reg_offset
++;
1668 const unsigned size
= type_size(ir
->type
);
1670 for (unsigned i
= 0; i
< size
; i
++) {
1671 switch (ir
->type
->base_type
) {
1672 case GLSL_TYPE_FLOAT
:
1673 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1675 case GLSL_TYPE_UINT
:
1676 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1679 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1681 case GLSL_TYPE_BOOL
:
1682 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1685 assert(!"Non-float/uint/int/bool constant");
1687 dst_reg
.reg_offset
++;
1695 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1697 ir_expression
*expr
= ir
->as_expression();
1703 assert(expr
->get_num_operands() <= 2);
1704 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1705 assert(expr
->operands
[i
]->type
->is_scalar());
1707 expr
->operands
[i
]->accept(this);
1708 op
[i
] = this->result
;
1710 resolve_ud_negate(&op
[i
]);
1713 switch (expr
->operation
) {
1714 case ir_unop_logic_not
:
1715 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1716 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1719 case ir_binop_logic_xor
:
1720 case ir_binop_logic_or
:
1721 case ir_binop_logic_and
:
1725 if (intel
->gen
>= 6) {
1726 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1728 inst
= emit(MOV(reg_null_f
, op
[0]));
1729 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1734 if (intel
->gen
>= 6) {
1735 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1737 inst
= emit(MOV(reg_null_d
, op
[0]));
1738 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1742 case ir_binop_greater
:
1743 case ir_binop_gequal
:
1745 case ir_binop_lequal
:
1746 case ir_binop_equal
:
1747 case ir_binop_all_equal
:
1748 case ir_binop_nequal
:
1749 case ir_binop_any_nequal
:
1750 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1751 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1753 emit(CMP(reg_null_d
, op
[0], op
[1],
1754 brw_conditional_for_comparison(expr
->operation
)));
1758 assert(!"not reached");
1759 fail("bad cond code\n");
1768 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1769 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1773 * Emit a gen6 IF statement with the comparison folded into the IF
1777 fs_visitor::emit_if_gen6(ir_if
*ir
)
1779 ir_expression
*expr
= ir
->condition
->as_expression();
1786 assert(expr
->get_num_operands() <= 2);
1787 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1788 assert(expr
->operands
[i
]->type
->is_scalar());
1790 expr
->operands
[i
]->accept(this);
1791 op
[i
] = this->result
;
1794 switch (expr
->operation
) {
1795 case ir_unop_logic_not
:
1796 case ir_binop_logic_xor
:
1797 case ir_binop_logic_or
:
1798 case ir_binop_logic_and
:
1799 /* For operations on bool arguments, only the low bit of the bool is
1800 * valid, and the others are undefined. Fall back to the condition
1806 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1807 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1811 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1814 case ir_binop_greater
:
1815 case ir_binop_gequal
:
1817 case ir_binop_lequal
:
1818 case ir_binop_equal
:
1819 case ir_binop_all_equal
:
1820 case ir_binop_nequal
:
1821 case ir_binop_any_nequal
:
1822 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1823 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1825 emit(IF(op
[0], op
[1],
1826 brw_conditional_for_comparison(expr
->operation
)));
1829 assert(!"not reached");
1830 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1831 fail("bad condition\n");
1836 emit_bool_to_cond_code(ir
->condition
);
1837 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1838 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1842 fs_visitor::visit(ir_if
*ir
)
1844 if (intel
->gen
< 6 && dispatch_width
== 16) {
1845 fail("Can't support (non-uniform) control flow on 16-wide\n");
1848 /* Don't point the annotation at the if statement, because then it plus
1849 * the then and else blocks get printed.
1851 this->base_ir
= ir
->condition
;
1853 if (intel
->gen
== 6) {
1856 emit_bool_to_cond_code(ir
->condition
);
1858 emit(IF(BRW_PREDICATE_NORMAL
));
1861 foreach_list(node
, &ir
->then_instructions
) {
1862 ir_instruction
*ir
= (ir_instruction
*)node
;
1868 if (!ir
->else_instructions
.is_empty()) {
1869 emit(BRW_OPCODE_ELSE
);
1871 foreach_list(node
, &ir
->else_instructions
) {
1872 ir_instruction
*ir
= (ir_instruction
*)node
;
1879 emit(BRW_OPCODE_ENDIF
);
1883 fs_visitor::visit(ir_loop
*ir
)
1885 fs_reg counter
= reg_undef
;
1887 if (intel
->gen
< 6 && dispatch_width
== 16) {
1888 fail("Can't support (non-uniform) control flow on 16-wide\n");
1892 this->base_ir
= ir
->counter
;
1893 ir
->counter
->accept(this);
1894 counter
= *(variable_storage(ir
->counter
));
1897 this->base_ir
= ir
->from
;
1898 ir
->from
->accept(this);
1900 emit(MOV(counter
, this->result
));
1904 this->base_ir
= NULL
;
1905 emit(BRW_OPCODE_DO
);
1908 this->base_ir
= ir
->to
;
1909 ir
->to
->accept(this);
1911 emit(CMP(reg_null_d
, counter
, this->result
,
1912 brw_conditional_for_comparison(ir
->cmp
)));
1914 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1915 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1918 foreach_list(node
, &ir
->body_instructions
) {
1919 ir_instruction
*ir
= (ir_instruction
*)node
;
1925 if (ir
->increment
) {
1926 this->base_ir
= ir
->increment
;
1927 ir
->increment
->accept(this);
1928 emit(ADD(counter
, counter
, this->result
));
1931 this->base_ir
= NULL
;
1932 emit(BRW_OPCODE_WHILE
);
1936 fs_visitor::visit(ir_loop_jump
*ir
)
1939 case ir_loop_jump::jump_break
:
1940 emit(BRW_OPCODE_BREAK
);
1942 case ir_loop_jump::jump_continue
:
1943 emit(BRW_OPCODE_CONTINUE
);
1949 fs_visitor::visit(ir_call
*ir
)
1951 assert(!"FINISHME");
1955 fs_visitor::visit(ir_return
*ir
)
1957 assert(!"FINISHME");
1961 fs_visitor::visit(ir_function
*ir
)
1963 /* Ignore function bodies other than main() -- we shouldn't see calls to
1964 * them since they should all be inlined before we get to ir_to_mesa.
1966 if (strcmp(ir
->name
, "main") == 0) {
1967 const ir_function_signature
*sig
;
1970 sig
= ir
->matching_signature(&empty
);
1974 foreach_list(node
, &sig
->body
) {
1975 ir_instruction
*ir
= (ir_instruction
*)node
;
1984 fs_visitor::visit(ir_function_signature
*ir
)
1986 assert(!"not reached");
1991 fs_visitor::emit(fs_inst inst
)
1993 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
2000 fs_visitor::emit(fs_inst
*inst
)
2002 if (force_uncompressed_stack
> 0)
2003 inst
->force_uncompressed
= true;
2004 else if (force_sechalf_stack
> 0)
2005 inst
->force_sechalf
= true;
2007 inst
->annotation
= this->current_annotation
;
2008 inst
->ir
= this->base_ir
;
2010 this->instructions
.push_tail(inst
);
2016 fs_visitor::emit(exec_list list
)
2018 foreach_list_safe(node
, &list
) {
2019 fs_inst
*inst
= (fs_inst
*)node
;
2025 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2027 fs_visitor::emit_dummy_fs()
2029 int reg_width
= dispatch_width
/ 8;
2031 /* Everyone's favorite color. */
2032 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2033 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2034 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2035 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2038 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2039 write
->base_mrf
= 2;
2040 write
->mlen
= 4 * reg_width
;
2044 /* The register location here is relative to the start of the URB
2045 * data. It will get adjusted to be a real location before
2046 * generate_code() time.
2049 fs_visitor::interp_reg(int location
, int channel
)
2051 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
2052 int stride
= (channel
& 1) * 4;
2054 assert(urb_setup
[location
] != -1);
2056 return brw_vec1_grf(regnr
, stride
);
2059 /** Emits the interpolation for the varying inputs. */
2061 fs_visitor::emit_interpolation_setup_gen4()
2063 this->current_annotation
= "compute pixel centers";
2064 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2065 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2066 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2067 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2069 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2070 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2072 this->current_annotation
= "compute pixel deltas from v0";
2074 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2075 fs_reg(this, glsl_type::vec2_type
);
2076 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2077 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2078 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2080 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2081 fs_reg(this, glsl_type::float_type
);
2082 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2083 fs_reg(this, glsl_type::float_type
);
2085 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2086 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2087 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2088 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2090 this->current_annotation
= "compute pos.w and 1/pos.w";
2091 /* Compute wpos.w. It's always in our setup, since it's needed to
2092 * interpolate the other attributes.
2094 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2095 emit(FS_OPCODE_LINTERP
, wpos_w
,
2096 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2097 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2098 interp_reg(VARYING_SLOT_POS
, 3));
2099 /* Compute the pixel 1/W value from wpos.w. */
2100 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2101 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2102 this->current_annotation
= NULL
;
2105 /** Emits the interpolation for the varying inputs. */
2107 fs_visitor::emit_interpolation_setup_gen6()
2109 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2111 /* If the pixel centers end up used, the setup is the same as for gen4. */
2112 this->current_annotation
= "compute pixel centers";
2113 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2114 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2115 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2116 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2117 emit(ADD(int_pixel_x
,
2118 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2119 fs_reg(brw_imm_v(0x10101010))));
2120 emit(ADD(int_pixel_y
,
2121 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2122 fs_reg(brw_imm_v(0x11001100))));
2124 /* As of gen6, we can no longer mix float and int sources. We have
2125 * to turn the integer pixel centers into floats for their actual
2128 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2129 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2130 emit(MOV(this->pixel_x
, int_pixel_x
));
2131 emit(MOV(this->pixel_y
, int_pixel_y
));
2133 this->current_annotation
= "compute pos.w";
2134 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2135 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2136 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2138 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2139 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2140 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2141 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2144 this->current_annotation
= NULL
;
2148 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2150 int reg_width
= dispatch_width
/ 8;
2152 fs_reg color
= outputs
[target
];
2155 /* If there's no color data to be written, skip it. */
2156 if (color
.file
== BAD_FILE
)
2159 color
.reg_offset
+= index
;
2161 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2162 /* SIMD8 write looks like:
2168 * gen6 SIMD16 DP write looks like:
2178 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2181 inst
->saturate
= c
->key
.clamp_fragment_color
;
2183 /* pre-gen6 SIMD16 single source DP write looks like:
2193 if (brw
->has_compr4
) {
2194 /* By setting the high bit of the MRF register number, we
2195 * indicate that we want COMPR4 mode - instead of doing the
2196 * usual destination + 1 for the second half we get
2199 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2202 inst
->saturate
= c
->key
.clamp_fragment_color
;
2204 push_force_uncompressed();
2205 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2207 inst
->saturate
= c
->key
.clamp_fragment_color
;
2208 pop_force_uncompressed();
2210 push_force_sechalf();
2211 color
.sechalf
= true;
2212 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2214 inst
->saturate
= c
->key
.clamp_fragment_color
;
2215 pop_force_sechalf();
2216 color
.sechalf
= false;
2222 fs_visitor::emit_fb_writes()
2224 this->current_annotation
= "FB write header";
2225 bool header_present
= true;
2226 /* We can potentially have a message length of up to 15, so we have to set
2227 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2231 int reg_width
= dispatch_width
/ 8;
2232 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2233 bool src0_alpha_to_render_target
= false;
2235 if (dispatch_width
== 16 && do_dual_src
) {
2236 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2237 do_dual_src
= false;
2240 /* From the Sandy Bridge PRM, volume 4, page 198:
2242 * "Dispatched Pixel Enables. One bit per pixel indicating
2243 * which pixels were originally enabled when the thread was
2244 * dispatched. This field is only required for the end-of-
2245 * thread message and on all dual-source messages."
2247 if (intel
->gen
>= 6 &&
2248 !this->fp
->UsesKill
&&
2250 c
->key
.nr_color_regions
== 1) {
2251 header_present
= false;
2254 if (header_present
) {
2255 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2257 c
->key
.replicate_alpha
;
2262 if (c
->aa_dest_stencil_reg
) {
2263 push_force_uncompressed();
2264 emit(MOV(fs_reg(MRF
, nr
++),
2265 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2266 pop_force_uncompressed();
2269 /* Reserve space for color. It'll be filled in per MRT below. */
2271 nr
+= 4 * reg_width
;
2274 if (src0_alpha_to_render_target
)
2277 if (c
->source_depth_to_render_target
) {
2278 if (intel
->gen
== 6 && dispatch_width
== 16) {
2279 /* For outputting oDepth on gen6, SIMD8 writes have to be
2280 * used. This would require 8-wide moves of each half to
2281 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2282 * Just bail on doing so for now.
2284 fail("Missing support for simd16 depth writes on gen6\n");
2287 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2288 /* Hand over gl_FragDepth. */
2289 assert(this->frag_depth
.file
!= BAD_FILE
);
2290 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2292 /* Pass through the payload depth. */
2293 emit(MOV(fs_reg(MRF
, nr
),
2294 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2299 if (c
->dest_depth_reg
) {
2300 emit(MOV(fs_reg(MRF
, nr
),
2301 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2306 fs_reg src0
= this->outputs
[0];
2307 fs_reg src1
= this->dual_src_output
;
2309 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2311 for (int i
= 0; i
< 4; i
++) {
2312 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2314 inst
->saturate
= c
->key
.clamp_fragment_color
;
2317 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2319 for (int i
= 0; i
< 4; i
++) {
2320 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2323 inst
->saturate
= c
->key
.clamp_fragment_color
;
2326 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2327 emit_shader_time_end();
2329 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2331 inst
->base_mrf
= base_mrf
;
2332 inst
->mlen
= nr
- base_mrf
;
2334 inst
->header_present
= header_present
;
2336 c
->prog_data
.dual_src_blend
= true;
2337 this->current_annotation
= NULL
;
2341 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2342 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2343 "FB write target %d",
2345 /* If src0_alpha_to_render_target is true, include source zero alpha
2346 * data in RenderTargetWrite message for targets > 0.
2348 int write_color_mrf
= color_mrf
;
2349 if (src0_alpha_to_render_target
&& target
!= 0) {
2351 fs_reg color
= outputs
[0];
2352 color
.reg_offset
+= 3;
2354 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2356 inst
->saturate
= c
->key
.clamp_fragment_color
;
2357 write_color_mrf
= color_mrf
+ reg_width
;
2360 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2361 emit_color_write(target
, i
, write_color_mrf
);
2364 if (target
== c
->key
.nr_color_regions
- 1) {
2367 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2368 emit_shader_time_end();
2371 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2372 inst
->target
= target
;
2373 inst
->base_mrf
= base_mrf
;
2374 if (src0_alpha_to_render_target
&& target
== 0)
2375 inst
->mlen
= nr
- base_mrf
- reg_width
;
2377 inst
->mlen
= nr
- base_mrf
;
2379 inst
->header_present
= header_present
;
2382 if (c
->key
.nr_color_regions
== 0) {
2383 /* Even if there's no color buffers enabled, we still need to send
2384 * alpha out the pipeline to our null renderbuffer to support
2385 * alpha-testing, alpha-to-coverage, and so on.
2387 emit_color_write(0, 3, color_mrf
);
2389 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2390 emit_shader_time_end();
2392 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2393 inst
->base_mrf
= base_mrf
;
2394 inst
->mlen
= nr
- base_mrf
;
2396 inst
->header_present
= header_present
;
2399 this->current_annotation
= NULL
;
2403 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2405 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2409 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2410 emit(MOV(temp
, *reg
));
2415 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2417 if (rvalue
->type
!= glsl_type::bool_type
)
2420 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2421 emit(AND(temp
, *reg
, fs_reg(1)));
2425 fs_visitor::fs_visitor(struct brw_context
*brw
,
2426 struct brw_wm_compile
*c
,
2427 struct gl_shader_program
*shader_prog
,
2428 struct gl_fragment_program
*fp
,
2429 unsigned dispatch_width
)
2430 : dispatch_width(dispatch_width
)
2435 this->shader_prog
= shader_prog
;
2436 this->intel
= &brw
->intel
;
2437 this->ctx
= &intel
->ctx
;
2438 this->mem_ctx
= ralloc_context(NULL
);
2440 shader
= (struct brw_shader
*)
2441 shader_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2444 this->failed
= false;
2445 this->variable_ht
= hash_table_ctor(0,
2446 hash_table_pointer_hash
,
2447 hash_table_pointer_compare
);
2449 memset(this->outputs
, 0, sizeof(this->outputs
));
2450 memset(this->output_components
, 0, sizeof(this->output_components
));
2451 this->first_non_payload_grf
= 0;
2452 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2454 this->current_annotation
= NULL
;
2455 this->base_ir
= NULL
;
2457 this->virtual_grf_sizes
= NULL
;
2458 this->virtual_grf_count
= 0;
2459 this->virtual_grf_array_size
= 0;
2460 this->virtual_grf_start
= NULL
;
2461 this->virtual_grf_end
= NULL
;
2462 this->live_intervals_valid
= false;
2464 this->params_remap
= NULL
;
2465 this->nr_params_remap
= 0;
2467 this->force_uncompressed_stack
= 0;
2468 this->force_sechalf_stack
= 0;
2470 memset(&this->param_size
, 0, sizeof(this->param_size
));
2473 fs_visitor::~fs_visitor()
2475 ralloc_free(this->mem_ctx
);
2476 hash_table_dtor(this->variable_ht
);