2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
82 fs_reg coordinate
, int coord_components
,
84 fs_reg lod
, fs_reg dPdy
, int grad_components
,
95 if (shadow_c
.file
!= BAD_FILE
) {
96 for (int i
= 0; i
< coord_components
; i
++) {
97 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
98 coordinate
= offset(coordinate
, 1);
101 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
102 * the unused slots must be zeroed.
104 for (int i
= coord_components
; i
< 3; i
++) {
105 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
110 /* There's no plain shadow compare message, so we use shadow
111 * compare with a bias of 0.0.
113 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
115 } else if (op
== ir_txb
|| op
== ir_txl
) {
116 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
);
119 unreachable("Should not get here.");
122 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
124 } else if (op
== ir_tex
) {
125 for (int i
= 0; i
< coord_components
; i
++) {
126 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
127 coordinate
= offset(coordinate
, 1);
129 /* zero the others. */
130 for (int i
= coord_components
; i
<3; i
++) {
131 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
133 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
135 } else if (op
== ir_txd
) {
138 for (int i
= 0; i
< coord_components
; i
++) {
139 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
140 coordinate
= offset(coordinate
, 1);
142 /* the slots for u and v are always present, but r is optional */
143 mlen
+= MAX2(coord_components
, 2);
146 * dPdx = dudx, dvdx, drdx
147 * dPdy = dudy, dvdy, drdy
149 * 1-arg: Does not exist.
151 * 2-arg: dudx dvdx dudy dvdy
152 * dPdx.x dPdx.y dPdy.x dPdy.y
155 * 3-arg: dudx dvdx drdx dudy dvdy drdy
156 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
159 for (int i
= 0; i
< grad_components
; i
++) {
160 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
161 dPdx
= offset(dPdx
, 1);
163 mlen
+= MAX2(grad_components
, 2);
165 for (int i
= 0; i
< grad_components
; i
++) {
166 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
167 dPdy
= offset(dPdy
, 1);
169 mlen
+= MAX2(grad_components
, 2);
170 } else if (op
== ir_txs
) {
171 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
173 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
176 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
177 * instructions. We'll need to do SIMD16 here.
180 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
182 for (int i
= 0; i
< coord_components
; i
++) {
183 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
185 coordinate
= offset(coordinate
, 1);
188 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
189 * be necessary for TXF (ld), but seems wise to do for all messages.
191 for (int i
= coord_components
; i
< 3; i
++) {
192 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
195 /* lod/bias appears after u/v/r. */
198 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
);
201 /* The unused upper half. */
206 /* Now, since we're doing simd16, the return is 2 interleaved
207 * vec4s where the odd-indexed ones are junk. We'll need to move
208 * this weirdness around to the expected layout.
211 dst
= fs_reg(GRF
, alloc
.allocate(8), orig_dst
.type
);
216 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
217 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
218 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
219 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
220 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
221 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
223 unreachable("not reached");
226 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
227 inst
->base_mrf
= base_mrf
;
229 inst
->header_size
= 1;
230 inst
->regs_written
= simd16
? 8 : 4;
233 for (int i
= 0; i
< 4; i
++) {
234 bld
.MOV(orig_dst
, dst
);
235 orig_dst
= offset(orig_dst
, 1);
236 dst
= offset(dst
, 2);
244 fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op
, fs_reg dst
,
245 fs_reg coordinate
, int vector_elements
,
246 fs_reg shadow_c
, fs_reg lod
,
249 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
250 bool has_lod
= op
== ir_txl
|| op
== ir_txb
|| op
== ir_txf
|| op
== ir_txs
;
252 if (has_lod
&& shadow_c
.file
!= BAD_FILE
)
253 no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
256 no16("textureGrad unsupported in SIMD16.");
258 /* Copy the coordinates. */
259 for (int i
= 0; i
< vector_elements
; i
++) {
260 bld
.MOV(retype(offset(message
, i
), coordinate
.type
), coordinate
);
261 coordinate
= offset(coordinate
, 1);
264 fs_reg msg_end
= offset(message
, vector_elements
);
266 /* Messages other than sample and ld require all three components */
267 if (vector_elements
> 0 && (has_lod
|| shadow_c
.file
!= BAD_FILE
)) {
268 for (int i
= vector_elements
; i
< 3; i
++) {
269 bld
.MOV(offset(message
, i
), fs_reg(0.0f
));
271 msg_end
= offset(message
, 3);
275 fs_reg msg_lod
= retype(msg_end
, op
== ir_txf
?
276 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
277 bld
.MOV(msg_lod
, lod
);
278 msg_end
= offset(msg_lod
, 1);
281 if (shadow_c
.file
!= BAD_FILE
) {
282 fs_reg msg_ref
= offset(message
, 3 + has_lod
);
283 bld
.MOV(msg_ref
, shadow_c
);
284 msg_end
= offset(msg_ref
, 1);
289 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
290 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
291 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
292 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
293 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
294 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
295 default: unreachable("not reached");
298 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
299 inst
->base_mrf
= message
.reg
- 1;
300 inst
->mlen
= msg_end
.reg
- inst
->base_mrf
;
301 inst
->header_size
= 1;
302 inst
->regs_written
= 8;
307 /* gen5's sampler has slots for u, v, r, array index, then optional
308 * parameters like shadow comparitor or LOD bias. If optional
309 * parameters aren't present, those base slots are optional and don't
310 * need to be included in the message.
312 * We don't fill in the unnecessary slots regardless, which may look
313 * surprising in the disassembly.
316 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
317 fs_reg coordinate
, int vector_elements
,
319 fs_reg lod
, fs_reg lod2
, int grad_components
,
320 fs_reg sample_index
, uint32_t sampler
,
323 int reg_width
= dispatch_width
/ 8;
324 unsigned header_size
= 0;
326 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
327 fs_reg msg_coords
= message
;
330 /* The offsets set up by the ir_texture visitor are in the
331 * m1 header, so we can't go headerless.
337 for (int i
= 0; i
< vector_elements
; i
++) {
338 bld
.MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
);
339 coordinate
= offset(coordinate
, 1);
341 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
342 fs_reg msg_lod
= offset(msg_coords
, 4);
344 if (shadow_c
.file
!= BAD_FILE
) {
345 fs_reg msg_shadow
= msg_lod
;
346 bld
.MOV(msg_shadow
, shadow_c
);
347 msg_lod
= offset(msg_shadow
, 1);
354 opcode
= SHADER_OPCODE_TEX
;
357 bld
.MOV(msg_lod
, lod
);
358 msg_end
= offset(msg_lod
, 1);
360 opcode
= FS_OPCODE_TXB
;
363 bld
.MOV(msg_lod
, lod
);
364 msg_end
= offset(msg_lod
, 1);
366 opcode
= SHADER_OPCODE_TXL
;
371 * dPdx = dudx, dvdx, drdx
372 * dPdy = dudy, dvdy, drdy
374 * Load up these values:
375 * - dudx dudy dvdx dvdy drdx drdy
376 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
379 for (int i
= 0; i
< grad_components
; i
++) {
380 bld
.MOV(msg_end
, lod
);
381 lod
= offset(lod
, 1);
382 msg_end
= offset(msg_end
, 1);
384 bld
.MOV(msg_end
, lod2
);
385 lod2
= offset(lod2
, 1);
386 msg_end
= offset(msg_end
, 1);
389 opcode
= SHADER_OPCODE_TXD
;
393 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
394 bld
.MOV(msg_lod
, lod
);
395 msg_end
= offset(msg_lod
, 1);
397 opcode
= SHADER_OPCODE_TXS
;
399 case ir_query_levels
:
401 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
402 msg_end
= offset(msg_lod
, 1);
404 opcode
= SHADER_OPCODE_TXS
;
407 msg_lod
= offset(msg_coords
, 3);
408 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
409 msg_end
= offset(msg_lod
, 1);
411 opcode
= SHADER_OPCODE_TXF
;
414 msg_lod
= offset(msg_coords
, 3);
416 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
418 bld
.MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
419 msg_end
= offset(msg_lod
, 2);
421 opcode
= SHADER_OPCODE_TXF_CMS
;
424 opcode
= SHADER_OPCODE_LOD
;
427 opcode
= SHADER_OPCODE_TG4
;
430 unreachable("not reached");
433 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
434 inst
->base_mrf
= message
.reg
;
435 inst
->mlen
= msg_end
.reg
- message
.reg
;
436 inst
->header_size
= header_size
;
437 inst
->regs_written
= 4 * reg_width
;
439 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
440 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
441 " disallowed by hardware\n");
448 is_high_sampler(const struct brw_device_info
*devinfo
, fs_reg sampler
)
450 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
453 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
457 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
458 fs_reg coordinate
, int coord_components
,
460 fs_reg lod
, fs_reg lod2
, int grad_components
,
461 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
464 int reg_width
= dispatch_width
/ 8;
465 unsigned header_size
= 0;
467 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
468 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
469 sources
[i
] = vgrf(glsl_type::float_type
);
473 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
474 is_high_sampler(devinfo
, sampler
)) {
475 /* For general texture offsets (no txf workaround), we need a header to
476 * put them in. Note that for SIMD16 we're making space for two actual
477 * hardware registers here, so the emit will have to fix up for this.
479 * * ir4_tg4 needs to place its channel select in the header,
480 * for interaction with ARB_texture_swizzle
482 * The sampler index is only 4-bits, so for larger sampler numbers we
483 * need to offset the Sampler State Pointer in the header.
486 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
490 if (shadow_c
.file
!= BAD_FILE
) {
491 bld
.MOV(sources
[length
], shadow_c
);
495 bool has_nonconstant_offset
=
496 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
497 bool coordinate_done
= false;
499 /* The sampler can only meaningfully compute LOD for fragment shader
500 * messages. For all other stages, we change the opcode to ir_txl and
501 * hardcode the LOD to 0.
503 if (stage
!= MESA_SHADER_FRAGMENT
&& op
== ir_tex
) {
508 /* Set up the LOD info */
514 bld
.MOV(sources
[length
], lod
);
518 bld
.MOV(sources
[length
], lod
);
522 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
524 /* Load dPdx and the coordinate together:
525 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
527 for (int i
= 0; i
< coord_components
; i
++) {
528 bld
.MOV(sources
[length
], coordinate
);
529 coordinate
= offset(coordinate
, 1);
532 /* For cube map array, the coordinate is (u,v,r,ai) but there are
533 * only derivatives for (u, v, r).
535 if (i
< grad_components
) {
536 bld
.MOV(sources
[length
], lod
);
537 lod
= offset(lod
, 1);
540 bld
.MOV(sources
[length
], lod2
);
541 lod2
= offset(lod2
, 1);
546 coordinate_done
= true;
550 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
553 case ir_query_levels
:
554 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u));
558 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
559 * On Gen9 they are u, v, lod, r
562 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
563 coordinate
= offset(coordinate
, 1);
566 if (devinfo
->gen
>= 9) {
567 if (coord_components
>= 2) {
568 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
569 coordinate
= offset(coordinate
, 1);
574 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
577 for (int i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
578 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
579 coordinate
= offset(coordinate
, 1);
583 coordinate_done
= true;
586 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
589 /* data from the multisample control surface */
590 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
593 /* there is no offsetting for this message; just copy in the integer
594 * texture coordinates
596 for (int i
= 0; i
< coord_components
; i
++) {
597 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
598 coordinate
= offset(coordinate
, 1);
602 coordinate_done
= true;
605 if (has_nonconstant_offset
) {
606 if (shadow_c
.file
!= BAD_FILE
)
607 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
609 /* More crazy intermixing */
610 for (int i
= 0; i
< 2; i
++) { /* u, v */
611 bld
.MOV(sources
[length
], coordinate
);
612 coordinate
= offset(coordinate
, 1);
616 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
617 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
618 offset_value
= offset(offset_value
, 1);
622 if (coord_components
== 3) { /* r if present */
623 bld
.MOV(sources
[length
], coordinate
);
624 coordinate
= offset(coordinate
, 1);
628 coordinate_done
= true;
633 /* Set up the coordinate (except for cases where it was done above) */
634 if (!coordinate_done
) {
635 for (int i
= 0; i
< coord_components
; i
++) {
636 bld
.MOV(sources
[length
], coordinate
);
637 coordinate
= offset(coordinate
, 1);
644 mlen
= length
* reg_width
- header_size
;
646 mlen
= length
* reg_width
;
648 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
649 BRW_REGISTER_TYPE_F
, dispatch_width
);
650 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
652 /* Generate the SEND */
655 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
656 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
657 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
658 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
659 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
660 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
661 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
662 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
663 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
665 if (has_nonconstant_offset
)
666 opcode
= SHADER_OPCODE_TG4_OFFSET
;
668 opcode
= SHADER_OPCODE_TG4
;
671 unreachable("not reached");
673 fs_inst
*inst
= bld
.emit(opcode
, dst
, src_payload
, sampler
);
676 inst
->header_size
= header_size
;
677 inst
->regs_written
= 4 * reg_width
;
679 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
680 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
681 " disallowed by hardware\n");
688 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
689 bool is_rect
, uint32_t sampler
, int texunit
)
691 bool needs_gl_clamp
= true;
692 fs_reg scale_x
, scale_y
;
694 /* The 965 requires the EU to do the normalization of GL rectangle
695 * texture coordinates. We use the program parameter state
696 * tracking to get the scaling factor.
700 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
701 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
702 struct gl_program_parameter_list
*params
= prog
->Parameters
;
703 int tokens
[STATE_LENGTH
] = {
711 no16("rectangle scale uniform setup not supported on SIMD16\n");
712 if (dispatch_width
== 16) {
716 GLuint index
= _mesa_add_state_reference(params
,
717 (gl_state_index
*)tokens
);
718 /* Try to find existing copies of the texrect scale uniforms. */
719 for (unsigned i
= 0; i
< uniforms
; i
++) {
720 if (stage_prog_data
->param
[i
] ==
721 &prog
->Parameters
->ParameterValues
[index
][0]) {
722 scale_x
= fs_reg(UNIFORM
, i
);
723 scale_y
= fs_reg(UNIFORM
, i
+ 1);
728 /* If we didn't already set them up, do so now. */
729 if (scale_x
.file
== BAD_FILE
) {
730 scale_x
= fs_reg(UNIFORM
, uniforms
);
731 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
733 stage_prog_data
->param
[uniforms
++] =
734 &prog
->Parameters
->ParameterValues
[index
][0];
735 stage_prog_data
->param
[uniforms
++] =
736 &prog
->Parameters
->ParameterValues
[index
][1];
740 /* The 965 requires the EU to do the normalization of GL rectangle
741 * texture coordinates. We use the program parameter state
742 * tracking to get the scaling factor.
744 if (devinfo
->gen
< 6 && is_rect
) {
745 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
746 fs_reg src
= coordinate
;
749 bld
.MUL(dst
, src
, scale_x
);
750 dst
= offset(dst
, 1);
751 src
= offset(src
, 1);
752 bld
.MUL(dst
, src
, scale_y
);
753 } else if (is_rect
) {
754 /* On gen6+, the sampler handles the rectangle coordinates
755 * natively, without needing rescaling. But that means we have
756 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
757 * not [0, 1] like the default case below.
759 needs_gl_clamp
= false;
761 for (int i
= 0; i
< 2; i
++) {
762 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
763 fs_reg chan
= coordinate
;
764 chan
= offset(chan
, i
);
766 set_condmod(BRW_CONDITIONAL_GE
,
767 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
769 /* Our parameter comes in as 1.0/width or 1.0/height,
770 * because that's what people normally want for doing
771 * texture rectangle handling. We need width or height
772 * for clamping, but we don't care enough to make a new
773 * parameter type, so just invert back.
775 fs_reg limit
= vgrf(glsl_type::float_type
);
776 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
777 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
779 set_condmod(BRW_CONDITIONAL_L
,
780 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
785 if (coord_components
> 0 && needs_gl_clamp
) {
786 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
787 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
788 fs_reg chan
= coordinate
;
789 chan
= offset(chan
, i
);
790 set_saturate(true, bld
.MOV(chan
, chan
));
797 /* Sample from the MCS surface attached to this multisample texture. */
799 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
801 int reg_width
= dispatch_width
/ 8;
802 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(components
* reg_width
),
803 BRW_REGISTER_TYPE_F
, dispatch_width
);
804 fs_reg dest
= vgrf(glsl_type::uvec4_type
);
805 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
807 /* parameters are: u, v, r; missing parameters are treated as zero */
808 for (int i
= 0; i
< components
; i
++) {
809 sources
[i
] = vgrf(glsl_type::float_type
);
810 bld
.MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
);
811 coordinate
= offset(coordinate
, 1);
814 bld
.LOAD_PAYLOAD(payload
, sources
, components
, 0);
816 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
818 inst
->mlen
= components
* reg_width
;
819 inst
->header_size
= 0;
820 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
821 * response, but the sampler always
829 fs_visitor::emit_texture(ir_texture_opcode op
,
830 const glsl_type
*dest_type
,
831 fs_reg coordinate
, int coord_components
,
833 fs_reg lod
, fs_reg lod2
, int grad_components
,
837 int gather_component
,
841 fs_reg sampler_reg
, int texunit
)
843 fs_inst
*inst
= NULL
;
846 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
847 * emitting anything other than setting up the constant result.
849 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
850 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
852 fs_reg res
= vgrf(glsl_type::vec4_type
);
855 for (int i
=0; i
<4; i
++) {
856 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
857 res
= offset(res
, 1);
863 if (coordinate
.file
!= BAD_FILE
) {
864 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
865 * samplers. This should only be a problem with GL_CLAMP on Gen7.
867 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
871 /* Writemasking doesn't eliminate channels on SIMD8 texture
872 * samples, so don't worry about them.
874 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
876 if (devinfo
->gen
>= 7) {
877 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
878 shadow_c
, lod
, lod2
, grad_components
,
879 sample_index
, mcs
, sampler_reg
,
881 } else if (devinfo
->gen
>= 5) {
882 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
883 shadow_c
, lod
, lod2
, grad_components
,
884 sample_index
, sampler
,
885 offset_value
.file
!= BAD_FILE
);
886 } else if (dispatch_width
== 16) {
887 inst
= emit_texture_gen4_simd16(op
, dst
, coordinate
, coord_components
,
888 shadow_c
, lod
, sampler
);
890 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
891 shadow_c
, lod
, lod2
, grad_components
,
895 if (shadow_c
.file
!= BAD_FILE
)
896 inst
->shadow_compare
= true;
898 if (offset_value
.file
== IMM
)
899 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
903 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
905 if (devinfo
->gen
== 6)
906 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
909 /* fixup #layers for cube map arrays */
910 if (op
== ir_txs
&& is_cube_array
) {
911 fs_reg depth
= offset(dst
, 2);
912 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
913 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
915 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
916 int components
= inst
->regs_written
/ (dst
.width
/ 8);
917 for (int i
= 0; i
< components
; i
++) {
919 fixed_payload
[i
] = fixed_depth
;
921 fixed_payload
[i
] = offset(dst
, i
);
924 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
927 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
931 * Apply workarounds for Gen6 gather with UINT/SINT
934 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
939 int width
= (wa
& WA_8BIT
) ? 8 : 16;
941 for (int i
= 0; i
< 4; i
++) {
942 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
943 /* Convert from UNORM to UINT */
944 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
948 /* Reinterpret the UINT value as a signed INT value by
949 * shifting the sign bit into place, then shifting back
952 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
953 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
956 dst
= offset(dst
, 1);
961 * Set up the gather channel based on the swizzle, for gather4.
964 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
966 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
968 case SWIZZLE_X
: return 0;
970 /* gather4 sampler is broken for green channel on RG32F --
971 * we must ask for blue instead.
973 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
976 case SWIZZLE_Z
: return 2;
977 case SWIZZLE_W
: return 3;
979 unreachable("Not reached"); /* zero, one swizzles handled already */
984 * Swizzle the result of a texture result. This is necessary for
985 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
988 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
989 fs_reg orig_val
, uint32_t sampler
)
991 if (op
== ir_query_levels
) {
992 /* # levels is in .w */
993 this->result
= offset(orig_val
, 3);
997 this->result
= orig_val
;
999 /* txs,lod don't actually sample the texture, so swizzling the result
1002 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
1005 if (dest_components
== 1) {
1006 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1007 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
1008 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
1009 swizzled_result
.type
= orig_val
.type
;
1011 for (int i
= 0; i
< 4; i
++) {
1012 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
1013 fs_reg l
= swizzled_result
;
1016 if (swiz
== SWIZZLE_ZERO
) {
1017 bld
.MOV(l
, fs_reg(0.0f
));
1018 } else if (swiz
== SWIZZLE_ONE
) {
1019 bld
.MOV(l
, fs_reg(1.0f
));
1021 bld
.MOV(l
, offset(orig_val
,
1022 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
1025 this->result
= swizzled_result
;
1030 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1032 * Many GLSL shaders contain the following pattern:
1034 * x = condition ? foo : bar
1036 * The compiler emits an ir_if tree for this, since each subexpression might be
1037 * a complex tree that could have side-effects or short-circuit logic.
1039 * However, the common case is to simply select one of two constants or
1040 * variable values---which is exactly what SEL is for. In this case, the
1041 * assembly looks like:
1049 * which can be easily translated into:
1051 * (+f0) SEL dst src0 src1
1053 * If src0 is an immediate value, we promote it to a temporary GRF.
1056 fs_visitor::try_replace_with_sel()
1058 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
1059 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
1061 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1063 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
1066 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
1067 for (int i
= 0; i
< 4; i
++) {
1068 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
1070 match
= (fs_inst
*) match
->prev
;
1073 /* The opcodes match; it looks like the right sequence of instructions. */
1074 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
1075 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
1076 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
1078 /* Check that the MOVs are the right form. */
1079 if (then_mov
->dst
.equals(else_mov
->dst
) &&
1080 !then_mov
->is_partial_write() &&
1081 !else_mov
->is_partial_write()) {
1083 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1084 while (!if_inst
->next
->is_tail_sentinel())
1085 if_inst
->next
->exec_node::remove();
1086 if_inst
->exec_node::remove();
1088 /* Only the last source register can be a constant, so if the MOV in
1089 * the "then" clause uses a constant, we need to put it in a temporary.
1091 fs_reg
src0(then_mov
->src
[0]);
1092 if (src0
.file
== IMM
) {
1093 src0
= vgrf(glsl_type::float_type
);
1094 src0
.type
= then_mov
->src
[0].type
;
1095 bld
.MOV(src0
, then_mov
->src
[0]);
1098 if (if_inst
->conditional_mod
) {
1099 /* Sandybridge-specific IF with embedded comparison */
1100 bld
.CMP(bld
.null_reg_d(), if_inst
->src
[0], if_inst
->src
[1],
1101 if_inst
->conditional_mod
);
1102 set_predicate(BRW_PREDICATE_NORMAL
,
1103 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1104 src0
, else_mov
->src
[0]));
1106 /* Separate CMP and IF instructions */
1107 set_predicate_inv(if_inst
->predicate
, if_inst
->predicate_inverse
,
1108 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1109 src0
, else_mov
->src
[0]));
1119 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
1120 fs_reg dst
, fs_reg offset
, fs_reg src0
,
1123 int reg_width
= dispatch_width
/ 8;
1126 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
1128 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1129 /* Initialize the sample mask in the message header. */
1130 bld
.exec_all().MOV(sources
[0], fs_reg(0u));
1132 if (stage
== MESA_SHADER_FRAGMENT
) {
1133 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1135 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1138 .MOV(component(sources
[0], 7),
1139 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1142 /* The execution mask is part of the side-band information sent together with
1143 * the message payload to the data port. It's implicitly ANDed with the sample
1144 * mask sent in the header to compute the actual set of channels that execute
1145 * the atomic operation.
1147 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1149 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1153 /* Set the atomic operation offset. */
1154 sources
[1] = vgrf(glsl_type::uint_type
);
1155 bld
.MOV(sources
[1], offset
);
1158 /* Set the atomic operation arguments. */
1159 if (src0
.file
!= BAD_FILE
) {
1160 sources
[length
] = vgrf(glsl_type::uint_type
);
1161 bld
.MOV(sources
[length
], src0
);
1165 if (src1
.file
!= BAD_FILE
) {
1166 sources
[length
] = vgrf(glsl_type::uint_type
);
1167 bld
.MOV(sources
[length
], src1
);
1171 int mlen
= 1 + (length
- 1) * reg_width
;
1172 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1173 BRW_REGISTER_TYPE_UD
, dispatch_width
);
1174 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, 1);
1176 /* Emit the instruction. */
1177 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
1178 fs_reg(surf_index
), fs_reg(atomic_op
));
1183 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
1186 int reg_width
= dispatch_width
/ 8;
1188 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1190 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1191 /* Initialize the sample mask in the message header. */
1193 .MOV(sources
[0], fs_reg(0u));
1195 if (stage
== MESA_SHADER_FRAGMENT
) {
1196 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1198 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1201 .MOV(component(sources
[0], 7),
1202 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1205 /* The execution mask is part of the side-band information sent together with
1206 * the message payload to the data port. It's implicitly ANDed with the sample
1207 * mask sent in the header to compute the actual set of channels that execute
1208 * the atomic operation.
1210 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1212 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1215 /* Set the surface read offset. */
1216 sources
[1] = vgrf(glsl_type::uint_type
);
1217 bld
.MOV(sources
[1], offset
);
1219 int mlen
= 1 + reg_width
;
1220 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1221 BRW_REGISTER_TYPE_UD
, dispatch_width
);
1222 fs_inst
*inst
= bld
.LOAD_PAYLOAD(src_payload
, sources
, 2, 1);
1224 /* Emit the instruction. */
1225 inst
= bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
1226 fs_reg(surf_index
), fs_reg(1));
1230 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1232 fs_visitor::emit_dummy_fs()
1234 int reg_width
= dispatch_width
/ 8;
1236 /* Everyone's favorite color. */
1237 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
1238 for (int i
= 0; i
< 4; i
++) {
1239 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
,
1240 dispatch_width
), fs_reg(color
[i
]));
1244 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
1246 if (devinfo
->gen
>= 6) {
1247 write
->base_mrf
= 2;
1248 write
->mlen
= 4 * reg_width
;
1250 write
->header_size
= 2;
1251 write
->base_mrf
= 0;
1252 write
->mlen
= 2 + 4 * reg_width
;
1255 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
1256 * varying to avoid GPU hangs, so set that.
1258 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1259 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
1260 memset(wm_prog_data
->urb_setup
, -1,
1261 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1263 /* We don't have any uniforms. */
1264 stage_prog_data
->nr_params
= 0;
1265 stage_prog_data
->nr_pull_params
= 0;
1266 stage_prog_data
->curb_read_length
= 0;
1267 stage_prog_data
->dispatch_grf_start_reg
= 2;
1268 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
1269 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
1274 /* The register location here is relative to the start of the URB
1275 * data. It will get adjusted to be a real location before
1276 * generate_code() time.
1279 fs_visitor::interp_reg(int location
, int channel
)
1281 assert(stage
== MESA_SHADER_FRAGMENT
);
1282 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1283 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
1284 int stride
= (channel
& 1) * 4;
1286 assert(prog_data
->urb_setup
[location
] != -1);
1288 return brw_vec1_grf(regnr
, stride
);
1291 /** Emits the interpolation for the varying inputs. */
1293 fs_visitor::emit_interpolation_setup_gen4()
1295 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1297 fs_builder abld
= bld
.annotate("compute pixel centers");
1298 this->pixel_x
= vgrf(glsl_type::uint_type
);
1299 this->pixel_y
= vgrf(glsl_type::uint_type
);
1300 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1301 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1302 abld
.ADD(this->pixel_x
,
1303 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1304 fs_reg(brw_imm_v(0x10101010)));
1305 abld
.ADD(this->pixel_y
,
1306 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1307 fs_reg(brw_imm_v(0x11001100)));
1309 abld
= bld
.annotate("compute pixel deltas from v0");
1311 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1312 vgrf(glsl_type::vec2_type
);
1313 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1314 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
1315 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
1317 if (devinfo
->has_pln
&& dispatch_width
== 16) {
1318 for (unsigned i
= 0; i
< 2; i
++) {
1319 abld
.half(i
).ADD(half(offset(delta_xy
, i
), 0),
1320 half(this->pixel_x
, i
), xstart
);
1321 abld
.half(i
).ADD(half(offset(delta_xy
, i
), 1),
1322 half(this->pixel_y
, i
), ystart
);
1325 abld
.ADD(offset(delta_xy
, 0), this->pixel_x
, xstart
);
1326 abld
.ADD(offset(delta_xy
, 1), this->pixel_y
, ystart
);
1329 abld
= bld
.annotate("compute pos.w and 1/pos.w");
1330 /* Compute wpos.w. It's always in our setup, since it's needed to
1331 * interpolate the other attributes.
1333 this->wpos_w
= vgrf(glsl_type::float_type
);
1334 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
1335 interp_reg(VARYING_SLOT_POS
, 3));
1336 /* Compute the pixel 1/W value from wpos.w. */
1337 this->pixel_w
= vgrf(glsl_type::float_type
);
1338 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1341 /** Emits the interpolation for the varying inputs. */
1343 fs_visitor::emit_interpolation_setup_gen6()
1345 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1347 fs_builder abld
= bld
.annotate("compute pixel centers");
1348 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1349 /* The "Register Region Restrictions" page says for BDW (and newer,
1352 * "When destination spans two registers, the source may be one or
1353 * two registers. The destination elements must be evenly split
1354 * between the two registers."
1356 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
1357 * compute our pixel centers.
1359 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
1360 BRW_REGISTER_TYPE_UW
, dispatch_width
* 2);
1363 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
1364 fs_reg(brw_imm_v(0x11001010)));
1366 this->pixel_x
= vgrf(glsl_type::float_type
);
1367 this->pixel_y
= vgrf(glsl_type::float_type
);
1368 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
1369 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
1371 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
1373 * "When destination spans two registers, the source MUST span two
1376 * Since the GRF source of the ADD will only read a single register, we
1377 * must do two separate ADDs in SIMD16.
1379 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
1380 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
1381 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1382 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1383 abld
.ADD(int_pixel_x
,
1384 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1385 fs_reg(brw_imm_v(0x10101010)));
1386 abld
.ADD(int_pixel_y
,
1387 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1388 fs_reg(brw_imm_v(0x11001100)));
1390 /* As of gen6, we can no longer mix float and int sources. We have
1391 * to turn the integer pixel centers into floats for their actual
1394 this->pixel_x
= vgrf(glsl_type::float_type
);
1395 this->pixel_y
= vgrf(glsl_type::float_type
);
1396 abld
.MOV(this->pixel_x
, int_pixel_x
);
1397 abld
.MOV(this->pixel_y
, int_pixel_y
);
1400 abld
= bld
.annotate("compute pos.w");
1401 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
1402 this->wpos_w
= vgrf(glsl_type::float_type
);
1403 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1405 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1406 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
1407 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
1412 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
,
1413 unsigned exec_size
, bool use_2nd_half
)
1415 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1418 if (key
->clamp_fragment_color
) {
1419 fs_reg tmp
= vgrf(glsl_type::vec4_type
);
1420 assert(color
.type
== BRW_REGISTER_TYPE_F
);
1421 for (unsigned i
= 0; i
< components
; i
++) {
1422 inst
= bld
.MOV(offset(tmp
, i
), offset(color
, i
));
1423 inst
->saturate
= true;
1428 if (exec_size
< dispatch_width
) {
1429 unsigned half_idx
= use_2nd_half
? 1 : 0;
1430 for (unsigned i
= 0; i
< components
; i
++)
1431 dst
[i
] = half(offset(color
, i
), half_idx
);
1433 for (unsigned i
= 0; i
< components
; i
++)
1434 dst
[i
] = offset(color
, i
);
1438 static enum brw_conditional_mod
1439 cond_for_alpha_func(GLenum func
)
1443 return BRW_CONDITIONAL_G
;
1445 return BRW_CONDITIONAL_GE
;
1447 return BRW_CONDITIONAL_L
;
1449 return BRW_CONDITIONAL_LE
;
1451 return BRW_CONDITIONAL_EQ
;
1453 return BRW_CONDITIONAL_NEQ
;
1455 unreachable("Not reached");
1460 * Alpha test support for when we compile it into the shader instead
1461 * of using the normal fixed-function alpha test.
1464 fs_visitor::emit_alpha_test()
1466 assert(stage
== MESA_SHADER_FRAGMENT
);
1467 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1468 const fs_builder abld
= bld
.annotate("Alpha test");
1471 if (key
->alpha_test_func
== GL_ALWAYS
)
1474 if (key
->alpha_test_func
== GL_NEVER
) {
1476 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1477 BRW_REGISTER_TYPE_UW
));
1478 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
1479 BRW_CONDITIONAL_NEQ
);
1482 fs_reg color
= offset(outputs
[0], 3);
1484 /* f0.1 &= func(color, ref) */
1485 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
1486 cond_for_alpha_func(key
->alpha_test_func
));
1488 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1489 cmp
->flag_subreg
= 1;
1493 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
1494 fs_reg color0
, fs_reg color1
,
1495 fs_reg src0_alpha
, unsigned components
,
1496 unsigned exec_size
, bool use_2nd_half
)
1498 assert(stage
== MESA_SHADER_FRAGMENT
);
1499 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1500 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1501 int header_size
= 2, payload_header_size
;
1503 /* We can potentially have a message length of up to 15, so we have to set
1504 * base_mrf to either 0 or 1 in order to fit in m0..m15.
1506 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
1509 /* From the Sandy Bridge PRM, volume 4, page 198:
1511 * "Dispatched Pixel Enables. One bit per pixel indicating
1512 * which pixels were originally enabled when the thread was
1513 * dispatched. This field is only required for the end-of-
1514 * thread message and on all dual-source messages."
1516 if (devinfo
->gen
>= 6 &&
1517 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
1518 color1
.file
== BAD_FILE
&&
1519 key
->nr_color_regions
== 1) {
1523 if (header_size
!= 0) {
1524 assert(header_size
== 2);
1525 /* Allocate 2 registers for a header */
1529 if (payload
.aa_dest_stencil_reg
) {
1530 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1));
1531 bld
.exec_all().annotate("FB write stencil/AA alpha")
1532 .MOV(sources
[length
],
1533 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
1537 prog_data
->uses_omask
=
1538 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
1539 if (prog_data
->uses_omask
) {
1540 assert(this->sample_mask
.file
!= BAD_FILE
);
1541 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
1542 * it's unsinged single words, one vgrf is always 16-wide.
1544 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1),
1545 BRW_REGISTER_TYPE_UW
, 16);
1546 bld
.exec_all().annotate("FB write oMask")
1547 .emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
1551 payload_header_size
= length
;
1553 if (color0
.file
== BAD_FILE
) {
1554 /* Even if there's no color buffers enabled, we still need to send
1555 * alpha out the pipeline to our null renderbuffer to support
1556 * alpha-testing, alpha-to-coverage, and so on.
1558 if (this->outputs
[0].file
!= BAD_FILE
)
1559 setup_color_payload(&sources
[length
+ 3], offset(this->outputs
[0], 3),
1560 1, exec_size
, false);
1562 } else if (color1
.file
== BAD_FILE
) {
1563 if (src0_alpha
.file
!= BAD_FILE
) {
1564 setup_color_payload(&sources
[length
], src0_alpha
, 1, exec_size
, false);
1568 setup_color_payload(&sources
[length
], color0
, components
,
1569 exec_size
, use_2nd_half
);
1572 setup_color_payload(&sources
[length
], color0
, components
,
1573 exec_size
, use_2nd_half
);
1575 setup_color_payload(&sources
[length
], color1
, components
,
1576 exec_size
, use_2nd_half
);
1580 if (source_depth_to_render_target
) {
1581 if (devinfo
->gen
== 6) {
1582 /* For outputting oDepth on gen6, SIMD8 writes have to be
1583 * used. This would require SIMD8 moves of each half to
1584 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1585 * Just bail on doing so for now.
1587 no16("Missing support for simd16 depth writes on gen6\n");
1590 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
1591 /* Hand over gl_FragDepth. */
1592 assert(this->frag_depth
.file
!= BAD_FILE
);
1593 if (exec_size
< dispatch_width
) {
1594 sources
[length
] = half(this->frag_depth
, use_2nd_half
);
1596 sources
[length
] = this->frag_depth
;
1599 /* Pass through the payload depth. */
1600 sources
[length
] = fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
1605 if (payload
.dest_depth_reg
)
1606 sources
[length
++] = fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0));
1608 const fs_builder ubld
= bld
.group(exec_size
, use_2nd_half
);
1611 if (devinfo
->gen
>= 7) {
1612 /* Send from the GRF */
1613 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
, exec_size
);
1614 load
= ubld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
1615 payload
.reg
= alloc
.allocate(load
->regs_written
);
1616 load
->dst
= payload
;
1617 write
= ubld
.emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
1618 write
->base_mrf
= -1;
1620 /* Send from the MRF */
1621 load
= ubld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
, exec_size
),
1622 sources
, length
, payload_header_size
);
1624 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
1625 * will do this for us if we just give it a COMPR4 destination.
1627 if (devinfo
->gen
< 6 && exec_size
== 16)
1628 load
->dst
.reg
|= BRW_MRF_COMPR4
;
1630 write
= ubld
.emit(FS_OPCODE_FB_WRITE
);
1631 write
->exec_size
= exec_size
;
1632 write
->base_mrf
= 1;
1635 write
->mlen
= load
->regs_written
;
1636 write
->header_size
= header_size
;
1637 if (prog_data
->uses_kill
) {
1638 write
->predicate
= BRW_PREDICATE_NORMAL
;
1639 write
->flag_subreg
= 1;
1645 fs_visitor::emit_fb_writes()
1647 assert(stage
== MESA_SHADER_FRAGMENT
);
1648 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1649 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1651 fs_inst
*inst
= NULL
;
1653 const fs_builder abld
= bld
.annotate("FB dual-source write");
1655 inst
= emit_single_fb_write(abld
, this->outputs
[0],
1656 this->dual_src_output
, reg_undef
, 4, 8);
1659 /* SIMD16 dual source blending requires to send two SIMD8 dual source
1660 * messages, where each message contains color data for 8 pixels. Color
1661 * data for the first group of pixels is stored in the "lower" half of
1662 * the color registers, so in SIMD16, the previous message did:
1668 * Here goes the second message, which packs color data for the
1669 * remaining 8 pixels. Color data for these pixels is stored in the
1670 * "upper" half of the color registers, so we need to do:
1676 if (dispatch_width
== 16) {
1677 inst
= emit_single_fb_write(abld
, this->outputs
[0],
1678 this->dual_src_output
, reg_undef
, 4, 8,
1683 prog_data
->dual_src_blend
= true;
1685 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
1686 /* Skip over outputs that weren't written. */
1687 if (this->outputs
[target
].file
== BAD_FILE
)
1690 const fs_builder abld
= bld
.annotate(
1691 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
1694 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
1695 src0_alpha
= offset(outputs
[0], 3);
1697 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
1699 this->output_components
[target
],
1701 inst
->target
= target
;
1706 /* Even if there's no color buffers enabled, we still need to send
1707 * alpha out the pipeline to our null renderbuffer to support
1708 * alpha-testing, alpha-to-coverage, and so on.
1710 inst
= emit_single_fb_write(bld
, reg_undef
, reg_undef
, reg_undef
, 0,
1719 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
1721 const struct brw_vue_prog_key
*key
=
1722 (const struct brw_vue_prog_key
*) this->key
;
1724 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1725 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
1726 for (int j
= 0; j
< 4; ++j
) {
1727 stage_prog_data
->param
[uniforms
+ j
] =
1728 (gl_constant_value
*) &clip_planes
[i
][j
];
1735 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
1737 * This does nothing if the shader uses gl_ClipDistance or user clipping is
1738 * disabled altogether.
1740 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
1742 struct brw_vue_prog_data
*vue_prog_data
=
1743 (struct brw_vue_prog_data
*) prog_data
;
1744 const struct brw_vue_prog_key
*key
=
1745 (const struct brw_vue_prog_key
*) this->key
;
1747 /* Bail unless some sort of legacy clipping is enabled */
1748 if (!key
->userclip_active
|| prog
->UsesClipDistanceOut
)
1751 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
1753 * "If a linked set of shaders forming the vertex stage contains no
1754 * static write to gl_ClipVertex or gl_ClipDistance, but the
1755 * application has requested clipping against user clip planes through
1756 * the API, then the coordinate written to gl_Position is used for
1757 * comparison against the user clip planes."
1759 * This function is only called if the shader didn't write to
1760 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
1761 * if the user wrote to it; otherwise we use gl_Position.
1764 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
1765 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
1766 clip_vertex
= VARYING_SLOT_POS
;
1768 /* If the clip vertex isn't written, skip this. Typically this means
1769 * the GS will set up clipping. */
1770 if (outputs
[clip_vertex
].file
== BAD_FILE
)
1773 setup_uniform_clipplane_values(clip_planes
);
1775 const fs_builder abld
= bld
.annotate("user clip distances");
1777 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
1778 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
1780 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1781 fs_reg u
= userplane
[i
];
1782 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
1783 output
.reg_offset
= i
& 3;
1785 abld
.MUL(output
, outputs
[clip_vertex
], u
);
1786 for (int j
= 1; j
< 4; j
++) {
1787 u
.reg
= userplane
[i
].reg
+ j
;
1788 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], j
), u
);
1794 fs_visitor::emit_urb_writes()
1796 int slot
, urb_offset
, length
;
1797 struct brw_vs_prog_data
*vs_prog_data
=
1798 (struct brw_vs_prog_data
*) prog_data
;
1799 const struct brw_vs_prog_key
*key
=
1800 (const struct brw_vs_prog_key
*) this->key
;
1801 const GLbitfield64 psiz_mask
=
1802 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
1803 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
1807 /* If we don't have any valid slots to write, just do a minimal urb write
1808 * send to terminate the shader. This includes 1 slot of undefined data,
1809 * because it's invalid to write 0 data:
1811 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
1812 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
1813 * Write Data Payload:
1815 * "The write data payload can be between 1 and 8 message phases long."
1817 if (vue_map
->slots_valid
== 0) {
1818 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
1819 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
1820 BRW_REGISTER_TYPE_UD
)));
1822 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1832 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
1833 fs_reg reg
, src
, zero
;
1835 int varying
= vue_map
->slot_to_varying
[slot
];
1837 case VARYING_SLOT_PSIZ
:
1839 /* The point size varying slot is the vue header and is always in the
1840 * vue map. But often none of the special varyings that live there
1841 * are written and in that case we can skip writing to the vue
1842 * header, provided the corresponding state properly clamps the
1843 * values further down the pipeline. */
1844 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
1845 assert(length
== 0);
1850 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1851 bld
.MOV(zero
, fs_reg(0u));
1853 sources
[length
++] = zero
;
1854 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
1855 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
1857 sources
[length
++] = zero
;
1859 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
1860 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
1862 sources
[length
++] = zero
;
1864 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
1865 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
1867 sources
[length
++] = zero
;
1870 case BRW_VARYING_SLOT_NDC
:
1871 case VARYING_SLOT_EDGE
:
1872 unreachable("unexpected scalar vs output");
1875 case BRW_VARYING_SLOT_PAD
:
1879 /* gl_Position is always in the vue map, but isn't always written by
1880 * the shader. Other varyings (clip distances) get added to the vue
1881 * map but don't always get written. In those cases, the
1882 * corresponding this->output[] slot will be invalid we and can skip
1883 * the urb write for the varying. If we've already queued up a vue
1884 * slot for writing we flush a mlen 5 urb write, otherwise we just
1885 * advance the urb_offset.
1887 if (this->outputs
[varying
].file
== BAD_FILE
) {
1895 if ((varying
== VARYING_SLOT_COL0
||
1896 varying
== VARYING_SLOT_COL1
||
1897 varying
== VARYING_SLOT_BFC0
||
1898 varying
== VARYING_SLOT_BFC1
) &&
1899 key
->clamp_vertex_color
) {
1900 /* We need to clamp these guys, so do a saturating MOV into a
1901 * temp register and use that for the payload.
1903 for (int i
= 0; i
< 4; i
++) {
1904 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
1905 src
= offset(this->outputs
[varying
], i
);
1906 set_saturate(true, bld
.MOV(reg
, src
));
1907 sources
[length
++] = reg
;
1910 for (int i
= 0; i
< 4; i
++)
1911 sources
[length
++] = offset(this->outputs
[varying
], i
);
1916 const fs_builder abld
= bld
.annotate("URB write");
1918 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
1919 * the last slot or if we need to flush (see BAD_FILE varying case
1920 * above), emit a URB write send now to flush out the data.
1922 int last
= slot
== vue_map
->num_slots
- 1;
1923 if (length
== 8 || last
)
1926 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
1927 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
1928 BRW_REGISTER_TYPE_F
, dispatch_width
);
1929 payload_sources
[0] =
1930 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1932 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
1933 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1936 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1938 inst
->mlen
= length
+ 1;
1939 inst
->offset
= urb_offset
;
1940 urb_offset
= slot
+ 1;
1948 fs_visitor::emit_cs_terminate()
1950 assert(devinfo
->gen
>= 7);
1952 /* We are getting the thread ID from the compute shader header */
1953 assert(stage
== MESA_SHADER_COMPUTE
);
1955 /* We can't directly send from g0, since sends with EOT have to use
1956 * g112-127. So, copy it to a virtual register, The register allocator will
1957 * make sure it uses the appropriate register range.
1959 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1960 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1961 bld
.exec_all().MOV(payload
, g0
);
1963 /* Send a message to the thread spawner to terminate the thread. */
1964 fs_inst
*inst
= bld
.exec_all()
1965 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1970 fs_visitor::emit_barrier()
1972 assert(devinfo
->gen
>= 7);
1974 /* We are getting the barrier ID from the compute shader header */
1975 assert(stage
== MESA_SHADER_COMPUTE
);
1977 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1979 /* Clear the message payload */
1980 bld
.exec_all().MOV(payload
, fs_reg(0u));
1982 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1983 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1984 bld
.exec_all().AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1986 /* Emit a gateway "barrier" message using the payload we set up, followed
1987 * by a wait instruction.
1989 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1992 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1994 gl_shader_stage stage
,
1996 struct brw_stage_prog_data
*prog_data
,
1997 struct gl_shader_program
*shader_prog
,
1998 struct gl_program
*prog
,
1999 unsigned dispatch_width
,
2000 int shader_time_index
)
2001 : backend_shader(compiler
, log_data
, mem_ctx
,
2002 shader_prog
, prog
, prog_data
, stage
),
2003 key(key
), prog_data(prog_data
),
2004 dispatch_width(dispatch_width
),
2005 shader_time_index(shader_time_index
),
2006 promoted_constants(0),
2007 bld(fs_builder(this, dispatch_width
).at_end())
2010 case MESA_SHADER_FRAGMENT
:
2011 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
2013 case MESA_SHADER_VERTEX
:
2014 case MESA_SHADER_GEOMETRY
:
2015 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
2017 case MESA_SHADER_COMPUTE
:
2018 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
2021 unreachable("unhandled shader stage");
2024 this->failed
= false;
2025 this->simd16_unsupported
= false;
2026 this->no16_msg
= NULL
;
2028 this->nir_locals
= NULL
;
2029 this->nir_globals
= NULL
;
2031 memset(&this->payload
, 0, sizeof(this->payload
));
2032 memset(this->outputs
, 0, sizeof(this->outputs
));
2033 memset(this->output_components
, 0, sizeof(this->output_components
));
2034 this->source_depth_to_render_target
= false;
2035 this->runtime_check_aads_emit
= false;
2036 this->first_non_payload_grf
= 0;
2037 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2039 this->virtual_grf_start
= NULL
;
2040 this->virtual_grf_end
= NULL
;
2041 this->live_intervals
= NULL
;
2042 this->regs_live_at_ip
= NULL
;
2045 this->last_scratch
= 0;
2046 this->pull_constant_loc
= NULL
;
2047 this->push_constant_loc
= NULL
;
2049 this->spilled_any_registers
= false;
2050 this->do_dual_src
= false;
2052 if (dispatch_width
== 8)
2053 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
2056 fs_visitor::~fs_visitor()