2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_shader_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_shader_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->is_in_uniform_block())
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
204 if (intel
->gen
< 6 ||
205 !x
.is_valid_3src() ||
206 !y
.is_valid_3src() ||
207 !a
.is_valid_3src()) {
208 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
209 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
210 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
211 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
213 emit(MUL(y_times_a
, y
, a
));
215 a
.negate
= !a
.negate
;
216 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
217 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
219 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
221 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
222 * we need to reorder the operands.
224 emit(LRP(dst
, a
, y
, x
));
229 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
230 fs_reg src0
, fs_reg src1
)
234 if (intel
->gen
>= 6) {
235 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
236 inst
->conditional_mod
= conditionalmod
;
238 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
240 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
241 inst
->predicate
= BRW_PREDICATE_NORMAL
;
245 /* Instruction selection: Produce a MOV.sat instead of
246 * MIN(MAX(val, 0), 1) when possible.
249 fs_visitor::try_emit_saturate(ir_expression
*ir
)
251 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
256 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
258 sat_val
->accept(this);
259 fs_reg src
= this->result
;
261 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
263 /* If the last instruction from our accept() didn't generate our
264 * src, generate a saturated MOV
266 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
267 if (!modify
|| modify
->regs_written
!= 1) {
268 this->result
= fs_reg(this, ir
->type
);
269 fs_inst
*inst
= emit(MOV(this->result
, src
));
270 inst
->saturate
= true;
272 modify
->saturate
= true;
281 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
283 /* 3-src instructions were introduced in gen6. */
287 /* MAD can only handle floating-point data. */
288 if (ir
->type
!= glsl_type::float_type
)
291 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
292 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
294 if (!mul
|| mul
->operation
!= ir_binop_mul
)
297 if (nonmul
->as_constant() ||
298 mul
->operands
[0]->as_constant() ||
299 mul
->operands
[1]->as_constant())
302 nonmul
->accept(this);
303 fs_reg src0
= this->result
;
305 mul
->operands
[0]->accept(this);
306 fs_reg src1
= this->result
;
308 mul
->operands
[1]->accept(this);
309 fs_reg src2
= this->result
;
311 this->result
= fs_reg(this, ir
->type
);
312 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
318 fs_visitor::visit(ir_expression
*ir
)
320 unsigned int operand
;
324 assert(ir
->get_num_operands() <= 3);
326 if (try_emit_saturate(ir
))
328 if (ir
->operation
== ir_binop_add
) {
329 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
333 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
334 ir
->operands
[operand
]->accept(this);
335 if (this->result
.file
== BAD_FILE
) {
337 fail("Failed to get tree for expression operand:\n");
338 ir
->operands
[operand
]->accept(&v
);
340 op
[operand
] = this->result
;
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
345 assert(!ir
->operands
[operand
]->type
->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
348 assert(!ir
->operands
[operand
]->type
->is_vector());
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
354 this->result
= fs_reg(this, ir
->type
);
356 switch (ir
->operation
) {
357 case ir_unop_logic_not
:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
361 emit(XOR(this->result
, op
[0], fs_reg(1)));
364 op
[0].negate
= !op
[0].negate
;
365 this->result
= op
[0];
369 op
[0].negate
= false;
370 this->result
= op
[0];
373 temp
= fs_reg(this, ir
->type
);
375 emit(MOV(this->result
, fs_reg(0.0f
)));
377 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
378 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
379 inst
->predicate
= BRW_PREDICATE_NORMAL
;
381 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
382 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
383 inst
->predicate
= BRW_PREDICATE_NORMAL
;
387 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
391 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
394 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
401 case ir_unop_sin_reduced
:
402 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
405 case ir_unop_cos_reduced
:
406 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
410 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
413 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
417 emit(ADD(this->result
, op
[0], op
[1]));
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
424 if (ir
->type
->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
430 * FINISHME: Emit just the MUL if we know an operand is small
433 if (intel
->gen
>= 7 && dispatch_width
== 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
436 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
438 emit(MUL(acc
, op
[0], op
[1]));
439 emit(MACH(reg_null_d
, op
[0], op
[1]));
440 emit(MOV(this->result
, fs_reg(acc
)));
442 emit(MUL(this->result
, op
[0], op
[1]));
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir
->type
->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir
->type
->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
457 case ir_binop_greater
:
458 case ir_binop_lequal
:
459 case ir_binop_gequal
:
461 case ir_binop_all_equal
:
462 case ir_binop_nequal
:
463 case ir_binop_any_nequal
:
464 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
465 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
467 emit(CMP(this->result
, op
[0], op
[1],
468 brw_conditional_for_comparison(ir
->operation
)));
471 case ir_binop_logic_xor
:
472 emit(XOR(this->result
, op
[0], op
[1]));
475 case ir_binop_logic_or
:
476 emit(OR(this->result
, op
[0], op
[1]));
479 case ir_binop_logic_and
:
480 emit(AND(this->result
, op
[0], op
[1]));
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
489 assert(!"not reached: should be handled by lower_noise");
492 case ir_quadop_vector
:
493 assert(!"not reached: should be handled by lower_quadop_vector");
496 case ir_binop_vector_extract
:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
500 case ir_triop_vector_insert
:
501 assert(!"not reached: should be handled by lower_vector_insert()");
505 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
509 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
512 case ir_unop_bitcast_i2f
:
513 case ir_unop_bitcast_u2f
:
514 op
[0].type
= BRW_REGISTER_TYPE_F
;
515 this->result
= op
[0];
518 case ir_unop_bitcast_f2u
:
519 op
[0].type
= BRW_REGISTER_TYPE_UD
;
520 this->result
= op
[0];
523 case ir_unop_bitcast_f2i
:
524 op
[0].type
= BRW_REGISTER_TYPE_D
;
525 this->result
= op
[0];
531 emit(MOV(this->result
, op
[0]));
535 emit(AND(this->result
, op
[0], fs_reg(1)));
538 temp
= fs_reg(this, glsl_type::int_type
);
539 emit(AND(temp
, op
[0], fs_reg(1)));
540 emit(MOV(this->result
, temp
));
544 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
547 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
551 emit(RNDZ(this->result
, op
[0]));
554 op
[0].negate
= !op
[0].negate
;
555 emit(RNDD(this->result
, op
[0]));
556 this->result
.negate
= true;
559 emit(RNDD(this->result
, op
[0]));
562 emit(FRC(this->result
, op
[0]));
564 case ir_unop_round_even
:
565 emit(RNDE(this->result
, op
[0]));
570 resolve_ud_negate(&op
[0]);
571 resolve_ud_negate(&op
[1]);
572 emit_minmax(ir
->operation
== ir_binop_min
?
573 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
574 this->result
, op
[0], op
[1]);
576 case ir_unop_pack_snorm_2x16
:
577 case ir_unop_pack_snorm_4x8
:
578 case ir_unop_pack_unorm_2x16
:
579 case ir_unop_pack_unorm_4x8
:
580 case ir_unop_unpack_snorm_2x16
:
581 case ir_unop_unpack_snorm_4x8
:
582 case ir_unop_unpack_unorm_2x16
:
583 case ir_unop_unpack_unorm_4x8
:
584 case ir_unop_unpack_half_2x16
:
585 case ir_unop_pack_half_2x16
:
586 assert(!"not reached: should be handled by lower_packing_builtins");
588 case ir_unop_unpack_half_2x16_split_x
:
589 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
591 case ir_unop_unpack_half_2x16_split_y
:
592 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
595 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
598 case ir_unop_bitfield_reverse
:
599 emit(BFREV(this->result
, op
[0]));
601 case ir_unop_bit_count
:
602 emit(CBIT(this->result
, op
[0]));
604 case ir_unop_find_msb
:
605 temp
= fs_reg(this, glsl_type::uint_type
);
606 emit(FBH(temp
, op
[0]));
608 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
609 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
610 * subtract the result from 31 to convert the MSB count into an LSB count.
613 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
614 emit(MOV(this->result
, temp
));
615 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
618 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
619 inst
->predicate
= BRW_PREDICATE_NORMAL
;
621 case ir_unop_find_lsb
:
622 emit(FBL(this->result
, op
[0]));
624 case ir_triop_bitfield_extract
:
625 /* Note that the instruction's argument order is reversed from GLSL
628 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
631 emit(BFI1(this->result
, op
[0], op
[1]));
634 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
636 case ir_quadop_bitfield_insert
:
637 assert(!"not reached: should be handled by "
638 "lower_instructions::bitfield_insert_to_bfm_bfi");
641 case ir_unop_bit_not
:
642 emit(NOT(this->result
, op
[0]));
644 case ir_binop_bit_and
:
645 emit(AND(this->result
, op
[0], op
[1]));
647 case ir_binop_bit_xor
:
648 emit(XOR(this->result
, op
[0], op
[1]));
650 case ir_binop_bit_or
:
651 emit(OR(this->result
, op
[0], op
[1]));
654 case ir_binop_lshift
:
655 emit(SHL(this->result
, op
[0], op
[1]));
658 case ir_binop_rshift
:
659 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
660 emit(ASR(this->result
, op
[0], op
[1]));
662 emit(SHR(this->result
, op
[0], op
[1]));
664 case ir_binop_pack_half_2x16_split
:
665 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
667 case ir_binop_ubo_load
: {
668 /* This IR node takes a constant uniform block and a constant or
669 * variable byte offset within the block and loads a vector from that.
671 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
672 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
673 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
675 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
676 packed_consts
.type
= result
.type
;
678 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
679 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
680 packed_consts
, surf_index
, const_offset_reg
));
682 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
683 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
684 /* UBO bools are any nonzero value. We consider bools to be
685 * values with the low bit set to 1. Convert them using CMP.
687 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
688 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
690 emit(MOV(result
, packed_consts
));
693 packed_consts
.smear
++;
696 /* The std140 packing rules don't allow vectors to cross 16-byte
697 * boundaries, and a reg is 32 bytes.
699 assert(packed_consts
.smear
< 8);
702 /* Turn the byte offset into a dword offset. */
703 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
704 emit(SHR(base_offset
, op
[1], fs_reg(2)));
706 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
707 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
710 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
711 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
717 result
.reg_offset
= 0;
722 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
728 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
729 const glsl_type
*type
, bool predicated
)
731 switch (type
->base_type
) {
732 case GLSL_TYPE_FLOAT
:
736 for (unsigned int i
= 0; i
< type
->components(); i
++) {
737 l
.type
= brw_type_for_base_type(type
);
738 r
.type
= brw_type_for_base_type(type
);
740 if (predicated
|| !l
.equals(r
)) {
741 fs_inst
*inst
= emit(MOV(l
, r
));
742 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
749 case GLSL_TYPE_ARRAY
:
750 for (unsigned int i
= 0; i
< type
->length
; i
++) {
751 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
755 case GLSL_TYPE_STRUCT
:
756 for (unsigned int i
= 0; i
< type
->length
; i
++) {
757 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
762 case GLSL_TYPE_SAMPLER
:
766 case GLSL_TYPE_ERROR
:
767 case GLSL_TYPE_INTERFACE
:
768 assert(!"not reached");
773 /* If the RHS processing resulted in an instruction generating a
774 * temporary value, and it would be easy to rewrite the instruction to
775 * generate its result right into the LHS instead, do so. This ends
776 * up reliably removing instructions where it can be tricky to do so
777 * later without real UD chain information.
780 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
783 fs_inst
*pre_rhs_inst
,
784 fs_inst
*last_rhs_inst
)
786 /* Only attempt if we're doing a direct assignment. */
788 !(ir
->lhs
->type
->is_scalar() ||
789 (ir
->lhs
->type
->is_vector() &&
790 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
793 /* Make sure the last instruction generated our source reg. */
794 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
800 /* If last_rhs_inst wrote a different number of components than our LHS,
801 * we can't safely rewrite it.
803 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
806 /* Success! Rewrite the instruction. */
813 fs_visitor::visit(ir_assignment
*ir
)
818 /* FINISHME: arrays on the lhs */
819 ir
->lhs
->accept(this);
822 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
824 ir
->rhs
->accept(this);
827 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
829 assert(l
.file
!= BAD_FILE
);
830 assert(r
.file
!= BAD_FILE
);
832 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
836 emit_bool_to_cond_code(ir
->condition
);
839 if (ir
->lhs
->type
->is_scalar() ||
840 ir
->lhs
->type
->is_vector()) {
841 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
842 if (ir
->write_mask
& (1 << i
)) {
843 inst
= emit(MOV(l
, r
));
845 inst
->predicate
= BRW_PREDICATE_NORMAL
;
851 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
856 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
857 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
867 if (ir
->shadow_comparitor
) {
868 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
869 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
870 coordinate
.reg_offset
++;
872 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
875 if (ir
->op
== ir_tex
) {
876 /* There's no plain shadow compare message, so we use shadow
877 * compare with a bias of 0.0.
879 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
881 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
882 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
885 assert(!"Should not get here.");
888 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
890 } else if (ir
->op
== ir_tex
) {
891 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
892 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
893 coordinate
.reg_offset
++;
895 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
897 } else if (ir
->op
== ir_txd
) {
900 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
901 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
902 coordinate
.reg_offset
++;
904 /* the slots for u and v are always present, but r is optional */
905 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
908 * dPdx = dudx, dvdx, drdx
909 * dPdy = dudy, dvdy, drdy
911 * 1-arg: Does not exist.
913 * 2-arg: dudx dvdx dudy dvdy
914 * dPdx.x dPdx.y dPdy.x dPdy.y
917 * 3-arg: dudx dvdx drdx dudy dvdy drdy
918 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
921 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
922 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
925 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
927 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
928 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
931 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
932 } else if (ir
->op
== ir_txs
) {
933 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
935 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
938 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
939 * instructions. We'll need to do SIMD16 here.
942 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
944 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
945 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
947 coordinate
.reg_offset
++;
950 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
951 * be necessary for TXF (ld), but seems wise to do for all messages.
953 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
954 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
957 /* lod/bias appears after u/v/r. */
960 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
963 /* The unused upper half. */
968 /* Now, since we're doing simd16, the return is 2 interleaved
969 * vec4s where the odd-indexed ones are junk. We'll need to move
970 * this weirdness around to the expected layout.
973 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
975 brw_type_for_base_type(ir
->type
) :
976 BRW_REGISTER_TYPE_F
));
979 fs_inst
*inst
= NULL
;
982 inst
= emit(SHADER_OPCODE_TEX
, dst
);
985 inst
= emit(FS_OPCODE_TXB
, dst
);
988 inst
= emit(SHADER_OPCODE_TXL
, dst
);
991 inst
= emit(SHADER_OPCODE_TXD
, dst
);
994 inst
= emit(SHADER_OPCODE_TXS
, dst
);
997 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1000 fail("unrecognized texture opcode");
1002 inst
->base_mrf
= base_mrf
;
1004 inst
->header_present
= true;
1005 inst
->regs_written
= simd16
? 8 : 4;
1008 for (int i
= 0; i
< 4; i
++) {
1009 emit(MOV(orig_dst
, dst
));
1010 orig_dst
.reg_offset
++;
1011 dst
.reg_offset
+= 2;
1018 /* gen5's sampler has slots for u, v, r, array index, then optional
1019 * parameters like shadow comparitor or LOD bias. If optional
1020 * parameters aren't present, those base slots are optional and don't
1021 * need to be included in the message.
1023 * We don't fill in the unnecessary slots regardless, which may look
1024 * surprising in the disassembly.
1027 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1028 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1029 fs_reg sample_index
)
1033 int reg_width
= dispatch_width
/ 8;
1034 bool header_present
= false;
1035 const int vector_elements
=
1036 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1038 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
1039 /* It appears that the ld instruction used for txf does its
1040 * address bounds check before adding in the offset. To work
1041 * around this, just add the integer offset to the integer texel
1042 * coordinate, and don't put the offset in the header.
1044 ir_constant
*offset
= ir
->offset
->as_constant();
1045 for (int i
= 0; i
< vector_elements
; i
++) {
1046 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1048 offset
->value
.i
[i
]));
1049 coordinate
.reg_offset
++;
1053 /* The offsets set up by the ir_texture visitor are in the
1054 * m1 header, so we can't go headerless.
1056 header_present
= true;
1061 for (int i
= 0; i
< vector_elements
; i
++) {
1062 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1064 coordinate
.reg_offset
++;
1067 mlen
+= vector_elements
* reg_width
;
1069 if (ir
->shadow_comparitor
) {
1070 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1072 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1076 fs_inst
*inst
= NULL
;
1079 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1082 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1083 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1086 inst
= emit(FS_OPCODE_TXB
, dst
);
1089 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1090 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1093 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1096 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1100 * dPdx = dudx, dvdx, drdx
1101 * dPdy = dudy, dvdy, drdy
1103 * Load up these values:
1104 * - dudx dudy dvdx dvdy drdx drdy
1105 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1107 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1108 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1112 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1117 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1121 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1123 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1126 mlen
= header_present
+ 4 * reg_width
;
1127 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1128 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1131 mlen
= header_present
+ 4 * reg_width
;
1134 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1136 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1138 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1141 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1144 inst
->base_mrf
= base_mrf
;
1146 inst
->header_present
= header_present
;
1147 inst
->regs_written
= 4;
1150 fail("Message length >11 disallowed by hardware\n");
1157 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1158 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1159 fs_reg sample_index
)
1163 int reg_width
= dispatch_width
/ 8;
1164 bool header_present
= false;
1167 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1168 /* The offsets set up by the ir_texture visitor are in the
1169 * m1 header, so we can't go headerless.
1171 header_present
= true;
1176 if (ir
->shadow_comparitor
) {
1177 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1181 /* Set up the LOD info */
1187 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1191 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1195 if (dispatch_width
== 16)
1196 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1198 /* Load dPdx and the coordinate together:
1199 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1201 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1202 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1203 coordinate
.reg_offset
++;
1206 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1207 * only derivatives for (u, v, r).
1209 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1210 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1214 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1222 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1226 /* It appears that the ld instruction used for txf does its
1227 * address bounds check before adding in the offset. To work
1228 * around this, just add the integer offset to the integer texel
1229 * coordinate, and don't put the offset in the header.
1232 ir_constant
*offset
= ir
->offset
->as_constant();
1233 offsets
[0] = offset
->value
.i
[0];
1234 offsets
[1] = offset
->value
.i
[1];
1235 offsets
[2] = offset
->value
.i
[2];
1237 memset(offsets
, 0, sizeof(offsets
));
1240 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1241 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1242 coordinate
, offsets
[0]));
1243 coordinate
.reg_offset
++;
1246 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1249 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1250 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1251 coordinate
, offsets
[i
]));
1252 coordinate
.reg_offset
++;
1257 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1260 /* constant zero MCS; we arrange to never actually have a compressed
1261 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1262 * if we ever support texturing from compressed multisample surfaces
1264 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1267 /* there is no offsetting for this message; just copy in the integer
1268 * texture coordinates
1270 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1271 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1273 coordinate
.reg_offset
++;
1279 /* Set up the coordinate (except for cases where it was done above) */
1280 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
&& ir
->op
!= ir_txf_ms
) {
1281 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1282 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1283 coordinate
.reg_offset
++;
1288 /* Generate the SEND */
1289 fs_inst
*inst
= NULL
;
1291 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1292 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1293 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1294 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1295 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1296 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
); break;
1297 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1298 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
); break;
1300 inst
->base_mrf
= base_mrf
;
1302 inst
->header_present
= header_present
;
1303 inst
->regs_written
= 4;
1306 fail("Message length >11 disallowed by hardware\n");
1313 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1314 bool is_rect
, int sampler
, int texunit
)
1316 fs_inst
*inst
= NULL
;
1317 bool needs_gl_clamp
= true;
1318 fs_reg scale_x
, scale_y
;
1320 /* The 965 requires the EU to do the normalization of GL rectangle
1321 * texture coordinates. We use the program parameter state
1322 * tracking to get the scaling factor.
1326 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1327 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1328 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1329 int tokens
[STATE_LENGTH
] = {
1331 STATE_TEXRECT_SCALE
,
1337 if (dispatch_width
== 16) {
1338 fail("rectangle scale uniform setup not supported on 16-wide\n");
1342 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1343 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1345 GLuint index
= _mesa_add_state_reference(params
,
1346 (gl_state_index
*)tokens
);
1347 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1348 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1349 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1350 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1353 /* The 965 requires the EU to do the normalization of GL rectangle
1354 * texture coordinates. We use the program parameter state
1355 * tracking to get the scaling factor.
1357 if (intel
->gen
< 6 && is_rect
) {
1358 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1359 fs_reg src
= coordinate
;
1362 emit(MUL(dst
, src
, scale_x
));
1365 emit(MUL(dst
, src
, scale_y
));
1366 } else if (is_rect
) {
1367 /* On gen6+, the sampler handles the rectangle coordinates
1368 * natively, without needing rescaling. But that means we have
1369 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1370 * not [0, 1] like the default case below.
1372 needs_gl_clamp
= false;
1374 for (int i
= 0; i
< 2; i
++) {
1375 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1376 fs_reg chan
= coordinate
;
1377 chan
.reg_offset
+= i
;
1379 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1380 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1382 /* Our parameter comes in as 1.0/width or 1.0/height,
1383 * because that's what people normally want for doing
1384 * texture rectangle handling. We need width or height
1385 * for clamping, but we don't care enough to make a new
1386 * parameter type, so just invert back.
1388 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1389 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1390 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1392 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1393 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1398 if (ir
->coordinate
&& needs_gl_clamp
) {
1399 for (unsigned int i
= 0;
1400 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1401 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1402 fs_reg chan
= coordinate
;
1403 chan
.reg_offset
+= i
;
1405 fs_inst
*inst
= emit(MOV(chan
, chan
));
1406 inst
->saturate
= true;
1414 fs_visitor::visit(ir_texture
*ir
)
1416 fs_inst
*inst
= NULL
;
1419 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, &fp
->Base
);
1420 /* FINISHME: We're failing to recompile our programs when the sampler is
1421 * updated. This only matters for the texture rectangle scale parameters
1422 * (pre-gen6, or gen6+ with GL_CLAMP).
1424 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1426 /* Should be lowered by do_lower_texture_projection */
1427 assert(!ir
->projector
);
1429 /* Generate code to compute all the subexpression trees. This has to be
1430 * done before loading any values into MRFs for the sampler message since
1431 * generating these values may involve SEND messages that need the MRFs.
1434 if (ir
->coordinate
) {
1435 ir
->coordinate
->accept(this);
1437 coordinate
= rescale_texcoord(ir
, this->result
,
1438 ir
->sampler
->type
->sampler_dimensionality
==
1439 GLSL_SAMPLER_DIM_RECT
,
1443 fs_reg shadow_comparitor
;
1444 if (ir
->shadow_comparitor
) {
1445 ir
->shadow_comparitor
->accept(this);
1446 shadow_comparitor
= this->result
;
1449 fs_reg lod
, lod2
, sample_index
;
1455 ir
->lod_info
.bias
->accept(this);
1459 ir
->lod_info
.grad
.dPdx
->accept(this);
1462 ir
->lod_info
.grad
.dPdy
->accept(this);
1463 lod2
= this->result
;
1468 ir
->lod_info
.lod
->accept(this);
1472 ir
->lod_info
.sample_index
->accept(this);
1473 sample_index
= this->result
;
1477 /* Writemasking doesn't eliminate channels on SIMD8 texture
1478 * samples, so don't worry about them.
1480 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1482 if (intel
->gen
>= 7) {
1483 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1484 lod
, lod2
, sample_index
);
1485 } else if (intel
->gen
>= 5) {
1486 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1487 lod
, lod2
, sample_index
);
1489 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1493 /* The header is set up by generate_tex() when necessary. */
1494 inst
->src
[0] = reg_undef
;
1496 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1497 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1499 inst
->sampler
= sampler
;
1501 if (ir
->shadow_comparitor
)
1502 inst
->shadow_compare
= true;
1504 /* fixup #layers for cube map arrays */
1505 if (ir
->op
== ir_txs
) {
1506 glsl_type
const *type
= ir
->sampler
->type
;
1507 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1508 type
->sampler_array
) {
1510 depth
.reg_offset
= 2;
1511 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1515 swizzle_result(ir
, dst
, sampler
);
1519 * Swizzle the result of a texture result. This is necessary for
1520 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1523 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1525 this->result
= orig_val
;
1527 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
)
1530 if (ir
->type
== glsl_type::float_type
) {
1531 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1532 assert(ir
->sampler
->type
->sampler_shadow
);
1533 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1534 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1536 for (int i
= 0; i
< 4; i
++) {
1537 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1538 fs_reg l
= swizzled_result
;
1541 if (swiz
== SWIZZLE_ZERO
) {
1542 emit(MOV(l
, fs_reg(0.0f
)));
1543 } else if (swiz
== SWIZZLE_ONE
) {
1544 emit(MOV(l
, fs_reg(1.0f
)));
1546 fs_reg r
= orig_val
;
1547 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1551 this->result
= swizzled_result
;
1556 fs_visitor::visit(ir_swizzle
*ir
)
1558 ir
->val
->accept(this);
1559 fs_reg val
= this->result
;
1561 if (ir
->type
->vector_elements
== 1) {
1562 this->result
.reg_offset
+= ir
->mask
.x
;
1566 fs_reg result
= fs_reg(this, ir
->type
);
1567 this->result
= result
;
1569 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1570 fs_reg channel
= val
;
1588 channel
.reg_offset
+= swiz
;
1589 emit(MOV(result
, channel
));
1590 result
.reg_offset
++;
1595 fs_visitor::visit(ir_discard
*ir
)
1597 assert(ir
->condition
== NULL
); /* FINISHME */
1599 /* We track our discarded pixels in f0.1. By predicating on it, we can
1600 * update just the flag bits that aren't yet discarded. By emitting a
1601 * CMP of g0 != g0, all our currently executing channels will get turned
1604 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1605 BRW_REGISTER_TYPE_UW
));
1606 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1607 BRW_CONDITIONAL_NZ
));
1608 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1609 cmp
->flag_subreg
= 1;
1611 if (intel
->gen
>= 6) {
1612 /* For performance, after a discard, jump to the end of the shader.
1613 * However, many people will do foliage by discarding based on a
1614 * texture's alpha mask, and then continue on to texture with the
1615 * remaining pixels. To avoid trashing the derivatives for those
1616 * texture samples, we'll only jump if all of the pixels in the subspan
1617 * have been discarded.
1619 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1620 discard_jump
->flag_subreg
= 1;
1621 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1622 discard_jump
->predicate_inverse
= true;
1627 fs_visitor::visit(ir_constant
*ir
)
1629 /* Set this->result to reg at the bottom of the function because some code
1630 * paths will cause this visitor to be applied to other fields. This will
1631 * cause the value stored in this->result to be modified.
1633 * Make reg constant so that it doesn't get accidentally modified along the
1634 * way. Yes, I actually had this problem. :(
1636 const fs_reg
reg(this, ir
->type
);
1637 fs_reg dst_reg
= reg
;
1639 if (ir
->type
->is_array()) {
1640 const unsigned size
= type_size(ir
->type
->fields
.array
);
1642 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1643 ir
->array_elements
[i
]->accept(this);
1644 fs_reg src_reg
= this->result
;
1646 dst_reg
.type
= src_reg
.type
;
1647 for (unsigned j
= 0; j
< size
; j
++) {
1648 emit(MOV(dst_reg
, src_reg
));
1649 src_reg
.reg_offset
++;
1650 dst_reg
.reg_offset
++;
1653 } else if (ir
->type
->is_record()) {
1654 foreach_list(node
, &ir
->components
) {
1655 ir_constant
*const field
= (ir_constant
*) node
;
1656 const unsigned size
= type_size(field
->type
);
1658 field
->accept(this);
1659 fs_reg src_reg
= this->result
;
1661 dst_reg
.type
= src_reg
.type
;
1662 for (unsigned j
= 0; j
< size
; j
++) {
1663 emit(MOV(dst_reg
, src_reg
));
1664 src_reg
.reg_offset
++;
1665 dst_reg
.reg_offset
++;
1669 const unsigned size
= type_size(ir
->type
);
1671 for (unsigned i
= 0; i
< size
; i
++) {
1672 switch (ir
->type
->base_type
) {
1673 case GLSL_TYPE_FLOAT
:
1674 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1676 case GLSL_TYPE_UINT
:
1677 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1680 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1682 case GLSL_TYPE_BOOL
:
1683 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1686 assert(!"Non-float/uint/int/bool constant");
1688 dst_reg
.reg_offset
++;
1696 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1698 ir_expression
*expr
= ir
->as_expression();
1704 assert(expr
->get_num_operands() <= 2);
1705 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1706 assert(expr
->operands
[i
]->type
->is_scalar());
1708 expr
->operands
[i
]->accept(this);
1709 op
[i
] = this->result
;
1711 resolve_ud_negate(&op
[i
]);
1714 switch (expr
->operation
) {
1715 case ir_unop_logic_not
:
1716 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1717 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1720 case ir_binop_logic_xor
:
1721 case ir_binop_logic_or
:
1722 case ir_binop_logic_and
:
1726 if (intel
->gen
>= 6) {
1727 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1729 inst
= emit(MOV(reg_null_f
, op
[0]));
1730 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1735 if (intel
->gen
>= 6) {
1736 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1738 inst
= emit(MOV(reg_null_d
, op
[0]));
1739 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1743 case ir_binop_greater
:
1744 case ir_binop_gequal
:
1746 case ir_binop_lequal
:
1747 case ir_binop_equal
:
1748 case ir_binop_all_equal
:
1749 case ir_binop_nequal
:
1750 case ir_binop_any_nequal
:
1751 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1752 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1754 emit(CMP(reg_null_d
, op
[0], op
[1],
1755 brw_conditional_for_comparison(expr
->operation
)));
1759 assert(!"not reached");
1760 fail("bad cond code\n");
1769 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1770 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1774 * Emit a gen6 IF statement with the comparison folded into the IF
1778 fs_visitor::emit_if_gen6(ir_if
*ir
)
1780 ir_expression
*expr
= ir
->condition
->as_expression();
1787 assert(expr
->get_num_operands() <= 2);
1788 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1789 assert(expr
->operands
[i
]->type
->is_scalar());
1791 expr
->operands
[i
]->accept(this);
1792 op
[i
] = this->result
;
1795 switch (expr
->operation
) {
1796 case ir_unop_logic_not
:
1797 case ir_binop_logic_xor
:
1798 case ir_binop_logic_or
:
1799 case ir_binop_logic_and
:
1800 /* For operations on bool arguments, only the low bit of the bool is
1801 * valid, and the others are undefined. Fall back to the condition
1807 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1808 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1812 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1815 case ir_binop_greater
:
1816 case ir_binop_gequal
:
1818 case ir_binop_lequal
:
1819 case ir_binop_equal
:
1820 case ir_binop_all_equal
:
1821 case ir_binop_nequal
:
1822 case ir_binop_any_nequal
:
1823 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1824 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1826 emit(IF(op
[0], op
[1],
1827 brw_conditional_for_comparison(expr
->operation
)));
1830 assert(!"not reached");
1831 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1832 fail("bad condition\n");
1837 emit_bool_to_cond_code(ir
->condition
);
1838 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1839 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1843 fs_visitor::visit(ir_if
*ir
)
1845 if (intel
->gen
< 6 && dispatch_width
== 16) {
1846 fail("Can't support (non-uniform) control flow on 16-wide\n");
1849 /* Don't point the annotation at the if statement, because then it plus
1850 * the then and else blocks get printed.
1852 this->base_ir
= ir
->condition
;
1854 if (intel
->gen
== 6) {
1857 emit_bool_to_cond_code(ir
->condition
);
1859 emit(IF(BRW_PREDICATE_NORMAL
));
1862 foreach_list(node
, &ir
->then_instructions
) {
1863 ir_instruction
*ir
= (ir_instruction
*)node
;
1869 if (!ir
->else_instructions
.is_empty()) {
1870 emit(BRW_OPCODE_ELSE
);
1872 foreach_list(node
, &ir
->else_instructions
) {
1873 ir_instruction
*ir
= (ir_instruction
*)node
;
1880 emit(BRW_OPCODE_ENDIF
);
1884 fs_visitor::visit(ir_loop
*ir
)
1886 fs_reg counter
= reg_undef
;
1888 if (intel
->gen
< 6 && dispatch_width
== 16) {
1889 fail("Can't support (non-uniform) control flow on 16-wide\n");
1893 this->base_ir
= ir
->counter
;
1894 ir
->counter
->accept(this);
1895 counter
= *(variable_storage(ir
->counter
));
1898 this->base_ir
= ir
->from
;
1899 ir
->from
->accept(this);
1901 emit(MOV(counter
, this->result
));
1905 this->base_ir
= NULL
;
1906 emit(BRW_OPCODE_DO
);
1909 this->base_ir
= ir
->to
;
1910 ir
->to
->accept(this);
1912 emit(CMP(reg_null_d
, counter
, this->result
,
1913 brw_conditional_for_comparison(ir
->cmp
)));
1915 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1916 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1919 foreach_list(node
, &ir
->body_instructions
) {
1920 ir_instruction
*ir
= (ir_instruction
*)node
;
1926 if (ir
->increment
) {
1927 this->base_ir
= ir
->increment
;
1928 ir
->increment
->accept(this);
1929 emit(ADD(counter
, counter
, this->result
));
1932 this->base_ir
= NULL
;
1933 emit(BRW_OPCODE_WHILE
);
1937 fs_visitor::visit(ir_loop_jump
*ir
)
1940 case ir_loop_jump::jump_break
:
1941 emit(BRW_OPCODE_BREAK
);
1943 case ir_loop_jump::jump_continue
:
1944 emit(BRW_OPCODE_CONTINUE
);
1950 fs_visitor::visit(ir_call
*ir
)
1952 assert(!"FINISHME");
1956 fs_visitor::visit(ir_return
*ir
)
1958 assert(!"FINISHME");
1962 fs_visitor::visit(ir_function
*ir
)
1964 /* Ignore function bodies other than main() -- we shouldn't see calls to
1965 * them since they should all be inlined before we get to ir_to_mesa.
1967 if (strcmp(ir
->name
, "main") == 0) {
1968 const ir_function_signature
*sig
;
1971 sig
= ir
->matching_signature(&empty
);
1975 foreach_list(node
, &sig
->body
) {
1976 ir_instruction
*ir
= (ir_instruction
*)node
;
1985 fs_visitor::visit(ir_function_signature
*ir
)
1987 assert(!"not reached");
1992 fs_visitor::emit(fs_inst inst
)
1994 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
2001 fs_visitor::emit(fs_inst
*inst
)
2003 if (force_uncompressed_stack
> 0)
2004 inst
->force_uncompressed
= true;
2005 else if (force_sechalf_stack
> 0)
2006 inst
->force_sechalf
= true;
2008 inst
->annotation
= this->current_annotation
;
2009 inst
->ir
= this->base_ir
;
2011 this->instructions
.push_tail(inst
);
2017 fs_visitor::emit(exec_list list
)
2019 foreach_list_safe(node
, &list
) {
2020 fs_inst
*inst
= (fs_inst
*)node
;
2026 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2028 fs_visitor::emit_dummy_fs()
2030 int reg_width
= dispatch_width
/ 8;
2032 /* Everyone's favorite color. */
2033 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2034 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2035 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2036 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2039 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2040 write
->base_mrf
= 2;
2041 write
->mlen
= 4 * reg_width
;
2045 /* The register location here is relative to the start of the URB
2046 * data. It will get adjusted to be a real location before
2047 * generate_code() time.
2050 fs_visitor::interp_reg(int location
, int channel
)
2052 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
2053 int stride
= (channel
& 1) * 4;
2055 assert(urb_setup
[location
] != -1);
2057 return brw_vec1_grf(regnr
, stride
);
2060 /** Emits the interpolation for the varying inputs. */
2062 fs_visitor::emit_interpolation_setup_gen4()
2064 this->current_annotation
= "compute pixel centers";
2065 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2066 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2067 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2068 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2070 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2071 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2073 this->current_annotation
= "compute pixel deltas from v0";
2075 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2076 fs_reg(this, glsl_type::vec2_type
);
2077 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2078 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2079 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2081 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2082 fs_reg(this, glsl_type::float_type
);
2083 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2084 fs_reg(this, glsl_type::float_type
);
2086 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2087 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2088 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2089 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2091 this->current_annotation
= "compute pos.w and 1/pos.w";
2092 /* Compute wpos.w. It's always in our setup, since it's needed to
2093 * interpolate the other attributes.
2095 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2096 emit(FS_OPCODE_LINTERP
, wpos_w
,
2097 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2098 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2099 interp_reg(VARYING_SLOT_POS
, 3));
2100 /* Compute the pixel 1/W value from wpos.w. */
2101 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2102 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2103 this->current_annotation
= NULL
;
2106 /** Emits the interpolation for the varying inputs. */
2108 fs_visitor::emit_interpolation_setup_gen6()
2110 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2112 /* If the pixel centers end up used, the setup is the same as for gen4. */
2113 this->current_annotation
= "compute pixel centers";
2114 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2115 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2116 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2117 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2118 emit(ADD(int_pixel_x
,
2119 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2120 fs_reg(brw_imm_v(0x10101010))));
2121 emit(ADD(int_pixel_y
,
2122 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2123 fs_reg(brw_imm_v(0x11001100))));
2125 /* As of gen6, we can no longer mix float and int sources. We have
2126 * to turn the integer pixel centers into floats for their actual
2129 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2130 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2131 emit(MOV(this->pixel_x
, int_pixel_x
));
2132 emit(MOV(this->pixel_y
, int_pixel_y
));
2134 this->current_annotation
= "compute pos.w";
2135 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2136 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2137 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2139 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2140 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2141 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2142 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2145 this->current_annotation
= NULL
;
2149 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2151 int reg_width
= dispatch_width
/ 8;
2153 fs_reg color
= outputs
[target
];
2156 /* If there's no color data to be written, skip it. */
2157 if (color
.file
== BAD_FILE
)
2160 color
.reg_offset
+= index
;
2162 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2163 /* SIMD8 write looks like:
2169 * gen6 SIMD16 DP write looks like:
2179 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2182 inst
->saturate
= c
->key
.clamp_fragment_color
;
2184 /* pre-gen6 SIMD16 single source DP write looks like:
2194 if (brw
->has_compr4
) {
2195 /* By setting the high bit of the MRF register number, we
2196 * indicate that we want COMPR4 mode - instead of doing the
2197 * usual destination + 1 for the second half we get
2200 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2203 inst
->saturate
= c
->key
.clamp_fragment_color
;
2205 push_force_uncompressed();
2206 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2208 inst
->saturate
= c
->key
.clamp_fragment_color
;
2209 pop_force_uncompressed();
2211 push_force_sechalf();
2212 color
.sechalf
= true;
2213 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2215 inst
->saturate
= c
->key
.clamp_fragment_color
;
2216 pop_force_sechalf();
2217 color
.sechalf
= false;
2223 fs_visitor::emit_fb_writes()
2225 this->current_annotation
= "FB write header";
2226 bool header_present
= true;
2227 /* We can potentially have a message length of up to 15, so we have to set
2228 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2232 int reg_width
= dispatch_width
/ 8;
2233 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2234 bool src0_alpha_to_render_target
= false;
2236 if (dispatch_width
== 16 && do_dual_src
) {
2237 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2238 do_dual_src
= false;
2241 /* From the Sandy Bridge PRM, volume 4, page 198:
2243 * "Dispatched Pixel Enables. One bit per pixel indicating
2244 * which pixels were originally enabled when the thread was
2245 * dispatched. This field is only required for the end-of-
2246 * thread message and on all dual-source messages."
2248 if (intel
->gen
>= 6 &&
2249 !this->fp
->UsesKill
&&
2251 c
->key
.nr_color_regions
== 1) {
2252 header_present
= false;
2255 if (header_present
) {
2256 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2258 c
->key
.nr_color_regions
> 1 &&
2259 c
->key
.sample_alpha_to_coverage
;
2264 if (c
->aa_dest_stencil_reg
) {
2265 push_force_uncompressed();
2266 emit(MOV(fs_reg(MRF
, nr
++),
2267 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2268 pop_force_uncompressed();
2271 /* Reserve space for color. It'll be filled in per MRT below. */
2273 nr
+= 4 * reg_width
;
2276 if (src0_alpha_to_render_target
)
2279 if (c
->source_depth_to_render_target
) {
2280 if (intel
->gen
== 6 && dispatch_width
== 16) {
2281 /* For outputting oDepth on gen6, SIMD8 writes have to be
2282 * used. This would require 8-wide moves of each half to
2283 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2284 * Just bail on doing so for now.
2286 fail("Missing support for simd16 depth writes on gen6\n");
2289 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2290 /* Hand over gl_FragDepth. */
2291 assert(this->frag_depth
.file
!= BAD_FILE
);
2292 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2294 /* Pass through the payload depth. */
2295 emit(MOV(fs_reg(MRF
, nr
),
2296 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2301 if (c
->dest_depth_reg
) {
2302 emit(MOV(fs_reg(MRF
, nr
),
2303 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2308 fs_reg src0
= this->outputs
[0];
2309 fs_reg src1
= this->dual_src_output
;
2311 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2313 for (int i
= 0; i
< 4; i
++) {
2314 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2316 inst
->saturate
= c
->key
.clamp_fragment_color
;
2319 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2321 for (int i
= 0; i
< 4; i
++) {
2322 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2325 inst
->saturate
= c
->key
.clamp_fragment_color
;
2328 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2329 emit_shader_time_end();
2331 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2333 inst
->base_mrf
= base_mrf
;
2334 inst
->mlen
= nr
- base_mrf
;
2336 inst
->header_present
= header_present
;
2338 c
->prog_data
.dual_src_blend
= true;
2339 this->current_annotation
= NULL
;
2343 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2344 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2345 "FB write target %d",
2347 /* If src0_alpha_to_render_target is true, include source zero alpha
2348 * data in RenderTargetWrite message for targets > 0.
2350 int write_color_mrf
= color_mrf
;
2351 if (src0_alpha_to_render_target
&& target
!= 0) {
2353 fs_reg color
= outputs
[0];
2354 color
.reg_offset
+= 3;
2356 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2358 inst
->saturate
= c
->key
.clamp_fragment_color
;
2359 write_color_mrf
= color_mrf
+ reg_width
;
2362 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2363 emit_color_write(target
, i
, write_color_mrf
);
2366 if (target
== c
->key
.nr_color_regions
- 1) {
2369 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2370 emit_shader_time_end();
2373 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2374 inst
->target
= target
;
2375 inst
->base_mrf
= base_mrf
;
2376 if (src0_alpha_to_render_target
&& target
== 0)
2377 inst
->mlen
= nr
- base_mrf
- reg_width
;
2379 inst
->mlen
= nr
- base_mrf
;
2381 inst
->header_present
= header_present
;
2384 if (c
->key
.nr_color_regions
== 0) {
2385 /* Even if there's no color buffers enabled, we still need to send
2386 * alpha out the pipeline to our null renderbuffer to support
2387 * alpha-testing, alpha-to-coverage, and so on.
2389 emit_color_write(0, 3, color_mrf
);
2391 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2392 emit_shader_time_end();
2394 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2395 inst
->base_mrf
= base_mrf
;
2396 inst
->mlen
= nr
- base_mrf
;
2398 inst
->header_present
= header_present
;
2401 this->current_annotation
= NULL
;
2405 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2407 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2411 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2412 emit(MOV(temp
, *reg
));
2417 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2419 if (rvalue
->type
!= glsl_type::bool_type
)
2422 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2423 emit(AND(temp
, *reg
, fs_reg(1)));
2427 fs_visitor::fs_visitor(struct brw_context
*brw
,
2428 struct brw_wm_compile
*c
,
2429 struct gl_shader_program
*shader_prog
,
2430 struct gl_fragment_program
*fp
,
2431 unsigned dispatch_width
)
2432 : dispatch_width(dispatch_width
)
2437 this->shader_prog
= shader_prog
;
2438 this->intel
= &brw
->intel
;
2439 this->ctx
= &intel
->ctx
;
2440 this->mem_ctx
= ralloc_context(NULL
);
2442 shader
= (struct brw_shader
*)
2443 shader_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2446 this->failed
= false;
2447 this->variable_ht
= hash_table_ctor(0,
2448 hash_table_pointer_hash
,
2449 hash_table_pointer_compare
);
2451 memset(this->outputs
, 0, sizeof(this->outputs
));
2452 memset(this->output_components
, 0, sizeof(this->output_components
));
2453 this->first_non_payload_grf
= 0;
2454 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2456 this->current_annotation
= NULL
;
2457 this->base_ir
= NULL
;
2459 this->virtual_grf_sizes
= NULL
;
2460 this->virtual_grf_count
= 0;
2461 this->virtual_grf_array_size
= 0;
2462 this->virtual_grf_start
= NULL
;
2463 this->virtual_grf_end
= NULL
;
2464 this->live_intervals_valid
= false;
2466 this->force_uncompressed_stack
= 0;
2467 this->force_sechalf_stack
= 0;
2469 memset(&this->param_size
, 0, sizeof(this->param_size
));
2472 fs_visitor::~fs_visitor()
2474 ralloc_free(this->mem_ctx
);
2475 hash_table_dtor(this->variable_ht
);