2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_shader_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_shader_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->is_in_uniform_block())
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
204 if (intel
->gen
< 6 || x
.file
!= GRF
|| y
.file
!= GRF
|| a
.file
!= GRF
) {
205 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
206 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
207 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
208 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
210 emit(MUL(y_times_a
, y
, a
));
212 a
.negate
= !a
.negate
;
213 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
214 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
216 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
218 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
219 * we need to reorder the operands.
221 emit(LRP(dst
, a
, y
, x
));
226 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
227 fs_reg src0
, fs_reg src1
)
231 if (intel
->gen
>= 6) {
232 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
233 inst
->conditional_mod
= conditionalmod
;
235 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
237 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
238 inst
->predicate
= BRW_PREDICATE_NORMAL
;
242 /* Instruction selection: Produce a MOV.sat instead of
243 * MIN(MAX(val, 0), 1) when possible.
246 fs_visitor::try_emit_saturate(ir_expression
*ir
)
248 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
253 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
255 sat_val
->accept(this);
256 fs_reg src
= this->result
;
258 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
260 /* If the last instruction from our accept() didn't generate our
261 * src, generate a saturated MOV
263 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
264 if (!modify
|| modify
->regs_written
!= 1) {
265 this->result
= fs_reg(this, ir
->type
);
266 fs_inst
*inst
= emit(MOV(this->result
, src
));
267 inst
->saturate
= true;
269 modify
->saturate
= true;
278 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
280 /* 3-src instructions were introduced in gen6. */
284 /* MAD can only handle floating-point data. */
285 if (ir
->type
!= glsl_type::float_type
)
288 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
289 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
291 if (!mul
|| mul
->operation
!= ir_binop_mul
)
294 if (nonmul
->as_constant() ||
295 mul
->operands
[0]->as_constant() ||
296 mul
->operands
[1]->as_constant())
299 nonmul
->accept(this);
300 fs_reg src0
= this->result
;
302 mul
->operands
[0]->accept(this);
303 fs_reg src1
= this->result
;
305 mul
->operands
[1]->accept(this);
306 fs_reg src2
= this->result
;
308 this->result
= fs_reg(this, ir
->type
);
309 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
315 fs_visitor::visit(ir_expression
*ir
)
317 unsigned int operand
;
321 assert(ir
->get_num_operands() <= 3);
323 if (try_emit_saturate(ir
))
325 if (ir
->operation
== ir_binop_add
) {
326 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
330 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
331 ir
->operands
[operand
]->accept(this);
332 if (this->result
.file
== BAD_FILE
) {
334 fail("Failed to get tree for expression operand:\n");
335 ir
->operands
[operand
]->accept(&v
);
337 op
[operand
] = this->result
;
339 /* Matrix expression operands should have been broken down to vector
340 * operations already.
342 assert(!ir
->operands
[operand
]->type
->is_matrix());
343 /* And then those vector operands should have been broken down to scalar.
345 assert(!ir
->operands
[operand
]->type
->is_vector());
348 /* Storage for our result. If our result goes into an assignment, it will
349 * just get copy-propagated out, so no worries.
351 this->result
= fs_reg(this, ir
->type
);
353 switch (ir
->operation
) {
354 case ir_unop_logic_not
:
355 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
356 * ones complement of the whole register, not just bit 0.
358 emit(XOR(this->result
, op
[0], fs_reg(1)));
361 op
[0].negate
= !op
[0].negate
;
362 this->result
= op
[0];
366 op
[0].negate
= false;
367 this->result
= op
[0];
370 temp
= fs_reg(this, ir
->type
);
372 emit(MOV(this->result
, fs_reg(0.0f
)));
374 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
375 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
376 inst
->predicate
= BRW_PREDICATE_NORMAL
;
378 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
379 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
380 inst
->predicate
= BRW_PREDICATE_NORMAL
;
384 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
388 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
391 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
395 assert(!"not reached: should be handled by ir_explog_to_explog2");
398 case ir_unop_sin_reduced
:
399 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
402 case ir_unop_cos_reduced
:
403 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
407 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
410 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
414 emit(ADD(this->result
, op
[0], op
[1]));
417 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 if (ir
->type
->is_integer()) {
422 /* For integer multiplication, the MUL uses the low 16 bits
423 * of one of the operands (src0 on gen6, src1 on gen7). The
424 * MACH accumulates in the contribution of the upper 16 bits
427 * FINISHME: Emit just the MUL if we know an operand is small
430 if (intel
->gen
>= 7 && dispatch_width
== 16)
431 fail("16-wide explicit accumulator operands unsupported\n");
433 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
435 emit(MUL(acc
, op
[0], op
[1]));
436 emit(MACH(reg_null_d
, op
[0], op
[1]));
437 emit(MOV(this->result
, fs_reg(acc
)));
439 emit(MUL(this->result
, op
[0], op
[1]));
443 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
444 assert(ir
->type
->is_integer());
445 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
448 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
449 assert(ir
->type
->is_integer());
450 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
454 case ir_binop_greater
:
455 case ir_binop_lequal
:
456 case ir_binop_gequal
:
458 case ir_binop_all_equal
:
459 case ir_binop_nequal
:
460 case ir_binop_any_nequal
:
461 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
462 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
464 emit(CMP(this->result
, op
[0], op
[1],
465 brw_conditional_for_comparison(ir
->operation
)));
468 case ir_binop_logic_xor
:
469 emit(XOR(this->result
, op
[0], op
[1]));
472 case ir_binop_logic_or
:
473 emit(OR(this->result
, op
[0], op
[1]));
476 case ir_binop_logic_and
:
477 emit(AND(this->result
, op
[0], op
[1]));
482 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 assert(!"not reached: should be handled by lower_noise");
489 case ir_quadop_vector
:
490 assert(!"not reached: should be handled by lower_quadop_vector");
494 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
498 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
501 case ir_unop_bitcast_i2f
:
502 case ir_unop_bitcast_u2f
:
503 op
[0].type
= BRW_REGISTER_TYPE_F
;
504 this->result
= op
[0];
507 case ir_unop_bitcast_f2u
:
508 op
[0].type
= BRW_REGISTER_TYPE_UD
;
509 this->result
= op
[0];
512 case ir_unop_bitcast_f2i
:
513 op
[0].type
= BRW_REGISTER_TYPE_D
;
514 this->result
= op
[0];
520 emit(MOV(this->result
, op
[0]));
524 inst
= emit(AND(this->result
, op
[0], fs_reg(1)));
527 temp
= fs_reg(this, glsl_type::int_type
);
528 emit(AND(temp
, op
[0], fs_reg(1)));
529 emit(MOV(this->result
, temp
));
533 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
536 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
540 emit(RNDZ(this->result
, op
[0]));
543 op
[0].negate
= !op
[0].negate
;
544 inst
= emit(RNDD(this->result
, op
[0]));
545 this->result
.negate
= true;
548 inst
= emit(RNDD(this->result
, op
[0]));
551 inst
= emit(FRC(this->result
, op
[0]));
553 case ir_unop_round_even
:
554 emit(RNDE(this->result
, op
[0]));
559 resolve_ud_negate(&op
[0]);
560 resolve_ud_negate(&op
[1]);
561 emit_minmax(ir
->operation
== ir_binop_min
?
562 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
563 this->result
, op
[0], op
[1]);
565 case ir_unop_pack_snorm_2x16
:
566 case ir_unop_pack_snorm_4x8
:
567 case ir_unop_pack_unorm_2x16
:
568 case ir_unop_pack_unorm_4x8
:
569 case ir_unop_unpack_snorm_2x16
:
570 case ir_unop_unpack_snorm_4x8
:
571 case ir_unop_unpack_unorm_2x16
:
572 case ir_unop_unpack_unorm_4x8
:
573 case ir_unop_unpack_half_2x16
:
574 case ir_unop_pack_half_2x16
:
575 assert(!"not reached: should be handled by lower_packing_builtins");
577 case ir_unop_unpack_half_2x16_split_x
:
578 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
580 case ir_unop_unpack_half_2x16_split_y
:
581 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
584 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
587 case ir_unop_bit_not
:
588 inst
= emit(NOT(this->result
, op
[0]));
590 case ir_binop_bit_and
:
591 inst
= emit(AND(this->result
, op
[0], op
[1]));
593 case ir_binop_bit_xor
:
594 inst
= emit(XOR(this->result
, op
[0], op
[1]));
596 case ir_binop_bit_or
:
597 inst
= emit(OR(this->result
, op
[0], op
[1]));
600 case ir_binop_lshift
:
601 inst
= emit(SHL(this->result
, op
[0], op
[1]));
604 case ir_binop_rshift
:
605 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
606 inst
= emit(ASR(this->result
, op
[0], op
[1]));
608 inst
= emit(SHR(this->result
, op
[0], op
[1]));
610 case ir_binop_pack_half_2x16_split
:
611 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
613 case ir_binop_ubo_load
: {
614 /* This IR node takes a constant uniform block and a constant or
615 * variable byte offset within the block and loads a vector from that.
617 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
618 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
619 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
621 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
622 packed_consts
.type
= result
.type
;
624 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
625 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
626 packed_consts
, surf_index
, const_offset_reg
));
628 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
629 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
630 /* UBO bools are any nonzero value. We consider bools to be
631 * values with the low bit set to 1. Convert them using CMP.
633 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
634 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
636 emit(MOV(result
, packed_consts
));
639 packed_consts
.smear
++;
642 /* The std140 packing rules don't allow vectors to cross 16-byte
643 * boundaries, and a reg is 32 bytes.
645 assert(packed_consts
.smear
< 8);
648 /* Turn the byte offset into a dword offset. */
649 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
650 emit(SHR(base_offset
, op
[1], fs_reg(2)));
652 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
653 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
656 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
657 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
663 result
.reg_offset
= 0;
668 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
674 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
675 const glsl_type
*type
, bool predicated
)
677 switch (type
->base_type
) {
678 case GLSL_TYPE_FLOAT
:
682 for (unsigned int i
= 0; i
< type
->components(); i
++) {
683 l
.type
= brw_type_for_base_type(type
);
684 r
.type
= brw_type_for_base_type(type
);
686 if (predicated
|| !l
.equals(r
)) {
687 fs_inst
*inst
= emit(MOV(l
, r
));
688 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
695 case GLSL_TYPE_ARRAY
:
696 for (unsigned int i
= 0; i
< type
->length
; i
++) {
697 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
701 case GLSL_TYPE_STRUCT
:
702 for (unsigned int i
= 0; i
< type
->length
; i
++) {
703 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
708 case GLSL_TYPE_SAMPLER
:
712 case GLSL_TYPE_ERROR
:
713 case GLSL_TYPE_INTERFACE
:
714 assert(!"not reached");
719 /* If the RHS processing resulted in an instruction generating a
720 * temporary value, and it would be easy to rewrite the instruction to
721 * generate its result right into the LHS instead, do so. This ends
722 * up reliably removing instructions where it can be tricky to do so
723 * later without real UD chain information.
726 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
729 fs_inst
*pre_rhs_inst
,
730 fs_inst
*last_rhs_inst
)
732 /* Only attempt if we're doing a direct assignment. */
734 !(ir
->lhs
->type
->is_scalar() ||
735 (ir
->lhs
->type
->is_vector() &&
736 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
739 /* Make sure the last instruction generated our source reg. */
740 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
746 /* If last_rhs_inst wrote a different number of components than our LHS,
747 * we can't safely rewrite it.
749 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
752 /* Success! Rewrite the instruction. */
759 fs_visitor::visit(ir_assignment
*ir
)
764 /* FINISHME: arrays on the lhs */
765 ir
->lhs
->accept(this);
768 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
770 ir
->rhs
->accept(this);
773 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
775 assert(l
.file
!= BAD_FILE
);
776 assert(r
.file
!= BAD_FILE
);
778 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
782 emit_bool_to_cond_code(ir
->condition
);
785 if (ir
->lhs
->type
->is_scalar() ||
786 ir
->lhs
->type
->is_vector()) {
787 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
788 if (ir
->write_mask
& (1 << i
)) {
789 inst
= emit(MOV(l
, r
));
791 inst
->predicate
= BRW_PREDICATE_NORMAL
;
797 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
802 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
803 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
813 if (ir
->shadow_comparitor
) {
814 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
815 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
816 coordinate
.reg_offset
++;
818 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
821 if (ir
->op
== ir_tex
) {
822 /* There's no plain shadow compare message, so we use shadow
823 * compare with a bias of 0.0.
825 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
827 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
828 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
831 assert(!"Should not get here.");
834 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
836 } else if (ir
->op
== ir_tex
) {
837 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
838 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
839 coordinate
.reg_offset
++;
841 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
843 } else if (ir
->op
== ir_txd
) {
846 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
847 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
848 coordinate
.reg_offset
++;
850 /* the slots for u and v are always present, but r is optional */
851 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
854 * dPdx = dudx, dvdx, drdx
855 * dPdy = dudy, dvdy, drdy
857 * 1-arg: Does not exist.
859 * 2-arg: dudx dvdx dudy dvdy
860 * dPdx.x dPdx.y dPdy.x dPdy.y
863 * 3-arg: dudx dvdx drdx dudy dvdy drdy
864 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
867 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
868 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
871 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
873 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
874 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
877 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
878 } else if (ir
->op
== ir_txs
) {
879 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
881 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
884 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
885 * instructions. We'll need to do SIMD16 here.
888 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
890 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
891 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
893 coordinate
.reg_offset
++;
896 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
897 * be necessary for TXF (ld), but seems wise to do for all messages.
899 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
900 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
903 /* lod/bias appears after u/v/r. */
906 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
909 /* The unused upper half. */
914 /* Now, since we're doing simd16, the return is 2 interleaved
915 * vec4s where the odd-indexed ones are junk. We'll need to move
916 * this weirdness around to the expected layout.
919 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
921 brw_type_for_base_type(ir
->type
) :
922 BRW_REGISTER_TYPE_F
));
925 fs_inst
*inst
= NULL
;
928 inst
= emit(SHADER_OPCODE_TEX
, dst
);
931 inst
= emit(FS_OPCODE_TXB
, dst
);
934 inst
= emit(SHADER_OPCODE_TXL
, dst
);
937 inst
= emit(SHADER_OPCODE_TXD
, dst
);
940 inst
= emit(SHADER_OPCODE_TXS
, dst
);
943 inst
= emit(SHADER_OPCODE_TXF
, dst
);
946 fail("unrecognized texture opcode");
948 inst
->base_mrf
= base_mrf
;
950 inst
->header_present
= true;
951 inst
->regs_written
= simd16
? 8 : 4;
954 for (int i
= 0; i
< 4; i
++) {
955 emit(MOV(orig_dst
, dst
));
956 orig_dst
.reg_offset
++;
964 /* gen5's sampler has slots for u, v, r, array index, then optional
965 * parameters like shadow comparitor or LOD bias. If optional
966 * parameters aren't present, those base slots are optional and don't
967 * need to be included in the message.
969 * We don't fill in the unnecessary slots regardless, which may look
970 * surprising in the disassembly.
973 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
974 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
979 int reg_width
= dispatch_width
/ 8;
980 bool header_present
= false;
981 const int vector_elements
=
982 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
984 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
985 /* It appears that the ld instruction used for txf does its
986 * address bounds check before adding in the offset. To work
987 * around this, just add the integer offset to the integer texel
988 * coordinate, and don't put the offset in the header.
990 ir_constant
*offset
= ir
->offset
->as_constant();
991 for (int i
= 0; i
< vector_elements
; i
++) {
992 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
994 offset
->value
.i
[i
]));
995 coordinate
.reg_offset
++;
999 /* The offsets set up by the ir_texture visitor are in the
1000 * m1 header, so we can't go headerless.
1002 header_present
= true;
1007 for (int i
= 0; i
< vector_elements
; i
++) {
1008 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1010 coordinate
.reg_offset
++;
1013 mlen
+= vector_elements
* reg_width
;
1015 if (ir
->shadow_comparitor
) {
1016 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1018 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1022 fs_inst
*inst
= NULL
;
1025 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1028 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1029 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1032 inst
= emit(FS_OPCODE_TXB
, dst
);
1035 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1036 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1039 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1042 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1046 * dPdx = dudx, dvdx, drdx
1047 * dPdy = dudy, dvdy, drdy
1049 * Load up these values:
1050 * - dudx dudy dvdx dvdy drdx drdy
1051 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1053 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1054 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1058 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1063 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1067 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1069 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1072 mlen
= header_present
+ 4 * reg_width
;
1073 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1074 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1077 mlen
= header_present
+ 4 * reg_width
;
1080 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1082 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1084 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1087 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1090 inst
->base_mrf
= base_mrf
;
1092 inst
->header_present
= header_present
;
1093 inst
->regs_written
= 4;
1096 fail("Message length >11 disallowed by hardware\n");
1103 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1104 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1105 fs_reg sample_index
)
1109 int reg_width
= dispatch_width
/ 8;
1110 bool header_present
= false;
1113 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1114 /* The offsets set up by the ir_texture visitor are in the
1115 * m1 header, so we can't go headerless.
1117 header_present
= true;
1122 if (ir
->shadow_comparitor
) {
1123 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1127 /* Set up the LOD info */
1133 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1137 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1141 if (dispatch_width
== 16)
1142 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1144 /* Load dPdx and the coordinate together:
1145 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1147 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1148 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1149 coordinate
.reg_offset
++;
1152 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1153 * only derivatives for (u, v, r).
1155 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1156 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1160 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1168 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1172 /* It appears that the ld instruction used for txf does its
1173 * address bounds check before adding in the offset. To work
1174 * around this, just add the integer offset to the integer texel
1175 * coordinate, and don't put the offset in the header.
1178 ir_constant
*offset
= ir
->offset
->as_constant();
1179 offsets
[0] = offset
->value
.i
[0];
1180 offsets
[1] = offset
->value
.i
[1];
1181 offsets
[2] = offset
->value
.i
[2];
1183 memset(offsets
, 0, sizeof(offsets
));
1186 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1187 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1188 coordinate
, offsets
[0]));
1189 coordinate
.reg_offset
++;
1192 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1195 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1196 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1197 coordinate
, offsets
[i
]));
1198 coordinate
.reg_offset
++;
1203 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1206 /* constant zero MCS; we arrange to never actually have a compressed
1207 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1208 * if we ever support texturing from compressed multisample surfaces
1210 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1213 /* there is no offsetting for this message; just copy in the integer
1214 * texture coordinates
1216 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1217 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1219 coordinate
.reg_offset
++;
1225 /* Set up the coordinate (except for cases where it was done above) */
1226 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
&& ir
->op
!= ir_txf_ms
) {
1227 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1228 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1229 coordinate
.reg_offset
++;
1234 /* Generate the SEND */
1235 fs_inst
*inst
= NULL
;
1237 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1238 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1239 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1240 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1241 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1242 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
); break;
1243 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1244 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
); break;
1246 inst
->base_mrf
= base_mrf
;
1248 inst
->header_present
= header_present
;
1249 inst
->regs_written
= 4;
1252 fail("Message length >11 disallowed by hardware\n");
1259 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1260 bool is_rect
, int sampler
, int texunit
)
1262 fs_inst
*inst
= NULL
;
1263 bool needs_gl_clamp
= true;
1264 fs_reg scale_x
, scale_y
;
1266 /* The 965 requires the EU to do the normalization of GL rectangle
1267 * texture coordinates. We use the program parameter state
1268 * tracking to get the scaling factor.
1272 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1273 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1274 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1275 int tokens
[STATE_LENGTH
] = {
1277 STATE_TEXRECT_SCALE
,
1283 if (dispatch_width
== 16) {
1284 fail("rectangle scale uniform setup not supported on 16-wide\n");
1288 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1289 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1291 GLuint index
= _mesa_add_state_reference(params
,
1292 (gl_state_index
*)tokens
);
1293 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1294 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1295 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1296 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1299 /* The 965 requires the EU to do the normalization of GL rectangle
1300 * texture coordinates. We use the program parameter state
1301 * tracking to get the scaling factor.
1303 if (intel
->gen
< 6 && is_rect
) {
1304 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1305 fs_reg src
= coordinate
;
1308 emit(MUL(dst
, src
, scale_x
));
1311 emit(MUL(dst
, src
, scale_y
));
1312 } else if (is_rect
) {
1313 /* On gen6+, the sampler handles the rectangle coordinates
1314 * natively, without needing rescaling. But that means we have
1315 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1316 * not [0, 1] like the default case below.
1318 needs_gl_clamp
= false;
1320 for (int i
= 0; i
< 2; i
++) {
1321 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1322 fs_reg chan
= coordinate
;
1323 chan
.reg_offset
+= i
;
1325 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1326 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1328 /* Our parameter comes in as 1.0/width or 1.0/height,
1329 * because that's what people normally want for doing
1330 * texture rectangle handling. We need width or height
1331 * for clamping, but we don't care enough to make a new
1332 * parameter type, so just invert back.
1334 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1335 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1336 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1338 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1339 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1344 if (ir
->coordinate
&& needs_gl_clamp
) {
1345 for (unsigned int i
= 0;
1346 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1347 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1348 fs_reg chan
= coordinate
;
1349 chan
.reg_offset
+= i
;
1351 fs_inst
*inst
= emit(MOV(chan
, chan
));
1352 inst
->saturate
= true;
1360 fs_visitor::visit(ir_texture
*ir
)
1362 fs_inst
*inst
= NULL
;
1365 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, &fp
->Base
);
1366 /* FINISHME: We're failing to recompile our programs when the sampler is
1367 * updated. This only matters for the texture rectangle scale parameters
1368 * (pre-gen6, or gen6+ with GL_CLAMP).
1370 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1372 /* Should be lowered by do_lower_texture_projection */
1373 assert(!ir
->projector
);
1375 /* Generate code to compute all the subexpression trees. This has to be
1376 * done before loading any values into MRFs for the sampler message since
1377 * generating these values may involve SEND messages that need the MRFs.
1380 if (ir
->coordinate
) {
1381 ir
->coordinate
->accept(this);
1383 coordinate
= rescale_texcoord(ir
, this->result
,
1384 ir
->sampler
->type
->sampler_dimensionality
==
1385 GLSL_SAMPLER_DIM_RECT
,
1389 fs_reg shadow_comparitor
;
1390 if (ir
->shadow_comparitor
) {
1391 ir
->shadow_comparitor
->accept(this);
1392 shadow_comparitor
= this->result
;
1395 fs_reg lod
, lod2
, sample_index
;
1401 ir
->lod_info
.bias
->accept(this);
1405 ir
->lod_info
.grad
.dPdx
->accept(this);
1408 ir
->lod_info
.grad
.dPdy
->accept(this);
1409 lod2
= this->result
;
1414 ir
->lod_info
.lod
->accept(this);
1418 ir
->lod_info
.sample_index
->accept(this);
1419 sample_index
= this->result
;
1423 /* Writemasking doesn't eliminate channels on SIMD8 texture
1424 * samples, so don't worry about them.
1426 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1428 if (intel
->gen
>= 7) {
1429 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1430 lod
, lod2
, sample_index
);
1431 } else if (intel
->gen
>= 5) {
1432 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1433 lod
, lod2
, sample_index
);
1435 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1439 /* The header is set up by generate_tex() when necessary. */
1440 inst
->src
[0] = reg_undef
;
1442 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1443 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1445 inst
->sampler
= sampler
;
1447 if (ir
->shadow_comparitor
)
1448 inst
->shadow_compare
= true;
1450 /* fixup #layers for cube map arrays */
1451 if (ir
->op
== ir_txs
) {
1452 glsl_type
const *type
= ir
->sampler
->type
;
1453 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1454 type
->sampler_array
) {
1456 depth
.reg_offset
= 2;
1457 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1461 swizzle_result(ir
, dst
, sampler
);
1465 * Swizzle the result of a texture result. This is necessary for
1466 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1469 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1471 this->result
= orig_val
;
1473 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
)
1476 if (ir
->type
== glsl_type::float_type
) {
1477 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1478 assert(ir
->sampler
->type
->sampler_shadow
);
1479 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1480 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1482 for (int i
= 0; i
< 4; i
++) {
1483 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1484 fs_reg l
= swizzled_result
;
1487 if (swiz
== SWIZZLE_ZERO
) {
1488 emit(MOV(l
, fs_reg(0.0f
)));
1489 } else if (swiz
== SWIZZLE_ONE
) {
1490 emit(MOV(l
, fs_reg(1.0f
)));
1492 fs_reg r
= orig_val
;
1493 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1497 this->result
= swizzled_result
;
1502 fs_visitor::visit(ir_swizzle
*ir
)
1504 ir
->val
->accept(this);
1505 fs_reg val
= this->result
;
1507 if (ir
->type
->vector_elements
== 1) {
1508 this->result
.reg_offset
+= ir
->mask
.x
;
1512 fs_reg result
= fs_reg(this, ir
->type
);
1513 this->result
= result
;
1515 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1516 fs_reg channel
= val
;
1534 channel
.reg_offset
+= swiz
;
1535 emit(MOV(result
, channel
));
1536 result
.reg_offset
++;
1541 fs_visitor::visit(ir_discard
*ir
)
1543 assert(ir
->condition
== NULL
); /* FINISHME */
1545 /* We track our discarded pixels in f0.1. By predicating on it, we can
1546 * update just the flag bits that aren't yet discarded. By emitting a
1547 * CMP of g0 != g0, all our currently executing channels will get turned
1550 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1551 BRW_REGISTER_TYPE_UW
));
1552 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1553 BRW_CONDITIONAL_NZ
));
1554 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1555 cmp
->flag_subreg
= 1;
1557 if (intel
->gen
>= 6) {
1558 /* For performance, after a discard, jump to the end of the shader.
1559 * However, many people will do foliage by discarding based on a
1560 * texture's alpha mask, and then continue on to texture with the
1561 * remaining pixels. To avoid trashing the derivatives for those
1562 * texture samples, we'll only jump if all of the pixels in the subspan
1563 * have been discarded.
1565 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1566 discard_jump
->flag_subreg
= 1;
1567 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1568 discard_jump
->predicate_inverse
= true;
1573 fs_visitor::visit(ir_constant
*ir
)
1575 /* Set this->result to reg at the bottom of the function because some code
1576 * paths will cause this visitor to be applied to other fields. This will
1577 * cause the value stored in this->result to be modified.
1579 * Make reg constant so that it doesn't get accidentally modified along the
1580 * way. Yes, I actually had this problem. :(
1582 const fs_reg
reg(this, ir
->type
);
1583 fs_reg dst_reg
= reg
;
1585 if (ir
->type
->is_array()) {
1586 const unsigned size
= type_size(ir
->type
->fields
.array
);
1588 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1589 ir
->array_elements
[i
]->accept(this);
1590 fs_reg src_reg
= this->result
;
1592 dst_reg
.type
= src_reg
.type
;
1593 for (unsigned j
= 0; j
< size
; j
++) {
1594 emit(MOV(dst_reg
, src_reg
));
1595 src_reg
.reg_offset
++;
1596 dst_reg
.reg_offset
++;
1599 } else if (ir
->type
->is_record()) {
1600 foreach_list(node
, &ir
->components
) {
1601 ir_constant
*const field
= (ir_constant
*) node
;
1602 const unsigned size
= type_size(field
->type
);
1604 field
->accept(this);
1605 fs_reg src_reg
= this->result
;
1607 dst_reg
.type
= src_reg
.type
;
1608 for (unsigned j
= 0; j
< size
; j
++) {
1609 emit(MOV(dst_reg
, src_reg
));
1610 src_reg
.reg_offset
++;
1611 dst_reg
.reg_offset
++;
1615 const unsigned size
= type_size(ir
->type
);
1617 for (unsigned i
= 0; i
< size
; i
++) {
1618 switch (ir
->type
->base_type
) {
1619 case GLSL_TYPE_FLOAT
:
1620 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1622 case GLSL_TYPE_UINT
:
1623 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1626 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1628 case GLSL_TYPE_BOOL
:
1629 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1632 assert(!"Non-float/uint/int/bool constant");
1634 dst_reg
.reg_offset
++;
1642 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1644 ir_expression
*expr
= ir
->as_expression();
1650 assert(expr
->get_num_operands() <= 2);
1651 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1652 assert(expr
->operands
[i
]->type
->is_scalar());
1654 expr
->operands
[i
]->accept(this);
1655 op
[i
] = this->result
;
1657 resolve_ud_negate(&op
[i
]);
1660 switch (expr
->operation
) {
1661 case ir_unop_logic_not
:
1662 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1663 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1666 case ir_binop_logic_xor
:
1667 case ir_binop_logic_or
:
1668 case ir_binop_logic_and
:
1672 if (intel
->gen
>= 6) {
1673 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1675 inst
= emit(MOV(reg_null_f
, op
[0]));
1676 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1681 if (intel
->gen
>= 6) {
1682 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1684 inst
= emit(MOV(reg_null_d
, op
[0]));
1685 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1689 case ir_binop_greater
:
1690 case ir_binop_gequal
:
1692 case ir_binop_lequal
:
1693 case ir_binop_equal
:
1694 case ir_binop_all_equal
:
1695 case ir_binop_nequal
:
1696 case ir_binop_any_nequal
:
1697 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1698 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1700 emit(CMP(reg_null_d
, op
[0], op
[1],
1701 brw_conditional_for_comparison(expr
->operation
)));
1705 assert(!"not reached");
1706 fail("bad cond code\n");
1715 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1716 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1720 * Emit a gen6 IF statement with the comparison folded into the IF
1724 fs_visitor::emit_if_gen6(ir_if
*ir
)
1726 ir_expression
*expr
= ir
->condition
->as_expression();
1733 assert(expr
->get_num_operands() <= 2);
1734 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1735 assert(expr
->operands
[i
]->type
->is_scalar());
1737 expr
->operands
[i
]->accept(this);
1738 op
[i
] = this->result
;
1741 switch (expr
->operation
) {
1742 case ir_unop_logic_not
:
1743 case ir_binop_logic_xor
:
1744 case ir_binop_logic_or
:
1745 case ir_binop_logic_and
:
1746 /* For operations on bool arguments, only the low bit of the bool is
1747 * valid, and the others are undefined. Fall back to the condition
1753 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1754 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1758 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1761 case ir_binop_greater
:
1762 case ir_binop_gequal
:
1764 case ir_binop_lequal
:
1765 case ir_binop_equal
:
1766 case ir_binop_all_equal
:
1767 case ir_binop_nequal
:
1768 case ir_binop_any_nequal
:
1769 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1770 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1772 emit(IF(op
[0], op
[1],
1773 brw_conditional_for_comparison(expr
->operation
)));
1776 assert(!"not reached");
1777 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1778 fail("bad condition\n");
1783 emit_bool_to_cond_code(ir
->condition
);
1784 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1785 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1789 fs_visitor::visit(ir_if
*ir
)
1791 if (intel
->gen
< 6 && dispatch_width
== 16) {
1792 fail("Can't support (non-uniform) control flow on 16-wide\n");
1795 /* Don't point the annotation at the if statement, because then it plus
1796 * the then and else blocks get printed.
1798 this->base_ir
= ir
->condition
;
1800 if (intel
->gen
== 6) {
1803 emit_bool_to_cond_code(ir
->condition
);
1805 emit(IF(BRW_PREDICATE_NORMAL
));
1808 foreach_list(node
, &ir
->then_instructions
) {
1809 ir_instruction
*ir
= (ir_instruction
*)node
;
1815 if (!ir
->else_instructions
.is_empty()) {
1816 emit(BRW_OPCODE_ELSE
);
1818 foreach_list(node
, &ir
->else_instructions
) {
1819 ir_instruction
*ir
= (ir_instruction
*)node
;
1826 emit(BRW_OPCODE_ENDIF
);
1830 fs_visitor::visit(ir_loop
*ir
)
1832 fs_reg counter
= reg_undef
;
1834 if (intel
->gen
< 6 && dispatch_width
== 16) {
1835 fail("Can't support (non-uniform) control flow on 16-wide\n");
1839 this->base_ir
= ir
->counter
;
1840 ir
->counter
->accept(this);
1841 counter
= *(variable_storage(ir
->counter
));
1844 this->base_ir
= ir
->from
;
1845 ir
->from
->accept(this);
1847 emit(MOV(counter
, this->result
));
1851 this->base_ir
= NULL
;
1852 emit(BRW_OPCODE_DO
);
1855 this->base_ir
= ir
->to
;
1856 ir
->to
->accept(this);
1858 emit(CMP(reg_null_d
, counter
, this->result
,
1859 brw_conditional_for_comparison(ir
->cmp
)));
1861 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1862 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1865 foreach_list(node
, &ir
->body_instructions
) {
1866 ir_instruction
*ir
= (ir_instruction
*)node
;
1872 if (ir
->increment
) {
1873 this->base_ir
= ir
->increment
;
1874 ir
->increment
->accept(this);
1875 emit(ADD(counter
, counter
, this->result
));
1878 this->base_ir
= NULL
;
1879 emit(BRW_OPCODE_WHILE
);
1883 fs_visitor::visit(ir_loop_jump
*ir
)
1886 case ir_loop_jump::jump_break
:
1887 emit(BRW_OPCODE_BREAK
);
1889 case ir_loop_jump::jump_continue
:
1890 emit(BRW_OPCODE_CONTINUE
);
1896 fs_visitor::visit(ir_call
*ir
)
1898 assert(!"FINISHME");
1902 fs_visitor::visit(ir_return
*ir
)
1904 assert(!"FINISHME");
1908 fs_visitor::visit(ir_function
*ir
)
1910 /* Ignore function bodies other than main() -- we shouldn't see calls to
1911 * them since they should all be inlined before we get to ir_to_mesa.
1913 if (strcmp(ir
->name
, "main") == 0) {
1914 const ir_function_signature
*sig
;
1917 sig
= ir
->matching_signature(&empty
);
1921 foreach_list(node
, &sig
->body
) {
1922 ir_instruction
*ir
= (ir_instruction
*)node
;
1931 fs_visitor::visit(ir_function_signature
*ir
)
1933 assert(!"not reached");
1938 fs_visitor::emit(fs_inst inst
)
1940 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1947 fs_visitor::emit(fs_inst
*inst
)
1949 if (force_uncompressed_stack
> 0)
1950 inst
->force_uncompressed
= true;
1951 else if (force_sechalf_stack
> 0)
1952 inst
->force_sechalf
= true;
1954 inst
->annotation
= this->current_annotation
;
1955 inst
->ir
= this->base_ir
;
1957 this->instructions
.push_tail(inst
);
1963 fs_visitor::emit(exec_list list
)
1965 foreach_list_safe(node
, &list
) {
1966 fs_inst
*inst
= (fs_inst
*)node
;
1972 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1974 fs_visitor::emit_dummy_fs()
1976 int reg_width
= dispatch_width
/ 8;
1978 /* Everyone's favorite color. */
1979 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
1980 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
1981 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
1982 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
1985 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1986 write
->base_mrf
= 2;
1987 write
->mlen
= 4 * reg_width
;
1991 /* The register location here is relative to the start of the URB
1992 * data. It will get adjusted to be a real location before
1993 * generate_code() time.
1996 fs_visitor::interp_reg(int location
, int channel
)
1998 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1999 int stride
= (channel
& 1) * 4;
2001 assert(urb_setup
[location
] != -1);
2003 return brw_vec1_grf(regnr
, stride
);
2006 /** Emits the interpolation for the varying inputs. */
2008 fs_visitor::emit_interpolation_setup_gen4()
2010 this->current_annotation
= "compute pixel centers";
2011 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2012 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2013 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2014 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2016 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2017 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2019 this->current_annotation
= "compute pixel deltas from v0";
2021 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2022 fs_reg(this, glsl_type::vec2_type
);
2023 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2024 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2025 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2027 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2028 fs_reg(this, glsl_type::float_type
);
2029 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2030 fs_reg(this, glsl_type::float_type
);
2032 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2033 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2034 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2035 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2037 this->current_annotation
= "compute pos.w and 1/pos.w";
2038 /* Compute wpos.w. It's always in our setup, since it's needed to
2039 * interpolate the other attributes.
2041 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2042 emit(FS_OPCODE_LINTERP
, wpos_w
,
2043 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2044 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2045 interp_reg(VARYING_SLOT_POS
, 3));
2046 /* Compute the pixel 1/W value from wpos.w. */
2047 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2048 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2049 this->current_annotation
= NULL
;
2052 /** Emits the interpolation for the varying inputs. */
2054 fs_visitor::emit_interpolation_setup_gen6()
2056 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2058 /* If the pixel centers end up used, the setup is the same as for gen4. */
2059 this->current_annotation
= "compute pixel centers";
2060 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2061 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2062 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2063 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2064 emit(ADD(int_pixel_x
,
2065 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2066 fs_reg(brw_imm_v(0x10101010))));
2067 emit(ADD(int_pixel_y
,
2068 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2069 fs_reg(brw_imm_v(0x11001100))));
2071 /* As of gen6, we can no longer mix float and int sources. We have
2072 * to turn the integer pixel centers into floats for their actual
2075 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2076 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2077 emit(MOV(this->pixel_x
, int_pixel_x
));
2078 emit(MOV(this->pixel_y
, int_pixel_y
));
2080 this->current_annotation
= "compute pos.w";
2081 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2082 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2083 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2085 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2086 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2087 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2088 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2091 this->current_annotation
= NULL
;
2095 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2097 int reg_width
= dispatch_width
/ 8;
2099 fs_reg color
= outputs
[target
];
2102 /* If there's no color data to be written, skip it. */
2103 if (color
.file
== BAD_FILE
)
2106 color
.reg_offset
+= index
;
2108 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2109 /* SIMD8 write looks like:
2115 * gen6 SIMD16 DP write looks like:
2125 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2128 inst
->saturate
= c
->key
.clamp_fragment_color
;
2130 /* pre-gen6 SIMD16 single source DP write looks like:
2140 if (brw
->has_compr4
) {
2141 /* By setting the high bit of the MRF register number, we
2142 * indicate that we want COMPR4 mode - instead of doing the
2143 * usual destination + 1 for the second half we get
2146 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2149 inst
->saturate
= c
->key
.clamp_fragment_color
;
2151 push_force_uncompressed();
2152 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2154 inst
->saturate
= c
->key
.clamp_fragment_color
;
2155 pop_force_uncompressed();
2157 push_force_sechalf();
2158 color
.sechalf
= true;
2159 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2161 inst
->saturate
= c
->key
.clamp_fragment_color
;
2162 pop_force_sechalf();
2163 color
.sechalf
= false;
2169 fs_visitor::emit_fb_writes()
2171 this->current_annotation
= "FB write header";
2172 bool header_present
= true;
2173 /* We can potentially have a message length of up to 15, so we have to set
2174 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2178 int reg_width
= dispatch_width
/ 8;
2179 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2180 bool src0_alpha_to_render_target
= false;
2182 if (dispatch_width
== 16 && do_dual_src
) {
2183 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2184 do_dual_src
= false;
2187 /* From the Sandy Bridge PRM, volume 4, page 198:
2189 * "Dispatched Pixel Enables. One bit per pixel indicating
2190 * which pixels were originally enabled when the thread was
2191 * dispatched. This field is only required for the end-of-
2192 * thread message and on all dual-source messages."
2194 if (intel
->gen
>= 6 &&
2195 !this->fp
->UsesKill
&&
2197 c
->key
.nr_color_regions
== 1) {
2198 header_present
= false;
2201 if (header_present
) {
2202 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2204 c
->key
.nr_color_regions
> 1 &&
2205 c
->key
.sample_alpha_to_coverage
;
2210 if (c
->aa_dest_stencil_reg
) {
2211 push_force_uncompressed();
2212 emit(MOV(fs_reg(MRF
, nr
++),
2213 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2214 pop_force_uncompressed();
2217 /* Reserve space for color. It'll be filled in per MRT below. */
2219 nr
+= 4 * reg_width
;
2222 if (src0_alpha_to_render_target
)
2225 if (c
->source_depth_to_render_target
) {
2226 if (intel
->gen
== 6 && dispatch_width
== 16) {
2227 /* For outputting oDepth on gen6, SIMD8 writes have to be
2228 * used. This would require 8-wide moves of each half to
2229 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2230 * Just bail on doing so for now.
2232 fail("Missing support for simd16 depth writes on gen6\n");
2235 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2236 /* Hand over gl_FragDepth. */
2237 assert(this->frag_depth
.file
!= BAD_FILE
);
2238 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2240 /* Pass through the payload depth. */
2241 emit(MOV(fs_reg(MRF
, nr
),
2242 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2247 if (c
->dest_depth_reg
) {
2248 emit(MOV(fs_reg(MRF
, nr
),
2249 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2254 fs_reg src0
= this->outputs
[0];
2255 fs_reg src1
= this->dual_src_output
;
2257 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2259 for (int i
= 0; i
< 4; i
++) {
2260 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2262 inst
->saturate
= c
->key
.clamp_fragment_color
;
2265 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2267 for (int i
= 0; i
< 4; i
++) {
2268 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2271 inst
->saturate
= c
->key
.clamp_fragment_color
;
2274 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2275 emit_shader_time_end();
2277 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2279 inst
->base_mrf
= base_mrf
;
2280 inst
->mlen
= nr
- base_mrf
;
2282 inst
->header_present
= header_present
;
2284 c
->prog_data
.dual_src_blend
= true;
2285 this->current_annotation
= NULL
;
2289 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2290 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2291 "FB write target %d",
2293 /* If src0_alpha_to_render_target is true, include source zero alpha
2294 * data in RenderTargetWrite message for targets > 0.
2296 int write_color_mrf
= color_mrf
;
2297 if (src0_alpha_to_render_target
&& target
!= 0) {
2299 fs_reg color
= outputs
[0];
2300 color
.reg_offset
+= 3;
2302 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2304 inst
->saturate
= c
->key
.clamp_fragment_color
;
2305 write_color_mrf
= color_mrf
+ reg_width
;
2308 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2309 emit_color_write(target
, i
, write_color_mrf
);
2312 if (target
== c
->key
.nr_color_regions
- 1) {
2315 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2316 emit_shader_time_end();
2319 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2320 inst
->target
= target
;
2321 inst
->base_mrf
= base_mrf
;
2322 if (src0_alpha_to_render_target
&& target
== 0)
2323 inst
->mlen
= nr
- base_mrf
- reg_width
;
2325 inst
->mlen
= nr
- base_mrf
;
2327 inst
->header_present
= header_present
;
2330 if (c
->key
.nr_color_regions
== 0) {
2331 /* Even if there's no color buffers enabled, we still need to send
2332 * alpha out the pipeline to our null renderbuffer to support
2333 * alpha-testing, alpha-to-coverage, and so on.
2335 emit_color_write(0, 3, color_mrf
);
2337 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2338 emit_shader_time_end();
2340 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2341 inst
->base_mrf
= base_mrf
;
2342 inst
->mlen
= nr
- base_mrf
;
2344 inst
->header_present
= header_present
;
2347 this->current_annotation
= NULL
;
2351 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2353 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2357 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2358 emit(MOV(temp
, *reg
));
2363 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2365 if (rvalue
->type
!= glsl_type::bool_type
)
2368 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2369 emit(AND(temp
, *reg
, fs_reg(1)));
2373 fs_visitor::fs_visitor(struct brw_context
*brw
,
2374 struct brw_wm_compile
*c
,
2375 struct gl_shader_program
*shader_prog
,
2376 struct gl_fragment_program
*fp
,
2377 unsigned dispatch_width
)
2378 : dispatch_width(dispatch_width
)
2383 this->shader_prog
= shader_prog
;
2384 this->intel
= &brw
->intel
;
2385 this->ctx
= &intel
->ctx
;
2386 this->mem_ctx
= ralloc_context(NULL
);
2388 shader
= (struct brw_shader
*)
2389 shader_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2392 this->failed
= false;
2393 this->variable_ht
= hash_table_ctor(0,
2394 hash_table_pointer_hash
,
2395 hash_table_pointer_compare
);
2397 memset(this->outputs
, 0, sizeof(this->outputs
));
2398 memset(this->output_components
, 0, sizeof(this->output_components
));
2399 this->first_non_payload_grf
= 0;
2400 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2402 this->current_annotation
= NULL
;
2403 this->base_ir
= NULL
;
2405 this->virtual_grf_sizes
= NULL
;
2406 this->virtual_grf_count
= 0;
2407 this->virtual_grf_array_size
= 0;
2408 this->virtual_grf_def
= NULL
;
2409 this->virtual_grf_use
= NULL
;
2410 this->live_intervals_valid
= false;
2412 this->force_uncompressed_stack
= 0;
2413 this->force_sechalf_stack
= 0;
2415 memset(&this->param_size
, 0, sizeof(this->param_size
));
2418 fs_visitor::~fs_visitor()
2420 ralloc_free(this->mem_ctx
);
2421 hash_table_dtor(this->variable_ht
);