2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_shader_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_shader_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->is_in_uniform_block())
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
203 fs_reg src0
, fs_reg src1
)
207 if (intel
->gen
>= 6) {
208 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
209 inst
->conditional_mod
= conditionalmod
;
211 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
213 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
218 /* Instruction selection: Produce a MOV.sat instead of
219 * MIN(MAX(val, 0), 1) when possible.
222 fs_visitor::try_emit_saturate(ir_expression
*ir
)
224 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
229 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
231 sat_val
->accept(this);
232 fs_reg src
= this->result
;
234 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
236 /* If the last instruction from our accept() didn't generate our
237 * src, generate a saturated MOV
239 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
240 if (!modify
|| modify
->regs_written() != 1) {
241 this->result
= fs_reg(this, ir
->type
);
242 fs_inst
*inst
= emit(MOV(this->result
, src
));
243 inst
->saturate
= true;
245 modify
->saturate
= true;
254 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
256 /* 3-src instructions were introduced in gen6. */
260 /* MAD can only handle floating-point data. */
261 if (ir
->type
!= glsl_type::float_type
)
264 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
265 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
267 if (!mul
|| mul
->operation
!= ir_binop_mul
)
270 if (nonmul
->as_constant() ||
271 mul
->operands
[0]->as_constant() ||
272 mul
->operands
[1]->as_constant())
275 nonmul
->accept(this);
276 fs_reg src0
= this->result
;
278 mul
->operands
[0]->accept(this);
279 fs_reg src1
= this->result
;
281 mul
->operands
[1]->accept(this);
282 fs_reg src2
= this->result
;
284 this->result
= fs_reg(this, ir
->type
);
285 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
291 fs_visitor::visit(ir_expression
*ir
)
293 unsigned int operand
;
297 assert(ir
->get_num_operands() <= 2);
299 if (try_emit_saturate(ir
))
301 if (ir
->operation
== ir_binop_add
) {
302 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
306 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
307 ir
->operands
[operand
]->accept(this);
308 if (this->result
.file
== BAD_FILE
) {
310 fail("Failed to get tree for expression operand:\n");
311 ir
->operands
[operand
]->accept(&v
);
313 op
[operand
] = this->result
;
315 /* Matrix expression operands should have been broken down to vector
316 * operations already.
318 assert(!ir
->operands
[operand
]->type
->is_matrix());
319 /* And then those vector operands should have been broken down to scalar.
321 assert(!ir
->operands
[operand
]->type
->is_vector());
324 /* Storage for our result. If our result goes into an assignment, it will
325 * just get copy-propagated out, so no worries.
327 this->result
= fs_reg(this, ir
->type
);
329 switch (ir
->operation
) {
330 case ir_unop_logic_not
:
331 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
332 * ones complement of the whole register, not just bit 0.
334 emit(XOR(this->result
, op
[0], fs_reg(1)));
337 op
[0].negate
= !op
[0].negate
;
338 this->result
= op
[0];
342 op
[0].negate
= false;
343 this->result
= op
[0];
346 temp
= fs_reg(this, ir
->type
);
348 emit(MOV(this->result
, fs_reg(0.0f
)));
350 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
351 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
352 inst
->predicate
= BRW_PREDICATE_NORMAL
;
354 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
355 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
356 inst
->predicate
= BRW_PREDICATE_NORMAL
;
360 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
364 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
367 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
371 assert(!"not reached: should be handled by ir_explog_to_explog2");
374 case ir_unop_sin_reduced
:
375 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
378 case ir_unop_cos_reduced
:
379 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
383 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
386 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
390 emit(ADD(this->result
, op
[0], op
[1]));
393 assert(!"not reached: should be handled by ir_sub_to_add_neg");
397 if (ir
->type
->is_integer()) {
398 /* For integer multiplication, the MUL uses the low 16 bits
399 * of one of the operands (src0 on gen6, src1 on gen7). The
400 * MACH accumulates in the contribution of the upper 16 bits
403 * FINISHME: Emit just the MUL if we know an operand is small
406 if (intel
->gen
>= 7 && dispatch_width
== 16)
407 fail("16-wide explicit accumulator operands unsupported\n");
409 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
411 emit(MUL(acc
, op
[0], op
[1]));
412 emit(MACH(reg_null_d
, op
[0], op
[1]));
413 emit(MOV(this->result
, fs_reg(acc
)));
415 emit(MUL(this->result
, op
[0], op
[1]));
419 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
420 assert(ir
->type
->is_integer());
421 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
424 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
425 assert(ir
->type
->is_integer());
426 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
430 case ir_binop_greater
:
431 case ir_binop_lequal
:
432 case ir_binop_gequal
:
434 case ir_binop_all_equal
:
435 case ir_binop_nequal
:
436 case ir_binop_any_nequal
:
437 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
438 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
440 emit(CMP(this->result
, op
[0], op
[1],
441 brw_conditional_for_comparison(ir
->operation
)));
444 case ir_binop_logic_xor
:
445 emit(XOR(this->result
, op
[0], op
[1]));
448 case ir_binop_logic_or
:
449 emit(OR(this->result
, op
[0], op
[1]));
452 case ir_binop_logic_and
:
453 emit(AND(this->result
, op
[0], op
[1]));
458 assert(!"not reached: should be handled by brw_fs_channel_expressions");
462 assert(!"not reached: should be handled by lower_noise");
465 case ir_quadop_vector
:
466 assert(!"not reached: should be handled by lower_quadop_vector");
470 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
474 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
477 case ir_unop_bitcast_i2f
:
478 case ir_unop_bitcast_u2f
:
479 op
[0].type
= BRW_REGISTER_TYPE_F
;
480 this->result
= op
[0];
483 case ir_unop_bitcast_f2u
:
484 op
[0].type
= BRW_REGISTER_TYPE_UD
;
485 this->result
= op
[0];
488 case ir_unop_bitcast_f2i
:
489 op
[0].type
= BRW_REGISTER_TYPE_D
;
490 this->result
= op
[0];
496 emit(MOV(this->result
, op
[0]));
500 inst
= emit(AND(this->result
, op
[0], fs_reg(1)));
503 temp
= fs_reg(this, glsl_type::int_type
);
504 emit(AND(temp
, op
[0], fs_reg(1)));
505 emit(MOV(this->result
, temp
));
509 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
512 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
516 emit(RNDZ(this->result
, op
[0]));
519 op
[0].negate
= !op
[0].negate
;
520 inst
= emit(RNDD(this->result
, op
[0]));
521 this->result
.negate
= true;
524 inst
= emit(RNDD(this->result
, op
[0]));
527 inst
= emit(FRC(this->result
, op
[0]));
529 case ir_unop_round_even
:
530 emit(RNDE(this->result
, op
[0]));
535 resolve_ud_negate(&op
[0]);
536 resolve_ud_negate(&op
[1]);
537 emit_minmax(ir
->operation
== ir_binop_min
?
538 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
539 this->result
, op
[0], op
[1]);
541 case ir_unop_pack_snorm_2x16
:
542 case ir_unop_pack_snorm_4x8
:
543 case ir_unop_pack_unorm_2x16
:
544 case ir_unop_pack_unorm_4x8
:
545 case ir_unop_unpack_snorm_2x16
:
546 case ir_unop_unpack_snorm_4x8
:
547 case ir_unop_unpack_unorm_2x16
:
548 case ir_unop_unpack_unorm_4x8
:
549 case ir_unop_unpack_half_2x16
:
550 case ir_unop_pack_half_2x16
:
551 assert(!"not reached: should be handled by lower_packing_builtins");
553 case ir_unop_unpack_half_2x16_split_x
:
554 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
556 case ir_unop_unpack_half_2x16_split_y
:
557 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
560 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
563 case ir_unop_bit_not
:
564 inst
= emit(NOT(this->result
, op
[0]));
566 case ir_binop_bit_and
:
567 inst
= emit(AND(this->result
, op
[0], op
[1]));
569 case ir_binop_bit_xor
:
570 inst
= emit(XOR(this->result
, op
[0], op
[1]));
572 case ir_binop_bit_or
:
573 inst
= emit(OR(this->result
, op
[0], op
[1]));
576 case ir_binop_lshift
:
577 inst
= emit(SHL(this->result
, op
[0], op
[1]));
580 case ir_binop_rshift
:
581 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
582 inst
= emit(ASR(this->result
, op
[0], op
[1]));
584 inst
= emit(SHR(this->result
, op
[0], op
[1]));
586 case ir_binop_pack_half_2x16_split
:
587 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
589 case ir_binop_ubo_load
:
590 /* This IR node takes a constant uniform block and a constant or
591 * variable byte offset within the block and loads a vector from that.
593 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
594 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
595 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
597 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
598 packed_consts
.type
= result
.type
;
600 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
601 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
602 packed_consts
, surf_index
, const_offset_reg
));
604 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
605 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
606 /* UBO bools are any nonzero value. We consider bools to be
607 * values with the low bit set to 1. Convert them using CMP.
609 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
610 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
612 emit(MOV(result
, packed_consts
));
615 packed_consts
.smear
++;
618 /* The std140 packing rules don't allow vectors to cross 16-byte
619 * boundaries, and a reg is 32 bytes.
621 assert(packed_consts
.smear
< 8);
624 /* Turn the byte offset into a dword offset. */
625 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
626 emit(SHR(base_offset
, op
[1], fs_reg(2)));
628 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
629 fs_reg offset
= fs_reg(this, glsl_type::int_type
);
630 emit(ADD(offset
, base_offset
, fs_reg(i
)));
631 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
, offset
));
633 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
634 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
640 result
.reg_offset
= 0;
646 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
647 const glsl_type
*type
, bool predicated
)
649 switch (type
->base_type
) {
650 case GLSL_TYPE_FLOAT
:
654 for (unsigned int i
= 0; i
< type
->components(); i
++) {
655 l
.type
= brw_type_for_base_type(type
);
656 r
.type
= brw_type_for_base_type(type
);
658 if (predicated
|| !l
.equals(r
)) {
659 fs_inst
*inst
= emit(MOV(l
, r
));
660 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
667 case GLSL_TYPE_ARRAY
:
668 for (unsigned int i
= 0; i
< type
->length
; i
++) {
669 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
673 case GLSL_TYPE_STRUCT
:
674 for (unsigned int i
= 0; i
< type
->length
; i
++) {
675 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
680 case GLSL_TYPE_SAMPLER
:
684 case GLSL_TYPE_ERROR
:
685 case GLSL_TYPE_INTERFACE
:
686 assert(!"not reached");
691 /* If the RHS processing resulted in an instruction generating a
692 * temporary value, and it would be easy to rewrite the instruction to
693 * generate its result right into the LHS instead, do so. This ends
694 * up reliably removing instructions where it can be tricky to do so
695 * later without real UD chain information.
698 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
701 fs_inst
*pre_rhs_inst
,
702 fs_inst
*last_rhs_inst
)
704 /* Only attempt if we're doing a direct assignment. */
706 !(ir
->lhs
->type
->is_scalar() ||
707 (ir
->lhs
->type
->is_vector() &&
708 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
711 /* Make sure the last instruction generated our source reg. */
712 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
718 /* If last_rhs_inst wrote a different number of components than our LHS,
719 * we can't safely rewrite it.
721 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written())
724 /* Success! Rewrite the instruction. */
731 fs_visitor::visit(ir_assignment
*ir
)
736 /* FINISHME: arrays on the lhs */
737 ir
->lhs
->accept(this);
740 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
742 ir
->rhs
->accept(this);
745 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
747 assert(l
.file
!= BAD_FILE
);
748 assert(r
.file
!= BAD_FILE
);
750 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
754 emit_bool_to_cond_code(ir
->condition
);
757 if (ir
->lhs
->type
->is_scalar() ||
758 ir
->lhs
->type
->is_vector()) {
759 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
760 if (ir
->write_mask
& (1 << i
)) {
761 inst
= emit(MOV(l
, r
));
763 inst
->predicate
= BRW_PREDICATE_NORMAL
;
769 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
774 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
775 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
785 if (ir
->shadow_comparitor
) {
786 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
787 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
788 coordinate
.reg_offset
++;
790 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
793 if (ir
->op
== ir_tex
) {
794 /* There's no plain shadow compare message, so we use shadow
795 * compare with a bias of 0.0.
797 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
799 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
800 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
803 assert(!"Should not get here.");
806 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
808 } else if (ir
->op
== ir_tex
) {
809 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
810 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
811 coordinate
.reg_offset
++;
813 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
815 } else if (ir
->op
== ir_txd
) {
818 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
819 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
820 coordinate
.reg_offset
++;
822 /* the slots for u and v are always present, but r is optional */
823 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
826 * dPdx = dudx, dvdx, drdx
827 * dPdy = dudy, dvdy, drdy
829 * 1-arg: Does not exist.
831 * 2-arg: dudx dvdx dudy dvdy
832 * dPdx.x dPdx.y dPdy.x dPdy.y
835 * 3-arg: dudx dvdx drdx dudy dvdy drdy
836 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
839 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
840 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
843 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
845 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
846 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
849 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
850 } else if (ir
->op
== ir_txs
) {
851 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
853 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
856 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
857 * instructions. We'll need to do SIMD16 here.
860 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
862 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
863 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
865 coordinate
.reg_offset
++;
868 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
869 * be necessary for TXF (ld), but seems wise to do for all messages.
871 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
872 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
875 /* lod/bias appears after u/v/r. */
878 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
881 /* The unused upper half. */
886 /* Now, since we're doing simd16, the return is 2 interleaved
887 * vec4s where the odd-indexed ones are junk. We'll need to move
888 * this weirdness around to the expected layout.
891 const glsl_type
*vec_type
=
892 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
893 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
894 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
895 : BRW_REGISTER_TYPE_F
;
898 fs_inst
*inst
= NULL
;
901 inst
= emit(SHADER_OPCODE_TEX
, dst
);
904 inst
= emit(FS_OPCODE_TXB
, dst
);
907 inst
= emit(SHADER_OPCODE_TXL
, dst
);
910 inst
= emit(SHADER_OPCODE_TXD
, dst
);
913 inst
= emit(SHADER_OPCODE_TXS
, dst
);
916 inst
= emit(SHADER_OPCODE_TXF
, dst
);
919 inst
->base_mrf
= base_mrf
;
921 inst
->header_present
= true;
924 for (int i
= 0; i
< 4; i
++) {
925 emit(MOV(orig_dst
, dst
));
926 orig_dst
.reg_offset
++;
934 /* gen5's sampler has slots for u, v, r, array index, then optional
935 * parameters like shadow comparitor or LOD bias. If optional
936 * parameters aren't present, those base slots are optional and don't
937 * need to be included in the message.
939 * We don't fill in the unnecessary slots regardless, which may look
940 * surprising in the disassembly.
943 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
944 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
948 int reg_width
= dispatch_width
/ 8;
949 bool header_present
= false;
950 const int vector_elements
=
951 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
953 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
954 /* It appears that the ld instruction used for txf does its
955 * address bounds check before adding in the offset. To work
956 * around this, just add the integer offset to the integer texel
957 * coordinate, and don't put the offset in the header.
959 ir_constant
*offset
= ir
->offset
->as_constant();
960 for (int i
= 0; i
< vector_elements
; i
++) {
961 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
963 offset
->value
.i
[i
]));
964 coordinate
.reg_offset
++;
968 /* The offsets set up by the ir_texture visitor are in the
969 * m1 header, so we can't go headerless.
971 header_present
= true;
976 for (int i
= 0; i
< vector_elements
; i
++) {
977 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
979 coordinate
.reg_offset
++;
982 mlen
+= vector_elements
* reg_width
;
984 if (ir
->shadow_comparitor
) {
985 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
987 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
991 fs_inst
*inst
= NULL
;
994 inst
= emit(SHADER_OPCODE_TEX
, dst
);
997 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
998 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1001 inst
= emit(FS_OPCODE_TXB
, dst
);
1004 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1005 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1008 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1011 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1015 * dPdx = dudx, dvdx, drdx
1016 * dPdy = dudy, dvdy, drdy
1018 * Load up these values:
1019 * - dudx dudy dvdx dvdy drdx drdy
1020 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1022 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1023 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1027 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1032 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1036 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1038 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1041 mlen
= header_present
+ 4 * reg_width
;
1043 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
1045 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1048 inst
->base_mrf
= base_mrf
;
1050 inst
->header_present
= header_present
;
1053 fail("Message length >11 disallowed by hardware\n");
1060 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1061 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
1065 int reg_width
= dispatch_width
/ 8;
1066 bool header_present
= false;
1069 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1070 /* The offsets set up by the ir_texture visitor are in the
1071 * m1 header, so we can't go headerless.
1073 header_present
= true;
1078 if (ir
->shadow_comparitor
) {
1079 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1083 /* Set up the LOD info */
1088 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1092 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1096 if (dispatch_width
== 16)
1097 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1099 /* Load dPdx and the coordinate together:
1100 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1102 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1103 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1104 coordinate
.reg_offset
++;
1107 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1108 * only derivatives for (u, v, r).
1110 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1111 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1115 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1123 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1127 /* It appears that the ld instruction used for txf does its
1128 * address bounds check before adding in the offset. To work
1129 * around this, just add the integer offset to the integer texel
1130 * coordinate, and don't put the offset in the header.
1133 ir_constant
*offset
= ir
->offset
->as_constant();
1134 offsets
[0] = offset
->value
.i
[0];
1135 offsets
[1] = offset
->value
.i
[1];
1136 offsets
[2] = offset
->value
.i
[2];
1138 memset(offsets
, 0, sizeof(offsets
));
1141 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1142 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1143 coordinate
, offsets
[0]));
1144 coordinate
.reg_offset
++;
1147 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1150 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1151 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1152 coordinate
, offsets
[i
]));
1153 coordinate
.reg_offset
++;
1159 /* Set up the coordinate (except for cases where it was done above) */
1160 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1161 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1162 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1163 coordinate
.reg_offset
++;
1168 /* Generate the SEND */
1169 fs_inst
*inst
= NULL
;
1171 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1172 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1173 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1174 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1175 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1176 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1178 inst
->base_mrf
= base_mrf
;
1180 inst
->header_present
= header_present
;
1183 fail("Message length >11 disallowed by hardware\n");
1190 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1191 bool is_rect
, int sampler
, int texunit
)
1193 fs_inst
*inst
= NULL
;
1194 bool needs_gl_clamp
= true;
1195 fs_reg scale_x
, scale_y
;
1197 /* The 965 requires the EU to do the normalization of GL rectangle
1198 * texture coordinates. We use the program parameter state
1199 * tracking to get the scaling factor.
1203 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1204 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1205 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1206 int tokens
[STATE_LENGTH
] = {
1208 STATE_TEXRECT_SCALE
,
1214 if (dispatch_width
== 16) {
1215 fail("rectangle scale uniform setup not supported on 16-wide\n");
1219 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1220 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1222 GLuint index
= _mesa_add_state_reference(params
,
1223 (gl_state_index
*)tokens
);
1224 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1225 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1226 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1227 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1230 /* The 965 requires the EU to do the normalization of GL rectangle
1231 * texture coordinates. We use the program parameter state
1232 * tracking to get the scaling factor.
1234 if (intel
->gen
< 6 && is_rect
) {
1235 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1236 fs_reg src
= coordinate
;
1239 emit(MUL(dst
, src
, scale_x
));
1242 emit(MUL(dst
, src
, scale_y
));
1243 } else if (is_rect
) {
1244 /* On gen6+, the sampler handles the rectangle coordinates
1245 * natively, without needing rescaling. But that means we have
1246 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1247 * not [0, 1] like the default case below.
1249 needs_gl_clamp
= false;
1251 for (int i
= 0; i
< 2; i
++) {
1252 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1253 fs_reg chan
= coordinate
;
1254 chan
.reg_offset
+= i
;
1256 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1257 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1259 /* Our parameter comes in as 1.0/width or 1.0/height,
1260 * because that's what people normally want for doing
1261 * texture rectangle handling. We need width or height
1262 * for clamping, but we don't care enough to make a new
1263 * parameter type, so just invert back.
1265 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1266 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1267 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1269 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1270 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1275 if (ir
->coordinate
&& needs_gl_clamp
) {
1276 for (unsigned int i
= 0;
1277 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1278 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1279 fs_reg chan
= coordinate
;
1280 chan
.reg_offset
+= i
;
1282 fs_inst
*inst
= emit(MOV(chan
, chan
));
1283 inst
->saturate
= true;
1291 fs_visitor::visit(ir_texture
*ir
)
1293 fs_inst
*inst
= NULL
;
1295 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1296 /* FINISHME: We're failing to recompile our programs when the sampler is
1297 * updated. This only matters for the texture rectangle scale parameters
1298 * (pre-gen6, or gen6+ with GL_CLAMP).
1300 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1302 /* Should be lowered by do_lower_texture_projection */
1303 assert(!ir
->projector
);
1305 /* Generate code to compute all the subexpression trees. This has to be
1306 * done before loading any values into MRFs for the sampler message since
1307 * generating these values may involve SEND messages that need the MRFs.
1310 if (ir
->coordinate
) {
1311 ir
->coordinate
->accept(this);
1313 coordinate
= rescale_texcoord(ir
, this->result
,
1314 ir
->sampler
->type
->sampler_dimensionality
==
1315 GLSL_SAMPLER_DIM_RECT
,
1319 fs_reg shadow_comparitor
;
1320 if (ir
->shadow_comparitor
) {
1321 ir
->shadow_comparitor
->accept(this);
1322 shadow_comparitor
= this->result
;
1330 ir
->lod_info
.bias
->accept(this);
1334 ir
->lod_info
.grad
.dPdx
->accept(this);
1337 ir
->lod_info
.grad
.dPdy
->accept(this);
1338 lod2
= this->result
;
1343 ir
->lod_info
.lod
->accept(this);
1348 /* Writemasking doesn't eliminate channels on SIMD8 texture
1349 * samples, so don't worry about them.
1351 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1353 if (intel
->gen
>= 7) {
1354 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1356 } else if (intel
->gen
>= 5) {
1357 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1360 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1364 /* The header is set up by generate_tex() when necessary. */
1365 inst
->src
[0] = reg_undef
;
1367 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1368 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1370 inst
->sampler
= sampler
;
1372 if (ir
->shadow_comparitor
)
1373 inst
->shadow_compare
= true;
1375 /* fixup #layers for cube map arrays */
1376 if (ir
->op
== ir_txs
) {
1377 glsl_type
const *type
= ir
->sampler
->type
;
1378 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1379 type
->sampler_array
) {
1381 depth
.reg_offset
= 2;
1382 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1386 swizzle_result(ir
, dst
, sampler
);
1390 * Swizzle the result of a texture result. This is necessary for
1391 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1394 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1396 this->result
= orig_val
;
1398 if (ir
->op
== ir_txs
)
1401 if (ir
->type
== glsl_type::float_type
) {
1402 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1403 assert(ir
->sampler
->type
->sampler_shadow
);
1404 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1405 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1407 for (int i
= 0; i
< 4; i
++) {
1408 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1409 fs_reg l
= swizzled_result
;
1412 if (swiz
== SWIZZLE_ZERO
) {
1413 emit(MOV(l
, fs_reg(0.0f
)));
1414 } else if (swiz
== SWIZZLE_ONE
) {
1415 emit(MOV(l
, fs_reg(1.0f
)));
1417 fs_reg r
= orig_val
;
1418 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1422 this->result
= swizzled_result
;
1427 fs_visitor::visit(ir_swizzle
*ir
)
1429 ir
->val
->accept(this);
1430 fs_reg val
= this->result
;
1432 if (ir
->type
->vector_elements
== 1) {
1433 this->result
.reg_offset
+= ir
->mask
.x
;
1437 fs_reg result
= fs_reg(this, ir
->type
);
1438 this->result
= result
;
1440 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1441 fs_reg channel
= val
;
1459 channel
.reg_offset
+= swiz
;
1460 emit(MOV(result
, channel
));
1461 result
.reg_offset
++;
1466 fs_visitor::visit(ir_discard
*ir
)
1468 assert(ir
->condition
== NULL
); /* FINISHME */
1470 /* We track our discarded pixels in f0.1. By predicating on it, we can
1471 * update just the flag bits that aren't yet discarded. By emitting a
1472 * CMP of g0 != g0, all our currently executing channels will get turned
1475 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1476 BRW_REGISTER_TYPE_UW
));
1477 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1478 BRW_CONDITIONAL_NZ
));
1479 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1480 cmp
->flag_subreg
= 1;
1482 if (intel
->gen
>= 6) {
1483 /* For performance, after a discard, jump to the end of the shader.
1484 * However, many people will do foliage by discarding based on a
1485 * texture's alpha mask, and then continue on to texture with the
1486 * remaining pixels. To avoid trashing the derivatives for those
1487 * texture samples, we'll only jump if all of the pixels in the subspan
1488 * have been discarded.
1490 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1491 discard_jump
->flag_subreg
= 1;
1492 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1493 discard_jump
->predicate_inverse
= true;
1498 fs_visitor::visit(ir_constant
*ir
)
1500 /* Set this->result to reg at the bottom of the function because some code
1501 * paths will cause this visitor to be applied to other fields. This will
1502 * cause the value stored in this->result to be modified.
1504 * Make reg constant so that it doesn't get accidentally modified along the
1505 * way. Yes, I actually had this problem. :(
1507 const fs_reg
reg(this, ir
->type
);
1508 fs_reg dst_reg
= reg
;
1510 if (ir
->type
->is_array()) {
1511 const unsigned size
= type_size(ir
->type
->fields
.array
);
1513 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1514 ir
->array_elements
[i
]->accept(this);
1515 fs_reg src_reg
= this->result
;
1517 dst_reg
.type
= src_reg
.type
;
1518 for (unsigned j
= 0; j
< size
; j
++) {
1519 emit(MOV(dst_reg
, src_reg
));
1520 src_reg
.reg_offset
++;
1521 dst_reg
.reg_offset
++;
1524 } else if (ir
->type
->is_record()) {
1525 foreach_list(node
, &ir
->components
) {
1526 ir_constant
*const field
= (ir_constant
*) node
;
1527 const unsigned size
= type_size(field
->type
);
1529 field
->accept(this);
1530 fs_reg src_reg
= this->result
;
1532 dst_reg
.type
= src_reg
.type
;
1533 for (unsigned j
= 0; j
< size
; j
++) {
1534 emit(MOV(dst_reg
, src_reg
));
1535 src_reg
.reg_offset
++;
1536 dst_reg
.reg_offset
++;
1540 const unsigned size
= type_size(ir
->type
);
1542 for (unsigned i
= 0; i
< size
; i
++) {
1543 switch (ir
->type
->base_type
) {
1544 case GLSL_TYPE_FLOAT
:
1545 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1547 case GLSL_TYPE_UINT
:
1548 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1551 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1553 case GLSL_TYPE_BOOL
:
1554 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1557 assert(!"Non-float/uint/int/bool constant");
1559 dst_reg
.reg_offset
++;
1567 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1569 ir_expression
*expr
= ir
->as_expression();
1575 assert(expr
->get_num_operands() <= 2);
1576 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1577 assert(expr
->operands
[i
]->type
->is_scalar());
1579 expr
->operands
[i
]->accept(this);
1580 op
[i
] = this->result
;
1582 resolve_ud_negate(&op
[i
]);
1585 switch (expr
->operation
) {
1586 case ir_unop_logic_not
:
1587 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1588 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1591 case ir_binop_logic_xor
:
1592 case ir_binop_logic_or
:
1593 case ir_binop_logic_and
:
1597 if (intel
->gen
>= 6) {
1598 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1600 inst
= emit(MOV(reg_null_f
, op
[0]));
1601 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1606 if (intel
->gen
>= 6) {
1607 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1609 inst
= emit(MOV(reg_null_d
, op
[0]));
1610 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1614 case ir_binop_greater
:
1615 case ir_binop_gequal
:
1617 case ir_binop_lequal
:
1618 case ir_binop_equal
:
1619 case ir_binop_all_equal
:
1620 case ir_binop_nequal
:
1621 case ir_binop_any_nequal
:
1622 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1623 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1625 emit(CMP(reg_null_d
, op
[0], op
[1],
1626 brw_conditional_for_comparison(expr
->operation
)));
1630 assert(!"not reached");
1631 fail("bad cond code\n");
1640 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1641 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1645 * Emit a gen6 IF statement with the comparison folded into the IF
1649 fs_visitor::emit_if_gen6(ir_if
*ir
)
1651 ir_expression
*expr
= ir
->condition
->as_expression();
1658 assert(expr
->get_num_operands() <= 2);
1659 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1660 assert(expr
->operands
[i
]->type
->is_scalar());
1662 expr
->operands
[i
]->accept(this);
1663 op
[i
] = this->result
;
1666 switch (expr
->operation
) {
1667 case ir_unop_logic_not
:
1668 case ir_binop_logic_xor
:
1669 case ir_binop_logic_or
:
1670 case ir_binop_logic_and
:
1671 /* For operations on bool arguments, only the low bit of the bool is
1672 * valid, and the others are undefined. Fall back to the condition
1678 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1679 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1683 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1686 case ir_binop_greater
:
1687 case ir_binop_gequal
:
1689 case ir_binop_lequal
:
1690 case ir_binop_equal
:
1691 case ir_binop_all_equal
:
1692 case ir_binop_nequal
:
1693 case ir_binop_any_nequal
:
1694 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1695 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1697 emit(IF(op
[0], op
[1],
1698 brw_conditional_for_comparison(expr
->operation
)));
1701 assert(!"not reached");
1702 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1703 fail("bad condition\n");
1708 emit_bool_to_cond_code(ir
->condition
);
1709 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1710 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1714 fs_visitor::visit(ir_if
*ir
)
1716 if (intel
->gen
< 6 && dispatch_width
== 16) {
1717 fail("Can't support (non-uniform) control flow on 16-wide\n");
1720 /* Don't point the annotation at the if statement, because then it plus
1721 * the then and else blocks get printed.
1723 this->base_ir
= ir
->condition
;
1725 if (intel
->gen
== 6) {
1728 emit_bool_to_cond_code(ir
->condition
);
1730 emit(IF(BRW_PREDICATE_NORMAL
));
1733 foreach_list(node
, &ir
->then_instructions
) {
1734 ir_instruction
*ir
= (ir_instruction
*)node
;
1740 if (!ir
->else_instructions
.is_empty()) {
1741 emit(BRW_OPCODE_ELSE
);
1743 foreach_list(node
, &ir
->else_instructions
) {
1744 ir_instruction
*ir
= (ir_instruction
*)node
;
1751 emit(BRW_OPCODE_ENDIF
);
1755 fs_visitor::visit(ir_loop
*ir
)
1757 fs_reg counter
= reg_undef
;
1759 if (intel
->gen
< 6 && dispatch_width
== 16) {
1760 fail("Can't support (non-uniform) control flow on 16-wide\n");
1764 this->base_ir
= ir
->counter
;
1765 ir
->counter
->accept(this);
1766 counter
= *(variable_storage(ir
->counter
));
1769 this->base_ir
= ir
->from
;
1770 ir
->from
->accept(this);
1772 emit(MOV(counter
, this->result
));
1776 this->base_ir
= NULL
;
1777 emit(BRW_OPCODE_DO
);
1780 this->base_ir
= ir
->to
;
1781 ir
->to
->accept(this);
1783 emit(CMP(reg_null_d
, counter
, this->result
,
1784 brw_conditional_for_comparison(ir
->cmp
)));
1786 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1787 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1790 foreach_list(node
, &ir
->body_instructions
) {
1791 ir_instruction
*ir
= (ir_instruction
*)node
;
1797 if (ir
->increment
) {
1798 this->base_ir
= ir
->increment
;
1799 ir
->increment
->accept(this);
1800 emit(ADD(counter
, counter
, this->result
));
1803 this->base_ir
= NULL
;
1804 emit(BRW_OPCODE_WHILE
);
1808 fs_visitor::visit(ir_loop_jump
*ir
)
1811 case ir_loop_jump::jump_break
:
1812 emit(BRW_OPCODE_BREAK
);
1814 case ir_loop_jump::jump_continue
:
1815 emit(BRW_OPCODE_CONTINUE
);
1821 fs_visitor::visit(ir_call
*ir
)
1823 assert(!"FINISHME");
1827 fs_visitor::visit(ir_return
*ir
)
1829 assert(!"FINISHME");
1833 fs_visitor::visit(ir_function
*ir
)
1835 /* Ignore function bodies other than main() -- we shouldn't see calls to
1836 * them since they should all be inlined before we get to ir_to_mesa.
1838 if (strcmp(ir
->name
, "main") == 0) {
1839 const ir_function_signature
*sig
;
1842 sig
= ir
->matching_signature(&empty
);
1846 foreach_list(node
, &sig
->body
) {
1847 ir_instruction
*ir
= (ir_instruction
*)node
;
1856 fs_visitor::visit(ir_function_signature
*ir
)
1858 assert(!"not reached");
1863 fs_visitor::emit(fs_inst inst
)
1865 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1872 fs_visitor::emit(fs_inst
*inst
)
1874 if (force_uncompressed_stack
> 0)
1875 inst
->force_uncompressed
= true;
1876 else if (force_sechalf_stack
> 0)
1877 inst
->force_sechalf
= true;
1879 inst
->annotation
= this->current_annotation
;
1880 inst
->ir
= this->base_ir
;
1882 this->instructions
.push_tail(inst
);
1888 fs_visitor::emit(exec_list list
)
1890 foreach_list_safe(node
, &list
) {
1891 fs_inst
*inst
= (fs_inst
*)node
;
1897 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1899 fs_visitor::emit_dummy_fs()
1901 int reg_width
= dispatch_width
/ 8;
1903 /* Everyone's favorite color. */
1904 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
1905 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
1906 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
1907 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
1910 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1911 write
->base_mrf
= 2;
1912 write
->mlen
= 4 * reg_width
;
1916 /* The register location here is relative to the start of the URB
1917 * data. It will get adjusted to be a real location before
1918 * generate_code() time.
1921 fs_visitor::interp_reg(int location
, int channel
)
1923 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1924 int stride
= (channel
& 1) * 4;
1926 assert(urb_setup
[location
] != -1);
1928 return brw_vec1_grf(regnr
, stride
);
1931 /** Emits the interpolation for the varying inputs. */
1933 fs_visitor::emit_interpolation_setup_gen4()
1935 this->current_annotation
= "compute pixel centers";
1936 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1937 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1938 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1939 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1941 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1942 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1944 this->current_annotation
= "compute pixel deltas from v0";
1946 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1947 fs_reg(this, glsl_type::vec2_type
);
1948 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1949 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1950 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1952 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1953 fs_reg(this, glsl_type::float_type
);
1954 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1955 fs_reg(this, glsl_type::float_type
);
1957 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1958 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
1959 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1960 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
1962 this->current_annotation
= "compute pos.w and 1/pos.w";
1963 /* Compute wpos.w. It's always in our setup, since it's needed to
1964 * interpolate the other attributes.
1966 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1967 emit(FS_OPCODE_LINTERP
, wpos_w
,
1968 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1969 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1970 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1971 /* Compute the pixel 1/W value from wpos.w. */
1972 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1973 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1974 this->current_annotation
= NULL
;
1977 /** Emits the interpolation for the varying inputs. */
1979 fs_visitor::emit_interpolation_setup_gen6()
1981 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1983 /* If the pixel centers end up used, the setup is the same as for gen4. */
1984 this->current_annotation
= "compute pixel centers";
1985 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1986 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1987 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1988 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1989 emit(ADD(int_pixel_x
,
1990 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1991 fs_reg(brw_imm_v(0x10101010))));
1992 emit(ADD(int_pixel_y
,
1993 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1994 fs_reg(brw_imm_v(0x11001100))));
1996 /* As of gen6, we can no longer mix float and int sources. We have
1997 * to turn the integer pixel centers into floats for their actual
2000 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2001 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2002 emit(MOV(this->pixel_x
, int_pixel_x
));
2003 emit(MOV(this->pixel_y
, int_pixel_y
));
2005 this->current_annotation
= "compute pos.w";
2006 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2007 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2008 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2010 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2011 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2012 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2013 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2016 this->current_annotation
= NULL
;
2020 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2022 int reg_width
= dispatch_width
/ 8;
2024 fs_reg color
= outputs
[target
];
2027 /* If there's no color data to be written, skip it. */
2028 if (color
.file
== BAD_FILE
)
2031 color
.reg_offset
+= index
;
2033 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2034 /* SIMD8 write looks like:
2040 * gen6 SIMD16 DP write looks like:
2050 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2053 inst
->saturate
= c
->key
.clamp_fragment_color
;
2055 /* pre-gen6 SIMD16 single source DP write looks like:
2065 if (brw
->has_compr4
) {
2066 /* By setting the high bit of the MRF register number, we
2067 * indicate that we want COMPR4 mode - instead of doing the
2068 * usual destination + 1 for the second half we get
2071 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2074 inst
->saturate
= c
->key
.clamp_fragment_color
;
2076 push_force_uncompressed();
2077 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2079 inst
->saturate
= c
->key
.clamp_fragment_color
;
2080 pop_force_uncompressed();
2082 push_force_sechalf();
2083 color
.sechalf
= true;
2084 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2086 inst
->saturate
= c
->key
.clamp_fragment_color
;
2087 pop_force_sechalf();
2088 color
.sechalf
= false;
2094 fs_visitor::emit_fb_writes()
2096 this->current_annotation
= "FB write header";
2097 bool header_present
= true;
2098 /* We can potentially have a message length of up to 15, so we have to set
2099 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2103 int reg_width
= dispatch_width
/ 8;
2104 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2105 bool src0_alpha_to_render_target
= false;
2107 if (dispatch_width
== 16 && do_dual_src
) {
2108 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2109 do_dual_src
= false;
2112 /* From the Sandy Bridge PRM, volume 4, page 198:
2114 * "Dispatched Pixel Enables. One bit per pixel indicating
2115 * which pixels were originally enabled when the thread was
2116 * dispatched. This field is only required for the end-of-
2117 * thread message and on all dual-source messages."
2119 if (intel
->gen
>= 6 &&
2120 !this->fp
->UsesKill
&&
2122 c
->key
.nr_color_regions
== 1) {
2123 header_present
= false;
2126 if (header_present
) {
2127 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2129 c
->key
.nr_color_regions
> 1 &&
2130 c
->key
.sample_alpha_to_coverage
;
2135 if (c
->aa_dest_stencil_reg
) {
2136 push_force_uncompressed();
2137 emit(MOV(fs_reg(MRF
, nr
++),
2138 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2139 pop_force_uncompressed();
2142 /* Reserve space for color. It'll be filled in per MRT below. */
2144 nr
+= 4 * reg_width
;
2147 if (src0_alpha_to_render_target
)
2150 if (c
->source_depth_to_render_target
) {
2151 if (intel
->gen
== 6 && dispatch_width
== 16) {
2152 /* For outputting oDepth on gen6, SIMD8 writes have to be
2153 * used. This would require 8-wide moves of each half to
2154 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2155 * Just bail on doing so for now.
2157 fail("Missing support for simd16 depth writes on gen6\n");
2160 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2161 /* Hand over gl_FragDepth. */
2162 assert(this->frag_depth
.file
!= BAD_FILE
);
2163 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2165 /* Pass through the payload depth. */
2166 emit(MOV(fs_reg(MRF
, nr
),
2167 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2172 if (c
->dest_depth_reg
) {
2173 emit(MOV(fs_reg(MRF
, nr
),
2174 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2179 fs_reg src0
= this->outputs
[0];
2180 fs_reg src1
= this->dual_src_output
;
2182 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2184 for (int i
= 0; i
< 4; i
++) {
2185 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2187 inst
->saturate
= c
->key
.clamp_fragment_color
;
2190 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2192 for (int i
= 0; i
< 4; i
++) {
2193 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2196 inst
->saturate
= c
->key
.clamp_fragment_color
;
2199 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2201 inst
->base_mrf
= base_mrf
;
2202 inst
->mlen
= nr
- base_mrf
;
2204 inst
->header_present
= header_present
;
2206 c
->prog_data
.dual_src_blend
= true;
2207 this->current_annotation
= NULL
;
2211 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2212 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2213 "FB write target %d",
2215 /* If src0_alpha_to_render_target is true, include source zero alpha
2216 * data in RenderTargetWrite message for targets > 0.
2218 int write_color_mrf
= color_mrf
;
2219 if (src0_alpha_to_render_target
&& target
!= 0) {
2221 fs_reg color
= outputs
[0];
2222 color
.reg_offset
+= 3;
2224 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2226 inst
->saturate
= c
->key
.clamp_fragment_color
;
2227 write_color_mrf
= color_mrf
+ reg_width
;
2230 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2231 emit_color_write(target
, i
, write_color_mrf
);
2233 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2234 inst
->target
= target
;
2235 inst
->base_mrf
= base_mrf
;
2236 if (src0_alpha_to_render_target
&& target
== 0)
2237 inst
->mlen
= nr
- base_mrf
- reg_width
;
2239 inst
->mlen
= nr
- base_mrf
;
2240 if (target
== c
->key
.nr_color_regions
- 1)
2242 inst
->header_present
= header_present
;
2245 if (c
->key
.nr_color_regions
== 0) {
2246 /* Even if there's no color buffers enabled, we still need to send
2247 * alpha out the pipeline to our null renderbuffer to support
2248 * alpha-testing, alpha-to-coverage, and so on.
2250 emit_color_write(0, 3, color_mrf
);
2252 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2253 inst
->base_mrf
= base_mrf
;
2254 inst
->mlen
= nr
- base_mrf
;
2256 inst
->header_present
= header_present
;
2259 this->current_annotation
= NULL
;
2263 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2265 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2269 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2270 emit(MOV(temp
, *reg
));
2275 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2277 if (rvalue
->type
!= glsl_type::bool_type
)
2280 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2281 emit(AND(temp
, *reg
, fs_reg(1)));
2285 fs_visitor::fs_visitor(struct brw_context
*brw
,
2286 struct brw_wm_compile
*c
,
2287 struct gl_shader_program
*prog
,
2288 struct gl_fragment_program
*fp
,
2289 unsigned dispatch_width
)
2290 : dispatch_width(dispatch_width
)
2296 this->intel
= &brw
->intel
;
2297 this->ctx
= &intel
->ctx
;
2298 this->mem_ctx
= ralloc_context(NULL
);
2300 shader
= (struct brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2303 this->failed
= false;
2304 this->variable_ht
= hash_table_ctor(0,
2305 hash_table_pointer_hash
,
2306 hash_table_pointer_compare
);
2308 memset(this->outputs
, 0, sizeof(this->outputs
));
2309 memset(this->output_components
, 0, sizeof(this->output_components
));
2310 this->first_non_payload_grf
= 0;
2311 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2313 this->current_annotation
= NULL
;
2314 this->base_ir
= NULL
;
2316 this->virtual_grf_sizes
= NULL
;
2317 this->virtual_grf_count
= 0;
2318 this->virtual_grf_array_size
= 0;
2319 this->virtual_grf_def
= NULL
;
2320 this->virtual_grf_use
= NULL
;
2321 this->live_intervals_valid
= false;
2323 this->force_uncompressed_stack
= 0;
2324 this->force_sechalf_stack
= 0;
2326 memset(&this->param_size
, 0, sizeof(this->param_size
));
2329 fs_visitor::~fs_visitor()
2331 ralloc_free(this->mem_ctx
);
2332 hash_table_dtor(this->variable_ht
);