2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
82 bool is_rect
, uint32_t sampler
, int texunit
)
84 bool needs_gl_clamp
= true;
85 fs_reg scale_x
, scale_y
;
87 /* The 965 requires the EU to do the normalization of GL rectangle
88 * texture coordinates. We use the program parameter state
89 * tracking to get the scaling factor.
93 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
94 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
95 struct gl_program_parameter_list
*params
= prog
->Parameters
;
96 int tokens
[STATE_LENGTH
] = {
104 no16("rectangle scale uniform setup not supported on SIMD16\n");
105 if (dispatch_width
== 16) {
109 GLuint index
= _mesa_add_state_reference(params
,
110 (gl_state_index
*)tokens
);
111 /* Try to find existing copies of the texrect scale uniforms. */
112 for (unsigned i
= 0; i
< uniforms
; i
++) {
113 if (stage_prog_data
->param
[i
] ==
114 &prog
->Parameters
->ParameterValues
[index
][0]) {
115 scale_x
= fs_reg(UNIFORM
, i
);
116 scale_y
= fs_reg(UNIFORM
, i
+ 1);
121 /* If we didn't already set them up, do so now. */
122 if (scale_x
.file
== BAD_FILE
) {
123 scale_x
= fs_reg(UNIFORM
, uniforms
);
124 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
126 stage_prog_data
->param
[uniforms
++] =
127 &prog
->Parameters
->ParameterValues
[index
][0];
128 stage_prog_data
->param
[uniforms
++] =
129 &prog
->Parameters
->ParameterValues
[index
][1];
133 /* The 965 requires the EU to do the normalization of GL rectangle
134 * texture coordinates. We use the program parameter state
135 * tracking to get the scaling factor.
137 if (devinfo
->gen
< 6 && is_rect
) {
138 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
139 fs_reg src
= coordinate
;
142 bld
.MUL(dst
, src
, scale_x
);
143 dst
= offset(dst
, bld
, 1);
144 src
= offset(src
, bld
, 1);
145 bld
.MUL(dst
, src
, scale_y
);
146 } else if (is_rect
) {
147 /* On gen6+, the sampler handles the rectangle coordinates
148 * natively, without needing rescaling. But that means we have
149 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
150 * not [0, 1] like the default case below.
152 needs_gl_clamp
= false;
154 for (int i
= 0; i
< 2; i
++) {
155 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
156 fs_reg chan
= coordinate
;
157 chan
= offset(chan
, bld
, i
);
159 set_condmod(BRW_CONDITIONAL_GE
,
160 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
162 /* Our parameter comes in as 1.0/width or 1.0/height,
163 * because that's what people normally want for doing
164 * texture rectangle handling. We need width or height
165 * for clamping, but we don't care enough to make a new
166 * parameter type, so just invert back.
168 fs_reg limit
= vgrf(glsl_type::float_type
);
169 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
170 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
172 set_condmod(BRW_CONDITIONAL_L
,
173 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
178 if (coord_components
> 0 && needs_gl_clamp
) {
179 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
180 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
181 fs_reg chan
= coordinate
;
182 chan
= offset(chan
, bld
, i
);
183 set_saturate(true, bld
.MOV(chan
, chan
));
190 /* Sample from the MCS surface attached to this multisample texture. */
192 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
193 const fs_reg
&sampler
)
195 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
196 const fs_reg srcs
[] = {
197 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
198 sampler
, fs_reg(), fs_reg(components
), fs_reg(0)
200 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
203 /* We only care about one reg of response, but the sampler always writes
206 inst
->regs_written
= 4 * dispatch_width
/ 8;
212 fs_visitor::emit_texture(ir_texture_opcode op
,
213 const glsl_type
*dest_type
,
214 fs_reg coordinate
, int coord_components
,
216 fs_reg lod
, fs_reg lod2
, int grad_components
,
220 int gather_component
,
224 fs_reg sampler_reg
, int texunit
)
226 fs_inst
*inst
= NULL
;
229 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
230 * emitting anything other than setting up the constant result.
232 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
233 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
235 fs_reg res
= vgrf(glsl_type::vec4_type
);
238 for (int i
=0; i
<4; i
++) {
239 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
240 res
= offset(res
, bld
, 1);
246 if (op
== ir_query_levels
) {
247 /* textureQueryLevels() is implemented in terms of TXS so we need to
248 * pass a valid LOD argument.
250 assert(lod
.file
== BAD_FILE
);
254 if (coordinate
.file
!= BAD_FILE
) {
255 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
256 * samplers. This should only be a problem with GL_CLAMP on Gen7.
258 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
262 /* Writemasking doesn't eliminate channels on SIMD8 texture
263 * samples, so don't worry about them.
265 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
266 const fs_reg srcs
[] = {
267 coordinate
, shadow_c
, lod
, lod2
,
268 sample_index
, mcs
, sampler_reg
, offset_value
,
269 fs_reg(coord_components
), fs_reg(grad_components
)
275 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
278 opcode
= FS_OPCODE_TXB_LOGICAL
;
281 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
284 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
287 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
290 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
293 case ir_query_levels
:
294 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
297 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
300 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
301 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
304 unreachable("Invalid texture opcode.");
307 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
308 inst
->regs_written
= 4 * dispatch_width
/ 8;
310 if (shadow_c
.file
!= BAD_FILE
)
311 inst
->shadow_compare
= true;
313 if (offset_value
.file
== IMM
)
314 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
318 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
320 if (devinfo
->gen
== 6)
321 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
324 /* fixup #layers for cube map arrays */
325 if (op
== ir_txs
&& is_cube_array
) {
326 fs_reg depth
= offset(dst
, bld
, 2);
327 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
328 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
330 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
331 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
332 for (int i
= 0; i
< components
; i
++) {
334 fixed_payload
[i
] = fixed_depth
;
336 fixed_payload
[i
] = offset(dst
, bld
, i
);
339 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
342 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
346 * Apply workarounds for Gen6 gather with UINT/SINT
349 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
354 int width
= (wa
& WA_8BIT
) ? 8 : 16;
356 for (int i
= 0; i
< 4; i
++) {
357 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
358 /* Convert from UNORM to UINT */
359 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
363 /* Reinterpret the UINT value as a signed INT value by
364 * shifting the sign bit into place, then shifting back
367 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
368 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
371 dst
= offset(dst
, bld
, 1);
376 * Set up the gather channel based on the swizzle, for gather4.
379 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
381 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
383 case SWIZZLE_X
: return 0;
385 /* gather4 sampler is broken for green channel on RG32F --
386 * we must ask for blue instead.
388 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
391 case SWIZZLE_Z
: return 2;
392 case SWIZZLE_W
: return 3;
394 unreachable("Not reached"); /* zero, one swizzles handled already */
399 * Swizzle the result of a texture result. This is necessary for
400 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
403 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
404 fs_reg orig_val
, uint32_t sampler
)
406 if (op
== ir_query_levels
) {
407 /* # levels is in .w */
408 this->result
= offset(orig_val
, bld
, 3);
412 this->result
= orig_val
;
414 /* txs,lod don't actually sample the texture, so swizzling the result
417 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
420 if (dest_components
== 1) {
421 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
422 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
423 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
424 swizzled_result
.type
= orig_val
.type
;
426 for (int i
= 0; i
< 4; i
++) {
427 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
428 fs_reg l
= swizzled_result
;
429 l
= offset(l
, bld
, i
);
431 if (swiz
== SWIZZLE_ZERO
) {
432 bld
.MOV(l
, fs_reg(0.0f
));
433 } else if (swiz
== SWIZZLE_ONE
) {
434 bld
.MOV(l
, fs_reg(1.0f
));
436 bld
.MOV(l
, offset(orig_val
, bld
,
437 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
440 this->result
= swizzled_result
;
445 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
447 * Many GLSL shaders contain the following pattern:
449 * x = condition ? foo : bar
451 * The compiler emits an ir_if tree for this, since each subexpression might be
452 * a complex tree that could have side-effects or short-circuit logic.
454 * However, the common case is to simply select one of two constants or
455 * variable values---which is exactly what SEL is for. In this case, the
456 * assembly looks like:
464 * which can be easily translated into:
466 * (+f0) SEL dst src0 src1
468 * If src0 is an immediate value, we promote it to a temporary GRF.
471 fs_visitor::try_replace_with_sel()
473 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
474 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
476 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
478 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
481 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
482 for (int i
= 0; i
< 4; i
++) {
483 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
485 match
= (fs_inst
*) match
->prev
;
488 /* The opcodes match; it looks like the right sequence of instructions. */
489 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
490 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
491 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
493 /* Check that the MOVs are the right form. */
494 if (then_mov
->dst
.equals(else_mov
->dst
) &&
495 !then_mov
->is_partial_write() &&
496 !else_mov
->is_partial_write()) {
498 /* Remove the matched instructions; we'll emit a SEL to replace them. */
499 while (!if_inst
->next
->is_tail_sentinel())
500 if_inst
->next
->exec_node::remove();
501 if_inst
->exec_node::remove();
503 /* Only the last source register can be a constant, so if the MOV in
504 * the "then" clause uses a constant, we need to put it in a temporary.
506 fs_reg
src0(then_mov
->src
[0]);
507 if (src0
.file
== IMM
) {
508 src0
= vgrf(glsl_type::float_type
);
509 src0
.type
= then_mov
->src
[0].type
;
510 bld
.MOV(src0
, then_mov
->src
[0]);
513 if (if_inst
->conditional_mod
) {
514 /* Sandybridge-specific IF with embedded comparison */
515 bld
.CMP(bld
.null_reg_d(), if_inst
->src
[0], if_inst
->src
[1],
516 if_inst
->conditional_mod
);
517 set_predicate(BRW_PREDICATE_NORMAL
,
518 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
519 src0
, else_mov
->src
[0]));
521 /* Separate CMP and IF instructions */
522 set_predicate_inv(if_inst
->predicate
, if_inst
->predicate_inverse
,
523 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
524 src0
, else_mov
->src
[0]));
534 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
535 fs_reg dst
, fs_reg offset
, fs_reg src0
,
538 int reg_width
= dispatch_width
/ 8;
541 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
543 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
544 /* Initialize the sample mask in the message header. */
545 bld
.exec_all().MOV(sources
[0], fs_reg(0u));
547 if (stage
== MESA_SHADER_FRAGMENT
) {
548 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
550 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
553 .MOV(component(sources
[0], 7),
554 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
557 /* The execution mask is part of the side-band information sent together with
558 * the message payload to the data port. It's implicitly ANDed with the sample
559 * mask sent in the header to compute the actual set of channels that execute
560 * the atomic operation.
562 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
564 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
568 /* Set the atomic operation offset. */
569 sources
[1] = vgrf(glsl_type::uint_type
);
570 bld
.MOV(sources
[1], offset
);
573 /* Set the atomic operation arguments. */
574 if (src0
.file
!= BAD_FILE
) {
575 sources
[length
] = vgrf(glsl_type::uint_type
);
576 bld
.MOV(sources
[length
], src0
);
580 if (src1
.file
!= BAD_FILE
) {
581 sources
[length
] = vgrf(glsl_type::uint_type
);
582 bld
.MOV(sources
[length
], src1
);
586 int mlen
= 1 + (length
- 1) * reg_width
;
587 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
588 BRW_REGISTER_TYPE_UD
);
589 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, 1);
591 /* Emit the instruction. */
592 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
593 fs_reg(surf_index
), fs_reg(atomic_op
));
598 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
601 int reg_width
= dispatch_width
/ 8;
603 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
605 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
606 /* Initialize the sample mask in the message header. */
608 .MOV(sources
[0], fs_reg(0u));
610 if (stage
== MESA_SHADER_FRAGMENT
) {
611 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
613 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
616 .MOV(component(sources
[0], 7),
617 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
620 /* The execution mask is part of the side-band information sent together with
621 * the message payload to the data port. It's implicitly ANDed with the sample
622 * mask sent in the header to compute the actual set of channels that execute
623 * the atomic operation.
625 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
627 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
630 /* Set the surface read offset. */
631 sources
[1] = vgrf(glsl_type::uint_type
);
632 bld
.MOV(sources
[1], offset
);
634 int mlen
= 1 + reg_width
;
635 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
636 BRW_REGISTER_TYPE_UD
);
637 fs_inst
*inst
= bld
.LOAD_PAYLOAD(src_payload
, sources
, 2, 1);
639 /* Emit the instruction. */
640 inst
= bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
641 fs_reg(surf_index
), fs_reg(1));
645 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
647 fs_visitor::emit_dummy_fs()
649 int reg_width
= dispatch_width
/ 8;
651 /* Everyone's favorite color. */
652 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
653 for (int i
= 0; i
< 4; i
++) {
654 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
659 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
661 if (devinfo
->gen
>= 6) {
663 write
->mlen
= 4 * reg_width
;
665 write
->header_size
= 2;
667 write
->mlen
= 2 + 4 * reg_width
;
670 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
671 * varying to avoid GPU hangs, so set that.
673 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
674 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
675 memset(wm_prog_data
->urb_setup
, -1,
676 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
678 /* We don't have any uniforms. */
679 stage_prog_data
->nr_params
= 0;
680 stage_prog_data
->nr_pull_params
= 0;
681 stage_prog_data
->curb_read_length
= 0;
682 stage_prog_data
->dispatch_grf_start_reg
= 2;
683 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
684 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
689 /* The register location here is relative to the start of the URB
690 * data. It will get adjusted to be a real location before
691 * generate_code() time.
694 fs_visitor::interp_reg(int location
, int channel
)
696 assert(stage
== MESA_SHADER_FRAGMENT
);
697 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
698 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
699 int stride
= (channel
& 1) * 4;
701 assert(prog_data
->urb_setup
[location
] != -1);
703 return brw_vec1_grf(regnr
, stride
);
706 /** Emits the interpolation for the varying inputs. */
708 fs_visitor::emit_interpolation_setup_gen4()
710 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
712 fs_builder abld
= bld
.annotate("compute pixel centers");
713 this->pixel_x
= vgrf(glsl_type::uint_type
);
714 this->pixel_y
= vgrf(glsl_type::uint_type
);
715 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
716 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
717 abld
.ADD(this->pixel_x
,
718 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
719 fs_reg(brw_imm_v(0x10101010)));
720 abld
.ADD(this->pixel_y
,
721 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
722 fs_reg(brw_imm_v(0x11001100)));
724 abld
= bld
.annotate("compute pixel deltas from v0");
726 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
727 vgrf(glsl_type::vec2_type
);
728 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
729 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
730 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
732 if (devinfo
->has_pln
&& dispatch_width
== 16) {
733 for (unsigned i
= 0; i
< 2; i
++) {
734 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
735 half(this->pixel_x
, i
), xstart
);
736 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
737 half(this->pixel_y
, i
), ystart
);
740 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
741 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
744 abld
= bld
.annotate("compute pos.w and 1/pos.w");
745 /* Compute wpos.w. It's always in our setup, since it's needed to
746 * interpolate the other attributes.
748 this->wpos_w
= vgrf(glsl_type::float_type
);
749 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
750 interp_reg(VARYING_SLOT_POS
, 3));
751 /* Compute the pixel 1/W value from wpos.w. */
752 this->pixel_w
= vgrf(glsl_type::float_type
);
753 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
756 /** Emits the interpolation for the varying inputs. */
758 fs_visitor::emit_interpolation_setup_gen6()
760 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
762 fs_builder abld
= bld
.annotate("compute pixel centers");
763 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
764 /* The "Register Region Restrictions" page says for BDW (and newer,
767 * "When destination spans two registers, the source may be one or
768 * two registers. The destination elements must be evenly split
769 * between the two registers."
771 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
772 * compute our pixel centers.
774 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
775 BRW_REGISTER_TYPE_UW
);
777 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
778 dbld
.ADD(int_pixel_xy
,
779 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
780 fs_reg(brw_imm_v(0x11001010)));
782 this->pixel_x
= vgrf(glsl_type::float_type
);
783 this->pixel_y
= vgrf(glsl_type::float_type
);
784 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
785 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
787 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
789 * "When destination spans two registers, the source MUST span two
792 * Since the GRF source of the ADD will only read a single register, we
793 * must do two separate ADDs in SIMD16.
795 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
796 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
797 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
798 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
799 abld
.ADD(int_pixel_x
,
800 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
801 fs_reg(brw_imm_v(0x10101010)));
802 abld
.ADD(int_pixel_y
,
803 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
804 fs_reg(brw_imm_v(0x11001100)));
806 /* As of gen6, we can no longer mix float and int sources. We have
807 * to turn the integer pixel centers into floats for their actual
810 this->pixel_x
= vgrf(glsl_type::float_type
);
811 this->pixel_y
= vgrf(glsl_type::float_type
);
812 abld
.MOV(this->pixel_x
, int_pixel_x
);
813 abld
.MOV(this->pixel_y
, int_pixel_y
);
816 abld
= bld
.annotate("compute pos.w");
817 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
818 this->wpos_w
= vgrf(glsl_type::float_type
);
819 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
821 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
822 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
823 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
827 static enum brw_conditional_mod
828 cond_for_alpha_func(GLenum func
)
832 return BRW_CONDITIONAL_G
;
834 return BRW_CONDITIONAL_GE
;
836 return BRW_CONDITIONAL_L
;
838 return BRW_CONDITIONAL_LE
;
840 return BRW_CONDITIONAL_EQ
;
842 return BRW_CONDITIONAL_NEQ
;
844 unreachable("Not reached");
849 * Alpha test support for when we compile it into the shader instead
850 * of using the normal fixed-function alpha test.
853 fs_visitor::emit_alpha_test()
855 assert(stage
== MESA_SHADER_FRAGMENT
);
856 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
857 const fs_builder abld
= bld
.annotate("Alpha test");
860 if (key
->alpha_test_func
== GL_ALWAYS
)
863 if (key
->alpha_test_func
== GL_NEVER
) {
865 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
866 BRW_REGISTER_TYPE_UW
));
867 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
868 BRW_CONDITIONAL_NEQ
);
871 fs_reg color
= offset(outputs
[0], bld
, 3);
873 /* f0.1 &= func(color, ref) */
874 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
875 cond_for_alpha_func(key
->alpha_test_func
));
877 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
878 cmp
->flag_subreg
= 1;
882 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
883 fs_reg color0
, fs_reg color1
,
884 fs_reg src0_alpha
, unsigned components
)
886 assert(stage
== MESA_SHADER_FRAGMENT
);
887 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
889 /* Hand over gl_FragDepth or the payload depth. */
890 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
891 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
895 if (source_depth_to_render_target
) {
896 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
897 src_depth
= frag_depth
;
899 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
902 const fs_reg sources
[] = {
903 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, sample_mask
,
906 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
907 sources
, ARRAY_SIZE(sources
));
909 if (prog_data
->uses_kill
) {
910 write
->predicate
= BRW_PREDICATE_NORMAL
;
911 write
->flag_subreg
= 1;
918 fs_visitor::emit_fb_writes()
920 assert(stage
== MESA_SHADER_FRAGMENT
);
921 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
922 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
924 fs_inst
*inst
= NULL
;
926 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
927 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
928 * would require SIMD8 moves of each half to message regs, e.g. by using
929 * the SIMD lowering pass. Unfortunately this is more difficult than it
930 * sounds because the SIMD8 single-source message lacks channel selects
931 * for the second and third subspans.
933 no16("Missing support for simd16 depth writes on gen6\n");
937 const fs_builder abld
= bld
.annotate("FB dual-source write");
939 inst
= emit_single_fb_write(abld
, this->outputs
[0],
940 this->dual_src_output
, reg_undef
, 4);
943 prog_data
->dual_src_blend
= true;
945 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
946 /* Skip over outputs that weren't written. */
947 if (this->outputs
[target
].file
== BAD_FILE
)
950 const fs_builder abld
= bld
.annotate(
951 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
954 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
955 src0_alpha
= offset(outputs
[0], bld
, 3);
957 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
959 this->output_components
[target
]);
960 inst
->target
= target
;
965 /* Even if there's no color buffers enabled, we still need to send
966 * alpha out the pipeline to our null renderbuffer to support
967 * alpha-testing, alpha-to-coverage, and so on.
969 /* FINISHME: Factor out this frequently recurring pattern into a
972 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
973 reg_undef
, offset(this->outputs
[0], bld
, 3) };
974 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
975 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
977 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
985 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
987 const struct brw_vue_prog_key
*key
=
988 (const struct brw_vue_prog_key
*) this->key
;
990 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
991 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
992 for (int j
= 0; j
< 4; ++j
) {
993 stage_prog_data
->param
[uniforms
+ j
] =
994 (gl_constant_value
*) &clip_planes
[i
][j
];
1001 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
1003 * This does nothing if the shader uses gl_ClipDistance or user clipping is
1004 * disabled altogether.
1006 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
1008 struct brw_vue_prog_data
*vue_prog_data
=
1009 (struct brw_vue_prog_data
*) prog_data
;
1010 const struct brw_vue_prog_key
*key
=
1011 (const struct brw_vue_prog_key
*) this->key
;
1013 /* Bail unless some sort of legacy clipping is enabled */
1014 if (!key
->userclip_active
|| prog
->UsesClipDistanceOut
)
1017 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
1019 * "If a linked set of shaders forming the vertex stage contains no
1020 * static write to gl_ClipVertex or gl_ClipDistance, but the
1021 * application has requested clipping against user clip planes through
1022 * the API, then the coordinate written to gl_Position is used for
1023 * comparison against the user clip planes."
1025 * This function is only called if the shader didn't write to
1026 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
1027 * if the user wrote to it; otherwise we use gl_Position.
1030 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
1031 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
1032 clip_vertex
= VARYING_SLOT_POS
;
1034 /* If the clip vertex isn't written, skip this. Typically this means
1035 * the GS will set up clipping. */
1036 if (outputs
[clip_vertex
].file
== BAD_FILE
)
1039 setup_uniform_clipplane_values(clip_planes
);
1041 const fs_builder abld
= bld
.annotate("user clip distances");
1043 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
1044 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
1046 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1047 fs_reg u
= userplane
[i
];
1048 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
1049 output
.reg_offset
= i
& 3;
1051 abld
.MUL(output
, outputs
[clip_vertex
], u
);
1052 for (int j
= 1; j
< 4; j
++) {
1053 u
.reg
= userplane
[i
].reg
+ j
;
1054 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
1060 fs_visitor::emit_urb_writes()
1062 int slot
, urb_offset
, length
;
1063 struct brw_vs_prog_data
*vs_prog_data
=
1064 (struct brw_vs_prog_data
*) prog_data
;
1065 const struct brw_vs_prog_key
*key
=
1066 (const struct brw_vs_prog_key
*) this->key
;
1067 const GLbitfield64 psiz_mask
=
1068 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
1069 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
1073 /* If we don't have any valid slots to write, just do a minimal urb write
1074 * send to terminate the shader. This includes 1 slot of undefined data,
1075 * because it's invalid to write 0 data:
1077 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
1078 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
1079 * Write Data Payload:
1081 * "The write data payload can be between 1 and 8 message phases long."
1083 if (vue_map
->slots_valid
== 0) {
1084 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
1085 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
1086 BRW_REGISTER_TYPE_UD
)));
1088 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1098 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
1099 fs_reg reg
, src
, zero
;
1101 int varying
= vue_map
->slot_to_varying
[slot
];
1103 case VARYING_SLOT_PSIZ
:
1105 /* The point size varying slot is the vue header and is always in the
1106 * vue map. But often none of the special varyings that live there
1107 * are written and in that case we can skip writing to the vue
1108 * header, provided the corresponding state properly clamps the
1109 * values further down the pipeline. */
1110 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
1111 assert(length
== 0);
1116 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1117 bld
.MOV(zero
, fs_reg(0u));
1119 sources
[length
++] = zero
;
1120 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
1121 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
1123 sources
[length
++] = zero
;
1125 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
1126 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
1128 sources
[length
++] = zero
;
1130 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
1131 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
1133 sources
[length
++] = zero
;
1136 case BRW_VARYING_SLOT_NDC
:
1137 case VARYING_SLOT_EDGE
:
1138 unreachable("unexpected scalar vs output");
1141 case BRW_VARYING_SLOT_PAD
:
1145 /* gl_Position is always in the vue map, but isn't always written by
1146 * the shader. Other varyings (clip distances) get added to the vue
1147 * map but don't always get written. In those cases, the
1148 * corresponding this->output[] slot will be invalid we and can skip
1149 * the urb write for the varying. If we've already queued up a vue
1150 * slot for writing we flush a mlen 5 urb write, otherwise we just
1151 * advance the urb_offset.
1153 if (this->outputs
[varying
].file
== BAD_FILE
) {
1161 if ((varying
== VARYING_SLOT_COL0
||
1162 varying
== VARYING_SLOT_COL1
||
1163 varying
== VARYING_SLOT_BFC0
||
1164 varying
== VARYING_SLOT_BFC1
) &&
1165 key
->clamp_vertex_color
) {
1166 /* We need to clamp these guys, so do a saturating MOV into a
1167 * temp register and use that for the payload.
1169 for (int i
= 0; i
< 4; i
++) {
1170 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
1171 src
= offset(this->outputs
[varying
], bld
, i
);
1172 set_saturate(true, bld
.MOV(reg
, src
));
1173 sources
[length
++] = reg
;
1176 for (int i
= 0; i
< 4; i
++)
1177 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
1182 const fs_builder abld
= bld
.annotate("URB write");
1184 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
1185 * the last slot or if we need to flush (see BAD_FILE varying case
1186 * above), emit a URB write send now to flush out the data.
1188 int last
= slot
== vue_map
->num_slots
- 1;
1189 if (length
== 8 || last
)
1192 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
1193 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
1194 BRW_REGISTER_TYPE_F
);
1195 payload_sources
[0] =
1196 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1198 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
1199 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1202 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1204 inst
->mlen
= length
+ 1;
1205 inst
->offset
= urb_offset
;
1206 urb_offset
= slot
+ 1;
1214 fs_visitor::emit_cs_terminate()
1216 assert(devinfo
->gen
>= 7);
1218 /* We are getting the thread ID from the compute shader header */
1219 assert(stage
== MESA_SHADER_COMPUTE
);
1221 /* We can't directly send from g0, since sends with EOT have to use
1222 * g112-127. So, copy it to a virtual register, The register allocator will
1223 * make sure it uses the appropriate register range.
1225 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1226 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1227 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
1229 /* Send a message to the thread spawner to terminate the thread. */
1230 fs_inst
*inst
= bld
.exec_all()
1231 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1236 fs_visitor::emit_barrier()
1238 assert(devinfo
->gen
>= 7);
1240 /* We are getting the barrier ID from the compute shader header */
1241 assert(stage
== MESA_SHADER_COMPUTE
);
1243 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1245 /* Clear the message payload */
1246 bld
.exec_all().MOV(payload
, fs_reg(0u));
1248 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1249 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1250 bld
.exec_all().AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1252 /* Emit a gateway "barrier" message using the payload we set up, followed
1253 * by a wait instruction.
1255 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1258 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1260 gl_shader_stage stage
,
1262 struct brw_stage_prog_data
*prog_data
,
1263 struct gl_shader_program
*shader_prog
,
1264 struct gl_program
*prog
,
1265 unsigned dispatch_width
,
1266 int shader_time_index
)
1267 : backend_shader(compiler
, log_data
, mem_ctx
,
1268 shader_prog
, prog
, prog_data
, stage
),
1269 key(key
), prog_data(prog_data
),
1270 dispatch_width(dispatch_width
),
1271 shader_time_index(shader_time_index
),
1272 promoted_constants(0),
1273 bld(fs_builder(this, dispatch_width
).at_end())
1276 case MESA_SHADER_FRAGMENT
:
1277 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1279 case MESA_SHADER_VERTEX
:
1280 case MESA_SHADER_GEOMETRY
:
1281 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
1283 case MESA_SHADER_COMPUTE
:
1284 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1287 unreachable("unhandled shader stage");
1290 this->failed
= false;
1291 this->simd16_unsupported
= false;
1292 this->no16_msg
= NULL
;
1294 this->nir_locals
= NULL
;
1295 this->nir_ssa_values
= NULL
;
1297 memset(&this->payload
, 0, sizeof(this->payload
));
1298 memset(this->outputs
, 0, sizeof(this->outputs
));
1299 memset(this->output_components
, 0, sizeof(this->output_components
));
1300 this->source_depth_to_render_target
= false;
1301 this->runtime_check_aads_emit
= false;
1302 this->first_non_payload_grf
= 0;
1303 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1305 this->virtual_grf_start
= NULL
;
1306 this->virtual_grf_end
= NULL
;
1307 this->live_intervals
= NULL
;
1308 this->regs_live_at_ip
= NULL
;
1311 this->last_scratch
= 0;
1312 this->pull_constant_loc
= NULL
;
1313 this->push_constant_loc
= NULL
;
1315 this->spilled_any_registers
= false;
1316 this->do_dual_src
= false;
1318 if (dispatch_width
== 8)
1319 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1322 fs_visitor::~fs_visitor()