2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation(ir
);
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
86 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
87 this->sample_mask
= *reg
;
89 /* gl_FragData or a user-defined FS output */
90 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
91 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
94 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
95 : ir
->type
->vector_elements
;
97 /* General color output. */
98 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
99 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
100 this->outputs
[output
] = *reg
;
101 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
102 this->output_components
[output
] = vector_elements
;
105 } else if (ir
->data
.mode
== ir_var_uniform
) {
106 int param_index
= uniforms
;
108 /* Thanks to the lower_ubo_reference pass, we will see only
109 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
110 * variables, so no need for them to be in variable_ht.
112 * Atomic counters take no uniform storage, no need to do
115 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
118 if (dispatch_width
== 16) {
119 if (!variable_storage(ir
)) {
120 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
125 param_size
[param_index
] = type_size(ir
->type
);
126 if (!strncmp(ir
->name
, "gl_", 3)) {
127 setup_builtin_uniform_values(ir
);
129 setup_uniform_values(ir
);
132 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
133 reg
->type
= brw_type_for_base_type(ir
->type
);
135 } else if (ir
->data
.mode
== ir_var_system_value
) {
136 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
137 reg
= emit_samplepos_setup(ir
);
138 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
139 reg
= emit_sampleid_setup(ir
);
140 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
141 reg
= emit_samplemaskin_setup(ir
);
146 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
148 hash_table_insert(this->variable_ht
, reg
, ir
);
152 fs_visitor::visit(ir_dereference_variable
*ir
)
154 fs_reg
*reg
= variable_storage(ir
->var
);
159 fs_visitor::visit(ir_dereference_record
*ir
)
161 const glsl_type
*struct_type
= ir
->record
->type
;
163 ir
->record
->accept(this);
165 unsigned int offset
= 0;
166 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
167 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
169 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
171 this->result
.reg_offset
+= offset
;
172 this->result
.type
= brw_type_for_base_type(ir
->type
);
176 fs_visitor::visit(ir_dereference_array
*ir
)
178 ir_constant
*constant_index
;
180 int element_size
= type_size(ir
->type
);
182 constant_index
= ir
->array_index
->as_constant();
184 ir
->array
->accept(this);
186 src
.type
= brw_type_for_base_type(ir
->type
);
188 if (constant_index
) {
189 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
190 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
192 /* Variable index array dereference. We attach the variable index
193 * component to the reg as a pointer to a register containing the
194 * offset. Currently only uniform arrays are supported in this patch,
195 * and that reladdr pointer is resolved by
196 * move_uniform_array_access_to_pull_constants(). All other array types
197 * are lowered by lower_variable_index_to_cond_assign().
199 ir
->array_index
->accept(this);
202 index_reg
= fs_reg(this, glsl_type::int_type
);
203 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
206 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
209 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
210 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
216 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
220 !x
.is_valid_3src() ||
221 !y
.is_valid_3src() ||
222 !a
.is_valid_3src()) {
223 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
224 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
225 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
226 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
228 emit(MUL(y_times_a
, y
, a
));
230 fs_reg negative_a
= a
;
231 negative_a
.negate
= !a
.negate
;
232 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
233 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
235 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
237 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
238 * we need to reorder the operands.
240 emit(LRP(dst
, a
, y
, x
));
245 fs_visitor::emit_minmax(uint32_t conditionalmod
, const fs_reg
&dst
,
246 const fs_reg
&src0
, const fs_reg
&src1
)
251 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
252 inst
->conditional_mod
= conditionalmod
;
254 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
256 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
257 inst
->predicate
= BRW_PREDICATE_NORMAL
;
261 /* Instruction selection: Produce a MOV.sat instead of
262 * MIN(MAX(val, 0), 1) when possible.
265 fs_visitor::try_emit_saturate(ir_expression
*ir
)
267 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
272 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
274 sat_val
->accept(this);
275 fs_reg src
= this->result
;
277 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
279 /* If the last instruction from our accept() didn't generate our
280 * src, generate a saturated MOV
282 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
283 if (!modify
|| modify
->regs_written
!= 1) {
284 this->result
= fs_reg(this, ir
->type
);
285 fs_inst
*inst
= emit(MOV(this->result
, src
));
286 inst
->saturate
= true;
288 modify
->saturate
= true;
297 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
299 /* 3-src instructions were introduced in gen6. */
303 /* MAD can only handle floating-point data. */
304 if (ir
->type
!= glsl_type::float_type
)
307 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
308 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
310 if (!mul
|| mul
->operation
!= ir_binop_mul
)
313 if (nonmul
->as_constant() ||
314 mul
->operands
[0]->as_constant() ||
315 mul
->operands
[1]->as_constant())
318 nonmul
->accept(this);
319 fs_reg src0
= this->result
;
321 mul
->operands
[0]->accept(this);
322 fs_reg src1
= this->result
;
324 mul
->operands
[1]->accept(this);
325 fs_reg src2
= this->result
;
327 this->result
= fs_reg(this, ir
->type
);
328 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
334 fs_visitor::visit(ir_expression
*ir
)
336 unsigned int operand
;
340 assert(ir
->get_num_operands() <= 3);
342 if (try_emit_saturate(ir
))
344 if (ir
->operation
== ir_binop_add
) {
345 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
349 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
350 ir
->operands
[operand
]->accept(this);
351 if (this->result
.file
== BAD_FILE
) {
352 fail("Failed to get tree for expression operand:\n");
353 ir
->operands
[operand
]->fprint(stderr
);
354 fprintf(stderr
, "\n");
356 assert(this->result
.is_valid_3src());
357 op
[operand
] = this->result
;
359 /* Matrix expression operands should have been broken down to vector
360 * operations already.
362 assert(!ir
->operands
[operand
]->type
->is_matrix());
363 /* And then those vector operands should have been broken down to scalar.
365 assert(!ir
->operands
[operand
]->type
->is_vector());
368 /* Storage for our result. If our result goes into an assignment, it will
369 * just get copy-propagated out, so no worries.
371 this->result
= fs_reg(this, ir
->type
);
373 switch (ir
->operation
) {
374 case ir_unop_logic_not
:
375 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
376 * ones complement of the whole register, not just bit 0.
378 emit(XOR(this->result
, op
[0], fs_reg(1)));
381 op
[0].negate
= !op
[0].negate
;
382 emit(MOV(this->result
, op
[0]));
386 op
[0].negate
= false;
387 emit(MOV(this->result
, op
[0]));
390 if (ir
->type
->is_float()) {
391 /* AND(val, 0x80000000) gives the sign bit.
393 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
396 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
398 op
[0].type
= BRW_REGISTER_TYPE_UD
;
399 this->result
.type
= BRW_REGISTER_TYPE_UD
;
400 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
402 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
403 inst
->predicate
= BRW_PREDICATE_NORMAL
;
405 this->result
.type
= BRW_REGISTER_TYPE_F
;
407 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
408 * -> non-negative val generates 0x00000000.
409 * Predicated OR sets 1 if val is positive.
411 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
413 emit(ASR(this->result
, op
[0], fs_reg(31)));
415 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
416 inst
->predicate
= BRW_PREDICATE_NORMAL
;
420 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
424 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
427 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
431 assert(!"not reached: should be handled by ir_explog_to_explog2");
434 case ir_unop_sin_reduced
:
435 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
438 case ir_unop_cos_reduced
:
439 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
443 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
446 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
450 emit(ADD(this->result
, op
[0], op
[1]));
453 assert(!"not reached: should be handled by ir_sub_to_add_neg");
457 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
458 /* For integer multiplication, the MUL uses the low 16 bits
459 * of one of the operands (src0 on gen6, src1 on gen7). The
460 * MACH accumulates in the contribution of the upper 16 bits
463 if (ir
->operands
[0]->is_uint16_constant()) {
465 emit(MUL(this->result
, op
[0], op
[1]));
467 emit(MUL(this->result
, op
[1], op
[0]));
468 } else if (ir
->operands
[1]->is_uint16_constant()) {
470 emit(MUL(this->result
, op
[1], op
[0]));
472 emit(MUL(this->result
, op
[0], op
[1]));
475 no16("SIMD16 explicit accumulator operands unsupported\n");
477 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
479 emit(MUL(acc
, op
[0], op
[1]));
480 emit(MACH(reg_null_d
, op
[0], op
[1]));
481 emit(MOV(this->result
, fs_reg(acc
)));
484 emit(MUL(this->result
, op
[0], op
[1]));
487 case ir_binop_imul_high
: {
489 no16("SIMD16 explicit accumulator operands unsupported\n");
491 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
493 emit(MUL(acc
, op
[0], op
[1]));
494 emit(MACH(this->result
, op
[0], op
[1]));
498 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
499 assert(ir
->type
->is_integer());
500 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
502 case ir_binop_carry
: {
504 no16("SIMD16 explicit accumulator operands unsupported\n");
506 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
508 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
509 emit(MOV(this->result
, fs_reg(acc
)));
512 case ir_binop_borrow
: {
514 no16("SIMD16 explicit accumulator operands unsupported\n");
516 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
518 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
519 emit(MOV(this->result
, fs_reg(acc
)));
523 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
524 assert(ir
->type
->is_integer());
525 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
529 case ir_binop_greater
:
530 case ir_binop_lequal
:
531 case ir_binop_gequal
:
533 case ir_binop_all_equal
:
534 case ir_binop_nequal
:
535 case ir_binop_any_nequal
:
536 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
537 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
539 emit(CMP(this->result
, op
[0], op
[1],
540 brw_conditional_for_comparison(ir
->operation
)));
543 case ir_binop_logic_xor
:
544 emit(XOR(this->result
, op
[0], op
[1]));
547 case ir_binop_logic_or
:
548 emit(OR(this->result
, op
[0], op
[1]));
551 case ir_binop_logic_and
:
552 emit(AND(this->result
, op
[0], op
[1]));
557 assert(!"not reached: should be handled by brw_fs_channel_expressions");
561 assert(!"not reached: should be handled by lower_noise");
564 case ir_quadop_vector
:
565 assert(!"not reached: should be handled by lower_quadop_vector");
568 case ir_binop_vector_extract
:
569 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
572 case ir_triop_vector_insert
:
573 assert(!"not reached: should be handled by lower_vector_insert()");
577 assert(!"not reached: should be handled by ldexp_to_arith()");
581 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
585 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
588 case ir_unop_bitcast_i2f
:
589 case ir_unop_bitcast_u2f
:
590 op
[0].type
= BRW_REGISTER_TYPE_F
;
591 this->result
= op
[0];
594 case ir_unop_bitcast_f2u
:
595 op
[0].type
= BRW_REGISTER_TYPE_UD
;
596 this->result
= op
[0];
599 case ir_unop_bitcast_f2i
:
600 op
[0].type
= BRW_REGISTER_TYPE_D
;
601 this->result
= op
[0];
607 emit(MOV(this->result
, op
[0]));
611 emit(AND(this->result
, op
[0], fs_reg(1)));
614 temp
= fs_reg(this, glsl_type::int_type
);
615 emit(AND(temp
, op
[0], fs_reg(1)));
616 emit(MOV(this->result
, temp
));
620 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
623 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
627 emit(RNDZ(this->result
, op
[0]));
630 op
[0].negate
= !op
[0].negate
;
631 emit(RNDD(this->result
, op
[0]));
632 this->result
.negate
= true;
635 emit(RNDD(this->result
, op
[0]));
638 emit(FRC(this->result
, op
[0]));
640 case ir_unop_round_even
:
641 emit(RNDE(this->result
, op
[0]));
646 resolve_ud_negate(&op
[0]);
647 resolve_ud_negate(&op
[1]);
648 emit_minmax(ir
->operation
== ir_binop_min
?
649 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
650 this->result
, op
[0], op
[1]);
652 case ir_unop_pack_snorm_2x16
:
653 case ir_unop_pack_snorm_4x8
:
654 case ir_unop_pack_unorm_2x16
:
655 case ir_unop_pack_unorm_4x8
:
656 case ir_unop_unpack_snorm_2x16
:
657 case ir_unop_unpack_snorm_4x8
:
658 case ir_unop_unpack_unorm_2x16
:
659 case ir_unop_unpack_unorm_4x8
:
660 case ir_unop_unpack_half_2x16
:
661 case ir_unop_pack_half_2x16
:
662 assert(!"not reached: should be handled by lower_packing_builtins");
664 case ir_unop_unpack_half_2x16_split_x
:
665 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
667 case ir_unop_unpack_half_2x16_split_y
:
668 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
671 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
674 case ir_unop_bitfield_reverse
:
675 emit(BFREV(this->result
, op
[0]));
677 case ir_unop_bit_count
:
678 emit(CBIT(this->result
, op
[0]));
680 case ir_unop_find_msb
:
681 temp
= fs_reg(this, glsl_type::uint_type
);
682 emit(FBH(temp
, op
[0]));
684 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
685 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
686 * subtract the result from 31 to convert the MSB count into an LSB count.
689 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
690 emit(MOV(this->result
, temp
));
691 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
694 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
695 inst
->predicate
= BRW_PREDICATE_NORMAL
;
697 case ir_unop_find_lsb
:
698 emit(FBL(this->result
, op
[0]));
700 case ir_triop_bitfield_extract
:
701 /* Note that the instruction's argument order is reversed from GLSL
704 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
707 emit(BFI1(this->result
, op
[0], op
[1]));
710 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
712 case ir_quadop_bitfield_insert
:
713 assert(!"not reached: should be handled by "
714 "lower_instructions::bitfield_insert_to_bfm_bfi");
717 case ir_unop_bit_not
:
718 emit(NOT(this->result
, op
[0]));
720 case ir_binop_bit_and
:
721 emit(AND(this->result
, op
[0], op
[1]));
723 case ir_binop_bit_xor
:
724 emit(XOR(this->result
, op
[0], op
[1]));
726 case ir_binop_bit_or
:
727 emit(OR(this->result
, op
[0], op
[1]));
730 case ir_binop_lshift
:
731 emit(SHL(this->result
, op
[0], op
[1]));
734 case ir_binop_rshift
:
735 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
736 emit(ASR(this->result
, op
[0], op
[1]));
738 emit(SHR(this->result
, op
[0], op
[1]));
740 case ir_binop_pack_half_2x16_split
:
741 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
743 case ir_binop_ubo_load
: {
744 /* This IR node takes a constant uniform block and a constant or
745 * variable byte offset within the block and loads a vector from that.
747 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
748 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
749 fs_reg surf_index
= fs_reg(c
->prog_data
.base
.binding_table
.ubo_start
+
750 uniform_block
->value
.u
[0]);
752 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
753 packed_consts
.type
= result
.type
;
755 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
756 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
757 packed_consts
, surf_index
, const_offset_reg
));
759 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
760 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
762 /* The std140 packing rules don't allow vectors to cross 16-byte
763 * boundaries, and a reg is 32 bytes.
765 assert(packed_consts
.subreg_offset
< 32);
767 /* UBO bools are any nonzero value. We consider bools to be
768 * values with the low bit set to 1. Convert them using CMP.
770 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
771 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
773 emit(MOV(result
, packed_consts
));
779 /* Turn the byte offset into a dword offset. */
780 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
781 emit(SHR(base_offset
, op
[1], fs_reg(2)));
783 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
784 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
787 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
788 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
794 result
.reg_offset
= 0;
799 /* Note that the instruction's argument order is reversed from GLSL
802 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
806 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
810 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
811 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
812 inst
->predicate
= BRW_PREDICATE_NORMAL
;
818 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
819 const glsl_type
*type
, bool predicated
)
821 switch (type
->base_type
) {
822 case GLSL_TYPE_FLOAT
:
826 for (unsigned int i
= 0; i
< type
->components(); i
++) {
827 l
.type
= brw_type_for_base_type(type
);
828 r
.type
= brw_type_for_base_type(type
);
830 if (predicated
|| !l
.equals(r
)) {
831 fs_inst
*inst
= emit(MOV(l
, r
));
832 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
839 case GLSL_TYPE_ARRAY
:
840 for (unsigned int i
= 0; i
< type
->length
; i
++) {
841 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
845 case GLSL_TYPE_STRUCT
:
846 for (unsigned int i
= 0; i
< type
->length
; i
++) {
847 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
852 case GLSL_TYPE_SAMPLER
:
853 case GLSL_TYPE_IMAGE
:
854 case GLSL_TYPE_ATOMIC_UINT
:
858 case GLSL_TYPE_ERROR
:
859 case GLSL_TYPE_INTERFACE
:
860 assert(!"not reached");
865 /* If the RHS processing resulted in an instruction generating a
866 * temporary value, and it would be easy to rewrite the instruction to
867 * generate its result right into the LHS instead, do so. This ends
868 * up reliably removing instructions where it can be tricky to do so
869 * later without real UD chain information.
872 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
875 fs_inst
*pre_rhs_inst
,
876 fs_inst
*last_rhs_inst
)
878 /* Only attempt if we're doing a direct assignment. */
880 !(ir
->lhs
->type
->is_scalar() ||
881 (ir
->lhs
->type
->is_vector() &&
882 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
885 /* Make sure the last instruction generated our source reg. */
886 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
892 /* If last_rhs_inst wrote a different number of components than our LHS,
893 * we can't safely rewrite it.
895 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
898 /* Success! Rewrite the instruction. */
905 fs_visitor::visit(ir_assignment
*ir
)
910 /* FINISHME: arrays on the lhs */
911 ir
->lhs
->accept(this);
914 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
916 ir
->rhs
->accept(this);
919 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
921 assert(l
.file
!= BAD_FILE
);
922 assert(r
.file
!= BAD_FILE
);
924 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
928 emit_bool_to_cond_code(ir
->condition
);
931 if (ir
->lhs
->type
->is_scalar() ||
932 ir
->lhs
->type
->is_vector()) {
933 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
934 if (ir
->write_mask
& (1 << i
)) {
935 inst
= emit(MOV(l
, r
));
937 inst
->predicate
= BRW_PREDICATE_NORMAL
;
943 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
948 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
949 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
959 if (ir
->shadow_comparitor
) {
960 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
961 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
962 coordinate
.reg_offset
++;
965 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
966 * the unused slots must be zeroed.
968 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
969 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
973 if (ir
->op
== ir_tex
) {
974 /* There's no plain shadow compare message, so we use shadow
975 * compare with a bias of 0.0.
977 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
979 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
980 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
983 assert(!"Should not get here.");
986 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
988 } else if (ir
->op
== ir_tex
) {
989 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
990 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
991 coordinate
.reg_offset
++;
993 /* zero the others. */
994 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
995 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
997 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
999 } else if (ir
->op
== ir_txd
) {
1002 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1003 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1004 coordinate
.reg_offset
++;
1006 /* the slots for u and v are always present, but r is optional */
1007 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
1010 * dPdx = dudx, dvdx, drdx
1011 * dPdy = dudy, dvdy, drdy
1013 * 1-arg: Does not exist.
1015 * 2-arg: dudx dvdx dudy dvdy
1016 * dPdx.x dPdx.y dPdy.x dPdy.y
1019 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1020 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1021 * m5 m6 m7 m8 m9 m10
1023 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1024 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1027 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1029 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1030 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1033 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1034 } else if (ir
->op
== ir_txs
) {
1035 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1037 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1040 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1041 * instructions. We'll need to do SIMD16 here.
1044 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1046 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1047 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1049 coordinate
.reg_offset
++;
1052 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1053 * be necessary for TXF (ld), but seems wise to do for all messages.
1055 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1056 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1059 /* lod/bias appears after u/v/r. */
1062 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1065 /* The unused upper half. */
1070 /* Now, since we're doing simd16, the return is 2 interleaved
1071 * vec4s where the odd-indexed ones are junk. We'll need to move
1072 * this weirdness around to the expected layout.
1075 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1077 brw_type_for_base_type(ir
->type
) :
1078 BRW_REGISTER_TYPE_F
));
1081 fs_inst
*inst
= NULL
;
1084 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1087 inst
= emit(FS_OPCODE_TXB
, dst
);
1090 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1093 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1096 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1099 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1102 fail("unrecognized texture opcode");
1104 inst
->base_mrf
= base_mrf
;
1106 inst
->header_present
= true;
1107 inst
->regs_written
= simd16
? 8 : 4;
1110 for (int i
= 0; i
< 4; i
++) {
1111 emit(MOV(orig_dst
, dst
));
1112 orig_dst
.reg_offset
++;
1113 dst
.reg_offset
+= 2;
1120 /* gen5's sampler has slots for u, v, r, array index, then optional
1121 * parameters like shadow comparitor or LOD bias. If optional
1122 * parameters aren't present, those base slots are optional and don't
1123 * need to be included in the message.
1125 * We don't fill in the unnecessary slots regardless, which may look
1126 * surprising in the disassembly.
1129 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1130 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1131 fs_reg sample_index
)
1135 int reg_width
= dispatch_width
/ 8;
1136 bool header_present
= false;
1137 const int vector_elements
=
1138 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1141 /* The offsets set up by the ir_texture visitor are in the
1142 * m1 header, so we can't go headerless.
1144 header_present
= true;
1149 for (int i
= 0; i
< vector_elements
; i
++) {
1150 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1152 coordinate
.reg_offset
++;
1154 mlen
+= vector_elements
* reg_width
;
1156 if (ir
->shadow_comparitor
) {
1157 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1159 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1163 fs_inst
*inst
= NULL
;
1166 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1169 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1170 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1173 inst
= emit(FS_OPCODE_TXB
, dst
);
1176 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1177 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1180 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1183 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1187 * dPdx = dudx, dvdx, drdx
1188 * dPdy = dudy, dvdy, drdy
1190 * Load up these values:
1191 * - dudx dudy dvdx dvdy drdx drdy
1192 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1194 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1195 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1199 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1204 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1208 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1210 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1212 case ir_query_levels
:
1213 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1215 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1218 mlen
= header_present
+ 4 * reg_width
;
1219 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1220 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1223 mlen
= header_present
+ 4 * reg_width
;
1226 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1228 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1230 inst
= emit(SHADER_OPCODE_TXF_CMS
, dst
);
1233 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1236 inst
= emit(SHADER_OPCODE_TG4
, dst
);
1239 fail("unrecognized texture opcode");
1242 inst
->base_mrf
= base_mrf
;
1244 inst
->header_present
= header_present
;
1245 inst
->regs_written
= 4;
1247 if (mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1248 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1249 " disallowed by hardware\n");
1256 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1257 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1258 fs_reg sample_index
, fs_reg mcs
, int sampler
)
1260 int reg_width
= dispatch_width
/ 8;
1261 bool header_present
= false;
1263 fs_reg payload
= fs_reg(this, glsl_type::float_type
);
1264 fs_reg next
= payload
;
1266 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
) || sampler
>= 16) {
1267 /* For general texture offsets (no txf workaround), we need a header to
1268 * put them in. Note that for SIMD16 we're making space for two actual
1269 * hardware registers here, so the emit will have to fix up for this.
1271 * * ir4_tg4 needs to place its channel select in the header,
1272 * for interaction with ARB_texture_swizzle
1274 * The sampler index is only 4-bits, so for larger sampler numbers we
1275 * need to offset the Sampler State Pointer in the header.
1277 header_present
= true;
1281 if (ir
->shadow_comparitor
) {
1282 emit(MOV(next
, shadow_c
));
1286 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
1287 bool coordinate_done
= false;
1289 /* Set up the LOD info */
1295 emit(MOV(next
, lod
));
1299 emit(MOV(next
, lod
));
1303 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1305 /* Load dPdx and the coordinate together:
1306 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1308 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1309 emit(MOV(next
, coordinate
));
1310 coordinate
.reg_offset
++;
1313 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1314 * only derivatives for (u, v, r).
1316 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1317 emit(MOV(next
, lod
));
1321 emit(MOV(next
, lod2
));
1327 coordinate_done
= true;
1331 emit(MOV(retype(next
, BRW_REGISTER_TYPE_UD
), lod
));
1334 case ir_query_levels
:
1335 emit(MOV(retype(next
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1339 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1340 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), coordinate
));
1341 coordinate
.reg_offset
++;
1344 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), lod
));
1347 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1348 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), coordinate
));
1349 coordinate
.reg_offset
++;
1353 coordinate_done
= true;
1356 emit(MOV(retype(next
, BRW_REGISTER_TYPE_UD
), sample_index
));
1359 /* data from the multisample control surface */
1360 emit(MOV(retype(next
, BRW_REGISTER_TYPE_UD
), mcs
));
1363 /* there is no offsetting for this message; just copy in the integer
1364 * texture coordinates
1366 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1367 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), coordinate
));
1368 coordinate
.reg_offset
++;
1372 coordinate_done
= true;
1375 if (has_nonconstant_offset
) {
1376 if (ir
->shadow_comparitor
)
1377 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1379 /* More crazy intermixing */
1380 ir
->offset
->accept(this);
1381 fs_reg offset_value
= this->result
;
1383 for (int i
= 0; i
< 2; i
++) { /* u, v */
1384 emit(MOV(next
, coordinate
));
1385 coordinate
.reg_offset
++;
1389 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1390 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), offset_value
));
1391 offset_value
.reg_offset
++;
1395 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1396 emit(MOV(next
, coordinate
));
1397 coordinate
.reg_offset
++;
1401 coordinate_done
= true;
1406 /* Set up the coordinate (except for cases where it was done above) */
1407 if (ir
->coordinate
&& !coordinate_done
) {
1408 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1409 emit(MOV(next
, coordinate
));
1410 coordinate
.reg_offset
++;
1415 /* Generate the SEND */
1416 fs_inst
*inst
= NULL
;
1418 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
, payload
); break;
1419 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
, payload
); break;
1420 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
, payload
); break;
1421 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
, payload
); break;
1422 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
, payload
); break;
1423 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_CMS
, dst
, payload
); break;
1424 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1425 case ir_query_levels
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1426 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
, payload
); break;
1428 if (has_nonconstant_offset
)
1429 inst
= emit(SHADER_OPCODE_TG4_OFFSET
, dst
, payload
);
1431 inst
= emit(SHADER_OPCODE_TG4
, dst
, payload
);
1434 inst
->base_mrf
= -1;
1436 inst
->mlen
= next
.reg_offset
* reg_width
- header_present
;
1438 inst
->mlen
= next
.reg_offset
* reg_width
;
1439 inst
->header_present
= header_present
;
1440 inst
->regs_written
= 4;
1442 virtual_grf_sizes
[payload
.reg
] = next
.reg_offset
;
1443 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1444 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1445 " disallowed by hardware\n");
1452 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1453 bool is_rect
, int sampler
, int texunit
)
1455 fs_inst
*inst
= NULL
;
1456 bool needs_gl_clamp
= true;
1457 fs_reg scale_x
, scale_y
;
1459 /* The 965 requires the EU to do the normalization of GL rectangle
1460 * texture coordinates. We use the program parameter state
1461 * tracking to get the scaling factor.
1465 (brw
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1466 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1467 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1468 int tokens
[STATE_LENGTH
] = {
1470 STATE_TEXRECT_SCALE
,
1476 no16("rectangle scale uniform setup not supported on SIMD16\n");
1477 if (dispatch_width
== 16) {
1481 scale_x
= fs_reg(UNIFORM
, uniforms
);
1482 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1484 GLuint index
= _mesa_add_state_reference(params
,
1485 (gl_state_index
*)tokens
);
1486 stage_prog_data
->param
[uniforms
++] =
1487 &prog
->Parameters
->ParameterValues
[index
][0].f
;
1488 stage_prog_data
->param
[uniforms
++] =
1489 &prog
->Parameters
->ParameterValues
[index
][1].f
;
1492 /* The 965 requires the EU to do the normalization of GL rectangle
1493 * texture coordinates. We use the program parameter state
1494 * tracking to get the scaling factor.
1496 if (brw
->gen
< 6 && is_rect
) {
1497 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1498 fs_reg src
= coordinate
;
1501 emit(MUL(dst
, src
, scale_x
));
1504 emit(MUL(dst
, src
, scale_y
));
1505 } else if (is_rect
) {
1506 /* On gen6+, the sampler handles the rectangle coordinates
1507 * natively, without needing rescaling. But that means we have
1508 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1509 * not [0, 1] like the default case below.
1511 needs_gl_clamp
= false;
1513 for (int i
= 0; i
< 2; i
++) {
1514 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1515 fs_reg chan
= coordinate
;
1516 chan
.reg_offset
+= i
;
1518 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1519 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1521 /* Our parameter comes in as 1.0/width or 1.0/height,
1522 * because that's what people normally want for doing
1523 * texture rectangle handling. We need width or height
1524 * for clamping, but we don't care enough to make a new
1525 * parameter type, so just invert back.
1527 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1528 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1529 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1531 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1532 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1537 if (ir
->coordinate
&& needs_gl_clamp
) {
1538 for (unsigned int i
= 0;
1539 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1540 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1541 fs_reg chan
= coordinate
;
1542 chan
.reg_offset
+= i
;
1544 fs_inst
*inst
= emit(MOV(chan
, chan
));
1545 inst
->saturate
= true;
1552 /* Sample from the MCS surface attached to this multisample texture. */
1554 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
)
1556 int reg_width
= dispatch_width
/ 8;
1557 fs_reg payload
= fs_reg(this, glsl_type::float_type
);
1558 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1559 fs_reg next
= payload
;
1561 /* parameters are: u, v, r, lod; missing parameters are treated as zero */
1562 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1563 emit(MOV(retype(next
, BRW_REGISTER_TYPE_D
), coordinate
));
1564 coordinate
.reg_offset
++;
1568 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
);
1569 virtual_grf_sizes
[payload
.reg
] = next
.reg_offset
;
1570 inst
->base_mrf
= -1;
1571 inst
->mlen
= next
.reg_offset
* reg_width
;
1572 inst
->header_present
= false;
1573 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of response,
1574 * but the sampler always writes 4/8
1576 inst
->sampler
= sampler
;
1582 fs_visitor::visit(ir_texture
*ir
)
1584 fs_inst
*inst
= NULL
;
1587 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1588 /* FINISHME: We're failing to recompile our programs when the sampler is
1589 * updated. This only matters for the texture rectangle scale parameters
1590 * (pre-gen6, or gen6+ with GL_CLAMP).
1592 int texunit
= prog
->SamplerUnits
[sampler
];
1594 if (ir
->op
== ir_tg4
) {
1595 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1596 * emitting anything other than setting up the constant result.
1598 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1599 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1600 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1602 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1605 for (int i
=0; i
<4; i
++) {
1606 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1613 /* Should be lowered by do_lower_texture_projection */
1614 assert(!ir
->projector
);
1616 /* Should be lowered */
1617 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1619 /* Generate code to compute all the subexpression trees. This has to be
1620 * done before loading any values into MRFs for the sampler message since
1621 * generating these values may involve SEND messages that need the MRFs.
1624 if (ir
->coordinate
) {
1625 ir
->coordinate
->accept(this);
1627 coordinate
= rescale_texcoord(ir
, this->result
,
1628 ir
->sampler
->type
->sampler_dimensionality
==
1629 GLSL_SAMPLER_DIM_RECT
,
1633 fs_reg shadow_comparitor
;
1634 if (ir
->shadow_comparitor
) {
1635 ir
->shadow_comparitor
->accept(this);
1636 shadow_comparitor
= this->result
;
1639 fs_reg lod
, lod2
, sample_index
, mcs
;
1644 case ir_query_levels
:
1647 ir
->lod_info
.bias
->accept(this);
1651 ir
->lod_info
.grad
.dPdx
->accept(this);
1654 ir
->lod_info
.grad
.dPdy
->accept(this);
1655 lod2
= this->result
;
1660 ir
->lod_info
.lod
->accept(this);
1664 ir
->lod_info
.sample_index
->accept(this);
1665 sample_index
= this->result
;
1667 if (brw
->gen
>= 7 && c
->key
.tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1668 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
1673 assert(!"Unrecognized texture opcode");
1676 /* Writemasking doesn't eliminate channels on SIMD8 texture
1677 * samples, so don't worry about them.
1679 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1681 if (brw
->gen
>= 7) {
1682 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1683 lod
, lod2
, sample_index
, mcs
, sampler
);
1684 } else if (brw
->gen
>= 5) {
1685 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1686 lod
, lod2
, sample_index
);
1688 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1692 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1693 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
1695 if (ir
->op
== ir_tg4
)
1696 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1698 inst
->sampler
= sampler
;
1700 if (ir
->shadow_comparitor
)
1701 inst
->shadow_compare
= true;
1703 /* fixup #layers for cube map arrays */
1704 if (ir
->op
== ir_txs
) {
1705 glsl_type
const *type
= ir
->sampler
->type
;
1706 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1707 type
->sampler_array
) {
1709 depth
.reg_offset
= 2;
1710 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1714 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
1715 emit_gen6_gather_wa(c
->key
.tex
.gen6_gather_wa
[sampler
], dst
);
1718 swizzle_result(ir
, dst
, sampler
);
1722 * Apply workarounds for Gen6 gather with UINT/SINT
1725 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
1730 int width
= (wa
& WA_8BIT
) ? 8 : 16;
1732 for (int i
= 0; i
< 4; i
++) {
1733 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
1734 /* Convert from UNORM to UINT */
1735 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
1736 emit(MOV(dst
, dst_f
));
1739 /* Reinterpret the UINT value as a signed INT value by
1740 * shifting the sign bit into place, then shifting back
1743 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
1744 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
1752 * Set up the gather channel based on the swizzle, for gather4.
1755 fs_visitor::gather_channel(ir_texture
*ir
, int sampler
)
1757 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1758 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1760 case SWIZZLE_X
: return 0;
1762 /* gather4 sampler is broken for green channel on RG32F --
1763 * we must ask for blue instead.
1765 if (c
->key
.tex
.gather_channel_quirk_mask
& (1<<sampler
))
1768 case SWIZZLE_Z
: return 2;
1769 case SWIZZLE_W
: return 3;
1771 assert(!"Not reached"); /* zero, one swizzles handled already */
1777 * Swizzle the result of a texture result. This is necessary for
1778 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1781 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1783 if (ir
->op
== ir_query_levels
) {
1784 /* # levels is in .w */
1785 orig_val
.reg_offset
+= 3;
1786 this->result
= orig_val
;
1790 this->result
= orig_val
;
1792 /* txs,lod don't actually sample the texture, so swizzling the result
1795 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
1798 if (ir
->type
== glsl_type::float_type
) {
1799 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1800 assert(ir
->sampler
->type
->sampler_shadow
);
1801 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1802 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1804 for (int i
= 0; i
< 4; i
++) {
1805 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1806 fs_reg l
= swizzled_result
;
1809 if (swiz
== SWIZZLE_ZERO
) {
1810 emit(MOV(l
, fs_reg(0.0f
)));
1811 } else if (swiz
== SWIZZLE_ONE
) {
1812 emit(MOV(l
, fs_reg(1.0f
)));
1814 fs_reg r
= orig_val
;
1815 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1819 this->result
= swizzled_result
;
1824 fs_visitor::visit(ir_swizzle
*ir
)
1826 ir
->val
->accept(this);
1827 fs_reg val
= this->result
;
1829 if (ir
->type
->vector_elements
== 1) {
1830 this->result
.reg_offset
+= ir
->mask
.x
;
1834 fs_reg result
= fs_reg(this, ir
->type
);
1835 this->result
= result
;
1837 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1838 fs_reg channel
= val
;
1856 channel
.reg_offset
+= swiz
;
1857 emit(MOV(result
, channel
));
1858 result
.reg_offset
++;
1863 fs_visitor::visit(ir_discard
*ir
)
1865 assert(ir
->condition
== NULL
); /* FINISHME */
1867 /* We track our discarded pixels in f0.1. By predicating on it, we can
1868 * update just the flag bits that aren't yet discarded. By emitting a
1869 * CMP of g0 != g0, all our currently executing channels will get turned
1872 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1873 BRW_REGISTER_TYPE_UW
));
1874 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1875 BRW_CONDITIONAL_NZ
));
1876 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1877 cmp
->flag_subreg
= 1;
1879 if (brw
->gen
>= 6) {
1880 /* For performance, after a discard, jump to the end of the shader.
1881 * However, many people will do foliage by discarding based on a
1882 * texture's alpha mask, and then continue on to texture with the
1883 * remaining pixels. To avoid trashing the derivatives for those
1884 * texture samples, we'll only jump if all of the pixels in the subspan
1885 * have been discarded.
1887 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1888 discard_jump
->flag_subreg
= 1;
1889 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1890 discard_jump
->predicate_inverse
= true;
1895 fs_visitor::visit(ir_constant
*ir
)
1897 /* Set this->result to reg at the bottom of the function because some code
1898 * paths will cause this visitor to be applied to other fields. This will
1899 * cause the value stored in this->result to be modified.
1901 * Make reg constant so that it doesn't get accidentally modified along the
1902 * way. Yes, I actually had this problem. :(
1904 const fs_reg
reg(this, ir
->type
);
1905 fs_reg dst_reg
= reg
;
1907 if (ir
->type
->is_array()) {
1908 const unsigned size
= type_size(ir
->type
->fields
.array
);
1910 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1911 ir
->array_elements
[i
]->accept(this);
1912 fs_reg src_reg
= this->result
;
1914 dst_reg
.type
= src_reg
.type
;
1915 for (unsigned j
= 0; j
< size
; j
++) {
1916 emit(MOV(dst_reg
, src_reg
));
1917 src_reg
.reg_offset
++;
1918 dst_reg
.reg_offset
++;
1921 } else if (ir
->type
->is_record()) {
1922 foreach_list(node
, &ir
->components
) {
1923 ir_constant
*const field
= (ir_constant
*) node
;
1924 const unsigned size
= type_size(field
->type
);
1926 field
->accept(this);
1927 fs_reg src_reg
= this->result
;
1929 dst_reg
.type
= src_reg
.type
;
1930 for (unsigned j
= 0; j
< size
; j
++) {
1931 emit(MOV(dst_reg
, src_reg
));
1932 src_reg
.reg_offset
++;
1933 dst_reg
.reg_offset
++;
1937 const unsigned size
= type_size(ir
->type
);
1939 for (unsigned i
= 0; i
< size
; i
++) {
1940 switch (ir
->type
->base_type
) {
1941 case GLSL_TYPE_FLOAT
:
1942 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1944 case GLSL_TYPE_UINT
:
1945 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1948 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1950 case GLSL_TYPE_BOOL
:
1951 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1954 assert(!"Non-float/uint/int/bool constant");
1956 dst_reg
.reg_offset
++;
1964 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1966 ir_expression
*expr
= ir
->as_expression();
1969 expr
->operation
!= ir_binop_logic_and
&&
1970 expr
->operation
!= ir_binop_logic_or
&&
1971 expr
->operation
!= ir_binop_logic_xor
) {
1975 assert(expr
->get_num_operands() <= 2);
1976 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1977 assert(expr
->operands
[i
]->type
->is_scalar());
1979 expr
->operands
[i
]->accept(this);
1980 op
[i
] = this->result
;
1982 resolve_ud_negate(&op
[i
]);
1985 switch (expr
->operation
) {
1986 case ir_unop_logic_not
:
1987 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1988 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1992 if (brw
->gen
>= 6) {
1993 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1995 inst
= emit(MOV(reg_null_f
, op
[0]));
1996 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2001 if (brw
->gen
>= 6) {
2002 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2004 inst
= emit(MOV(reg_null_d
, op
[0]));
2005 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2009 case ir_binop_greater
:
2010 case ir_binop_gequal
:
2012 case ir_binop_lequal
:
2013 case ir_binop_equal
:
2014 case ir_binop_all_equal
:
2015 case ir_binop_nequal
:
2016 case ir_binop_any_nequal
:
2017 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2018 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2020 emit(CMP(reg_null_d
, op
[0], op
[1],
2021 brw_conditional_for_comparison(expr
->operation
)));
2025 assert(!"not reached");
2026 fail("bad cond code\n");
2034 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2035 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2039 * Emit a gen6 IF statement with the comparison folded into the IF
2043 fs_visitor::emit_if_gen6(ir_if
*ir
)
2045 ir_expression
*expr
= ir
->condition
->as_expression();
2052 assert(expr
->get_num_operands() <= 2);
2053 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2054 assert(expr
->operands
[i
]->type
->is_scalar());
2056 expr
->operands
[i
]->accept(this);
2057 op
[i
] = this->result
;
2060 switch (expr
->operation
) {
2061 case ir_unop_logic_not
:
2062 case ir_binop_logic_xor
:
2063 case ir_binop_logic_or
:
2064 case ir_binop_logic_and
:
2065 /* For operations on bool arguments, only the low bit of the bool is
2066 * valid, and the others are undefined. Fall back to the condition
2072 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2073 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2077 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2080 case ir_binop_greater
:
2081 case ir_binop_gequal
:
2083 case ir_binop_lequal
:
2084 case ir_binop_equal
:
2085 case ir_binop_all_equal
:
2086 case ir_binop_nequal
:
2087 case ir_binop_any_nequal
:
2088 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2089 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2091 emit(IF(op
[0], op
[1],
2092 brw_conditional_for_comparison(expr
->operation
)));
2095 assert(!"not reached");
2096 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2097 fail("bad condition\n");
2102 emit_bool_to_cond_code(ir
->condition
);
2103 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
2104 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2108 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2110 * Many GLSL shaders contain the following pattern:
2112 * x = condition ? foo : bar
2114 * The compiler emits an ir_if tree for this, since each subexpression might be
2115 * a complex tree that could have side-effects or short-circuit logic.
2117 * However, the common case is to simply select one of two constants or
2118 * variable values---which is exactly what SEL is for. In this case, the
2119 * assembly looks like:
2127 * which can be easily translated into:
2129 * (+f0) SEL dst src0 src1
2131 * If src0 is an immediate value, we promote it to a temporary GRF.
2134 fs_visitor::try_replace_with_sel()
2136 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2137 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2139 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2141 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2144 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2145 for (int i
= 0; i
< 4; i
++) {
2146 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2148 match
= (fs_inst
*) match
->prev
;
2151 /* The opcodes match; it looks like the right sequence of instructions. */
2152 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2153 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2154 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2156 /* Check that the MOVs are the right form. */
2157 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2158 !then_mov
->is_partial_write() &&
2159 !else_mov
->is_partial_write()) {
2161 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2162 while (!if_inst
->next
->is_tail_sentinel())
2163 if_inst
->next
->remove();
2166 /* Only the last source register can be a constant, so if the MOV in
2167 * the "then" clause uses a constant, we need to put it in a temporary.
2169 fs_reg
src0(then_mov
->src
[0]);
2170 if (src0
.file
== IMM
) {
2171 src0
= fs_reg(this, glsl_type::float_type
);
2172 src0
.type
= then_mov
->src
[0].type
;
2173 emit(MOV(src0
, then_mov
->src
[0]));
2177 if (if_inst
->conditional_mod
) {
2178 /* Sandybridge-specific IF with embedded comparison */
2179 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2180 if_inst
->conditional_mod
));
2181 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2182 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2184 /* Separate CMP and IF instructions */
2185 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2186 sel
->predicate
= if_inst
->predicate
;
2187 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2193 fs_visitor::visit(ir_if
*ir
)
2196 no16("Can't support (non-uniform) control flow on SIMD16\n");
2199 /* Don't point the annotation at the if statement, because then it plus
2200 * the then and else blocks get printed.
2202 this->base_ir
= ir
->condition
;
2204 if (brw
->gen
== 6) {
2207 emit_bool_to_cond_code(ir
->condition
);
2209 emit(IF(BRW_PREDICATE_NORMAL
));
2212 foreach_list(node
, &ir
->then_instructions
) {
2213 ir_instruction
*ir
= (ir_instruction
*)node
;
2219 if (!ir
->else_instructions
.is_empty()) {
2220 emit(BRW_OPCODE_ELSE
);
2222 foreach_list(node
, &ir
->else_instructions
) {
2223 ir_instruction
*ir
= (ir_instruction
*)node
;
2230 emit(BRW_OPCODE_ENDIF
);
2232 try_replace_with_sel();
2236 fs_visitor::visit(ir_loop
*ir
)
2239 no16("Can't support (non-uniform) control flow on SIMD16\n");
2242 this->base_ir
= NULL
;
2243 emit(BRW_OPCODE_DO
);
2245 foreach_list(node
, &ir
->body_instructions
) {
2246 ir_instruction
*ir
= (ir_instruction
*)node
;
2252 this->base_ir
= NULL
;
2253 emit(BRW_OPCODE_WHILE
);
2257 fs_visitor::visit(ir_loop_jump
*ir
)
2260 case ir_loop_jump::jump_break
:
2261 emit(BRW_OPCODE_BREAK
);
2263 case ir_loop_jump::jump_continue
:
2264 emit(BRW_OPCODE_CONTINUE
);
2270 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2272 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2273 ir
->actual_parameters
.get_head());
2274 ir_variable
*location
= deref
->variable_referenced();
2275 unsigned surf_index
= (c
->prog_data
.base
.binding_table
.abo_start
+
2276 location
->data
.atomic
.buffer_index
);
2278 /* Calculate the surface offset */
2279 fs_reg
offset(this, glsl_type::uint_type
);
2280 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2283 deref_array
->array_index
->accept(this);
2285 fs_reg
tmp(this, glsl_type::uint_type
);
2286 emit(MUL(tmp
, this->result
, ATOMIC_COUNTER_SIZE
));
2287 emit(ADD(offset
, tmp
, location
->data
.atomic
.offset
));
2289 offset
= location
->data
.atomic
.offset
;
2292 /* Emit the appropriate machine instruction */
2293 const char *callee
= ir
->callee
->function_name();
2294 ir
->return_deref
->accept(this);
2295 fs_reg dst
= this->result
;
2297 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2298 emit_untyped_surface_read(surf_index
, dst
, offset
);
2300 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2301 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2302 fs_reg(), fs_reg());
2304 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2305 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2306 fs_reg(), fs_reg());
2311 fs_visitor::visit(ir_call
*ir
)
2313 const char *callee
= ir
->callee
->function_name();
2315 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2316 !strcmp("__intrinsic_atomic_increment", callee
) ||
2317 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2318 visit_atomic_counter_intrinsic(ir
);
2320 assert(!"Unsupported intrinsic.");
2325 fs_visitor::visit(ir_return
*ir
)
2327 assert(!"FINISHME");
2331 fs_visitor::visit(ir_function
*ir
)
2333 /* Ignore function bodies other than main() -- we shouldn't see calls to
2334 * them since they should all be inlined before we get to ir_to_mesa.
2336 if (strcmp(ir
->name
, "main") == 0) {
2337 const ir_function_signature
*sig
;
2340 sig
= ir
->matching_signature(NULL
, &empty
);
2344 foreach_list(node
, &sig
->body
) {
2345 ir_instruction
*ir
= (ir_instruction
*)node
;
2354 fs_visitor::visit(ir_function_signature
*ir
)
2356 assert(!"not reached");
2361 fs_visitor::visit(ir_emit_vertex
*)
2363 assert(!"not reached");
2367 fs_visitor::visit(ir_end_primitive
*)
2369 assert(!"not reached");
2373 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2374 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2377 const unsigned operand_len
= dispatch_width
/ 8;
2380 /* Initialize the sample mask in the message header. */
2381 emit(MOV(brw_uvec_mrf(8, mlen
, 0), brw_imm_ud(0)))
2382 ->force_writemask_all
= true;
2385 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2386 ->force_writemask_all
= true;
2388 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2389 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2390 ->force_writemask_all
= true;
2395 /* Set the atomic operation offset. */
2396 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2397 mlen
+= operand_len
;
2399 /* Set the atomic operation arguments. */
2400 if (src0
.file
!= BAD_FILE
) {
2401 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src0
));
2402 mlen
+= operand_len
;
2405 if (src1
.file
!= BAD_FILE
) {
2406 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src1
));
2407 mlen
+= operand_len
;
2410 /* Emit the instruction. */
2411 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2412 atomic_op
, surf_index
);
2419 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2422 const unsigned operand_len
= dispatch_width
/ 8;
2425 /* Initialize the sample mask in the message header. */
2426 emit(MOV(brw_uvec_mrf(8, mlen
, 0), brw_imm_ud(0)))
2427 ->force_writemask_all
= true;
2430 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2431 ->force_writemask_all
= true;
2433 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2434 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2435 ->force_writemask_all
= true;
2440 /* Set the surface read offset. */
2441 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2442 mlen
+= operand_len
;
2444 /* Emit the instruction. */
2445 fs_inst
*inst
= new(mem_ctx
)
2446 fs_inst(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, surf_index
);
2453 fs_visitor::emit(fs_inst
*inst
)
2455 if (force_uncompressed_stack
> 0)
2456 inst
->force_uncompressed
= true;
2458 inst
->annotation
= this->current_annotation
;
2459 inst
->ir
= this->base_ir
;
2461 this->instructions
.push_tail(inst
);
2467 fs_visitor::emit(exec_list list
)
2469 foreach_list_safe(node
, &list
) {
2470 fs_inst
*inst
= (fs_inst
*)node
;
2476 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2478 fs_visitor::emit_dummy_fs()
2480 int reg_width
= dispatch_width
/ 8;
2482 /* Everyone's favorite color. */
2483 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2484 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2485 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2486 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2489 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2490 write
->base_mrf
= 2;
2491 write
->mlen
= 4 * reg_width
;
2495 /* The register location here is relative to the start of the URB
2496 * data. It will get adjusted to be a real location before
2497 * generate_code() time.
2500 fs_visitor::interp_reg(int location
, int channel
)
2502 int regnr
= c
->prog_data
.urb_setup
[location
] * 2 + channel
/ 2;
2503 int stride
= (channel
& 1) * 4;
2505 assert(c
->prog_data
.urb_setup
[location
] != -1);
2507 return brw_vec1_grf(regnr
, stride
);
2510 /** Emits the interpolation for the varying inputs. */
2512 fs_visitor::emit_interpolation_setup_gen4()
2514 this->current_annotation
= "compute pixel centers";
2515 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2516 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2517 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2518 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2520 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2521 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2523 this->current_annotation
= "compute pixel deltas from v0";
2525 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2526 fs_reg(this, glsl_type::vec2_type
);
2527 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2528 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2529 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2531 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2532 fs_reg(this, glsl_type::float_type
);
2533 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2534 fs_reg(this, glsl_type::float_type
);
2536 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2537 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2538 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2539 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2541 this->current_annotation
= "compute pos.w and 1/pos.w";
2542 /* Compute wpos.w. It's always in our setup, since it's needed to
2543 * interpolate the other attributes.
2545 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2546 emit(FS_OPCODE_LINTERP
, wpos_w
,
2547 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2548 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2549 interp_reg(VARYING_SLOT_POS
, 3));
2550 /* Compute the pixel 1/W value from wpos.w. */
2551 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2552 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2553 this->current_annotation
= NULL
;
2556 /** Emits the interpolation for the varying inputs. */
2558 fs_visitor::emit_interpolation_setup_gen6()
2560 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2562 /* If the pixel centers end up used, the setup is the same as for gen4. */
2563 this->current_annotation
= "compute pixel centers";
2564 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2565 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2566 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2567 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2568 emit(ADD(int_pixel_x
,
2569 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2570 fs_reg(brw_imm_v(0x10101010))));
2571 emit(ADD(int_pixel_y
,
2572 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2573 fs_reg(brw_imm_v(0x11001100))));
2575 /* As of gen6, we can no longer mix float and int sources. We have
2576 * to turn the integer pixel centers into floats for their actual
2579 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2580 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2581 emit(MOV(this->pixel_x
, int_pixel_x
));
2582 emit(MOV(this->pixel_y
, int_pixel_y
));
2584 this->current_annotation
= "compute pos.w";
2585 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2586 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2587 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2589 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2590 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2591 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2592 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2595 this->current_annotation
= NULL
;
2599 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2601 int reg_width
= dispatch_width
/ 8;
2603 fs_reg color
= outputs
[target
];
2606 /* If there's no color data to be written, skip it. */
2607 if (color
.file
== BAD_FILE
)
2610 color
.reg_offset
+= index
;
2612 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2613 /* SIMD8 write looks like:
2619 * gen6 SIMD16 DP write looks like:
2629 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2632 inst
->saturate
= c
->key
.clamp_fragment_color
;
2634 /* pre-gen6 SIMD16 single source DP write looks like:
2644 if (brw
->has_compr4
) {
2645 /* By setting the high bit of the MRF register number, we
2646 * indicate that we want COMPR4 mode - instead of doing the
2647 * usual destination + 1 for the second half we get
2650 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2653 inst
->saturate
= c
->key
.clamp_fragment_color
;
2655 push_force_uncompressed();
2656 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2658 inst
->saturate
= c
->key
.clamp_fragment_color
;
2659 pop_force_uncompressed();
2661 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2663 inst
->force_sechalf
= true;
2664 inst
->saturate
= c
->key
.clamp_fragment_color
;
2670 cond_for_alpha_func(GLenum func
)
2674 return BRW_CONDITIONAL_G
;
2676 return BRW_CONDITIONAL_GE
;
2678 return BRW_CONDITIONAL_L
;
2680 return BRW_CONDITIONAL_LE
;
2682 return BRW_CONDITIONAL_EQ
;
2684 return BRW_CONDITIONAL_NEQ
;
2686 assert(!"Not reached");
2692 * Alpha test support for when we compile it into the shader instead
2693 * of using the normal fixed-function alpha test.
2696 fs_visitor::emit_alpha_test()
2698 this->current_annotation
= "Alpha test";
2701 if (c
->key
.alpha_test_func
== GL_ALWAYS
)
2704 if (c
->key
.alpha_test_func
== GL_NEVER
) {
2706 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2707 BRW_REGISTER_TYPE_UW
));
2708 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2709 BRW_CONDITIONAL_NEQ
));
2712 fs_reg color
= outputs
[0];
2713 color
.reg_offset
+= 3;
2715 /* f0.1 &= func(color, ref) */
2716 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(c
->key
.alpha_test_ref
),
2717 cond_for_alpha_func(c
->key
.alpha_test_func
)));
2719 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2720 cmp
->flag_subreg
= 1;
2724 fs_visitor::emit_fb_writes()
2726 this->current_annotation
= "FB write header";
2727 bool header_present
= true;
2728 /* We can potentially have a message length of up to 15, so we have to set
2729 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2733 int reg_width
= dispatch_width
/ 8;
2734 bool src0_alpha_to_render_target
= false;
2737 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
2738 if (dispatch_width
== 16)
2739 do_dual_src
= false;
2742 /* From the Sandy Bridge PRM, volume 4, page 198:
2744 * "Dispatched Pixel Enables. One bit per pixel indicating
2745 * which pixels were originally enabled when the thread was
2746 * dispatched. This field is only required for the end-of-
2747 * thread message and on all dual-source messages."
2749 if (brw
->gen
>= 6 &&
2750 (brw
->is_haswell
|| brw
->gen
>= 8 || !this->fp
->UsesKill
) &&
2752 c
->key
.nr_color_regions
== 1) {
2753 header_present
= false;
2756 if (header_present
) {
2757 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
2759 c
->key
.replicate_alpha
;
2764 if (c
->aa_dest_stencil_reg
) {
2765 push_force_uncompressed();
2766 emit(MOV(fs_reg(MRF
, nr
++),
2767 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2768 pop_force_uncompressed();
2771 c
->prog_data
.uses_omask
=
2772 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
2773 if(c
->prog_data
.uses_omask
) {
2774 this->current_annotation
= "FB write oMask";
2775 assert(this->sample_mask
.file
!= BAD_FILE
);
2776 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
2777 emit(FS_OPCODE_SET_OMASK
, fs_reg(MRF
, nr
, BRW_REGISTER_TYPE_UW
), this->sample_mask
);
2781 /* Reserve space for color. It'll be filled in per MRT below. */
2783 nr
+= 4 * reg_width
;
2786 if (src0_alpha_to_render_target
)
2789 if (c
->source_depth_to_render_target
) {
2790 if (brw
->gen
== 6) {
2791 /* For outputting oDepth on gen6, SIMD8 writes have to be
2792 * used. This would require SIMD8 moves of each half to
2793 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2794 * Just bail on doing so for now.
2796 no16("Missing support for simd16 depth writes on gen6\n");
2799 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2800 /* Hand over gl_FragDepth. */
2801 assert(this->frag_depth
.file
!= BAD_FILE
);
2802 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2804 /* Pass through the payload depth. */
2805 emit(MOV(fs_reg(MRF
, nr
),
2806 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2811 if (c
->dest_depth_reg
) {
2812 emit(MOV(fs_reg(MRF
, nr
),
2813 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2818 fs_reg src0
= this->outputs
[0];
2819 fs_reg src1
= this->dual_src_output
;
2821 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2823 for (int i
= 0; i
< 4; i
++) {
2824 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2826 inst
->saturate
= c
->key
.clamp_fragment_color
;
2829 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2831 for (int i
= 0; i
< 4; i
++) {
2832 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2835 inst
->saturate
= c
->key
.clamp_fragment_color
;
2838 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2839 emit_shader_time_end();
2841 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2843 inst
->base_mrf
= base_mrf
;
2844 inst
->mlen
= nr
- base_mrf
;
2846 inst
->header_present
= header_present
;
2847 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2848 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2849 inst
->flag_subreg
= 1;
2852 c
->prog_data
.dual_src_blend
= true;
2853 this->current_annotation
= NULL
;
2857 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2858 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2859 "FB write target %d",
2861 /* If src0_alpha_to_render_target is true, include source zero alpha
2862 * data in RenderTargetWrite message for targets > 0.
2864 int write_color_mrf
= color_mrf
;
2865 if (src0_alpha_to_render_target
&& target
!= 0) {
2867 fs_reg color
= outputs
[0];
2868 color
.reg_offset
+= 3;
2870 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2872 inst
->saturate
= c
->key
.clamp_fragment_color
;
2873 write_color_mrf
= color_mrf
+ reg_width
;
2876 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2877 emit_color_write(target
, i
, write_color_mrf
);
2880 if (target
== c
->key
.nr_color_regions
- 1) {
2883 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2884 emit_shader_time_end();
2887 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2888 inst
->target
= target
;
2889 inst
->base_mrf
= base_mrf
;
2890 if (src0_alpha_to_render_target
&& target
== 0)
2891 inst
->mlen
= nr
- base_mrf
- reg_width
;
2893 inst
->mlen
= nr
- base_mrf
;
2895 inst
->header_present
= header_present
;
2896 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2897 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2898 inst
->flag_subreg
= 1;
2902 if (c
->key
.nr_color_regions
== 0) {
2903 /* Even if there's no color buffers enabled, we still need to send
2904 * alpha out the pipeline to our null renderbuffer to support
2905 * alpha-testing, alpha-to-coverage, and so on.
2907 emit_color_write(0, 3, color_mrf
);
2909 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2910 emit_shader_time_end();
2912 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2913 inst
->base_mrf
= base_mrf
;
2914 inst
->mlen
= nr
- base_mrf
;
2916 inst
->header_present
= header_present
;
2917 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2918 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2919 inst
->flag_subreg
= 1;
2923 this->current_annotation
= NULL
;
2927 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2929 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2933 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2934 emit(MOV(temp
, *reg
));
2939 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2941 if (rvalue
->type
!= glsl_type::bool_type
)
2944 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2945 emit(AND(temp
, *reg
, fs_reg(1)));
2949 fs_visitor::fs_visitor(struct brw_context
*brw
,
2950 struct brw_wm_compile
*c
,
2951 struct gl_shader_program
*shader_prog
,
2952 struct gl_fragment_program
*fp
,
2953 unsigned dispatch_width
)
2954 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &c
->prog_data
.base
,
2955 MESA_SHADER_FRAGMENT
),
2956 dispatch_width(dispatch_width
)
2960 this->mem_ctx
= ralloc_context(NULL
);
2961 this->failed
= false;
2962 this->simd16_unsupported
= false;
2963 this->no16_msg
= NULL
;
2964 this->variable_ht
= hash_table_ctor(0,
2965 hash_table_pointer_hash
,
2966 hash_table_pointer_compare
);
2968 memset(this->outputs
, 0, sizeof(this->outputs
));
2969 memset(this->output_components
, 0, sizeof(this->output_components
));
2970 this->first_non_payload_grf
= 0;
2971 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2973 this->current_annotation
= NULL
;
2974 this->base_ir
= NULL
;
2976 this->virtual_grf_sizes
= NULL
;
2977 this->virtual_grf_count
= 0;
2978 this->virtual_grf_array_size
= 0;
2979 this->virtual_grf_start
= NULL
;
2980 this->virtual_grf_end
= NULL
;
2981 this->live_intervals
= NULL
;
2982 this->regs_live_at_ip
= NULL
;
2985 this->pull_constant_loc
= NULL
;
2986 this->push_constant_loc
= NULL
;
2988 this->force_uncompressed_stack
= 0;
2990 this->spilled_any_registers
= false;
2991 this->do_dual_src
= false;
2993 if (dispatch_width
== 8)
2994 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
2997 fs_visitor::~fs_visitor()
2999 ralloc_free(this->mem_ctx
);
3000 hash_table_dtor(this->variable_ht
);