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i965/fs: Don't double-accept operands of logical and/or/xor operations.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_visitor.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "brw_fs.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50
51 void
52 fs_visitor::visit(ir_variable *ir)
53 {
54 fs_reg *reg = NULL;
55
56 if (variable_storage(ir))
57 return;
58
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
64 } else {
65 reg = emit_general_interpolation(ir);
66 }
67 assert(reg);
68 hash_table_insert(this->variable_ht, reg, ir);
69 return;
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
72
73 if (ir->index > 0) {
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
82 }
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
85 } else {
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
89
90 int vector_elements =
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
93
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
100 }
101 }
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
104
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
108 */
109 if (ir->is_in_uniform_block())
110 return;
111
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
115 }
116 return;
117 }
118
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
122 } else {
123 setup_uniform_values(ir);
124 }
125
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
128 }
129
130 if (!reg)
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
132
133 hash_table_insert(this->variable_ht, reg, ir);
134 }
135
136 void
137 fs_visitor::visit(ir_dereference_variable *ir)
138 {
139 fs_reg *reg = variable_storage(ir->var);
140 this->result = *reg;
141 }
142
143 void
144 fs_visitor::visit(ir_dereference_record *ir)
145 {
146 const glsl_type *struct_type = ir->record->type;
147
148 ir->record->accept(this);
149
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
153 break;
154 offset += type_size(struct_type->fields.structure[i].type);
155 }
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
158 }
159
160 void
161 fs_visitor::visit(ir_dereference_array *ir)
162 {
163 ir_constant *constant_index;
164 fs_reg src;
165 int element_size = type_size(ir->type);
166
167 constant_index = ir->array_index->as_constant();
168
169 ir->array->accept(this);
170 src = this->result;
171 src.type = brw_type_for_base_type(ir->type);
172
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
176 } else {
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
183 */
184 ir->array_index->accept(this);
185
186 fs_reg index_reg;
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
189
190 if (src.reladdr) {
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
192 }
193
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
196 }
197 this->result = src;
198 }
199
200 void
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
202 {
203 if (brw->gen < 6 ||
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
211
212 emit(MUL(y_times_a, y, a));
213
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
217
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
219 } else {
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
222 */
223 emit(LRP(dst, a, y, x));
224 }
225 }
226
227 void
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
230 {
231 fs_inst *inst;
232
233 if (brw->gen >= 6) {
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
236 } else {
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
238
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
241 }
242 }
243
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
246 */
247 bool
248 fs_visitor::try_emit_saturate(ir_expression *ir)
249 {
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
251
252 if (!sat_val)
253 return false;
254
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
256
257 sat_val->accept(this);
258 fs_reg src = this->result;
259
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
261
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
264 */
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
270 } else {
271 modify->saturate = true;
272 this->result = src;
273 }
274
275
276 return true;
277 }
278
279 bool
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
281 {
282 /* 3-src instructions were introduced in gen6. */
283 if (brw->gen < 6)
284 return false;
285
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
288 return false;
289
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
292
293 if (!mul || mul->operation != ir_binop_mul)
294 return false;
295
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
299 return false;
300
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
303
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
306
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
309
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
312
313 return true;
314 }
315
316 void
317 fs_visitor::visit(ir_expression *ir)
318 {
319 unsigned int operand;
320 fs_reg op[3], temp;
321 fs_inst *inst;
322
323 assert(ir->get_num_operands() <= 3);
324
325 if (try_emit_saturate(ir))
326 return;
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
329 return;
330 }
331
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
337 printf("\n");
338 }
339 assert(this->result.is_valid_3src());
340 op[operand] = this->result;
341
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
344 */
345 assert(!ir->operands[operand]->type->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
347 */
348 assert(!ir->operands[operand]->type->is_vector());
349 }
350
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
353 */
354 this->result = fs_reg(this, ir->type);
355
356 switch (ir->operation) {
357 case ir_unop_logic_not:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
360 */
361 emit(XOR(this->result, op[0], fs_reg(1)));
362 break;
363 case ir_unop_neg:
364 op[0].negate = !op[0].negate;
365 emit(MOV(this->result, op[0]));
366 break;
367 case ir_unop_abs:
368 op[0].abs = true;
369 op[0].negate = false;
370 emit(MOV(this->result, op[0]));
371 break;
372 case ir_unop_sign:
373 temp = fs_reg(this, ir->type);
374
375 emit(MOV(this->result, fs_reg(0.0f)));
376
377 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
378 inst = emit(MOV(this->result, fs_reg(1.0f)));
379 inst->predicate = BRW_PREDICATE_NORMAL;
380
381 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
382 inst = emit(MOV(this->result, fs_reg(-1.0f)));
383 inst->predicate = BRW_PREDICATE_NORMAL;
384
385 break;
386 case ir_unop_rcp:
387 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
388 break;
389
390 case ir_unop_exp2:
391 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
392 break;
393 case ir_unop_log2:
394 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
395 break;
396 case ir_unop_exp:
397 case ir_unop_log:
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
399 break;
400 case ir_unop_sin:
401 case ir_unop_sin_reduced:
402 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
403 break;
404 case ir_unop_cos:
405 case ir_unop_cos_reduced:
406 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
407 break;
408
409 case ir_unop_dFdx:
410 emit(FS_OPCODE_DDX, this->result, op[0]);
411 break;
412 case ir_unop_dFdy:
413 emit(FS_OPCODE_DDY, this->result, op[0]);
414 break;
415
416 case ir_binop_add:
417 emit(ADD(this->result, op[0], op[1]));
418 break;
419 case ir_binop_sub:
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 break;
422
423 case ir_binop_mul:
424 if (ir->type->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
428 * of that operand.
429 *
430 * FINISHME: Emit just the MUL if we know an operand is small
431 * enough.
432 */
433 if (brw->gen >= 7 && dispatch_width == 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
435
436 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
437
438 emit(MUL(acc, op[0], op[1]));
439 emit(MACH(reg_null_d, op[0], op[1]));
440 emit(MOV(this->result, fs_reg(acc)));
441 } else {
442 emit(MUL(this->result, op[0], op[1]));
443 }
444 break;
445 case ir_binop_div:
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir->type->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
449 break;
450 case ir_binop_mod:
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir->type->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
454 break;
455
456 case ir_binop_less:
457 case ir_binop_greater:
458 case ir_binop_lequal:
459 case ir_binop_gequal:
460 case ir_binop_equal:
461 case ir_binop_all_equal:
462 case ir_binop_nequal:
463 case ir_binop_any_nequal:
464 resolve_bool_comparison(ir->operands[0], &op[0]);
465 resolve_bool_comparison(ir->operands[1], &op[1]);
466
467 emit(CMP(this->result, op[0], op[1],
468 brw_conditional_for_comparison(ir->operation)));
469 break;
470
471 case ir_binop_logic_xor:
472 emit(XOR(this->result, op[0], op[1]));
473 break;
474
475 case ir_binop_logic_or:
476 emit(OR(this->result, op[0], op[1]));
477 break;
478
479 case ir_binop_logic_and:
480 emit(AND(this->result, op[0], op[1]));
481 break;
482
483 case ir_binop_dot:
484 case ir_unop_any:
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 break;
487
488 case ir_unop_noise:
489 assert(!"not reached: should be handled by lower_noise");
490 break;
491
492 case ir_quadop_vector:
493 assert(!"not reached: should be handled by lower_quadop_vector");
494 break;
495
496 case ir_binop_vector_extract:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
498 break;
499
500 case ir_triop_vector_insert:
501 assert(!"not reached: should be handled by lower_vector_insert()");
502 break;
503
504 case ir_binop_ldexp:
505 assert(!"not reached: should be handled by ldexp_to_arith()");
506 break;
507
508 case ir_unop_sqrt:
509 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
510 break;
511
512 case ir_unop_rsq:
513 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
514 break;
515
516 case ir_unop_bitcast_i2f:
517 case ir_unop_bitcast_u2f:
518 op[0].type = BRW_REGISTER_TYPE_F;
519 this->result = op[0];
520 break;
521 case ir_unop_i2u:
522 case ir_unop_bitcast_f2u:
523 op[0].type = BRW_REGISTER_TYPE_UD;
524 this->result = op[0];
525 break;
526 case ir_unop_u2i:
527 case ir_unop_bitcast_f2i:
528 op[0].type = BRW_REGISTER_TYPE_D;
529 this->result = op[0];
530 break;
531 case ir_unop_i2f:
532 case ir_unop_u2f:
533 case ir_unop_f2i:
534 case ir_unop_f2u:
535 emit(MOV(this->result, op[0]));
536 break;
537
538 case ir_unop_b2i:
539 emit(AND(this->result, op[0], fs_reg(1)));
540 break;
541 case ir_unop_b2f:
542 temp = fs_reg(this, glsl_type::int_type);
543 emit(AND(temp, op[0], fs_reg(1)));
544 emit(MOV(this->result, temp));
545 break;
546
547 case ir_unop_f2b:
548 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
549 break;
550 case ir_unop_i2b:
551 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
552 break;
553
554 case ir_unop_trunc:
555 emit(RNDZ(this->result, op[0]));
556 break;
557 case ir_unop_ceil:
558 op[0].negate = !op[0].negate;
559 emit(RNDD(this->result, op[0]));
560 this->result.negate = true;
561 break;
562 case ir_unop_floor:
563 emit(RNDD(this->result, op[0]));
564 break;
565 case ir_unop_fract:
566 emit(FRC(this->result, op[0]));
567 break;
568 case ir_unop_round_even:
569 emit(RNDE(this->result, op[0]));
570 break;
571
572 case ir_binop_min:
573 case ir_binop_max:
574 resolve_ud_negate(&op[0]);
575 resolve_ud_negate(&op[1]);
576 emit_minmax(ir->operation == ir_binop_min ?
577 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
578 this->result, op[0], op[1]);
579 break;
580 case ir_unop_pack_snorm_2x16:
581 case ir_unop_pack_snorm_4x8:
582 case ir_unop_pack_unorm_2x16:
583 case ir_unop_pack_unorm_4x8:
584 case ir_unop_unpack_snorm_2x16:
585 case ir_unop_unpack_snorm_4x8:
586 case ir_unop_unpack_unorm_2x16:
587 case ir_unop_unpack_unorm_4x8:
588 case ir_unop_unpack_half_2x16:
589 case ir_unop_pack_half_2x16:
590 assert(!"not reached: should be handled by lower_packing_builtins");
591 break;
592 case ir_unop_unpack_half_2x16_split_x:
593 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
594 break;
595 case ir_unop_unpack_half_2x16_split_y:
596 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
597 break;
598 case ir_binop_pow:
599 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
600 break;
601
602 case ir_unop_bitfield_reverse:
603 emit(BFREV(this->result, op[0]));
604 break;
605 case ir_unop_bit_count:
606 emit(CBIT(this->result, op[0]));
607 break;
608 case ir_unop_find_msb:
609 temp = fs_reg(this, glsl_type::uint_type);
610 emit(FBH(temp, op[0]));
611
612 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
613 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
614 * subtract the result from 31 to convert the MSB count into an LSB count.
615 */
616
617 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
618 emit(MOV(this->result, temp));
619 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
620
621 temp.negate = true;
622 inst = emit(ADD(this->result, temp, fs_reg(31)));
623 inst->predicate = BRW_PREDICATE_NORMAL;
624 break;
625 case ir_unop_find_lsb:
626 emit(FBL(this->result, op[0]));
627 break;
628 case ir_triop_bitfield_extract:
629 /* Note that the instruction's argument order is reversed from GLSL
630 * and the IR.
631 */
632 emit(BFE(this->result, op[2], op[1], op[0]));
633 break;
634 case ir_binop_bfm:
635 emit(BFI1(this->result, op[0], op[1]));
636 break;
637 case ir_triop_bfi:
638 emit(BFI2(this->result, op[0], op[1], op[2]));
639 break;
640 case ir_quadop_bitfield_insert:
641 assert(!"not reached: should be handled by "
642 "lower_instructions::bitfield_insert_to_bfm_bfi");
643 break;
644
645 case ir_unop_bit_not:
646 emit(NOT(this->result, op[0]));
647 break;
648 case ir_binop_bit_and:
649 emit(AND(this->result, op[0], op[1]));
650 break;
651 case ir_binop_bit_xor:
652 emit(XOR(this->result, op[0], op[1]));
653 break;
654 case ir_binop_bit_or:
655 emit(OR(this->result, op[0], op[1]));
656 break;
657
658 case ir_binop_lshift:
659 emit(SHL(this->result, op[0], op[1]));
660 break;
661
662 case ir_binop_rshift:
663 if (ir->type->base_type == GLSL_TYPE_INT)
664 emit(ASR(this->result, op[0], op[1]));
665 else
666 emit(SHR(this->result, op[0], op[1]));
667 break;
668 case ir_binop_pack_half_2x16_split:
669 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
670 break;
671 case ir_binop_ubo_load: {
672 /* This IR node takes a constant uniform block and a constant or
673 * variable byte offset within the block and loads a vector from that.
674 */
675 ir_constant *uniform_block = ir->operands[0]->as_constant();
676 ir_constant *const_offset = ir->operands[1]->as_constant();
677 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
678 if (const_offset) {
679 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
680 packed_consts.type = result.type;
681
682 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
683 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
684 packed_consts, surf_index, const_offset_reg));
685
686 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
687 for (int i = 0; i < ir->type->vector_elements; i++) {
688 /* UBO bools are any nonzero value. We consider bools to be
689 * values with the low bit set to 1. Convert them using CMP.
690 */
691 if (ir->type->base_type == GLSL_TYPE_BOOL) {
692 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
693 } else {
694 emit(MOV(result, packed_consts));
695 }
696
697 packed_consts.smear++;
698 result.reg_offset++;
699
700 /* The std140 packing rules don't allow vectors to cross 16-byte
701 * boundaries, and a reg is 32 bytes.
702 */
703 assert(packed_consts.smear < 8);
704 }
705 } else {
706 /* Turn the byte offset into a dword offset. */
707 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
708 emit(SHR(base_offset, op[1], fs_reg(2)));
709
710 for (int i = 0; i < ir->type->vector_elements; i++) {
711 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
712 base_offset, i));
713
714 if (ir->type->base_type == GLSL_TYPE_BOOL)
715 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
716
717 result.reg_offset++;
718 }
719 }
720
721 result.reg_offset = 0;
722 break;
723 }
724
725 case ir_triop_fma:
726 /* Note that the instruction's argument order is reversed from GLSL
727 * and the IR.
728 */
729 emit(MAD(this->result, op[2], op[1], op[0]));
730 break;
731
732 case ir_triop_lrp:
733 emit_lrp(this->result, op[0], op[1], op[2]);
734 break;
735
736 case ir_triop_csel:
737 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
738 inst = emit(BRW_OPCODE_SEL, this->result, op[1], op[2]);
739 inst->predicate = BRW_PREDICATE_NORMAL;
740 break;
741 }
742 }
743
744 void
745 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
746 const glsl_type *type, bool predicated)
747 {
748 switch (type->base_type) {
749 case GLSL_TYPE_FLOAT:
750 case GLSL_TYPE_UINT:
751 case GLSL_TYPE_INT:
752 case GLSL_TYPE_BOOL:
753 for (unsigned int i = 0; i < type->components(); i++) {
754 l.type = brw_type_for_base_type(type);
755 r.type = brw_type_for_base_type(type);
756
757 if (predicated || !l.equals(r)) {
758 fs_inst *inst = emit(MOV(l, r));
759 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
760 }
761
762 l.reg_offset++;
763 r.reg_offset++;
764 }
765 break;
766 case GLSL_TYPE_ARRAY:
767 for (unsigned int i = 0; i < type->length; i++) {
768 emit_assignment_writes(l, r, type->fields.array, predicated);
769 }
770 break;
771
772 case GLSL_TYPE_STRUCT:
773 for (unsigned int i = 0; i < type->length; i++) {
774 emit_assignment_writes(l, r, type->fields.structure[i].type,
775 predicated);
776 }
777 break;
778
779 case GLSL_TYPE_SAMPLER:
780 break;
781
782 case GLSL_TYPE_VOID:
783 case GLSL_TYPE_ERROR:
784 case GLSL_TYPE_INTERFACE:
785 assert(!"not reached");
786 break;
787 }
788 }
789
790 /* If the RHS processing resulted in an instruction generating a
791 * temporary value, and it would be easy to rewrite the instruction to
792 * generate its result right into the LHS instead, do so. This ends
793 * up reliably removing instructions where it can be tricky to do so
794 * later without real UD chain information.
795 */
796 bool
797 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
798 fs_reg dst,
799 fs_reg src,
800 fs_inst *pre_rhs_inst,
801 fs_inst *last_rhs_inst)
802 {
803 /* Only attempt if we're doing a direct assignment. */
804 if (ir->condition ||
805 !(ir->lhs->type->is_scalar() ||
806 (ir->lhs->type->is_vector() &&
807 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
808 return false;
809
810 /* Make sure the last instruction generated our source reg. */
811 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
812 last_rhs_inst,
813 src);
814 if (!modify)
815 return false;
816
817 /* If last_rhs_inst wrote a different number of components than our LHS,
818 * we can't safely rewrite it.
819 */
820 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
821 return false;
822
823 /* Success! Rewrite the instruction. */
824 modify->dst = dst;
825
826 return true;
827 }
828
829 void
830 fs_visitor::visit(ir_assignment *ir)
831 {
832 fs_reg l, r;
833 fs_inst *inst;
834
835 /* FINISHME: arrays on the lhs */
836 ir->lhs->accept(this);
837 l = this->result;
838
839 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
840
841 ir->rhs->accept(this);
842 r = this->result;
843
844 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
845
846 assert(l.file != BAD_FILE);
847 assert(r.file != BAD_FILE);
848
849 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
850 return;
851
852 if (ir->condition) {
853 emit_bool_to_cond_code(ir->condition);
854 }
855
856 if (ir->lhs->type->is_scalar() ||
857 ir->lhs->type->is_vector()) {
858 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
859 if (ir->write_mask & (1 << i)) {
860 inst = emit(MOV(l, r));
861 if (ir->condition)
862 inst->predicate = BRW_PREDICATE_NORMAL;
863 r.reg_offset++;
864 }
865 l.reg_offset++;
866 }
867 } else {
868 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
869 }
870 }
871
872 fs_inst *
873 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
874 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
875 {
876 int mlen;
877 int base_mrf = 1;
878 bool simd16 = false;
879 fs_reg orig_dst;
880
881 /* g0 header. */
882 mlen = 1;
883
884 if (ir->shadow_comparitor) {
885 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
886 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
887 coordinate.reg_offset++;
888 }
889
890 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
891 * the unused slots must be zeroed.
892 */
893 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
894 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
895 }
896 mlen += 3;
897
898 if (ir->op == ir_tex) {
899 /* There's no plain shadow compare message, so we use shadow
900 * compare with a bias of 0.0.
901 */
902 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
903 mlen++;
904 } else if (ir->op == ir_txb || ir->op == ir_txl) {
905 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
906 mlen++;
907 } else {
908 assert(!"Should not get here.");
909 }
910
911 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
912 mlen++;
913 } else if (ir->op == ir_tex) {
914 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
915 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
916 coordinate.reg_offset++;
917 }
918 /* zero the others. */
919 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
920 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
921 }
922 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
923 mlen += 3;
924 } else if (ir->op == ir_txd) {
925 fs_reg &dPdx = lod;
926
927 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
928 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
929 coordinate.reg_offset++;
930 }
931 /* the slots for u and v are always present, but r is optional */
932 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
933
934 /* P = u, v, r
935 * dPdx = dudx, dvdx, drdx
936 * dPdy = dudy, dvdy, drdy
937 *
938 * 1-arg: Does not exist.
939 *
940 * 2-arg: dudx dvdx dudy dvdy
941 * dPdx.x dPdx.y dPdy.x dPdy.y
942 * m4 m5 m6 m7
943 *
944 * 3-arg: dudx dvdx drdx dudy dvdy drdy
945 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
946 * m5 m6 m7 m8 m9 m10
947 */
948 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
949 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
950 dPdx.reg_offset++;
951 }
952 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
953
954 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
955 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
956 dPdy.reg_offset++;
957 }
958 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
959 } else if (ir->op == ir_txs) {
960 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
961 simd16 = true;
962 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
963 mlen += 2;
964 } else {
965 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
966 * instructions. We'll need to do SIMD16 here.
967 */
968 simd16 = true;
969 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
970
971 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
972 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
973 coordinate));
974 coordinate.reg_offset++;
975 }
976
977 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
978 * be necessary for TXF (ld), but seems wise to do for all messages.
979 */
980 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
981 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
982 }
983
984 /* lod/bias appears after u/v/r. */
985 mlen += 6;
986
987 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
988 mlen++;
989
990 /* The unused upper half. */
991 mlen++;
992 }
993
994 if (simd16) {
995 /* Now, since we're doing simd16, the return is 2 interleaved
996 * vec4s where the odd-indexed ones are junk. We'll need to move
997 * this weirdness around to the expected layout.
998 */
999 orig_dst = dst;
1000 dst = fs_reg(GRF, virtual_grf_alloc(8),
1001 (brw->is_g4x ?
1002 brw_type_for_base_type(ir->type) :
1003 BRW_REGISTER_TYPE_F));
1004 }
1005
1006 fs_inst *inst = NULL;
1007 switch (ir->op) {
1008 case ir_tex:
1009 inst = emit(SHADER_OPCODE_TEX, dst);
1010 break;
1011 case ir_txb:
1012 inst = emit(FS_OPCODE_TXB, dst);
1013 break;
1014 case ir_txl:
1015 inst = emit(SHADER_OPCODE_TXL, dst);
1016 break;
1017 case ir_txd:
1018 inst = emit(SHADER_OPCODE_TXD, dst);
1019 break;
1020 case ir_txs:
1021 inst = emit(SHADER_OPCODE_TXS, dst);
1022 break;
1023 case ir_txf:
1024 inst = emit(SHADER_OPCODE_TXF, dst);
1025 break;
1026 default:
1027 fail("unrecognized texture opcode");
1028 }
1029 inst->base_mrf = base_mrf;
1030 inst->mlen = mlen;
1031 inst->header_present = true;
1032 inst->regs_written = simd16 ? 8 : 4;
1033
1034 if (simd16) {
1035 for (int i = 0; i < 4; i++) {
1036 emit(MOV(orig_dst, dst));
1037 orig_dst.reg_offset++;
1038 dst.reg_offset += 2;
1039 }
1040 }
1041
1042 return inst;
1043 }
1044
1045 /* gen5's sampler has slots for u, v, r, array index, then optional
1046 * parameters like shadow comparitor or LOD bias. If optional
1047 * parameters aren't present, those base slots are optional and don't
1048 * need to be included in the message.
1049 *
1050 * We don't fill in the unnecessary slots regardless, which may look
1051 * surprising in the disassembly.
1052 */
1053 fs_inst *
1054 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1055 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1056 fs_reg sample_index)
1057 {
1058 int mlen = 0;
1059 int base_mrf = 2;
1060 int reg_width = dispatch_width / 8;
1061 bool header_present = false;
1062 const int vector_elements =
1063 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1064
1065 if (ir->offset != NULL && ir->op == ir_txf) {
1066 /* It appears that the ld instruction used for txf does its
1067 * address bounds check before adding in the offset. To work
1068 * around this, just add the integer offset to the integer texel
1069 * coordinate, and don't put the offset in the header.
1070 */
1071 ir_constant *offset = ir->offset->as_constant();
1072 for (int i = 0; i < vector_elements; i++) {
1073 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1074 coordinate,
1075 offset->value.i[i]));
1076 coordinate.reg_offset++;
1077 }
1078 } else {
1079 if (ir->offset) {
1080 /* The offsets set up by the ir_texture visitor are in the
1081 * m1 header, so we can't go headerless.
1082 */
1083 header_present = true;
1084 mlen++;
1085 base_mrf--;
1086 }
1087
1088 for (int i = 0; i < vector_elements; i++) {
1089 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1090 coordinate));
1091 coordinate.reg_offset++;
1092 }
1093 }
1094 mlen += vector_elements * reg_width;
1095
1096 if (ir->shadow_comparitor) {
1097 mlen = MAX2(mlen, header_present + 4 * reg_width);
1098
1099 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1100 mlen += reg_width;
1101 }
1102
1103 fs_inst *inst = NULL;
1104 switch (ir->op) {
1105 case ir_tex:
1106 inst = emit(SHADER_OPCODE_TEX, dst);
1107 break;
1108 case ir_txb:
1109 mlen = MAX2(mlen, header_present + 4 * reg_width);
1110 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1111 mlen += reg_width;
1112
1113 inst = emit(FS_OPCODE_TXB, dst);
1114 break;
1115 case ir_txl:
1116 mlen = MAX2(mlen, header_present + 4 * reg_width);
1117 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1118 mlen += reg_width;
1119
1120 inst = emit(SHADER_OPCODE_TXL, dst);
1121 break;
1122 case ir_txd: {
1123 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1124
1125 /**
1126 * P = u, v, r
1127 * dPdx = dudx, dvdx, drdx
1128 * dPdy = dudy, dvdy, drdy
1129 *
1130 * Load up these values:
1131 * - dudx dudy dvdx dvdy drdx drdy
1132 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1133 */
1134 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1135 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1136 lod.reg_offset++;
1137 mlen += reg_width;
1138
1139 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1140 lod2.reg_offset++;
1141 mlen += reg_width;
1142 }
1143
1144 inst = emit(SHADER_OPCODE_TXD, dst);
1145 break;
1146 }
1147 case ir_txs:
1148 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1149 mlen += reg_width;
1150 inst = emit(SHADER_OPCODE_TXS, dst);
1151 break;
1152 case ir_txf:
1153 mlen = header_present + 4 * reg_width;
1154 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1155 inst = emit(SHADER_OPCODE_TXF, dst);
1156 break;
1157 case ir_txf_ms:
1158 mlen = header_present + 4 * reg_width;
1159
1160 /* lod */
1161 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1162 /* sample index */
1163 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1164 mlen += reg_width;
1165 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1166 break;
1167 case ir_lod:
1168 inst = emit(SHADER_OPCODE_LOD, dst);
1169 break;
1170 }
1171 inst->base_mrf = base_mrf;
1172 inst->mlen = mlen;
1173 inst->header_present = header_present;
1174 inst->regs_written = 4;
1175
1176 if (mlen > 11) {
1177 fail("Message length >11 disallowed by hardware\n");
1178 }
1179
1180 return inst;
1181 }
1182
1183 fs_inst *
1184 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1185 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1186 fs_reg sample_index)
1187 {
1188 int mlen = 0;
1189 int base_mrf = 2;
1190 int reg_width = dispatch_width / 8;
1191 bool header_present = false;
1192 int offsets[3];
1193
1194 if (ir->offset && ir->op != ir_txf) {
1195 /* The offsets set up by the ir_texture visitor are in the
1196 * m1 header, so we can't go headerless.
1197 */
1198 header_present = true;
1199 mlen++;
1200 base_mrf--;
1201 }
1202
1203 if (ir->shadow_comparitor) {
1204 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1205 mlen += reg_width;
1206 }
1207
1208 /* Set up the LOD info */
1209 switch (ir->op) {
1210 case ir_tex:
1211 case ir_lod:
1212 break;
1213 case ir_txb:
1214 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1215 mlen += reg_width;
1216 break;
1217 case ir_txl:
1218 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1219 mlen += reg_width;
1220 break;
1221 case ir_txd: {
1222 if (dispatch_width == 16)
1223 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1224
1225 /* Load dPdx and the coordinate together:
1226 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1227 */
1228 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1229 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1230 coordinate.reg_offset++;
1231 mlen += reg_width;
1232
1233 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1234 * only derivatives for (u, v, r).
1235 */
1236 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1237 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1238 lod.reg_offset++;
1239 mlen += reg_width;
1240
1241 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1242 lod2.reg_offset++;
1243 mlen += reg_width;
1244 }
1245 }
1246 break;
1247 }
1248 case ir_txs:
1249 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1250 mlen += reg_width;
1251 break;
1252 case ir_txf:
1253 /* It appears that the ld instruction used for txf does its
1254 * address bounds check before adding in the offset. To work
1255 * around this, just add the integer offset to the integer texel
1256 * coordinate, and don't put the offset in the header.
1257 */
1258 if (ir->offset) {
1259 ir_constant *offset = ir->offset->as_constant();
1260 offsets[0] = offset->value.i[0];
1261 offsets[1] = offset->value.i[1];
1262 offsets[2] = offset->value.i[2];
1263 } else {
1264 memset(offsets, 0, sizeof(offsets));
1265 }
1266
1267 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1268 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1269 coordinate, offsets[0]));
1270 coordinate.reg_offset++;
1271 mlen += reg_width;
1272
1273 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1274 mlen += reg_width;
1275
1276 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1277 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1278 coordinate, offsets[i]));
1279 coordinate.reg_offset++;
1280 mlen += reg_width;
1281 }
1282 break;
1283 case ir_txf_ms:
1284 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1285 mlen += reg_width;
1286
1287 /* constant zero MCS; we arrange to never actually have a compressed
1288 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1289 * if we ever support texturing from compressed multisample surfaces
1290 */
1291 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1292 mlen += reg_width;
1293
1294 /* there is no offsetting for this message; just copy in the integer
1295 * texture coordinates
1296 */
1297 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1298 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1299 coordinate));
1300 coordinate.reg_offset++;
1301 mlen += reg_width;
1302 }
1303 break;
1304 }
1305
1306 /* Set up the coordinate (except for cases where it was done above) */
1307 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
1308 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1309 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1310 coordinate.reg_offset++;
1311 mlen += reg_width;
1312 }
1313 }
1314
1315 /* Generate the SEND */
1316 fs_inst *inst = NULL;
1317 switch (ir->op) {
1318 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1319 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1320 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1321 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1322 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1323 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1324 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1325 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1326 }
1327 inst->base_mrf = base_mrf;
1328 inst->mlen = mlen;
1329 inst->header_present = header_present;
1330 inst->regs_written = 4;
1331
1332 if (mlen > 11) {
1333 fail("Message length >11 disallowed by hardware\n");
1334 }
1335
1336 return inst;
1337 }
1338
1339 fs_reg
1340 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1341 bool is_rect, int sampler, int texunit)
1342 {
1343 fs_inst *inst = NULL;
1344 bool needs_gl_clamp = true;
1345 fs_reg scale_x, scale_y;
1346
1347 /* The 965 requires the EU to do the normalization of GL rectangle
1348 * texture coordinates. We use the program parameter state
1349 * tracking to get the scaling factor.
1350 */
1351 if (is_rect &&
1352 (brw->gen < 6 ||
1353 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1354 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1355 struct gl_program_parameter_list *params = fp->Base.Parameters;
1356 int tokens[STATE_LENGTH] = {
1357 STATE_INTERNAL,
1358 STATE_TEXRECT_SCALE,
1359 texunit,
1360 0,
1361 0
1362 };
1363
1364 if (dispatch_width == 16) {
1365 fail("rectangle scale uniform setup not supported on 16-wide\n");
1366 return coordinate;
1367 }
1368
1369 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1370 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1371
1372 GLuint index = _mesa_add_state_reference(params,
1373 (gl_state_index *)tokens);
1374 c->prog_data.param[c->prog_data.nr_params++] =
1375 &fp->Base.Parameters->ParameterValues[index][0].f;
1376 c->prog_data.param[c->prog_data.nr_params++] =
1377 &fp->Base.Parameters->ParameterValues[index][1].f;
1378 }
1379
1380 /* The 965 requires the EU to do the normalization of GL rectangle
1381 * texture coordinates. We use the program parameter state
1382 * tracking to get the scaling factor.
1383 */
1384 if (brw->gen < 6 && is_rect) {
1385 fs_reg dst = fs_reg(this, ir->coordinate->type);
1386 fs_reg src = coordinate;
1387 coordinate = dst;
1388
1389 emit(MUL(dst, src, scale_x));
1390 dst.reg_offset++;
1391 src.reg_offset++;
1392 emit(MUL(dst, src, scale_y));
1393 } else if (is_rect) {
1394 /* On gen6+, the sampler handles the rectangle coordinates
1395 * natively, without needing rescaling. But that means we have
1396 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1397 * not [0, 1] like the default case below.
1398 */
1399 needs_gl_clamp = false;
1400
1401 for (int i = 0; i < 2; i++) {
1402 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1403 fs_reg chan = coordinate;
1404 chan.reg_offset += i;
1405
1406 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1407 inst->conditional_mod = BRW_CONDITIONAL_G;
1408
1409 /* Our parameter comes in as 1.0/width or 1.0/height,
1410 * because that's what people normally want for doing
1411 * texture rectangle handling. We need width or height
1412 * for clamping, but we don't care enough to make a new
1413 * parameter type, so just invert back.
1414 */
1415 fs_reg limit = fs_reg(this, glsl_type::float_type);
1416 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1417 emit(SHADER_OPCODE_RCP, limit, limit);
1418
1419 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1420 inst->conditional_mod = BRW_CONDITIONAL_L;
1421 }
1422 }
1423 }
1424
1425 if (ir->coordinate && needs_gl_clamp) {
1426 for (unsigned int i = 0;
1427 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1428 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1429 fs_reg chan = coordinate;
1430 chan.reg_offset += i;
1431
1432 fs_inst *inst = emit(MOV(chan, chan));
1433 inst->saturate = true;
1434 }
1435 }
1436 }
1437 return coordinate;
1438 }
1439
1440 void
1441 fs_visitor::visit(ir_texture *ir)
1442 {
1443 fs_inst *inst = NULL;
1444
1445 int sampler =
1446 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1447 /* FINISHME: We're failing to recompile our programs when the sampler is
1448 * updated. This only matters for the texture rectangle scale parameters
1449 * (pre-gen6, or gen6+ with GL_CLAMP).
1450 */
1451 int texunit = fp->Base.SamplerUnits[sampler];
1452
1453 /* Should be lowered by do_lower_texture_projection */
1454 assert(!ir->projector);
1455
1456 /* Generate code to compute all the subexpression trees. This has to be
1457 * done before loading any values into MRFs for the sampler message since
1458 * generating these values may involve SEND messages that need the MRFs.
1459 */
1460 fs_reg coordinate;
1461 if (ir->coordinate) {
1462 ir->coordinate->accept(this);
1463
1464 coordinate = rescale_texcoord(ir, this->result,
1465 ir->sampler->type->sampler_dimensionality ==
1466 GLSL_SAMPLER_DIM_RECT,
1467 sampler, texunit);
1468 }
1469
1470 fs_reg shadow_comparitor;
1471 if (ir->shadow_comparitor) {
1472 ir->shadow_comparitor->accept(this);
1473 shadow_comparitor = this->result;
1474 }
1475
1476 fs_reg lod, lod2, sample_index;
1477 switch (ir->op) {
1478 case ir_tex:
1479 case ir_lod:
1480 break;
1481 case ir_txb:
1482 ir->lod_info.bias->accept(this);
1483 lod = this->result;
1484 break;
1485 case ir_txd:
1486 ir->lod_info.grad.dPdx->accept(this);
1487 lod = this->result;
1488
1489 ir->lod_info.grad.dPdy->accept(this);
1490 lod2 = this->result;
1491 break;
1492 case ir_txf:
1493 case ir_txl:
1494 case ir_txs:
1495 ir->lod_info.lod->accept(this);
1496 lod = this->result;
1497 break;
1498 case ir_txf_ms:
1499 ir->lod_info.sample_index->accept(this);
1500 sample_index = this->result;
1501 break;
1502 };
1503
1504 /* Writemasking doesn't eliminate channels on SIMD8 texture
1505 * samples, so don't worry about them.
1506 */
1507 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1508
1509 if (brw->gen >= 7) {
1510 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1511 lod, lod2, sample_index);
1512 } else if (brw->gen >= 5) {
1513 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1514 lod, lod2, sample_index);
1515 } else {
1516 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1517 lod, lod2);
1518 }
1519
1520 /* The header is set up by generate_tex() when necessary. */
1521 inst->src[0] = reg_undef;
1522
1523 if (ir->offset != NULL && ir->op != ir_txf)
1524 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1525
1526 inst->sampler = sampler;
1527
1528 if (ir->shadow_comparitor)
1529 inst->shadow_compare = true;
1530
1531 /* fixup #layers for cube map arrays */
1532 if (ir->op == ir_txs) {
1533 glsl_type const *type = ir->sampler->type;
1534 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1535 type->sampler_array) {
1536 fs_reg depth = dst;
1537 depth.reg_offset = 2;
1538 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1539 }
1540 }
1541
1542 swizzle_result(ir, dst, sampler);
1543 }
1544
1545 /**
1546 * Swizzle the result of a texture result. This is necessary for
1547 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1548 */
1549 void
1550 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1551 {
1552 this->result = orig_val;
1553
1554 if (ir->op == ir_txs || ir->op == ir_lod)
1555 return;
1556
1557 if (ir->type == glsl_type::float_type) {
1558 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1559 assert(ir->sampler->type->sampler_shadow);
1560 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1561 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1562
1563 for (int i = 0; i < 4; i++) {
1564 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1565 fs_reg l = swizzled_result;
1566 l.reg_offset += i;
1567
1568 if (swiz == SWIZZLE_ZERO) {
1569 emit(MOV(l, fs_reg(0.0f)));
1570 } else if (swiz == SWIZZLE_ONE) {
1571 emit(MOV(l, fs_reg(1.0f)));
1572 } else {
1573 fs_reg r = orig_val;
1574 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1575 emit(MOV(l, r));
1576 }
1577 }
1578 this->result = swizzled_result;
1579 }
1580 }
1581
1582 void
1583 fs_visitor::visit(ir_swizzle *ir)
1584 {
1585 ir->val->accept(this);
1586 fs_reg val = this->result;
1587
1588 if (ir->type->vector_elements == 1) {
1589 this->result.reg_offset += ir->mask.x;
1590 return;
1591 }
1592
1593 fs_reg result = fs_reg(this, ir->type);
1594 this->result = result;
1595
1596 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1597 fs_reg channel = val;
1598 int swiz = 0;
1599
1600 switch (i) {
1601 case 0:
1602 swiz = ir->mask.x;
1603 break;
1604 case 1:
1605 swiz = ir->mask.y;
1606 break;
1607 case 2:
1608 swiz = ir->mask.z;
1609 break;
1610 case 3:
1611 swiz = ir->mask.w;
1612 break;
1613 }
1614
1615 channel.reg_offset += swiz;
1616 emit(MOV(result, channel));
1617 result.reg_offset++;
1618 }
1619 }
1620
1621 void
1622 fs_visitor::visit(ir_discard *ir)
1623 {
1624 assert(ir->condition == NULL); /* FINISHME */
1625
1626 /* We track our discarded pixels in f0.1. By predicating on it, we can
1627 * update just the flag bits that aren't yet discarded. By emitting a
1628 * CMP of g0 != g0, all our currently executing channels will get turned
1629 * off.
1630 */
1631 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1632 BRW_REGISTER_TYPE_UW));
1633 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1634 BRW_CONDITIONAL_NZ));
1635 cmp->predicate = BRW_PREDICATE_NORMAL;
1636 cmp->flag_subreg = 1;
1637
1638 if (brw->gen >= 6) {
1639 /* For performance, after a discard, jump to the end of the shader.
1640 * However, many people will do foliage by discarding based on a
1641 * texture's alpha mask, and then continue on to texture with the
1642 * remaining pixels. To avoid trashing the derivatives for those
1643 * texture samples, we'll only jump if all of the pixels in the subspan
1644 * have been discarded.
1645 */
1646 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1647 discard_jump->flag_subreg = 1;
1648 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1649 discard_jump->predicate_inverse = true;
1650 }
1651 }
1652
1653 void
1654 fs_visitor::visit(ir_constant *ir)
1655 {
1656 /* Set this->result to reg at the bottom of the function because some code
1657 * paths will cause this visitor to be applied to other fields. This will
1658 * cause the value stored in this->result to be modified.
1659 *
1660 * Make reg constant so that it doesn't get accidentally modified along the
1661 * way. Yes, I actually had this problem. :(
1662 */
1663 const fs_reg reg(this, ir->type);
1664 fs_reg dst_reg = reg;
1665
1666 if (ir->type->is_array()) {
1667 const unsigned size = type_size(ir->type->fields.array);
1668
1669 for (unsigned i = 0; i < ir->type->length; i++) {
1670 ir->array_elements[i]->accept(this);
1671 fs_reg src_reg = this->result;
1672
1673 dst_reg.type = src_reg.type;
1674 for (unsigned j = 0; j < size; j++) {
1675 emit(MOV(dst_reg, src_reg));
1676 src_reg.reg_offset++;
1677 dst_reg.reg_offset++;
1678 }
1679 }
1680 } else if (ir->type->is_record()) {
1681 foreach_list(node, &ir->components) {
1682 ir_constant *const field = (ir_constant *) node;
1683 const unsigned size = type_size(field->type);
1684
1685 field->accept(this);
1686 fs_reg src_reg = this->result;
1687
1688 dst_reg.type = src_reg.type;
1689 for (unsigned j = 0; j < size; j++) {
1690 emit(MOV(dst_reg, src_reg));
1691 src_reg.reg_offset++;
1692 dst_reg.reg_offset++;
1693 }
1694 }
1695 } else {
1696 const unsigned size = type_size(ir->type);
1697
1698 for (unsigned i = 0; i < size; i++) {
1699 switch (ir->type->base_type) {
1700 case GLSL_TYPE_FLOAT:
1701 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1702 break;
1703 case GLSL_TYPE_UINT:
1704 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1705 break;
1706 case GLSL_TYPE_INT:
1707 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1708 break;
1709 case GLSL_TYPE_BOOL:
1710 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1711 break;
1712 default:
1713 assert(!"Non-float/uint/int/bool constant");
1714 }
1715 dst_reg.reg_offset++;
1716 }
1717 }
1718
1719 this->result = reg;
1720 }
1721
1722 void
1723 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1724 {
1725 ir_expression *expr = ir->as_expression();
1726
1727 if (expr &&
1728 expr->operation != ir_binop_logic_and &&
1729 expr->operation != ir_binop_logic_or &&
1730 expr->operation != ir_binop_logic_xor) {
1731 fs_reg op[2];
1732 fs_inst *inst;
1733
1734 assert(expr->get_num_operands() <= 2);
1735 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1736 assert(expr->operands[i]->type->is_scalar());
1737
1738 expr->operands[i]->accept(this);
1739 op[i] = this->result;
1740
1741 resolve_ud_negate(&op[i]);
1742 }
1743
1744 switch (expr->operation) {
1745 case ir_unop_logic_not:
1746 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1747 inst->conditional_mod = BRW_CONDITIONAL_Z;
1748 break;
1749
1750 case ir_unop_f2b:
1751 if (brw->gen >= 6) {
1752 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1753 } else {
1754 inst = emit(MOV(reg_null_f, op[0]));
1755 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1756 }
1757 break;
1758
1759 case ir_unop_i2b:
1760 if (brw->gen >= 6) {
1761 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1762 } else {
1763 inst = emit(MOV(reg_null_d, op[0]));
1764 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1765 }
1766 break;
1767
1768 case ir_binop_greater:
1769 case ir_binop_gequal:
1770 case ir_binop_less:
1771 case ir_binop_lequal:
1772 case ir_binop_equal:
1773 case ir_binop_all_equal:
1774 case ir_binop_nequal:
1775 case ir_binop_any_nequal:
1776 resolve_bool_comparison(expr->operands[0], &op[0]);
1777 resolve_bool_comparison(expr->operands[1], &op[1]);
1778
1779 emit(CMP(reg_null_d, op[0], op[1],
1780 brw_conditional_for_comparison(expr->operation)));
1781 break;
1782
1783 default:
1784 assert(!"not reached");
1785 fail("bad cond code\n");
1786 break;
1787 }
1788 return;
1789 }
1790
1791 ir->accept(this);
1792
1793 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1794 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1795 }
1796
1797 /**
1798 * Emit a gen6 IF statement with the comparison folded into the IF
1799 * instruction.
1800 */
1801 void
1802 fs_visitor::emit_if_gen6(ir_if *ir)
1803 {
1804 ir_expression *expr = ir->condition->as_expression();
1805
1806 if (expr) {
1807 fs_reg op[2];
1808 fs_inst *inst;
1809 fs_reg temp;
1810
1811 assert(expr->get_num_operands() <= 2);
1812 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1813 assert(expr->operands[i]->type->is_scalar());
1814
1815 expr->operands[i]->accept(this);
1816 op[i] = this->result;
1817 }
1818
1819 switch (expr->operation) {
1820 case ir_unop_logic_not:
1821 case ir_binop_logic_xor:
1822 case ir_binop_logic_or:
1823 case ir_binop_logic_and:
1824 /* For operations on bool arguments, only the low bit of the bool is
1825 * valid, and the others are undefined. Fall back to the condition
1826 * code path.
1827 */
1828 break;
1829
1830 case ir_unop_f2b:
1831 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1832 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1833 return;
1834
1835 case ir_unop_i2b:
1836 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1837 return;
1838
1839 case ir_binop_greater:
1840 case ir_binop_gequal:
1841 case ir_binop_less:
1842 case ir_binop_lequal:
1843 case ir_binop_equal:
1844 case ir_binop_all_equal:
1845 case ir_binop_nequal:
1846 case ir_binop_any_nequal:
1847 resolve_bool_comparison(expr->operands[0], &op[0]);
1848 resolve_bool_comparison(expr->operands[1], &op[1]);
1849
1850 emit(IF(op[0], op[1],
1851 brw_conditional_for_comparison(expr->operation)));
1852 return;
1853 default:
1854 assert(!"not reached");
1855 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1856 fail("bad condition\n");
1857 return;
1858 }
1859 }
1860
1861 emit_bool_to_cond_code(ir->condition);
1862 fs_inst *inst = emit(BRW_OPCODE_IF);
1863 inst->predicate = BRW_PREDICATE_NORMAL;
1864 }
1865
1866 /**
1867 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1868 *
1869 * Many GLSL shaders contain the following pattern:
1870 *
1871 * x = condition ? foo : bar
1872 *
1873 * The compiler emits an ir_if tree for this, since each subexpression might be
1874 * a complex tree that could have side-effects or short-circuit logic.
1875 *
1876 * However, the common case is to simply select one of two constants or
1877 * variable values---which is exactly what SEL is for. In this case, the
1878 * assembly looks like:
1879 *
1880 * (+f0) IF
1881 * MOV dst src0
1882 * ELSE
1883 * MOV dst src1
1884 * ENDIF
1885 *
1886 * which can be easily translated into:
1887 *
1888 * (+f0) SEL dst src0 src1
1889 *
1890 * If src0 is an immediate value, we promote it to a temporary GRF.
1891 */
1892 void
1893 fs_visitor::try_replace_with_sel()
1894 {
1895 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1896 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1897
1898 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1899 int opcodes[] = {
1900 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1901 };
1902
1903 fs_inst *match = (fs_inst *) endif_inst->prev;
1904 for (int i = 0; i < 4; i++) {
1905 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1906 return;
1907 match = (fs_inst *) match->prev;
1908 }
1909
1910 /* The opcodes match; it looks like the right sequence of instructions. */
1911 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1912 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1913 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1914
1915 /* Check that the MOVs are the right form. */
1916 if (then_mov->dst.equals(else_mov->dst) &&
1917 !then_mov->is_partial_write() &&
1918 !else_mov->is_partial_write()) {
1919
1920 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1921 while (!if_inst->next->is_tail_sentinel())
1922 if_inst->next->remove();
1923 if_inst->remove();
1924
1925 /* Only the last source register can be a constant, so if the MOV in
1926 * the "then" clause uses a constant, we need to put it in a temporary.
1927 */
1928 fs_reg src0(then_mov->src[0]);
1929 if (src0.file == IMM) {
1930 src0 = fs_reg(this, glsl_type::float_type);
1931 src0.type = then_mov->src[0].type;
1932 emit(MOV(src0, then_mov->src[0]));
1933 }
1934
1935 fs_inst *sel;
1936 if (if_inst->conditional_mod) {
1937 /* Sandybridge-specific IF with embedded comparison */
1938 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
1939 if_inst->conditional_mod));
1940 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1941 sel->predicate = BRW_PREDICATE_NORMAL;
1942 } else {
1943 /* Separate CMP and IF instructions */
1944 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1945 sel->predicate = if_inst->predicate;
1946 sel->predicate_inverse = if_inst->predicate_inverse;
1947 }
1948 }
1949 }
1950
1951 void
1952 fs_visitor::visit(ir_if *ir)
1953 {
1954 if (brw->gen < 6 && dispatch_width == 16) {
1955 fail("Can't support (non-uniform) control flow on 16-wide\n");
1956 }
1957
1958 /* Don't point the annotation at the if statement, because then it plus
1959 * the then and else blocks get printed.
1960 */
1961 this->base_ir = ir->condition;
1962
1963 if (brw->gen == 6) {
1964 emit_if_gen6(ir);
1965 } else {
1966 emit_bool_to_cond_code(ir->condition);
1967
1968 emit(IF(BRW_PREDICATE_NORMAL));
1969 }
1970
1971 foreach_list(node, &ir->then_instructions) {
1972 ir_instruction *ir = (ir_instruction *)node;
1973 this->base_ir = ir;
1974
1975 ir->accept(this);
1976 }
1977
1978 if (!ir->else_instructions.is_empty()) {
1979 emit(BRW_OPCODE_ELSE);
1980
1981 foreach_list(node, &ir->else_instructions) {
1982 ir_instruction *ir = (ir_instruction *)node;
1983 this->base_ir = ir;
1984
1985 ir->accept(this);
1986 }
1987 }
1988
1989 emit(BRW_OPCODE_ENDIF);
1990
1991 try_replace_with_sel();
1992 }
1993
1994 void
1995 fs_visitor::visit(ir_loop *ir)
1996 {
1997 fs_reg counter = reg_undef;
1998
1999 if (brw->gen < 6 && dispatch_width == 16) {
2000 fail("Can't support (non-uniform) control flow on 16-wide\n");
2001 }
2002
2003 if (ir->counter) {
2004 this->base_ir = ir->counter;
2005 ir->counter->accept(this);
2006 counter = *(variable_storage(ir->counter));
2007
2008 if (ir->from) {
2009 this->base_ir = ir->from;
2010 ir->from->accept(this);
2011
2012 emit(MOV(counter, this->result));
2013 }
2014 }
2015
2016 this->base_ir = NULL;
2017 emit(BRW_OPCODE_DO);
2018
2019 if (ir->to) {
2020 this->base_ir = ir->to;
2021 ir->to->accept(this);
2022
2023 emit(CMP(reg_null_d, counter, this->result,
2024 brw_conditional_for_comparison(ir->cmp)));
2025
2026 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2027 inst->predicate = BRW_PREDICATE_NORMAL;
2028 }
2029
2030 foreach_list(node, &ir->body_instructions) {
2031 ir_instruction *ir = (ir_instruction *)node;
2032
2033 this->base_ir = ir;
2034 ir->accept(this);
2035 }
2036
2037 if (ir->increment) {
2038 this->base_ir = ir->increment;
2039 ir->increment->accept(this);
2040 emit(ADD(counter, counter, this->result));
2041 }
2042
2043 this->base_ir = NULL;
2044 emit(BRW_OPCODE_WHILE);
2045 }
2046
2047 void
2048 fs_visitor::visit(ir_loop_jump *ir)
2049 {
2050 switch (ir->mode) {
2051 case ir_loop_jump::jump_break:
2052 emit(BRW_OPCODE_BREAK);
2053 break;
2054 case ir_loop_jump::jump_continue:
2055 emit(BRW_OPCODE_CONTINUE);
2056 break;
2057 }
2058 }
2059
2060 void
2061 fs_visitor::visit(ir_call *ir)
2062 {
2063 assert(!"FINISHME");
2064 }
2065
2066 void
2067 fs_visitor::visit(ir_return *ir)
2068 {
2069 assert(!"FINISHME");
2070 }
2071
2072 void
2073 fs_visitor::visit(ir_function *ir)
2074 {
2075 /* Ignore function bodies other than main() -- we shouldn't see calls to
2076 * them since they should all be inlined before we get to ir_to_mesa.
2077 */
2078 if (strcmp(ir->name, "main") == 0) {
2079 const ir_function_signature *sig;
2080 exec_list empty;
2081
2082 sig = ir->matching_signature(NULL, &empty);
2083
2084 assert(sig);
2085
2086 foreach_list(node, &sig->body) {
2087 ir_instruction *ir = (ir_instruction *)node;
2088 this->base_ir = ir;
2089
2090 ir->accept(this);
2091 }
2092 }
2093 }
2094
2095 void
2096 fs_visitor::visit(ir_function_signature *ir)
2097 {
2098 assert(!"not reached");
2099 (void)ir;
2100 }
2101
2102 void
2103 fs_visitor::visit(ir_emit_vertex *)
2104 {
2105 assert(!"not reached");
2106 }
2107
2108 void
2109 fs_visitor::visit(ir_end_primitive *)
2110 {
2111 assert(!"not reached");
2112 }
2113
2114 fs_inst *
2115 fs_visitor::emit(fs_inst inst)
2116 {
2117 fs_inst *list_inst = new(mem_ctx) fs_inst;
2118 *list_inst = inst;
2119 emit(list_inst);
2120 return list_inst;
2121 }
2122
2123 fs_inst *
2124 fs_visitor::emit(fs_inst *inst)
2125 {
2126 if (force_uncompressed_stack > 0)
2127 inst->force_uncompressed = true;
2128 else if (force_sechalf_stack > 0)
2129 inst->force_sechalf = true;
2130
2131 inst->annotation = this->current_annotation;
2132 inst->ir = this->base_ir;
2133
2134 this->instructions.push_tail(inst);
2135
2136 return inst;
2137 }
2138
2139 void
2140 fs_visitor::emit(exec_list list)
2141 {
2142 foreach_list_safe(node, &list) {
2143 fs_inst *inst = (fs_inst *)node;
2144 inst->remove();
2145 emit(inst);
2146 }
2147 }
2148
2149 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2150 void
2151 fs_visitor::emit_dummy_fs()
2152 {
2153 int reg_width = dispatch_width / 8;
2154
2155 /* Everyone's favorite color. */
2156 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2157 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2158 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2159 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2160
2161 fs_inst *write;
2162 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2163 write->base_mrf = 2;
2164 write->mlen = 4 * reg_width;
2165 write->eot = true;
2166 }
2167
2168 /* The register location here is relative to the start of the URB
2169 * data. It will get adjusted to be a real location before
2170 * generate_code() time.
2171 */
2172 struct brw_reg
2173 fs_visitor::interp_reg(int location, int channel)
2174 {
2175 int regnr = c->prog_data.urb_setup[location] * 2 + channel / 2;
2176 int stride = (channel & 1) * 4;
2177
2178 assert(c->prog_data.urb_setup[location] != -1);
2179
2180 return brw_vec1_grf(regnr, stride);
2181 }
2182
2183 /** Emits the interpolation for the varying inputs. */
2184 void
2185 fs_visitor::emit_interpolation_setup_gen4()
2186 {
2187 this->current_annotation = "compute pixel centers";
2188 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2189 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2190 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2191 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2192
2193 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2194 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2195
2196 this->current_annotation = "compute pixel deltas from v0";
2197 if (brw->has_pln) {
2198 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2199 fs_reg(this, glsl_type::vec2_type);
2200 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2201 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2202 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2203 } else {
2204 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2205 fs_reg(this, glsl_type::float_type);
2206 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2207 fs_reg(this, glsl_type::float_type);
2208 }
2209 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2210 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2211 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2212 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2213
2214 this->current_annotation = "compute pos.w and 1/pos.w";
2215 /* Compute wpos.w. It's always in our setup, since it's needed to
2216 * interpolate the other attributes.
2217 */
2218 this->wpos_w = fs_reg(this, glsl_type::float_type);
2219 emit(FS_OPCODE_LINTERP, wpos_w,
2220 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2221 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2222 interp_reg(VARYING_SLOT_POS, 3));
2223 /* Compute the pixel 1/W value from wpos.w. */
2224 this->pixel_w = fs_reg(this, glsl_type::float_type);
2225 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2226 this->current_annotation = NULL;
2227 }
2228
2229 /** Emits the interpolation for the varying inputs. */
2230 void
2231 fs_visitor::emit_interpolation_setup_gen6()
2232 {
2233 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2234
2235 /* If the pixel centers end up used, the setup is the same as for gen4. */
2236 this->current_annotation = "compute pixel centers";
2237 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2238 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2239 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2240 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2241 emit(ADD(int_pixel_x,
2242 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2243 fs_reg(brw_imm_v(0x10101010))));
2244 emit(ADD(int_pixel_y,
2245 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2246 fs_reg(brw_imm_v(0x11001100))));
2247
2248 /* As of gen6, we can no longer mix float and int sources. We have
2249 * to turn the integer pixel centers into floats for their actual
2250 * use.
2251 */
2252 this->pixel_x = fs_reg(this, glsl_type::float_type);
2253 this->pixel_y = fs_reg(this, glsl_type::float_type);
2254 emit(MOV(this->pixel_x, int_pixel_x));
2255 emit(MOV(this->pixel_y, int_pixel_y));
2256
2257 this->current_annotation = "compute pos.w";
2258 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2259 this->wpos_w = fs_reg(this, glsl_type::float_type);
2260 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2261
2262 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2263 uint8_t reg = c->barycentric_coord_reg[i];
2264 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2265 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2266 }
2267
2268 this->current_annotation = NULL;
2269 }
2270
2271 void
2272 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2273 {
2274 int reg_width = dispatch_width / 8;
2275 fs_inst *inst;
2276 fs_reg color = outputs[target];
2277 fs_reg mrf;
2278
2279 /* If there's no color data to be written, skip it. */
2280 if (color.file == BAD_FILE)
2281 return;
2282
2283 color.reg_offset += index;
2284
2285 if (dispatch_width == 8 || brw->gen >= 6) {
2286 /* SIMD8 write looks like:
2287 * m + 0: r0
2288 * m + 1: r1
2289 * m + 2: g0
2290 * m + 3: g1
2291 *
2292 * gen6 SIMD16 DP write looks like:
2293 * m + 0: r0
2294 * m + 1: r1
2295 * m + 2: g0
2296 * m + 3: g1
2297 * m + 4: b0
2298 * m + 5: b1
2299 * m + 6: a0
2300 * m + 7: a1
2301 */
2302 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2303 color.type),
2304 color));
2305 inst->saturate = c->key.clamp_fragment_color;
2306 } else {
2307 /* pre-gen6 SIMD16 single source DP write looks like:
2308 * m + 0: r0
2309 * m + 1: g0
2310 * m + 2: b0
2311 * m + 3: a0
2312 * m + 4: r1
2313 * m + 5: g1
2314 * m + 6: b1
2315 * m + 7: a1
2316 */
2317 if (brw->has_compr4) {
2318 /* By setting the high bit of the MRF register number, we
2319 * indicate that we want COMPR4 mode - instead of doing the
2320 * usual destination + 1 for the second half we get
2321 * destination + 4.
2322 */
2323 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2324 color.type),
2325 color));
2326 inst->saturate = c->key.clamp_fragment_color;
2327 } else {
2328 push_force_uncompressed();
2329 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2330 color));
2331 inst->saturate = c->key.clamp_fragment_color;
2332 pop_force_uncompressed();
2333
2334 push_force_sechalf();
2335 color.sechalf = true;
2336 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2337 color));
2338 inst->saturate = c->key.clamp_fragment_color;
2339 pop_force_sechalf();
2340 color.sechalf = false;
2341 }
2342 }
2343 }
2344
2345 void
2346 fs_visitor::emit_fb_writes()
2347 {
2348 this->current_annotation = "FB write header";
2349 bool header_present = true;
2350 /* We can potentially have a message length of up to 15, so we have to set
2351 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2352 */
2353 int base_mrf = 1;
2354 int nr = base_mrf;
2355 int reg_width = dispatch_width / 8;
2356 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2357 bool src0_alpha_to_render_target = false;
2358
2359 if (dispatch_width == 16 && do_dual_src) {
2360 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2361 do_dual_src = false;
2362 }
2363
2364 /* From the Sandy Bridge PRM, volume 4, page 198:
2365 *
2366 * "Dispatched Pixel Enables. One bit per pixel indicating
2367 * which pixels were originally enabled when the thread was
2368 * dispatched. This field is only required for the end-of-
2369 * thread message and on all dual-source messages."
2370 */
2371 if (brw->gen >= 6 &&
2372 !this->fp->UsesKill &&
2373 !do_dual_src &&
2374 c->key.nr_color_regions == 1) {
2375 header_present = false;
2376 }
2377
2378 if (header_present) {
2379 src0_alpha_to_render_target = brw->gen >= 6 &&
2380 !do_dual_src &&
2381 c->key.replicate_alpha;
2382 /* m2, m3 header */
2383 nr += 2;
2384 }
2385
2386 if (c->aa_dest_stencil_reg) {
2387 push_force_uncompressed();
2388 emit(MOV(fs_reg(MRF, nr++),
2389 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2390 pop_force_uncompressed();
2391 }
2392
2393 /* Reserve space for color. It'll be filled in per MRT below. */
2394 int color_mrf = nr;
2395 nr += 4 * reg_width;
2396 if (do_dual_src)
2397 nr += 4;
2398 if (src0_alpha_to_render_target)
2399 nr += reg_width;
2400
2401 if (c->source_depth_to_render_target) {
2402 if (brw->gen == 6 && dispatch_width == 16) {
2403 /* For outputting oDepth on gen6, SIMD8 writes have to be
2404 * used. This would require 8-wide moves of each half to
2405 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2406 * Just bail on doing so for now.
2407 */
2408 fail("Missing support for simd16 depth writes on gen6\n");
2409 }
2410
2411 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2412 /* Hand over gl_FragDepth. */
2413 assert(this->frag_depth.file != BAD_FILE);
2414 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2415 } else {
2416 /* Pass through the payload depth. */
2417 emit(MOV(fs_reg(MRF, nr),
2418 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2419 }
2420 nr += reg_width;
2421 }
2422
2423 if (c->dest_depth_reg) {
2424 emit(MOV(fs_reg(MRF, nr),
2425 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2426 nr += reg_width;
2427 }
2428
2429 if (do_dual_src) {
2430 fs_reg src0 = this->outputs[0];
2431 fs_reg src1 = this->dual_src_output;
2432
2433 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2434 "FB write src0");
2435 for (int i = 0; i < 4; i++) {
2436 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2437 src0.reg_offset++;
2438 inst->saturate = c->key.clamp_fragment_color;
2439 }
2440
2441 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2442 "FB write src1");
2443 for (int i = 0; i < 4; i++) {
2444 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2445 src1));
2446 src1.reg_offset++;
2447 inst->saturate = c->key.clamp_fragment_color;
2448 }
2449
2450 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2451 emit_shader_time_end();
2452
2453 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2454 inst->target = 0;
2455 inst->base_mrf = base_mrf;
2456 inst->mlen = nr - base_mrf;
2457 inst->eot = true;
2458 inst->header_present = header_present;
2459
2460 c->prog_data.dual_src_blend = true;
2461 this->current_annotation = NULL;
2462 return;
2463 }
2464
2465 for (int target = 0; target < c->key.nr_color_regions; target++) {
2466 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2467 "FB write target %d",
2468 target);
2469 /* If src0_alpha_to_render_target is true, include source zero alpha
2470 * data in RenderTargetWrite message for targets > 0.
2471 */
2472 int write_color_mrf = color_mrf;
2473 if (src0_alpha_to_render_target && target != 0) {
2474 fs_inst *inst;
2475 fs_reg color = outputs[0];
2476 color.reg_offset += 3;
2477
2478 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2479 color));
2480 inst->saturate = c->key.clamp_fragment_color;
2481 write_color_mrf = color_mrf + reg_width;
2482 }
2483
2484 for (unsigned i = 0; i < this->output_components[target]; i++)
2485 emit_color_write(target, i, write_color_mrf);
2486
2487 bool eot = false;
2488 if (target == c->key.nr_color_regions - 1) {
2489 eot = true;
2490
2491 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2492 emit_shader_time_end();
2493 }
2494
2495 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2496 inst->target = target;
2497 inst->base_mrf = base_mrf;
2498 if (src0_alpha_to_render_target && target == 0)
2499 inst->mlen = nr - base_mrf - reg_width;
2500 else
2501 inst->mlen = nr - base_mrf;
2502 inst->eot = eot;
2503 inst->header_present = header_present;
2504 }
2505
2506 if (c->key.nr_color_regions == 0) {
2507 /* Even if there's no color buffers enabled, we still need to send
2508 * alpha out the pipeline to our null renderbuffer to support
2509 * alpha-testing, alpha-to-coverage, and so on.
2510 */
2511 emit_color_write(0, 3, color_mrf);
2512
2513 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2514 emit_shader_time_end();
2515
2516 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2517 inst->base_mrf = base_mrf;
2518 inst->mlen = nr - base_mrf;
2519 inst->eot = true;
2520 inst->header_present = header_present;
2521 }
2522
2523 this->current_annotation = NULL;
2524 }
2525
2526 void
2527 fs_visitor::resolve_ud_negate(fs_reg *reg)
2528 {
2529 if (reg->type != BRW_REGISTER_TYPE_UD ||
2530 !reg->negate)
2531 return;
2532
2533 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2534 emit(MOV(temp, *reg));
2535 *reg = temp;
2536 }
2537
2538 void
2539 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2540 {
2541 if (rvalue->type != glsl_type::bool_type)
2542 return;
2543
2544 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2545 emit(AND(temp, *reg, fs_reg(1)));
2546 *reg = temp;
2547 }
2548
2549 fs_visitor::fs_visitor(struct brw_context *brw,
2550 struct brw_wm_compile *c,
2551 struct gl_shader_program *shader_prog,
2552 struct gl_fragment_program *fp,
2553 unsigned dispatch_width)
2554 : dispatch_width(dispatch_width)
2555 {
2556 this->c = c;
2557 this->brw = brw;
2558 this->fp = fp;
2559 this->shader_prog = shader_prog;
2560 this->ctx = &brw->ctx;
2561 this->mem_ctx = ralloc_context(NULL);
2562 if (shader_prog)
2563 shader = (struct brw_shader *)
2564 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2565 else
2566 shader = NULL;
2567 this->failed = false;
2568 this->variable_ht = hash_table_ctor(0,
2569 hash_table_pointer_hash,
2570 hash_table_pointer_compare);
2571
2572 memset(this->outputs, 0, sizeof(this->outputs));
2573 memset(this->output_components, 0, sizeof(this->output_components));
2574 this->first_non_payload_grf = 0;
2575 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2576
2577 this->current_annotation = NULL;
2578 this->base_ir = NULL;
2579
2580 this->virtual_grf_sizes = NULL;
2581 this->virtual_grf_count = 0;
2582 this->virtual_grf_array_size = 0;
2583 this->virtual_grf_start = NULL;
2584 this->virtual_grf_end = NULL;
2585 this->live_intervals_valid = false;
2586
2587 this->params_remap = NULL;
2588 this->nr_params_remap = 0;
2589
2590 this->force_uncompressed_stack = 0;
2591 this->force_sechalf_stack = 0;
2592
2593 memset(&this->param_size, 0, sizeof(this->param_size));
2594 }
2595
2596 fs_visitor::~fs_visitor()
2597 {
2598 ralloc_free(this->mem_ctx);
2599 hash_table_dtor(this->variable_ht);
2600 }