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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
44 #include "main/uniforms.h"
45 #include "glsl/glsl_types.h"
46 #include "glsl/ir_optimization.h"
47 #include "program/sampler.h"
51 fs_visitor::emit_vs_system_value(int location
)
53 fs_reg
*reg
= new(this->mem_ctx
)
54 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
55 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
58 case SYSTEM_VALUE_BASE_VERTEX
:
60 vs_prog_data
->uses_vertexid
= true;
62 case SYSTEM_VALUE_VERTEX_ID
:
63 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
65 vs_prog_data
->uses_vertexid
= true;
67 case SYSTEM_VALUE_INSTANCE_ID
:
69 vs_prog_data
->uses_instanceid
= true;
72 unreachable("not reached");
79 fs_visitor::visit(ir_variable
*ir
)
83 if (variable_storage(ir
))
86 if (ir
->data
.mode
== ir_var_shader_in
) {
87 assert(ir
->data
.location
!= -1);
88 if (stage
== MESA_SHADER_VERTEX
) {
89 reg
= new(this->mem_ctx
)
90 fs_reg(ATTR
, ir
->data
.location
,
91 brw_type_for_base_type(ir
->type
->get_scalar_type()));
92 } else if (ir
->data
.location
== VARYING_SLOT_POS
) {
93 reg
= emit_fragcoord_interpolation(ir
->data
.pixel_center_integer
,
94 ir
->data
.origin_upper_left
);
95 } else if (ir
->data
.location
== VARYING_SLOT_FACE
) {
96 reg
= emit_frontfacing_interpolation();
98 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
99 emit_general_interpolation(*reg
, ir
->name
, ir
->type
,
100 (glsl_interp_qualifier
) ir
->data
.interpolation
,
101 ir
->data
.location
, ir
->data
.centroid
,
105 hash_table_insert(this->variable_ht
, reg
, ir
);
107 } else if (ir
->data
.mode
== ir_var_shader_out
) {
108 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
110 if (stage
== MESA_SHADER_VERTEX
) {
111 int vector_elements
=
112 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
113 : ir
->type
->vector_elements
;
115 for (int i
= 0; i
< (type_size(ir
->type
) + 3) / 4; i
++) {
116 int output
= ir
->data
.location
+ i
;
117 this->outputs
[output
] = *reg
;
118 this->outputs
[output
].reg_offset
= i
* 4;
119 this->output_components
[output
] = vector_elements
;
122 } else if (ir
->data
.index
> 0) {
123 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
124 assert(ir
->data
.index
== 1);
125 this->dual_src_output
= *reg
;
126 this->do_dual_src
= true;
127 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
128 /* Writing gl_FragColor outputs to all color regions. */
129 assert(stage
== MESA_SHADER_FRAGMENT
);
130 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
131 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
132 this->outputs
[i
] = *reg
;
133 this->output_components
[i
] = 4;
135 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
136 this->frag_depth
= *reg
;
137 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
138 this->sample_mask
= *reg
;
140 /* gl_FragData or a user-defined FS output */
141 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
142 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
144 int vector_elements
=
145 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
146 : ir
->type
->vector_elements
;
148 /* General color output. */
149 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
150 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
151 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
152 this->output_components
[output
] = vector_elements
;
155 } else if (ir
->data
.mode
== ir_var_uniform
) {
156 int param_index
= uniforms
;
158 /* Thanks to the lower_ubo_reference pass, we will see only
159 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
160 * variables, so no need for them to be in variable_ht.
162 * Some uniforms, such as samplers and atomic counters, have no actual
163 * storage, so we should ignore them.
165 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
168 if (dispatch_width
== 16) {
169 if (!variable_storage(ir
)) {
170 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
175 param_size
[param_index
] = type_size(ir
->type
);
176 if (!strncmp(ir
->name
, "gl_", 3)) {
177 setup_builtin_uniform_values(ir
);
179 setup_uniform_values(ir
);
182 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
183 reg
->type
= brw_type_for_base_type(ir
->type
);
185 } else if (ir
->data
.mode
== ir_var_system_value
) {
186 switch (ir
->data
.location
) {
187 case SYSTEM_VALUE_BASE_VERTEX
:
188 case SYSTEM_VALUE_VERTEX_ID
:
189 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
190 case SYSTEM_VALUE_INSTANCE_ID
:
191 reg
= emit_vs_system_value(ir
->data
.location
);
193 case SYSTEM_VALUE_SAMPLE_POS
:
194 reg
= emit_samplepos_setup();
196 case SYSTEM_VALUE_SAMPLE_ID
:
197 reg
= emit_sampleid_setup();
199 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
200 assert(brw
->gen
>= 7);
202 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
203 BRW_REGISTER_TYPE_D
));
209 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
211 hash_table_insert(this->variable_ht
, reg
, ir
);
215 fs_visitor::visit(ir_dereference_variable
*ir
)
217 fs_reg
*reg
= variable_storage(ir
->var
);
220 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
221 this->result
= fs_reg(reg_null_d
);
228 fs_visitor::visit(ir_dereference_record
*ir
)
230 const glsl_type
*struct_type
= ir
->record
->type
;
232 ir
->record
->accept(this);
234 unsigned int off
= 0;
235 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
236 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
238 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
240 this->result
= offset(this->result
, off
);
241 this->result
.type
= brw_type_for_base_type(ir
->type
);
245 fs_visitor::visit(ir_dereference_array
*ir
)
247 ir_constant
*constant_index
;
249 int element_size
= type_size(ir
->type
);
251 constant_index
= ir
->array_index
->as_constant();
253 ir
->array
->accept(this);
255 src
.type
= brw_type_for_base_type(ir
->type
);
257 if (constant_index
) {
258 if (src
.file
== ATTR
) {
259 /* Attribute arrays get loaded as one vec4 per element. In that case
260 * offset the source register.
262 src
.reg
+= constant_index
->value
.i
[0];
264 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
265 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
268 /* Variable index array dereference. We attach the variable index
269 * component to the reg as a pointer to a register containing the
270 * offset. Currently only uniform arrays are supported in this patch,
271 * and that reladdr pointer is resolved by
272 * move_uniform_array_access_to_pull_constants(). All other array types
273 * are lowered by lower_variable_index_to_cond_assign().
275 ir
->array_index
->accept(this);
278 index_reg
= vgrf(glsl_type::int_type
);
279 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
282 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
285 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
286 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
292 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
296 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
297 fs_reg y_times_a
= vgrf(glsl_type::float_type
);
298 fs_reg one_minus_a
= vgrf(glsl_type::float_type
);
299 fs_reg x_times_one_minus_a
= vgrf(glsl_type::float_type
);
301 emit(MUL(y_times_a
, y
, a
));
303 fs_reg negative_a
= a
;
304 negative_a
.negate
= !a
.negate
;
305 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
306 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
308 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
310 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
311 * we need to reorder the operands.
313 emit(LRP(dst
, a
, y
, x
));
318 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
319 const fs_reg
&src0
, const fs_reg
&src1
)
321 assert(conditionalmod
== BRW_CONDITIONAL_GE
||
322 conditionalmod
== BRW_CONDITIONAL_L
);
327 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
328 inst
->conditional_mod
= conditionalmod
;
330 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
332 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
333 inst
->predicate
= BRW_PREDICATE_NORMAL
;
338 fs_visitor::try_emit_saturate(ir_expression
*ir
)
340 if (ir
->operation
!= ir_unop_saturate
)
343 ir_rvalue
*sat_val
= ir
->operands
[0];
345 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
347 sat_val
->accept(this);
348 fs_reg src
= this->result
;
350 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
352 /* If the last instruction from our accept() generated our
353 * src, just set the saturate flag instead of emmitting a separate mov.
355 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
356 if (modify
&& modify
->regs_written
== modify
->dst
.width
/ 8 &&
357 modify
->can_do_saturate()) {
358 modify
->saturate
= true;
367 fs_visitor::try_emit_line(ir_expression
*ir
)
369 /* LINE's src0 must be of type float. */
370 if (ir
->type
!= glsl_type::float_type
)
373 ir_rvalue
*nonmul
= ir
->operands
[1];
374 ir_expression
*mul
= ir
->operands
[0]->as_expression();
376 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
377 nonmul
= ir
->operands
[0];
378 mul
= ir
->operands
[1]->as_expression();
380 if (!mul
|| mul
->operation
!= ir_binop_mul
)
384 ir_constant
*const_add
= nonmul
->as_constant();
388 int add_operand_vf
= brw_float_to_vf(const_add
->value
.f
[0]);
389 if (add_operand_vf
== -1)
392 ir_rvalue
*non_const_mul
= mul
->operands
[1];
393 ir_constant
*const_mul
= mul
->operands
[0]->as_constant();
395 const_mul
= mul
->operands
[1]->as_constant();
400 non_const_mul
= mul
->operands
[0];
403 int mul_operand_vf
= brw_float_to_vf(const_mul
->value
.f
[0]);
404 if (mul_operand_vf
== -1)
407 non_const_mul
->accept(this);
408 fs_reg src1
= this->result
;
410 fs_reg src0
= vgrf(ir
->type
);
411 emit(BRW_OPCODE_MOV
, src0
,
412 fs_reg((uint8_t)mul_operand_vf
, 0, 0, (uint8_t)add_operand_vf
));
414 this->result
= vgrf(ir
->type
);
415 emit(BRW_OPCODE_LINE
, this->result
, src0
, src1
);
420 fs_visitor::try_emit_mad(ir_expression
*ir
)
422 /* 3-src instructions were introduced in gen6. */
426 /* MAD can only handle floating-point data. */
427 if (ir
->type
!= glsl_type::float_type
)
432 bool mul_negate
, mul_abs
;
434 for (int i
= 0; i
< 2; i
++) {
438 mul
= ir
->operands
[i
]->as_expression();
439 nonmul
= ir
->operands
[1 - i
];
441 if (mul
&& mul
->operation
== ir_unop_abs
) {
442 mul
= mul
->operands
[0]->as_expression();
444 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
445 mul
= mul
->operands
[0]->as_expression();
449 if (mul
&& mul
->operation
== ir_binop_mul
)
453 if (!mul
|| mul
->operation
!= ir_binop_mul
)
456 nonmul
->accept(this);
457 fs_reg src0
= this->result
;
459 mul
->operands
[0]->accept(this);
460 fs_reg src1
= this->result
;
461 src1
.negate
^= mul_negate
;
466 mul
->operands
[1]->accept(this);
467 fs_reg src2
= this->result
;
472 this->result
= vgrf(ir
->type
);
473 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
479 pack_pixel_offset(float x
)
481 /* Clamp upper end of the range to +7/16. See explanation in non-constant
482 * offset case below. */
483 int n
= MIN2((int)(x
* 16), 7);
488 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
490 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
491 * 8 channels at a time, same as the barycentric coords presented in
492 * the FS payload. this requires a bit of extra work to support.
494 no16("interpolate_at_* not yet supported in SIMD16 mode.");
496 assert(stage
== MESA_SHADER_FRAGMENT
);
497 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
499 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
500 ir_swizzle
* swiz
= NULL
;
502 /* the api does not allow a swizzle here, but the varying packing code
503 * may have pushed one into here.
505 swiz
= ir
->operands
[0]->as_swizzle();
507 deref
= swiz
->val
->as_dereference();
510 ir_variable
* var
= deref
->variable_referenced();
513 /* 1. collect interpolation factors */
515 fs_reg dst_x
= vgrf(glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
516 fs_reg dst_y
= offset(dst_x
, 1);
518 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
519 * even when there is no payload. in the per-slot offset case, we'll replace this with
520 * the proper source data. */
521 fs_reg src
= vgrf(glsl_type::float_type
);
522 int mlen
= 1; /* one reg unless overriden */
523 int reg_width
= dispatch_width
/ 8;
526 switch (ir
->operation
) {
527 case ir_unop_interpolate_at_centroid
:
528 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
531 case ir_binop_interpolate_at_sample
: {
532 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
533 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
535 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
536 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
540 case ir_binop_interpolate_at_offset
: {
541 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
543 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
544 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
545 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
548 /* pack the operands: hw wants offsets as 4 bit signed ints */
549 ir
->operands
[1]->accept(this);
550 src
= vgrf(glsl_type::ivec2_type
);
552 for (int i
= 0; i
< 2; i
++) {
553 fs_reg temp
= vgrf(glsl_type::float_type
);
554 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
555 emit(MOV(src2
, temp
)); /* float to int */
557 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
558 * that we support a maximum offset of +0.5, which isn't representable
559 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
560 * which is the opposite of what the shader author wanted.
562 * This is legal due to ARB_gpu_shader5's quantization rules:
564 * "Not all values of <offset> may be supported; x and y offsets may
565 * be rounded to fixed-point values with the number of fraction bits
566 * given by the implementation-dependent constant
567 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
570 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
571 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
573 src2
= offset(src2
, 1);
574 this->result
= offset(this->result
, 1);
577 mlen
= 2 * reg_width
;
578 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
585 unreachable("not reached");
589 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
590 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
591 INTERP_QUALIFIER_NOPERSPECTIVE
;
593 /* 2. emit linterp */
595 fs_reg res
= vgrf(ir
->type
);
598 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
599 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
600 emit(FS_OPCODE_LINTERP
, res
,
602 fs_reg(interp_reg(var
->data
.location
, ch
)));
603 res
= offset(res
, 1);
608 fs_visitor::visit(ir_expression
*ir
)
610 unsigned int operand
;
613 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
615 assert(ir
->get_num_operands() <= 3);
617 if (try_emit_saturate(ir
))
620 /* Deal with the real oddball stuff first */
621 switch (ir
->operation
) {
623 if (brw
->gen
<= 5 && try_emit_line(ir
))
625 if (try_emit_mad(ir
))
630 ir
->operands
[1]->accept(this);
631 op
[1] = this->result
;
632 ir
->operands
[2]->accept(this);
633 op
[2] = this->result
;
635 emit_bool_to_cond_code(ir
->operands
[0]);
637 this->result
= vgrf(ir
->type
);
638 inst
= emit(SEL(this->result
, op
[1], op
[2]));
639 inst
->predicate
= BRW_PREDICATE_NORMAL
;
642 case ir_unop_interpolate_at_centroid
:
643 case ir_binop_interpolate_at_offset
:
644 case ir_binop_interpolate_at_sample
:
645 emit_interpolate_expression(ir
);
652 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
653 ir
->operands
[operand
]->accept(this);
654 if (this->result
.file
== BAD_FILE
) {
655 fail("Failed to get tree for expression operand:\n");
656 ir
->operands
[operand
]->fprint(stderr
);
657 fprintf(stderr
, "\n");
659 assert(this->result
.file
== GRF
||
660 this->result
.file
== UNIFORM
|| this->result
.file
== ATTR
);
661 op
[operand
] = this->result
;
663 /* Matrix expression operands should have been broken down to vector
664 * operations already.
666 assert(!ir
->operands
[operand
]->type
->is_matrix());
667 /* And then those vector operands should have been broken down to scalar.
669 assert(!ir
->operands
[operand
]->type
->is_vector());
672 /* Storage for our result. If our result goes into an assignment, it will
673 * just get copy-propagated out, so no worries.
675 this->result
= vgrf(ir
->type
);
677 switch (ir
->operation
) {
678 case ir_unop_logic_not
:
679 emit(NOT(this->result
, op
[0]));
682 op
[0].negate
= !op
[0].negate
;
683 emit(MOV(this->result
, op
[0]));
687 op
[0].negate
= false;
688 emit(MOV(this->result
, op
[0]));
691 if (ir
->type
->is_float()) {
692 /* AND(val, 0x80000000) gives the sign bit.
694 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
697 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
699 op
[0].type
= BRW_REGISTER_TYPE_UD
;
700 this->result
.type
= BRW_REGISTER_TYPE_UD
;
701 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
703 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
704 inst
->predicate
= BRW_PREDICATE_NORMAL
;
706 this->result
.type
= BRW_REGISTER_TYPE_F
;
708 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
709 * -> non-negative val generates 0x00000000.
710 * Predicated OR sets 1 if val is positive.
712 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
714 emit(ASR(this->result
, op
[0], fs_reg(31)));
716 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
717 inst
->predicate
= BRW_PREDICATE_NORMAL
;
721 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
725 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
728 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
732 unreachable("not reached: should be handled by ir_explog_to_explog2");
734 case ir_unop_sin_reduced
:
735 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
738 case ir_unop_cos_reduced
:
739 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
743 /* Select one of the two opcodes based on the glHint value. */
744 if (fs_key
->high_quality_derivatives
)
745 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
747 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
750 case ir_unop_dFdx_coarse
:
751 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
754 case ir_unop_dFdx_fine
:
755 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
759 /* Select one of the two opcodes based on the glHint value. */
760 if (fs_key
->high_quality_derivatives
)
761 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
763 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
766 case ir_unop_dFdy_coarse
:
767 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
770 case ir_unop_dFdy_fine
:
771 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
775 emit(ADD(this->result
, op
[0], op
[1]));
778 unreachable("not reached: should be handled by ir_sub_to_add_neg");
781 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
782 /* For integer multiplication, the MUL uses the low 16 bits
783 * of one of the operands (src0 on gen6, src1 on gen7). The
784 * MACH accumulates in the contribution of the upper 16 bits
787 if (ir
->operands
[0]->is_uint16_constant()) {
789 emit(MUL(this->result
, op
[0], op
[1]));
791 emit(MUL(this->result
, op
[1], op
[0]));
792 } else if (ir
->operands
[1]->is_uint16_constant()) {
794 emit(MUL(this->result
, op
[1], op
[0]));
796 emit(MUL(this->result
, op
[0], op
[1]));
799 no16("SIMD16 explicit accumulator operands unsupported\n");
801 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
804 emit(MUL(acc
, op
[0], op
[1]));
805 emit(MACH(reg_null_d
, op
[0], op
[1]));
806 emit(MOV(this->result
, fs_reg(acc
)));
809 emit(MUL(this->result
, op
[0], op
[1]));
812 case ir_binop_imul_high
: {
814 no16("SIMD16 explicit accumulator operands unsupported\n");
816 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
819 fs_inst
*mul
= emit(MUL(acc
, op
[0], op
[1]));
820 emit(MACH(this->result
, op
[0], op
[1]));
822 /* Until Gen8, integer multiplies read 32-bits from one source, and
823 * 16-bits from the other, and relying on the MACH instruction to
824 * generate the high bits of the result.
826 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
827 * but in order to do a 64x64-bit multiply we have to simulate the
828 * previous behavior and then use a MACH instruction.
830 * FINISHME: Don't use source modifiers on src1.
833 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
834 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
835 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
836 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
838 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
845 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
846 assert(ir
->type
->is_integer());
847 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
849 case ir_binop_carry
: {
851 no16("SIMD16 explicit accumulator operands unsupported\n");
853 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
854 BRW_REGISTER_TYPE_UD
);
856 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
857 emit(MOV(this->result
, fs_reg(acc
)));
860 case ir_binop_borrow
: {
862 no16("SIMD16 explicit accumulator operands unsupported\n");
864 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
865 BRW_REGISTER_TYPE_UD
);
867 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
868 emit(MOV(this->result
, fs_reg(acc
)));
872 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
873 assert(ir
->type
->is_integer());
874 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
878 case ir_binop_greater
:
879 case ir_binop_lequal
:
880 case ir_binop_gequal
:
882 case ir_binop_all_equal
:
883 case ir_binop_nequal
:
884 case ir_binop_any_nequal
:
886 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
887 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
890 emit(CMP(this->result
, op
[0], op
[1],
891 brw_conditional_for_comparison(ir
->operation
)));
894 case ir_binop_logic_xor
:
895 emit(XOR(this->result
, op
[0], op
[1]));
898 case ir_binop_logic_or
:
899 emit(OR(this->result
, op
[0], op
[1]));
902 case ir_binop_logic_and
:
903 emit(AND(this->result
, op
[0], op
[1]));
908 unreachable("not reached: should be handled by brw_fs_channel_expressions");
911 unreachable("not reached: should be handled by lower_noise");
913 case ir_quadop_vector
:
914 unreachable("not reached: should be handled by lower_quadop_vector");
916 case ir_binop_vector_extract
:
917 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
919 case ir_triop_vector_insert
:
920 unreachable("not reached: should be handled by lower_vector_insert()");
923 unreachable("not reached: should be handled by ldexp_to_arith()");
926 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
930 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
933 case ir_unop_bitcast_i2f
:
934 case ir_unop_bitcast_u2f
:
935 op
[0].type
= BRW_REGISTER_TYPE_F
;
936 this->result
= op
[0];
939 case ir_unop_bitcast_f2u
:
940 op
[0].type
= BRW_REGISTER_TYPE_UD
;
941 this->result
= op
[0];
944 case ir_unop_bitcast_f2i
:
945 op
[0].type
= BRW_REGISTER_TYPE_D
;
946 this->result
= op
[0];
952 emit(MOV(this->result
, op
[0]));
956 emit(AND(this->result
, op
[0], fs_reg(1)));
960 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
962 op
[0].type
= BRW_REGISTER_TYPE_D
;
963 this->result
.type
= BRW_REGISTER_TYPE_D
;
964 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
965 this->result
.type
= BRW_REGISTER_TYPE_F
;
969 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
972 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
976 emit(RNDZ(this->result
, op
[0]));
979 fs_reg tmp
= vgrf(ir
->type
);
980 op
[0].negate
= !op
[0].negate
;
981 emit(RNDD(tmp
, op
[0]));
983 emit(MOV(this->result
, tmp
));
987 emit(RNDD(this->result
, op
[0]));
990 emit(FRC(this->result
, op
[0]));
992 case ir_unop_round_even
:
993 emit(RNDE(this->result
, op
[0]));
998 resolve_ud_negate(&op
[0]);
999 resolve_ud_negate(&op
[1]);
1000 emit_minmax(ir
->operation
== ir_binop_min
?
1001 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
1002 this->result
, op
[0], op
[1]);
1004 case ir_unop_pack_snorm_2x16
:
1005 case ir_unop_pack_snorm_4x8
:
1006 case ir_unop_pack_unorm_2x16
:
1007 case ir_unop_pack_unorm_4x8
:
1008 case ir_unop_unpack_snorm_2x16
:
1009 case ir_unop_unpack_snorm_4x8
:
1010 case ir_unop_unpack_unorm_2x16
:
1011 case ir_unop_unpack_unorm_4x8
:
1012 case ir_unop_unpack_half_2x16
:
1013 case ir_unop_pack_half_2x16
:
1014 unreachable("not reached: should be handled by lower_packing_builtins");
1015 case ir_unop_unpack_half_2x16_split_x
:
1016 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
1018 case ir_unop_unpack_half_2x16_split_y
:
1019 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
1022 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
1025 case ir_unop_bitfield_reverse
:
1026 emit(BFREV(this->result
, op
[0]));
1028 case ir_unop_bit_count
:
1029 emit(CBIT(this->result
, op
[0]));
1031 case ir_unop_find_msb
:
1032 temp
= vgrf(glsl_type::uint_type
);
1033 emit(FBH(temp
, op
[0]));
1035 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1036 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1037 * subtract the result from 31 to convert the MSB count into an LSB count.
1040 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1041 emit(MOV(this->result
, temp
));
1042 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1045 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
1046 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1048 case ir_unop_find_lsb
:
1049 emit(FBL(this->result
, op
[0]));
1051 case ir_unop_saturate
:
1052 inst
= emit(MOV(this->result
, op
[0]));
1053 inst
->saturate
= true;
1055 case ir_triop_bitfield_extract
:
1056 /* Note that the instruction's argument order is reversed from GLSL
1059 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
1062 emit(BFI1(this->result
, op
[0], op
[1]));
1065 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
1067 case ir_quadop_bitfield_insert
:
1068 unreachable("not reached: should be handled by "
1069 "lower_instructions::bitfield_insert_to_bfm_bfi");
1071 case ir_unop_bit_not
:
1072 emit(NOT(this->result
, op
[0]));
1074 case ir_binop_bit_and
:
1075 emit(AND(this->result
, op
[0], op
[1]));
1077 case ir_binop_bit_xor
:
1078 emit(XOR(this->result
, op
[0], op
[1]));
1080 case ir_binop_bit_or
:
1081 emit(OR(this->result
, op
[0], op
[1]));
1084 case ir_binop_lshift
:
1085 emit(SHL(this->result
, op
[0], op
[1]));
1088 case ir_binop_rshift
:
1089 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1090 emit(ASR(this->result
, op
[0], op
[1]));
1092 emit(SHR(this->result
, op
[0], op
[1]));
1094 case ir_binop_pack_half_2x16_split
:
1095 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
1097 case ir_binop_ubo_load
: {
1098 /* This IR node takes a constant uniform block and a constant or
1099 * variable byte offset within the block and loads a vector from that.
1101 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1102 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
1105 if (const_uniform_block
) {
1106 /* The block index is a constant, so just emit the binding table entry
1109 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1110 const_uniform_block
->value
.u
[0]);
1112 /* The block index is not a constant. Evaluate the index expression
1113 * per-channel and add the base UBO index; the generator will select
1114 * a value from any live channel.
1116 surf_index
= vgrf(glsl_type::uint_type
);
1117 emit(ADD(surf_index
, op
[0],
1118 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1119 ->force_writemask_all
= true;
1121 /* Assume this may touch any UBO. It would be nice to provide
1122 * a tighter bound, but the array information is already lowered away.
1124 brw_mark_surface_used(prog_data
,
1125 stage_prog_data
->binding_table
.ubo_start
+
1126 shader_prog
->NumUniformBlocks
- 1);
1130 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1131 packed_consts
.type
= result
.type
;
1133 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
1134 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
1135 packed_consts
, surf_index
, const_offset_reg
));
1137 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1138 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
1140 /* The std140 packing rules don't allow vectors to cross 16-byte
1141 * boundaries, and a reg is 32 bytes.
1143 assert(packed_consts
.subreg_offset
< 32);
1145 /* UBO bools are any nonzero value. We consider bools to be
1146 * values with the low bit set to 1. Convert them using CMP.
1148 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1149 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
1151 emit(MOV(result
, packed_consts
));
1154 result
= offset(result
, 1);
1157 /* Turn the byte offset into a dword offset. */
1158 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1159 emit(SHR(base_offset
, op
[1], fs_reg(2)));
1161 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1162 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
1165 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
1166 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
1168 result
= offset(result
, 1);
1172 result
.reg_offset
= 0;
1177 /* Note that the instruction's argument order is reversed from GLSL
1180 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
1184 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1188 case ir_unop_interpolate_at_centroid
:
1189 case ir_binop_interpolate_at_offset
:
1190 case ir_binop_interpolate_at_sample
:
1191 unreachable("already handled above");
1201 case ir_unop_pack_double_2x32
:
1202 case ir_unop_unpack_double_2x32
:
1203 case ir_unop_frexp_sig
:
1204 case ir_unop_frexp_exp
:
1205 unreachable("fp64 todo");
1211 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1212 const glsl_type
*type
, bool predicated
)
1214 switch (type
->base_type
) {
1215 case GLSL_TYPE_FLOAT
:
1216 case GLSL_TYPE_UINT
:
1218 case GLSL_TYPE_BOOL
:
1219 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1220 l
.type
= brw_type_for_base_type(type
);
1221 r
.type
= brw_type_for_base_type(type
);
1223 if (predicated
|| !l
.equals(r
)) {
1224 fs_inst
*inst
= emit(MOV(l
, r
));
1225 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1232 case GLSL_TYPE_ARRAY
:
1233 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1234 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1238 case GLSL_TYPE_STRUCT
:
1239 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1240 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1245 case GLSL_TYPE_SAMPLER
:
1246 case GLSL_TYPE_IMAGE
:
1247 case GLSL_TYPE_ATOMIC_UINT
:
1250 case GLSL_TYPE_DOUBLE
:
1251 case GLSL_TYPE_VOID
:
1252 case GLSL_TYPE_ERROR
:
1253 case GLSL_TYPE_INTERFACE
:
1254 unreachable("not reached");
1258 /* If the RHS processing resulted in an instruction generating a
1259 * temporary value, and it would be easy to rewrite the instruction to
1260 * generate its result right into the LHS instead, do so. This ends
1261 * up reliably removing instructions where it can be tricky to do so
1262 * later without real UD chain information.
1265 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1268 fs_inst
*pre_rhs_inst
,
1269 fs_inst
*last_rhs_inst
)
1271 /* Only attempt if we're doing a direct assignment. */
1272 if (ir
->condition
||
1273 !(ir
->lhs
->type
->is_scalar() ||
1274 (ir
->lhs
->type
->is_vector() &&
1275 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1278 /* Make sure the last instruction generated our source reg. */
1279 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1285 /* If last_rhs_inst wrote a different number of components than our LHS,
1286 * we can't safely rewrite it.
1288 if (alloc
.sizes
[dst
.reg
] != modify
->regs_written
)
1291 /* Success! Rewrite the instruction. */
1298 fs_visitor::visit(ir_assignment
*ir
)
1303 /* FINISHME: arrays on the lhs */
1304 ir
->lhs
->accept(this);
1307 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1309 ir
->rhs
->accept(this);
1312 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1314 assert(l
.file
!= BAD_FILE
);
1315 assert(r
.file
!= BAD_FILE
);
1317 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1320 if (ir
->condition
) {
1321 emit_bool_to_cond_code(ir
->condition
);
1324 if (ir
->lhs
->type
->is_scalar() ||
1325 ir
->lhs
->type
->is_vector()) {
1326 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1327 if (ir
->write_mask
& (1 << i
)) {
1328 inst
= emit(MOV(l
, r
));
1330 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1336 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1341 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
1342 fs_reg coordinate
, int coord_components
,
1344 fs_reg lod
, fs_reg dPdy
, int grad_components
,
1349 bool simd16
= false;
1355 if (shadow_c
.file
!= BAD_FILE
) {
1356 for (int i
= 0; i
< coord_components
; i
++) {
1357 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1358 coordinate
= offset(coordinate
, 1);
1361 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1362 * the unused slots must be zeroed.
1364 for (int i
= coord_components
; i
< 3; i
++) {
1365 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1370 /* There's no plain shadow compare message, so we use shadow
1371 * compare with a bias of 0.0.
1373 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1375 } else if (op
== ir_txb
|| op
== ir_txl
) {
1376 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1379 unreachable("Should not get here.");
1382 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1384 } else if (op
== ir_tex
) {
1385 for (int i
= 0; i
< coord_components
; i
++) {
1386 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1387 coordinate
= offset(coordinate
, 1);
1389 /* zero the others. */
1390 for (int i
= coord_components
; i
<3; i
++) {
1391 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1393 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1395 } else if (op
== ir_txd
) {
1398 for (int i
= 0; i
< coord_components
; i
++) {
1399 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1400 coordinate
= offset(coordinate
, 1);
1402 /* the slots for u and v are always present, but r is optional */
1403 mlen
+= MAX2(coord_components
, 2);
1406 * dPdx = dudx, dvdx, drdx
1407 * dPdy = dudy, dvdy, drdy
1409 * 1-arg: Does not exist.
1411 * 2-arg: dudx dvdx dudy dvdy
1412 * dPdx.x dPdx.y dPdy.x dPdy.y
1415 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1416 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1417 * m5 m6 m7 m8 m9 m10
1419 for (int i
= 0; i
< grad_components
; i
++) {
1420 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1421 dPdx
= offset(dPdx
, 1);
1423 mlen
+= MAX2(grad_components
, 2);
1425 for (int i
= 0; i
< grad_components
; i
++) {
1426 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1427 dPdy
= offset(dPdy
, 1);
1429 mlen
+= MAX2(grad_components
, 2);
1430 } else if (op
== ir_txs
) {
1431 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1433 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1436 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1437 * instructions. We'll need to do SIMD16 here.
1440 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
1442 for (int i
= 0; i
< coord_components
; i
++) {
1443 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1445 coordinate
= offset(coordinate
, 1);
1448 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1449 * be necessary for TXF (ld), but seems wise to do for all messages.
1451 for (int i
= coord_components
; i
< 3; i
++) {
1452 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1455 /* lod/bias appears after u/v/r. */
1458 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1461 /* The unused upper half. */
1466 /* Now, since we're doing simd16, the return is 2 interleaved
1467 * vec4s where the odd-indexed ones are junk. We'll need to move
1468 * this weirdness around to the expected layout.
1471 dst
= fs_reg(GRF
, alloc
.allocate(8), orig_dst
.type
);
1476 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1477 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1478 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1479 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1480 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1481 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1483 unreachable("not reached");
1486 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1487 inst
->base_mrf
= base_mrf
;
1489 inst
->header_present
= true;
1490 inst
->regs_written
= simd16
? 8 : 4;
1493 for (int i
= 0; i
< 4; i
++) {
1494 emit(MOV(orig_dst
, dst
));
1495 orig_dst
= offset(orig_dst
, 1);
1496 dst
= offset(dst
, 2);
1503 /* gen5's sampler has slots for u, v, r, array index, then optional
1504 * parameters like shadow comparitor or LOD bias. If optional
1505 * parameters aren't present, those base slots are optional and don't
1506 * need to be included in the message.
1508 * We don't fill in the unnecessary slots regardless, which may look
1509 * surprising in the disassembly.
1512 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
1513 fs_reg coordinate
, int vector_elements
,
1515 fs_reg lod
, fs_reg lod2
, int grad_components
,
1516 fs_reg sample_index
, uint32_t sampler
,
1519 int reg_width
= dispatch_width
/ 8;
1520 bool header_present
= false;
1522 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1523 fs_reg msg_coords
= message
;
1526 /* The offsets set up by the ir_texture visitor are in the
1527 * m1 header, so we can't go headerless.
1529 header_present
= true;
1533 for (int i
= 0; i
< vector_elements
; i
++) {
1534 emit(MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
));
1535 coordinate
= offset(coordinate
, 1);
1537 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
1538 fs_reg msg_lod
= offset(msg_coords
, 4);
1540 if (shadow_c
.file
!= BAD_FILE
) {
1541 fs_reg msg_shadow
= msg_lod
;
1542 emit(MOV(msg_shadow
, shadow_c
));
1543 msg_lod
= offset(msg_shadow
, 1);
1550 opcode
= SHADER_OPCODE_TEX
;
1553 emit(MOV(msg_lod
, lod
));
1554 msg_end
= offset(msg_lod
, 1);
1556 opcode
= FS_OPCODE_TXB
;
1559 emit(MOV(msg_lod
, lod
));
1560 msg_end
= offset(msg_lod
, 1);
1562 opcode
= SHADER_OPCODE_TXL
;
1567 * dPdx = dudx, dvdx, drdx
1568 * dPdy = dudy, dvdy, drdy
1570 * Load up these values:
1571 * - dudx dudy dvdx dvdy drdx drdy
1572 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1575 for (int i
= 0; i
< grad_components
; i
++) {
1576 emit(MOV(msg_end
, lod
));
1577 lod
= offset(lod
, 1);
1578 msg_end
= offset(msg_end
, 1);
1580 emit(MOV(msg_end
, lod2
));
1581 lod2
= offset(lod2
, 1);
1582 msg_end
= offset(msg_end
, 1);
1585 opcode
= SHADER_OPCODE_TXD
;
1589 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
1590 emit(MOV(msg_lod
, lod
));
1591 msg_end
= offset(msg_lod
, 1);
1593 opcode
= SHADER_OPCODE_TXS
;
1595 case ir_query_levels
:
1597 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1598 msg_end
= offset(msg_lod
, 1);
1600 opcode
= SHADER_OPCODE_TXS
;
1603 msg_lod
= offset(msg_coords
, 3);
1604 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
));
1605 msg_end
= offset(msg_lod
, 1);
1607 opcode
= SHADER_OPCODE_TXF
;
1610 msg_lod
= offset(msg_coords
, 3);
1612 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1614 emit(MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
));
1615 msg_end
= offset(msg_lod
, 2);
1617 opcode
= SHADER_OPCODE_TXF_CMS
;
1620 opcode
= SHADER_OPCODE_LOD
;
1623 opcode
= SHADER_OPCODE_TG4
;
1626 unreachable("not reached");
1629 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1630 inst
->base_mrf
= message
.reg
;
1631 inst
->mlen
= msg_end
.reg
- message
.reg
;
1632 inst
->header_present
= header_present
;
1633 inst
->regs_written
= 4 * reg_width
;
1635 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1636 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1637 " disallowed by hardware\n");
1644 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1646 if (brw
->gen
< 8 && !brw
->is_haswell
)
1649 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1653 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
1654 fs_reg coordinate
, int coord_components
,
1656 fs_reg lod
, fs_reg lod2
, int grad_components
,
1657 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
1658 fs_reg offset_value
)
1660 int reg_width
= dispatch_width
/ 8;
1661 bool header_present
= false;
1663 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1664 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1665 sources
[i
] = vgrf(glsl_type::float_type
);
1669 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
1670 is_high_sampler(brw
, sampler
)) {
1671 /* For general texture offsets (no txf workaround), we need a header to
1672 * put them in. Note that for SIMD16 we're making space for two actual
1673 * hardware registers here, so the emit will have to fix up for this.
1675 * * ir4_tg4 needs to place its channel select in the header,
1676 * for interaction with ARB_texture_swizzle
1678 * The sampler index is only 4-bits, so for larger sampler numbers we
1679 * need to offset the Sampler State Pointer in the header.
1681 header_present
= true;
1682 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1686 if (shadow_c
.file
!= BAD_FILE
) {
1687 emit(MOV(sources
[length
], shadow_c
));
1691 bool has_nonconstant_offset
=
1692 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
1693 bool coordinate_done
= false;
1695 /* Set up the LOD info */
1701 emit(MOV(sources
[length
], lod
));
1705 emit(MOV(sources
[length
], lod
));
1709 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1711 /* Load dPdx and the coordinate together:
1712 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1714 for (int i
= 0; i
< coord_components
; i
++) {
1715 emit(MOV(sources
[length
], coordinate
));
1716 coordinate
= offset(coordinate
, 1);
1719 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1720 * only derivatives for (u, v, r).
1722 if (i
< grad_components
) {
1723 emit(MOV(sources
[length
], lod
));
1724 lod
= offset(lod
, 1);
1727 emit(MOV(sources
[length
], lod2
));
1728 lod2
= offset(lod2
, 1);
1733 coordinate_done
= true;
1737 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1740 case ir_query_levels
:
1741 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1745 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1746 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1747 coordinate
= offset(coordinate
, 1);
1750 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1753 for (int i
= 1; i
< coord_components
; i
++) {
1754 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1755 coordinate
= offset(coordinate
, 1);
1759 coordinate_done
= true;
1762 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1765 /* data from the multisample control surface */
1766 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1769 /* there is no offsetting for this message; just copy in the integer
1770 * texture coordinates
1772 for (int i
= 0; i
< coord_components
; i
++) {
1773 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1774 coordinate
= offset(coordinate
, 1);
1778 coordinate_done
= true;
1781 if (has_nonconstant_offset
) {
1782 if (shadow_c
.file
!= BAD_FILE
)
1783 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1785 /* More crazy intermixing */
1786 for (int i
= 0; i
< 2; i
++) { /* u, v */
1787 emit(MOV(sources
[length
], coordinate
));
1788 coordinate
= offset(coordinate
, 1);
1792 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1793 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1794 offset_value
= offset(offset_value
, 1);
1798 if (coord_components
== 3) { /* r if present */
1799 emit(MOV(sources
[length
], coordinate
));
1800 coordinate
= offset(coordinate
, 1);
1804 coordinate_done
= true;
1809 /* Set up the coordinate (except for cases where it was done above) */
1810 if (!coordinate_done
) {
1811 for (int i
= 0; i
< coord_components
; i
++) {
1812 emit(MOV(sources
[length
], coordinate
));
1813 coordinate
= offset(coordinate
, 1);
1820 mlen
= length
* reg_width
- header_present
;
1822 mlen
= length
* reg_width
;
1824 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1825 BRW_REGISTER_TYPE_F
);
1826 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1828 /* Generate the SEND */
1831 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1832 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1833 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1834 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1835 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1836 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1837 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1838 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1839 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1841 if (has_nonconstant_offset
)
1842 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1844 opcode
= SHADER_OPCODE_TG4
;
1847 unreachable("not reached");
1849 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1850 inst
->base_mrf
= -1;
1852 inst
->header_present
= header_present
;
1853 inst
->regs_written
= 4 * reg_width
;
1855 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1856 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1857 " disallowed by hardware\n");
1863 static struct brw_sampler_prog_key_data
*
1864 get_tex(gl_shader_stage stage
, const void *key
)
1867 case MESA_SHADER_FRAGMENT
:
1868 return &((brw_wm_prog_key
*) key
)->tex
;
1869 case MESA_SHADER_VERTEX
:
1870 return &((brw_vue_prog_key
*) key
)->tex
;
1872 unreachable("unhandled shader stage");
1877 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
1878 bool is_rect
, uint32_t sampler
, int texunit
)
1880 fs_inst
*inst
= NULL
;
1881 bool needs_gl_clamp
= true;
1882 fs_reg scale_x
, scale_y
;
1883 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
1885 /* The 965 requires the EU to do the normalization of GL rectangle
1886 * texture coordinates. We use the program parameter state
1887 * tracking to get the scaling factor.
1891 (brw
->gen
>= 6 && (tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
1892 tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
1893 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1894 int tokens
[STATE_LENGTH
] = {
1896 STATE_TEXRECT_SCALE
,
1902 no16("rectangle scale uniform setup not supported on SIMD16\n");
1903 if (dispatch_width
== 16) {
1907 GLuint index
= _mesa_add_state_reference(params
,
1908 (gl_state_index
*)tokens
);
1909 /* Try to find existing copies of the texrect scale uniforms. */
1910 for (unsigned i
= 0; i
< uniforms
; i
++) {
1911 if (stage_prog_data
->param
[i
] ==
1912 &prog
->Parameters
->ParameterValues
[index
][0]) {
1913 scale_x
= fs_reg(UNIFORM
, i
);
1914 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1919 /* If we didn't already set them up, do so now. */
1920 if (scale_x
.file
== BAD_FILE
) {
1921 scale_x
= fs_reg(UNIFORM
, uniforms
);
1922 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1924 stage_prog_data
->param
[uniforms
++] =
1925 &prog
->Parameters
->ParameterValues
[index
][0];
1926 stage_prog_data
->param
[uniforms
++] =
1927 &prog
->Parameters
->ParameterValues
[index
][1];
1931 /* The 965 requires the EU to do the normalization of GL rectangle
1932 * texture coordinates. We use the program parameter state
1933 * tracking to get the scaling factor.
1935 if (brw
->gen
< 6 && is_rect
) {
1936 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
1937 fs_reg src
= coordinate
;
1940 emit(MUL(dst
, src
, scale_x
));
1941 dst
= offset(dst
, 1);
1942 src
= offset(src
, 1);
1943 emit(MUL(dst
, src
, scale_y
));
1944 } else if (is_rect
) {
1945 /* On gen6+, the sampler handles the rectangle coordinates
1946 * natively, without needing rescaling. But that means we have
1947 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1948 * not [0, 1] like the default case below.
1950 needs_gl_clamp
= false;
1952 for (int i
= 0; i
< 2; i
++) {
1953 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1954 fs_reg chan
= coordinate
;
1955 chan
= offset(chan
, i
);
1957 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1958 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1960 /* Our parameter comes in as 1.0/width or 1.0/height,
1961 * because that's what people normally want for doing
1962 * texture rectangle handling. We need width or height
1963 * for clamping, but we don't care enough to make a new
1964 * parameter type, so just invert back.
1966 fs_reg limit
= vgrf(glsl_type::float_type
);
1967 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1968 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1970 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1971 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1976 if (coord_components
> 0 && needs_gl_clamp
) {
1977 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
1978 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1979 fs_reg chan
= coordinate
;
1980 chan
= offset(chan
, i
);
1982 fs_inst
*inst
= emit(MOV(chan
, chan
));
1983 inst
->saturate
= true;
1990 /* Sample from the MCS surface attached to this multisample texture. */
1992 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
1994 int reg_width
= dispatch_width
/ 8;
1995 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(components
* reg_width
),
1996 BRW_REGISTER_TYPE_F
);
1997 fs_reg dest
= vgrf(glsl_type::uvec4_type
);
1998 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
2000 /* parameters are: u, v, r; missing parameters are treated as zero */
2001 for (int i
= 0; i
< components
; i
++) {
2002 sources
[i
] = vgrf(glsl_type::float_type
);
2003 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
2004 coordinate
= offset(coordinate
, 1);
2007 emit(LOAD_PAYLOAD(payload
, sources
, components
));
2009 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
2010 inst
->base_mrf
= -1;
2011 inst
->mlen
= components
* reg_width
;
2012 inst
->header_present
= false;
2013 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
2014 * response, but the sampler always
2022 fs_visitor::emit_texture(ir_texture_opcode op
,
2023 const glsl_type
*dest_type
,
2024 fs_reg coordinate
, int coord_components
,
2026 fs_reg lod
, fs_reg lod2
, int grad_components
,
2027 fs_reg sample_index
,
2028 fs_reg offset_value
,
2030 int gather_component
,
2034 fs_reg sampler_reg
, int texunit
)
2036 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2037 fs_inst
*inst
= NULL
;
2040 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2041 * emitting anything other than setting up the constant result.
2043 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], gather_component
);
2044 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2046 fs_reg res
= vgrf(glsl_type::vec4_type
);
2049 for (int i
=0; i
<4; i
++) {
2050 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
2051 res
= offset(res
, 1);
2057 if (coordinate
.file
!= BAD_FILE
) {
2058 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
2059 * samplers. This should only be a problem with GL_CLAMP on Gen7.
2061 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
2065 /* Writemasking doesn't eliminate channels on SIMD8 texture
2066 * samples, so don't worry about them.
2068 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
2070 if (brw
->gen
>= 7) {
2071 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
2072 shadow_c
, lod
, lod2
, grad_components
,
2073 sample_index
, mcs
, sampler_reg
,
2075 } else if (brw
->gen
>= 5) {
2076 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
2077 shadow_c
, lod
, lod2
, grad_components
,
2078 sample_index
, sampler
,
2079 offset_value
.file
!= BAD_FILE
);
2081 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
2082 shadow_c
, lod
, lod2
, grad_components
,
2086 if (shadow_c
.file
!= BAD_FILE
)
2087 inst
->shadow_compare
= true;
2089 if (offset_value
.file
== IMM
)
2090 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
2094 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
2097 emit_gen6_gather_wa(tex
->gen6_gather_wa
[sampler
], dst
);
2100 /* fixup #layers for cube map arrays */
2101 if (op
== ir_txs
&& is_cube_array
) {
2102 fs_reg depth
= offset(dst
, 2);
2103 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
2104 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
2106 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
2107 int components
= inst
->regs_written
/ (dst
.width
/ 8);
2108 for (int i
= 0; i
< components
; i
++) {
2110 fixed_payload
[i
] = fixed_depth
;
2112 fixed_payload
[i
] = offset(dst
, i
);
2115 emit(LOAD_PAYLOAD(dst
, fixed_payload
, components
));
2118 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
2122 fs_visitor::visit(ir_texture
*ir
)
2124 const struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2126 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2128 ir_rvalue
*nonconst_sampler_index
=
2129 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2131 /* Handle non-constant sampler array indexing */
2133 if (nonconst_sampler_index
) {
2134 /* The highest sampler which may be used by this operation is
2135 * the last element of the array. Mark it here, because the generator
2136 * doesn't have enough information to determine the bound.
2138 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2139 ->array
->type
->array_size();
2141 uint32_t max_used
= sampler
+ array_size
- 1;
2142 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2143 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2145 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2148 brw_mark_surface_used(prog_data
, max_used
);
2150 /* Emit code to evaluate the actual indexing expression */
2151 nonconst_sampler_index
->accept(this);
2152 fs_reg temp
= vgrf(glsl_type::uint_type
);
2153 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
2154 ->force_writemask_all
= true;
2157 /* Single sampler, or constant array index; the indexing expression
2158 * is just an immediate.
2160 sampler_reg
= fs_reg(sampler
);
2163 /* FINISHME: We're failing to recompile our programs when the sampler is
2164 * updated. This only matters for the texture rectangle scale parameters
2165 * (pre-gen6, or gen6+ with GL_CLAMP).
2167 int texunit
= prog
->SamplerUnits
[sampler
];
2169 /* Should be lowered by do_lower_texture_projection */
2170 assert(!ir
->projector
);
2172 /* Should be lowered */
2173 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2175 /* Generate code to compute all the subexpression trees. This has to be
2176 * done before loading any values into MRFs for the sampler message since
2177 * generating these values may involve SEND messages that need the MRFs.
2180 int coord_components
= 0;
2181 if (ir
->coordinate
) {
2182 coord_components
= ir
->coordinate
->type
->vector_elements
;
2183 ir
->coordinate
->accept(this);
2184 coordinate
= this->result
;
2187 fs_reg shadow_comparitor
;
2188 if (ir
->shadow_comparitor
) {
2189 ir
->shadow_comparitor
->accept(this);
2190 shadow_comparitor
= this->result
;
2193 fs_reg offset_value
;
2195 ir_constant
*const_offset
= ir
->offset
->as_constant();
2197 /* Store the header bitfield in an IMM register. This allows us to
2198 * use offset_value.file to distinguish between no offset, a constant
2199 * offset, and a non-constant offset.
2202 fs_reg(brw_texture_offset(ctx
, const_offset
->value
.i
,
2203 const_offset
->type
->vector_elements
));
2205 ir
->offset
->accept(this);
2206 offset_value
= this->result
;
2210 fs_reg lod
, lod2
, sample_index
, mcs
;
2211 int grad_components
= 0;
2216 case ir_query_levels
:
2219 ir
->lod_info
.bias
->accept(this);
2223 ir
->lod_info
.grad
.dPdx
->accept(this);
2226 ir
->lod_info
.grad
.dPdy
->accept(this);
2227 lod2
= this->result
;
2229 grad_components
= ir
->lod_info
.grad
.dPdx
->type
->vector_elements
;
2234 ir
->lod_info
.lod
->accept(this);
2238 ir
->lod_info
.sample_index
->accept(this);
2239 sample_index
= this->result
;
2241 if (brw
->gen
>= 7 && tex
->compressed_multisample_layout_mask
& (1<<sampler
))
2242 mcs
= emit_mcs_fetch(coordinate
, ir
->coordinate
->type
->vector_elements
,
2248 unreachable("Unrecognized texture opcode");
2251 int gather_component
= 0;
2252 if (ir
->op
== ir_tg4
)
2253 gather_component
= ir
->lod_info
.component
->as_constant()->value
.i
[0];
2256 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
;
2258 bool is_cube_array
=
2259 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2260 ir
->sampler
->type
->sampler_array
;
2262 emit_texture(ir
->op
, ir
->type
, coordinate
, coord_components
,
2263 shadow_comparitor
, lod
, lod2
, grad_components
,
2264 sample_index
, offset_value
, mcs
,
2265 gather_component
, is_cube_array
, is_rect
, sampler
,
2266 sampler_reg
, texunit
);
2270 * Apply workarounds for Gen6 gather with UINT/SINT
2273 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2278 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2280 for (int i
= 0; i
< 4; i
++) {
2281 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2282 /* Convert from UNORM to UINT */
2283 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2284 emit(MOV(dst
, dst_f
));
2287 /* Reinterpret the UINT value as a signed INT value by
2288 * shifting the sign bit into place, then shifting back
2291 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2292 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2295 dst
= offset(dst
, 1);
2300 * Set up the gather channel based on the swizzle, for gather4.
2303 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
2305 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2306 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], orig_chan
);
2308 case SWIZZLE_X
: return 0;
2310 /* gather4 sampler is broken for green channel on RG32F --
2311 * we must ask for blue instead.
2313 if (tex
->gather_channel_quirk_mask
& (1<<sampler
))
2316 case SWIZZLE_Z
: return 2;
2317 case SWIZZLE_W
: return 3;
2319 unreachable("Not reached"); /* zero, one swizzles handled already */
2324 * Swizzle the result of a texture result. This is necessary for
2325 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2328 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
2329 fs_reg orig_val
, uint32_t sampler
)
2331 if (op
== ir_query_levels
) {
2332 /* # levels is in .w */
2333 this->result
= offset(orig_val
, 3);
2337 this->result
= orig_val
;
2339 /* txs,lod don't actually sample the texture, so swizzling the result
2342 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
2345 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2347 if (dest_components
== 1) {
2348 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2349 } else if (tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2350 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
2351 swizzled_result
.type
= orig_val
.type
;
2353 for (int i
= 0; i
< 4; i
++) {
2354 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], i
);
2355 fs_reg l
= swizzled_result
;
2358 if (swiz
== SWIZZLE_ZERO
) {
2359 emit(MOV(l
, fs_reg(0.0f
)));
2360 } else if (swiz
== SWIZZLE_ONE
) {
2361 emit(MOV(l
, fs_reg(1.0f
)));
2363 emit(MOV(l
, offset(orig_val
,
2364 GET_SWZ(tex
->swizzles
[sampler
], i
))));
2367 this->result
= swizzled_result
;
2372 fs_visitor::visit(ir_swizzle
*ir
)
2374 ir
->val
->accept(this);
2375 fs_reg val
= this->result
;
2377 if (ir
->type
->vector_elements
== 1) {
2378 this->result
= offset(this->result
, ir
->mask
.x
);
2382 fs_reg result
= vgrf(ir
->type
);
2383 this->result
= result
;
2385 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2386 fs_reg channel
= val
;
2404 emit(MOV(result
, offset(channel
, swiz
)));
2405 result
= offset(result
, 1);
2410 fs_visitor::visit(ir_discard
*ir
)
2412 /* We track our discarded pixels in f0.1. By predicating on it, we can
2413 * update just the flag bits that aren't yet discarded. If there's no
2414 * condition, we emit a CMP of g0 != g0, so all currently executing
2415 * channels will get turned off.
2418 if (ir
->condition
) {
2419 emit_bool_to_cond_code(ir
->condition
);
2420 cmp
= (fs_inst
*) this->instructions
.get_tail();
2421 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
2423 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2424 BRW_REGISTER_TYPE_UW
));
2425 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
2427 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2428 cmp
->flag_subreg
= 1;
2430 if (brw
->gen
>= 6) {
2431 /* For performance, after a discard, jump to the end of the shader.
2432 * Only jump if all relevant channels have been discarded.
2434 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2435 discard_jump
->flag_subreg
= 1;
2437 discard_jump
->predicate
= (dispatch_width
== 8)
2438 ? BRW_PREDICATE_ALIGN1_ANY8H
2439 : BRW_PREDICATE_ALIGN1_ANY16H
;
2440 discard_jump
->predicate_inverse
= true;
2445 fs_visitor::visit(ir_constant
*ir
)
2447 /* Set this->result to reg at the bottom of the function because some code
2448 * paths will cause this visitor to be applied to other fields. This will
2449 * cause the value stored in this->result to be modified.
2451 * Make reg constant so that it doesn't get accidentally modified along the
2452 * way. Yes, I actually had this problem. :(
2454 const fs_reg reg
= vgrf(ir
->type
);
2455 fs_reg dst_reg
= reg
;
2457 if (ir
->type
->is_array()) {
2458 const unsigned size
= type_size(ir
->type
->fields
.array
);
2460 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2461 ir
->array_elements
[i
]->accept(this);
2462 fs_reg src_reg
= this->result
;
2464 dst_reg
.type
= src_reg
.type
;
2465 for (unsigned j
= 0; j
< size
; j
++) {
2466 emit(MOV(dst_reg
, src_reg
));
2467 src_reg
= offset(src_reg
, 1);
2468 dst_reg
= offset(dst_reg
, 1);
2471 } else if (ir
->type
->is_record()) {
2472 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2473 const unsigned size
= type_size(field
->type
);
2475 field
->accept(this);
2476 fs_reg src_reg
= this->result
;
2478 dst_reg
.type
= src_reg
.type
;
2479 for (unsigned j
= 0; j
< size
; j
++) {
2480 emit(MOV(dst_reg
, src_reg
));
2481 src_reg
= offset(src_reg
, 1);
2482 dst_reg
= offset(dst_reg
, 1);
2486 const unsigned size
= type_size(ir
->type
);
2488 for (unsigned i
= 0; i
< size
; i
++) {
2489 switch (ir
->type
->base_type
) {
2490 case GLSL_TYPE_FLOAT
:
2491 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2493 case GLSL_TYPE_UINT
:
2494 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2497 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2499 case GLSL_TYPE_BOOL
:
2501 fs_reg(ir
->value
.b
[i
] != 0 ? (int)ctx
->Const
.UniformBooleanTrue
2505 unreachable("Non-float/uint/int/bool constant");
2507 dst_reg
= offset(dst_reg
, 1);
2515 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2517 ir_expression
*expr
= ir
->as_expression();
2519 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2522 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2523 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2530 assert(expr
->get_num_operands() <= 3);
2531 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2532 assert(expr
->operands
[i
]->type
->is_scalar());
2534 expr
->operands
[i
]->accept(this);
2535 op
[i
] = this->result
;
2537 resolve_ud_negate(&op
[i
]);
2540 switch (expr
->operation
) {
2541 case ir_unop_logic_not
:
2542 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2543 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2546 case ir_binop_logic_xor
:
2547 if (brw
->gen
<= 5) {
2548 fs_reg temp
= vgrf(ir
->type
);
2549 emit(XOR(temp
, op
[0], op
[1]));
2550 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2552 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2554 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2557 case ir_binop_logic_or
:
2558 if (brw
->gen
<= 5) {
2559 fs_reg temp
= vgrf(ir
->type
);
2560 emit(OR(temp
, op
[0], op
[1]));
2561 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2563 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2565 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2568 case ir_binop_logic_and
:
2569 if (brw
->gen
<= 5) {
2570 fs_reg temp
= vgrf(ir
->type
);
2571 emit(AND(temp
, op
[0], op
[1]));
2572 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2574 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2576 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2580 if (brw
->gen
>= 6) {
2581 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2583 inst
= emit(MOV(reg_null_f
, op
[0]));
2584 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2589 if (brw
->gen
>= 6) {
2590 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2592 inst
= emit(MOV(reg_null_d
, op
[0]));
2593 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2597 case ir_binop_greater
:
2598 case ir_binop_gequal
:
2600 case ir_binop_lequal
:
2601 case ir_binop_equal
:
2602 case ir_binop_all_equal
:
2603 case ir_binop_nequal
:
2604 case ir_binop_any_nequal
:
2605 if (brw
->gen
<= 5) {
2606 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2607 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2610 emit(CMP(reg_null_d
, op
[0], op
[1],
2611 brw_conditional_for_comparison(expr
->operation
)));
2614 case ir_triop_csel
: {
2615 /* Expand the boolean condition into the flag register. */
2616 inst
= emit(MOV(reg_null_d
, op
[0]));
2617 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2619 /* Select which boolean to return. */
2620 fs_reg temp
= vgrf(expr
->operands
[1]->type
);
2621 inst
= emit(SEL(temp
, op
[1], op
[2]));
2622 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2624 /* Expand the result to a condition code. */
2625 inst
= emit(MOV(reg_null_d
, temp
));
2626 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2631 unreachable("not reached");
2636 * Emit a gen6 IF statement with the comparison folded into the IF
2640 fs_visitor::emit_if_gen6(ir_if
*ir
)
2642 ir_expression
*expr
= ir
->condition
->as_expression();
2644 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2649 assert(expr
->get_num_operands() <= 3);
2650 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2651 assert(expr
->operands
[i
]->type
->is_scalar());
2653 expr
->operands
[i
]->accept(this);
2654 op
[i
] = this->result
;
2657 switch (expr
->operation
) {
2658 case ir_unop_logic_not
:
2659 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2662 case ir_binop_logic_xor
:
2663 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2666 case ir_binop_logic_or
:
2667 temp
= vgrf(glsl_type::bool_type
);
2668 emit(OR(temp
, op
[0], op
[1]));
2669 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2672 case ir_binop_logic_and
:
2673 temp
= vgrf(glsl_type::bool_type
);
2674 emit(AND(temp
, op
[0], op
[1]));
2675 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2679 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2680 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2684 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2687 case ir_binop_greater
:
2688 case ir_binop_gequal
:
2690 case ir_binop_lequal
:
2691 case ir_binop_equal
:
2692 case ir_binop_all_equal
:
2693 case ir_binop_nequal
:
2694 case ir_binop_any_nequal
:
2695 if (brw
->gen
<= 5) {
2696 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2697 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2700 emit(IF(op
[0], op
[1],
2701 brw_conditional_for_comparison(expr
->operation
)));
2704 case ir_triop_csel
: {
2705 /* Expand the boolean condition into the flag register. */
2706 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2707 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2709 /* Select which boolean to use as the result. */
2710 fs_reg temp
= vgrf(expr
->operands
[1]->type
);
2711 inst
= emit(SEL(temp
, op
[1], op
[2]));
2712 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2714 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2719 unreachable("not reached");
2723 ir
->condition
->accept(this);
2724 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2728 fs_visitor::try_opt_frontfacing_ternary(ir_if
*ir
)
2730 ir_dereference_variable
*deref
= ir
->condition
->as_dereference_variable();
2731 if (!deref
|| strcmp(deref
->var
->name
, "gl_FrontFacing") != 0)
2734 if (ir
->then_instructions
.length() != 1 ||
2735 ir
->else_instructions
.length() != 1)
2738 ir_assignment
*then_assign
=
2739 ((ir_instruction
*)ir
->then_instructions
.head
)->as_assignment();
2740 ir_assignment
*else_assign
=
2741 ((ir_instruction
*)ir
->else_instructions
.head
)->as_assignment();
2743 if (!then_assign
|| then_assign
->condition
||
2744 !else_assign
|| else_assign
->condition
||
2745 then_assign
->write_mask
!= else_assign
->write_mask
||
2746 !then_assign
->lhs
->equals(else_assign
->lhs
))
2749 ir_constant
*then_rhs
= then_assign
->rhs
->as_constant();
2750 ir_constant
*else_rhs
= else_assign
->rhs
->as_constant();
2752 if (!then_rhs
|| !else_rhs
)
2755 if ((then_rhs
->is_one() || then_rhs
->is_negative_one()) &&
2756 (else_rhs
->is_one() || else_rhs
->is_negative_one())) {
2757 assert(then_rhs
->is_one() == else_rhs
->is_negative_one());
2758 assert(else_rhs
->is_one() == then_rhs
->is_negative_one());
2760 then_assign
->lhs
->accept(this);
2761 fs_reg dst
= this->result
;
2762 dst
.type
= BRW_REGISTER_TYPE_D
;
2763 fs_reg tmp
= vgrf(glsl_type::int_type
);
2765 if (brw
->gen
>= 6) {
2766 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
2767 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
2769 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
2771 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
2772 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
2774 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
2777 if (then_rhs
->is_negative_one()) {
2778 assert(else_rhs
->is_one());
2782 tmp
.type
= BRW_REGISTER_TYPE_W
;
2783 tmp
.subreg_offset
= 2;
2786 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
2787 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
2789 tmp
.type
= BRW_REGISTER_TYPE_D
;
2790 tmp
.subreg_offset
= 0;
2793 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
2794 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
2796 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
2798 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
2799 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
2801 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
2804 if (then_rhs
->is_negative_one()) {
2805 assert(else_rhs
->is_one());
2809 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
2811 emit(AND(dst
, tmp
, fs_reg(0xbf800000)));
2819 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2821 * Many GLSL shaders contain the following pattern:
2823 * x = condition ? foo : bar
2825 * The compiler emits an ir_if tree for this, since each subexpression might be
2826 * a complex tree that could have side-effects or short-circuit logic.
2828 * However, the common case is to simply select one of two constants or
2829 * variable values---which is exactly what SEL is for. In this case, the
2830 * assembly looks like:
2838 * which can be easily translated into:
2840 * (+f0) SEL dst src0 src1
2842 * If src0 is an immediate value, we promote it to a temporary GRF.
2845 fs_visitor::try_replace_with_sel()
2847 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2848 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2850 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2852 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2855 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2856 for (int i
= 0; i
< 4; i
++) {
2857 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2859 match
= (fs_inst
*) match
->prev
;
2862 /* The opcodes match; it looks like the right sequence of instructions. */
2863 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2864 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2865 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2867 /* Check that the MOVs are the right form. */
2868 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2869 !then_mov
->is_partial_write() &&
2870 !else_mov
->is_partial_write()) {
2872 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2873 while (!if_inst
->next
->is_tail_sentinel())
2874 if_inst
->next
->exec_node::remove();
2875 if_inst
->exec_node::remove();
2877 /* Only the last source register can be a constant, so if the MOV in
2878 * the "then" clause uses a constant, we need to put it in a temporary.
2880 fs_reg
src0(then_mov
->src
[0]);
2881 if (src0
.file
== IMM
) {
2882 src0
= vgrf(glsl_type::float_type
);
2883 src0
.type
= then_mov
->src
[0].type
;
2884 emit(MOV(src0
, then_mov
->src
[0]));
2888 if (if_inst
->conditional_mod
) {
2889 /* Sandybridge-specific IF with embedded comparison */
2890 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2891 if_inst
->conditional_mod
));
2892 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2893 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2895 /* Separate CMP and IF instructions */
2896 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2897 sel
->predicate
= if_inst
->predicate
;
2898 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2908 fs_visitor::visit(ir_if
*ir
)
2910 if (try_opt_frontfacing_ternary(ir
))
2913 /* Don't point the annotation at the if statement, because then it plus
2914 * the then and else blocks get printed.
2916 this->base_ir
= ir
->condition
;
2918 if (brw
->gen
== 6) {
2921 emit_bool_to_cond_code(ir
->condition
);
2923 emit(IF(BRW_PREDICATE_NORMAL
));
2926 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2927 this->base_ir
= ir_
;
2931 if (!ir
->else_instructions
.is_empty()) {
2932 emit(BRW_OPCODE_ELSE
);
2934 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2935 this->base_ir
= ir_
;
2940 emit(BRW_OPCODE_ENDIF
);
2942 if (!try_replace_with_sel() && brw
->gen
< 6) {
2943 no16("Can't support (non-uniform) control flow on SIMD16\n");
2948 fs_visitor::visit(ir_loop
*ir
)
2951 no16("Can't support (non-uniform) control flow on SIMD16\n");
2954 this->base_ir
= NULL
;
2955 emit(BRW_OPCODE_DO
);
2957 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2958 this->base_ir
= ir_
;
2962 this->base_ir
= NULL
;
2963 emit(BRW_OPCODE_WHILE
);
2967 fs_visitor::visit(ir_loop_jump
*ir
)
2970 case ir_loop_jump::jump_break
:
2971 emit(BRW_OPCODE_BREAK
);
2973 case ir_loop_jump::jump_continue
:
2974 emit(BRW_OPCODE_CONTINUE
);
2980 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2982 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2983 ir
->actual_parameters
.get_head());
2984 ir_variable
*location
= deref
->variable_referenced();
2985 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2986 location
->data
.binding
);
2988 /* Calculate the surface offset */
2989 fs_reg offset
= vgrf(glsl_type::uint_type
);
2990 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2993 deref_array
->array_index
->accept(this);
2995 fs_reg tmp
= vgrf(glsl_type::uint_type
);
2996 emit(MUL(tmp
, this->result
, fs_reg(ATOMIC_COUNTER_SIZE
)));
2997 emit(ADD(offset
, tmp
, fs_reg(location
->data
.atomic
.offset
)));
2999 offset
= fs_reg(location
->data
.atomic
.offset
);
3002 /* Emit the appropriate machine instruction */
3003 const char *callee
= ir
->callee
->function_name();
3004 ir
->return_deref
->accept(this);
3005 fs_reg dst
= this->result
;
3007 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3008 emit_untyped_surface_read(surf_index
, dst
, offset
);
3010 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3011 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
3012 fs_reg(), fs_reg());
3014 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3015 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
3016 fs_reg(), fs_reg());
3021 fs_visitor::visit(ir_call
*ir
)
3023 const char *callee
= ir
->callee
->function_name();
3025 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3026 !strcmp("__intrinsic_atomic_increment", callee
) ||
3027 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
3028 visit_atomic_counter_intrinsic(ir
);
3030 unreachable("Unsupported intrinsic.");
3035 fs_visitor::visit(ir_return
*)
3037 unreachable("FINISHME");
3041 fs_visitor::visit(ir_function
*ir
)
3043 /* Ignore function bodies other than main() -- we shouldn't see calls to
3044 * them since they should all be inlined before we get to ir_to_mesa.
3046 if (strcmp(ir
->name
, "main") == 0) {
3047 const ir_function_signature
*sig
;
3050 sig
= ir
->matching_signature(NULL
, &empty
, false);
3054 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
3055 this->base_ir
= ir_
;
3062 fs_visitor::visit(ir_function_signature
*)
3064 unreachable("not reached");
3068 fs_visitor::visit(ir_emit_vertex
*)
3070 unreachable("not reached");
3074 fs_visitor::visit(ir_end_primitive
*)
3076 unreachable("not reached");
3080 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
3081 fs_reg dst
, fs_reg offset
, fs_reg src0
,
3084 int reg_width
= dispatch_width
/ 8;
3087 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
3089 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3090 /* Initialize the sample mask in the message header. */
3091 emit(MOV(sources
[0], fs_reg(0u)))
3092 ->force_writemask_all
= true;
3094 if (stage
== MESA_SHADER_FRAGMENT
) {
3095 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
3096 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
3097 ->force_writemask_all
= true;
3099 emit(MOV(component(sources
[0], 7),
3100 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
3101 ->force_writemask_all
= true;
3104 /* The execution mask is part of the side-band information sent together with
3105 * the message payload to the data port. It's implicitly ANDed with the sample
3106 * mask sent in the header to compute the actual set of channels that execute
3107 * the atomic operation.
3109 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
3110 emit(MOV(component(sources
[0], 7),
3111 fs_reg(0xffff)))->force_writemask_all
= true;
3115 /* Set the atomic operation offset. */
3116 sources
[1] = vgrf(glsl_type::uint_type
);
3117 emit(MOV(sources
[1], offset
));
3120 /* Set the atomic operation arguments. */
3121 if (src0
.file
!= BAD_FILE
) {
3122 sources
[length
] = vgrf(glsl_type::uint_type
);
3123 emit(MOV(sources
[length
], src0
));
3127 if (src1
.file
!= BAD_FILE
) {
3128 sources
[length
] = vgrf(glsl_type::uint_type
);
3129 emit(MOV(sources
[length
], src1
));
3133 int mlen
= 1 + (length
- 1) * reg_width
;
3134 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
3135 BRW_REGISTER_TYPE_UD
);
3136 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
3138 /* Emit the instruction. */
3139 fs_inst
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
3140 fs_reg(atomic_op
), fs_reg(surf_index
));
3145 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
3148 int reg_width
= dispatch_width
/ 8;
3150 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
3152 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3153 /* Initialize the sample mask in the message header. */
3154 emit(MOV(sources
[0], fs_reg(0u)))
3155 ->force_writemask_all
= true;
3157 if (stage
== MESA_SHADER_FRAGMENT
) {
3158 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
3159 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
3160 ->force_writemask_all
= true;
3162 emit(MOV(component(sources
[0], 7),
3163 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
3164 ->force_writemask_all
= true;
3167 /* The execution mask is part of the side-band information sent together with
3168 * the message payload to the data port. It's implicitly ANDed with the sample
3169 * mask sent in the header to compute the actual set of channels that execute
3170 * the atomic operation.
3172 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
3173 emit(MOV(component(sources
[0], 7),
3174 fs_reg(0xffff)))->force_writemask_all
= true;
3177 /* Set the surface read offset. */
3178 sources
[1] = vgrf(glsl_type::uint_type
);
3179 emit(MOV(sources
[1], offset
));
3181 int mlen
= 1 + reg_width
;
3182 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
3183 BRW_REGISTER_TYPE_UD
);
3184 fs_inst
*inst
= emit(LOAD_PAYLOAD(src_payload
, sources
, 2));
3186 /* Emit the instruction. */
3187 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
3188 fs_reg(surf_index
));
3193 fs_visitor::emit(fs_inst
*inst
)
3195 if (dispatch_width
== 16 && inst
->exec_size
== 8)
3196 inst
->force_uncompressed
= true;
3198 inst
->annotation
= this->current_annotation
;
3199 inst
->ir
= this->base_ir
;
3201 this->instructions
.push_tail(inst
);
3207 fs_visitor::emit(exec_list list
)
3209 foreach_in_list_safe(fs_inst
, inst
, &list
) {
3210 inst
->exec_node::remove();
3215 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
3217 fs_visitor::emit_dummy_fs()
3219 int reg_width
= dispatch_width
/ 8;
3221 /* Everyone's favorite color. */
3222 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
3223 for (int i
= 0; i
< 4; i
++) {
3224 emit(MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
,
3225 dispatch_width
), fs_reg(color
[i
])));
3229 write
= emit(FS_OPCODE_FB_WRITE
);
3231 if (brw
->gen
>= 6) {
3232 write
->base_mrf
= 2;
3233 write
->mlen
= 4 * reg_width
;
3235 write
->header_present
= true;
3236 write
->base_mrf
= 0;
3237 write
->mlen
= 2 + 4 * reg_width
;
3240 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
3241 * varying to avoid GPU hangs, so set that.
3243 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3244 wm_prog_data
->num_varying_inputs
= brw
->gen
< 6 ? 1 : 0;
3245 memset(wm_prog_data
->urb_setup
, -1,
3246 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
3248 /* We don't have any uniforms. */
3249 stage_prog_data
->nr_params
= 0;
3250 stage_prog_data
->nr_pull_params
= 0;
3251 stage_prog_data
->curb_read_length
= 0;
3252 stage_prog_data
->dispatch_grf_start_reg
= 2;
3253 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
3254 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
3259 /* The register location here is relative to the start of the URB
3260 * data. It will get adjusted to be a real location before
3261 * generate_code() time.
3264 fs_visitor::interp_reg(int location
, int channel
)
3266 assert(stage
== MESA_SHADER_FRAGMENT
);
3267 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3268 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
3269 int stride
= (channel
& 1) * 4;
3271 assert(prog_data
->urb_setup
[location
] != -1);
3273 return brw_vec1_grf(regnr
, stride
);
3276 /** Emits the interpolation for the varying inputs. */
3278 fs_visitor::emit_interpolation_setup_gen4()
3280 this->current_annotation
= "compute pixel centers";
3281 this->pixel_x
= vgrf(glsl_type::uint_type
);
3282 this->pixel_y
= vgrf(glsl_type::uint_type
);
3283 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3284 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3286 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
3287 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
3289 this->current_annotation
= "compute pixel deltas from v0";
3291 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3292 vgrf(glsl_type::vec2_type
);
3293 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3294 offset(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
], 1);
3296 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3297 vgrf(glsl_type::float_type
);
3298 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3299 vgrf(glsl_type::float_type
);
3301 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3302 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
3303 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3304 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
3306 this->current_annotation
= "compute pos.w and 1/pos.w";
3307 /* Compute wpos.w. It's always in our setup, since it's needed to
3308 * interpolate the other attributes.
3310 this->wpos_w
= vgrf(glsl_type::float_type
);
3311 emit(FS_OPCODE_LINTERP
, wpos_w
,
3312 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3313 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3314 interp_reg(VARYING_SLOT_POS
, 3));
3315 /* Compute the pixel 1/W value from wpos.w. */
3316 this->pixel_w
= vgrf(glsl_type::float_type
);
3317 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
3318 this->current_annotation
= NULL
;
3321 /** Emits the interpolation for the varying inputs. */
3323 fs_visitor::emit_interpolation_setup_gen6()
3325 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
3327 /* If the pixel centers end up used, the setup is the same as for gen4. */
3328 this->current_annotation
= "compute pixel centers";
3329 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
3330 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
3331 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3332 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3333 emit(ADD(int_pixel_x
,
3334 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
3335 fs_reg(brw_imm_v(0x10101010))));
3336 emit(ADD(int_pixel_y
,
3337 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
3338 fs_reg(brw_imm_v(0x11001100))));
3340 /* As of gen6, we can no longer mix float and int sources. We have
3341 * to turn the integer pixel centers into floats for their actual
3344 this->pixel_x
= vgrf(glsl_type::float_type
);
3345 this->pixel_y
= vgrf(glsl_type::float_type
);
3346 emit(MOV(this->pixel_x
, int_pixel_x
));
3347 emit(MOV(this->pixel_y
, int_pixel_y
));
3349 this->current_annotation
= "compute pos.w";
3350 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
3351 this->wpos_w
= vgrf(glsl_type::float_type
);
3352 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
3354 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3355 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
3356 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
3357 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
3360 this->current_annotation
= NULL
;
3364 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
,
3367 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3370 if (color
.file
== BAD_FILE
) {
3371 return 4 * (dispatch_width
/ 8);
3374 uint8_t colors_enabled
;
3375 if (components
== 0) {
3376 /* We want to write one component to the alpha channel */
3377 colors_enabled
= 0x8;
3379 /* Enable the first components-many channels */
3380 colors_enabled
= (1 << components
) - 1;
3383 if (dispatch_width
== 8 || (brw
->gen
>= 6 && !do_dual_src
)) {
3384 /* SIMD8 write looks like:
3390 * gen6 SIMD16 DP write looks like:
3401 for (unsigned i
= 0; i
< 4; ++i
) {
3402 if (colors_enabled
& (1 << i
)) {
3403 dst
[len
] = fs_reg(GRF
, alloc
.allocate(color
.width
/ 8),
3404 color
.type
, color
.width
);
3405 inst
= emit(MOV(dst
[len
], offset(color
, i
)));
3406 inst
->saturate
= key
->clamp_fragment_color
;
3407 } else if (color
.width
== 16) {
3408 /* We need two BAD_FILE slots for a 16-wide color */
3414 } else if (brw
->gen
>= 6 && do_dual_src
) {
3415 /* SIMD16 dual source blending for gen6+.
3417 * From the SNB PRM, volume 4, part 1, page 193:
3419 * "The dual source render target messages only have SIMD8 forms due to
3420 * maximum message length limitations. SIMD16 pixel shaders must send two
3421 * of these messages to cover all of the pixels. Each message contains
3422 * two colors (4 channels each) for each pixel in the message payload."
3424 * So in SIMD16 dual source blending we will send 2 SIMD8 messages,
3425 * each one will call this function twice (one for each color involved),
3426 * so in each pass we only write 4 registers. Notice that the second
3427 * SIMD8 message needs to read color data from the 2nd half of the color
3428 * registers, so it needs to call this with use_2nd_half = true.
3430 for (unsigned i
= 0; i
< 4; ++i
) {
3431 if (colors_enabled
& (1 << i
)) {
3432 dst
[i
] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3433 inst
= emit(MOV(dst
[i
], half(offset(color
, i
),
3434 use_2nd_half
? 1 : 0)));
3435 inst
->saturate
= key
->clamp_fragment_color
;
3437 inst
->force_sechalf
= true;
3442 /* pre-gen6 SIMD16 single source DP write looks like:
3452 for (unsigned i
= 0; i
< 4; ++i
) {
3453 if (colors_enabled
& (1 << i
)) {
3454 dst
[i
] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3455 inst
= emit(MOV(dst
[i
], half(offset(color
, i
), 0)));
3456 inst
->saturate
= key
->clamp_fragment_color
;
3458 dst
[i
+ 4] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3459 inst
= emit(MOV(dst
[i
+ 4], half(offset(color
, i
), 1)));
3460 inst
->saturate
= key
->clamp_fragment_color
;
3461 inst
->force_sechalf
= true;
3468 static enum brw_conditional_mod
3469 cond_for_alpha_func(GLenum func
)
3473 return BRW_CONDITIONAL_G
;
3475 return BRW_CONDITIONAL_GE
;
3477 return BRW_CONDITIONAL_L
;
3479 return BRW_CONDITIONAL_LE
;
3481 return BRW_CONDITIONAL_EQ
;
3483 return BRW_CONDITIONAL_NEQ
;
3485 unreachable("Not reached");
3490 * Alpha test support for when we compile it into the shader instead
3491 * of using the normal fixed-function alpha test.
3494 fs_visitor::emit_alpha_test()
3496 assert(stage
== MESA_SHADER_FRAGMENT
);
3497 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3498 this->current_annotation
= "Alpha test";
3501 if (key
->alpha_test_func
== GL_ALWAYS
)
3504 if (key
->alpha_test_func
== GL_NEVER
) {
3506 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3507 BRW_REGISTER_TYPE_UW
));
3508 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3509 BRW_CONDITIONAL_NEQ
));
3512 fs_reg color
= offset(outputs
[0], 3);
3514 /* f0.1 &= func(color, ref) */
3515 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3516 cond_for_alpha_func(key
->alpha_test_func
)));
3518 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3519 cmp
->flag_subreg
= 1;
3523 fs_visitor::emit_single_fb_write(fs_reg color0
, fs_reg color1
,
3524 fs_reg src0_alpha
, unsigned components
,
3527 assert(stage
== MESA_SHADER_FRAGMENT
);
3528 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3529 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3531 this->current_annotation
= "FB write header";
3532 bool header_present
= true;
3533 int reg_size
= dispatch_width
/ 8;
3535 /* We can potentially have a message length of up to 15, so we have to set
3536 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3538 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
3541 /* From the Sandy Bridge PRM, volume 4, page 198:
3543 * "Dispatched Pixel Enables. One bit per pixel indicating
3544 * which pixels were originally enabled when the thread was
3545 * dispatched. This field is only required for the end-of-
3546 * thread message and on all dual-source messages."
3548 if (brw
->gen
>= 6 &&
3549 (brw
->is_haswell
|| brw
->gen
>= 8 || !prog_data
->uses_kill
) &&
3550 color1
.file
== BAD_FILE
&&
3551 key
->nr_color_regions
== 1) {
3552 header_present
= false;
3556 /* Allocate 2 registers for a header */
3559 if (payload
.aa_dest_stencil_reg
) {
3560 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1));
3561 emit(MOV(sources
[length
],
3562 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3566 prog_data
->uses_omask
=
3567 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3568 if (prog_data
->uses_omask
) {
3569 this->current_annotation
= "FB write oMask";
3570 assert(this->sample_mask
.file
!= BAD_FILE
);
3571 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
3572 * it's unsinged single words, one vgrf is always 16-wide.
3574 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1),
3575 BRW_REGISTER_TYPE_UW
, 16);
3576 emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
3580 if (color0
.file
== BAD_FILE
) {
3581 /* Even if there's no color buffers enabled, we still need to send
3582 * alpha out the pipeline to our null renderbuffer to support
3583 * alpha-testing, alpha-to-coverage, and so on.
3585 length
+= setup_color_payload(sources
+ length
, this->outputs
[0], 0,
3587 } else if (color1
.file
== BAD_FILE
) {
3588 if (src0_alpha
.file
!= BAD_FILE
) {
3589 sources
[length
] = fs_reg(GRF
, alloc
.allocate(reg_size
),
3590 src0_alpha
.type
, src0_alpha
.width
);
3591 fs_inst
*inst
= emit(MOV(sources
[length
], src0_alpha
));
3592 inst
->saturate
= key
->clamp_fragment_color
;
3596 length
+= setup_color_payload(sources
+ length
, color0
, components
,
3599 length
+= setup_color_payload(sources
+ length
, color0
, components
,
3601 length
+= setup_color_payload(sources
+ length
, color1
, components
,
3605 if (source_depth_to_render_target
) {
3606 if (brw
->gen
== 6) {
3607 /* For outputting oDepth on gen6, SIMD8 writes have to be
3608 * used. This would require SIMD8 moves of each half to
3609 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3610 * Just bail on doing so for now.
3612 no16("Missing support for simd16 depth writes on gen6\n");
3615 sources
[length
] = vgrf(glsl_type::float_type
);
3616 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3617 /* Hand over gl_FragDepth. */
3618 assert(this->frag_depth
.file
!= BAD_FILE
);
3619 emit(MOV(sources
[length
], this->frag_depth
));
3621 /* Pass through the payload depth. */
3622 emit(MOV(sources
[length
],
3623 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3628 if (payload
.dest_depth_reg
) {
3629 sources
[length
] = vgrf(glsl_type::float_type
);
3630 emit(MOV(sources
[length
],
3631 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3637 if (brw
->gen
>= 7) {
3638 /* Send from the GRF */
3639 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3640 load
= emit(LOAD_PAYLOAD(payload
, sources
, length
));
3641 payload
.reg
= alloc
.allocate(load
->regs_written
);
3642 payload
.width
= dispatch_width
;
3643 load
->dst
= payload
;
3644 write
= emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
3645 write
->base_mrf
= -1;
3647 /* Send from the MRF */
3648 load
= emit(LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3650 write
= emit(FS_OPCODE_FB_WRITE
);
3651 write
->exec_size
= dispatch_width
;
3652 write
->base_mrf
= 1;
3655 write
->mlen
= load
->regs_written
;
3656 write
->header_present
= header_present
;
3657 if (prog_data
->uses_kill
) {
3658 write
->predicate
= BRW_PREDICATE_NORMAL
;
3659 write
->flag_subreg
= 1;
3665 fs_visitor::emit_fb_writes()
3667 assert(stage
== MESA_SHADER_FRAGMENT
);
3668 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3669 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3671 fs_inst
*inst
= NULL
;
3673 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3674 "FB dual-source write");
3675 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3679 /* SIMD16 dual source blending requires to send two SIMD8 dual source
3680 * messages, where each message contains color data for 8 pixels. Color
3681 * data for the first group of pixels is stored in the "lower" half of
3682 * the color registers, so in SIMD16, the previous message did:
3688 * Here goes the second message, which packs color data for the
3689 * remaining 8 pixels. Color data for these pixels is stored in the
3690 * "upper" half of the color registers, so we need to do:
3696 if (dispatch_width
== 16) {
3697 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3698 reg_undef
, 4, true);
3702 prog_data
->dual_src_blend
= true;
3704 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3705 /* Skip over outputs that weren't written. */
3706 if (this->outputs
[target
].file
== BAD_FILE
)
3709 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3710 "FB write target %d",
3713 if (brw
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
3714 src0_alpha
= offset(outputs
[0], 3);
3716 inst
= emit_single_fb_write(this->outputs
[target
], reg_undef
,
3718 this->output_components
[target
]);
3719 inst
->target
= target
;
3724 /* Even if there's no color buffers enabled, we still need to send
3725 * alpha out the pipeline to our null renderbuffer to support
3726 * alpha-testing, alpha-to-coverage, and so on.
3728 inst
= emit_single_fb_write(reg_undef
, reg_undef
, reg_undef
, 0);
3733 this->current_annotation
= NULL
;
3737 fs_visitor::setup_uniform_clipplane_values()
3739 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
3740 const struct brw_vue_prog_key
*key
=
3741 (const struct brw_vue_prog_key
*) this->key
;
3743 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
3744 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
3745 for (int j
= 0; j
< 4; ++j
) {
3746 stage_prog_data
->param
[uniforms
+ j
] =
3747 (gl_constant_value
*) &clip_planes
[i
][j
];
3753 void fs_visitor::compute_clip_distance()
3755 struct brw_vue_prog_data
*vue_prog_data
=
3756 (struct brw_vue_prog_data
*) prog_data
;
3757 const struct brw_vue_prog_key
*key
=
3758 (const struct brw_vue_prog_key
*) this->key
;
3760 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3762 * "If a linked set of shaders forming the vertex stage contains no
3763 * static write to gl_ClipVertex or gl_ClipDistance, but the
3764 * application has requested clipping against user clip planes through
3765 * the API, then the coordinate written to gl_Position is used for
3766 * comparison against the user clip planes."
3768 * This function is only called if the shader didn't write to
3769 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3770 * if the user wrote to it; otherwise we use gl_Position.
3773 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3774 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
3775 clip_vertex
= VARYING_SLOT_POS
;
3777 /* If the clip vertex isn't written, skip this. Typically this means
3778 * the GS will set up clipping. */
3779 if (outputs
[clip_vertex
].file
== BAD_FILE
)
3782 setup_uniform_clipplane_values();
3784 current_annotation
= "user clip distances";
3786 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
3787 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
3789 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
3790 fs_reg u
= userplane
[i
];
3791 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
3792 output
.reg_offset
= i
& 3;
3794 emit(MUL(output
, outputs
[clip_vertex
], u
));
3795 for (int j
= 1; j
< 4; j
++) {
3796 u
.reg
= userplane
[i
].reg
+ j
;
3797 emit(MAD(output
, output
, offset(outputs
[clip_vertex
], j
), u
));
3803 fs_visitor::emit_urb_writes()
3805 int slot
, urb_offset
, length
;
3806 struct brw_vs_prog_data
*vs_prog_data
=
3807 (struct brw_vs_prog_data
*) prog_data
;
3808 const struct brw_vs_prog_key
*key
=
3809 (const struct brw_vs_prog_key
*) this->key
;
3810 const GLbitfield64 psiz_mask
=
3811 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
3812 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
3816 /* Lower legacy ff and ClipVertex clipping to clip distances */
3817 if (key
->base
.userclip_active
&& !prog
->UsesClipDistanceOut
)
3818 compute_clip_distance();
3820 /* If we don't have any valid slots to write, just do a minimal urb write
3821 * send to terminate the shader. */
3822 if (vue_map
->slots_valid
== 0) {
3824 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3825 fs_inst
*inst
= emit(MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
3826 BRW_REGISTER_TYPE_UD
))));
3827 inst
->force_writemask_all
= true;
3829 inst
= emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
3839 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
3840 fs_reg reg
, src
, zero
;
3842 int varying
= vue_map
->slot_to_varying
[slot
];
3844 case VARYING_SLOT_PSIZ
:
3846 /* The point size varying slot is the vue header and is always in the
3847 * vue map. But often none of the special varyings that live there
3848 * are written and in that case we can skip writing to the vue
3849 * header, provided the corresponding state properly clamps the
3850 * values further down the pipeline. */
3851 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
3852 assert(length
== 0);
3857 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3858 emit(MOV(zero
, fs_reg(0u)));
3860 sources
[length
++] = zero
;
3861 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
3862 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
3864 sources
[length
++] = zero
;
3866 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
3867 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
3869 sources
[length
++] = zero
;
3871 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
3872 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
3874 sources
[length
++] = zero
;
3877 case BRW_VARYING_SLOT_NDC
:
3878 case VARYING_SLOT_EDGE
:
3879 unreachable("unexpected scalar vs output");
3882 case BRW_VARYING_SLOT_PAD
:
3886 /* gl_Position is always in the vue map, but isn't always written by
3887 * the shader. Other varyings (clip distances) get added to the vue
3888 * map but don't always get written. In those cases, the
3889 * corresponding this->output[] slot will be invalid we and can skip
3890 * the urb write for the varying. If we've already queued up a vue
3891 * slot for writing we flush a mlen 5 urb write, otherwise we just
3892 * advance the urb_offset.
3894 if (this->outputs
[varying
].file
== BAD_FILE
) {
3902 if ((varying
== VARYING_SLOT_COL0
||
3903 varying
== VARYING_SLOT_COL1
||
3904 varying
== VARYING_SLOT_BFC0
||
3905 varying
== VARYING_SLOT_BFC1
) &&
3906 key
->clamp_vertex_color
) {
3907 /* We need to clamp these guys, so do a saturating MOV into a
3908 * temp register and use that for the payload.
3910 for (int i
= 0; i
< 4; i
++) {
3911 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
3912 src
= offset(this->outputs
[varying
], i
);
3913 fs_inst
*inst
= emit(MOV(reg
, src
));
3914 inst
->saturate
= true;
3915 sources
[length
++] = reg
;
3918 for (int i
= 0; i
< 4; i
++)
3919 sources
[length
++] = offset(this->outputs
[varying
], i
);
3924 current_annotation
= "URB write";
3926 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
3927 * the last slot or if we need to flush (see BAD_FILE varying case
3928 * above), emit a URB write send now to flush out the data.
3930 int last
= slot
== vue_map
->num_slots
- 1;
3931 if (length
== 8 || last
)
3934 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
3935 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
3936 BRW_REGISTER_TYPE_F
);
3938 /* We need WE_all on the MOV for the message header (the URB handles)
3939 * so do a MOV to a dummy register and set force_writemask_all on the
3940 * MOV. LOAD_PAYLOAD will preserve that.
3942 fs_reg dummy
= fs_reg(GRF
, alloc
.allocate(1),
3943 BRW_REGISTER_TYPE_UD
);
3944 fs_inst
*inst
= emit(MOV(dummy
, fs_reg(retype(brw_vec8_grf(1, 0),
3945 BRW_REGISTER_TYPE_UD
))));
3946 inst
->force_writemask_all
= true;
3947 payload_sources
[0] = dummy
;
3949 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
3950 emit(LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1));
3952 inst
= emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
3954 inst
->mlen
= length
+ 1;
3955 inst
->offset
= urb_offset
;
3956 urb_offset
= slot
+ 1;
3964 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3966 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3970 fs_reg temp
= vgrf(glsl_type::uint_type
);
3971 emit(MOV(temp
, *reg
));
3976 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3978 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3979 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3982 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3984 assert(brw
->gen
<= 5);
3986 if (rvalue
->type
!= glsl_type::bool_type
)
3989 fs_reg and_result
= vgrf(glsl_type::bool_type
);
3990 fs_reg neg_result
= vgrf(glsl_type::bool_type
);
3991 emit(AND(and_result
, *reg
, fs_reg(1)));
3992 emit(MOV(neg_result
, negate(and_result
)));
3996 fs_visitor::fs_visitor(struct brw_context
*brw
,
3998 const struct brw_wm_prog_key
*key
,
3999 struct brw_wm_prog_data
*prog_data
,
4000 struct gl_shader_program
*shader_prog
,
4001 struct gl_fragment_program
*fp
,
4002 unsigned dispatch_width
)
4003 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
4004 MESA_SHADER_FRAGMENT
),
4005 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
4006 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
4007 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
4008 key(key
), prog_data(&prog_data
->base
),
4009 dispatch_width(dispatch_width
)
4011 this->mem_ctx
= mem_ctx
;
4015 fs_visitor::fs_visitor(struct brw_context
*brw
,
4017 const struct brw_vs_prog_key
*key
,
4018 struct brw_vs_prog_data
*prog_data
,
4019 struct gl_shader_program
*shader_prog
,
4020 struct gl_vertex_program
*cp
,
4021 unsigned dispatch_width
)
4022 : backend_visitor(brw
, shader_prog
, &cp
->Base
, &prog_data
->base
.base
,
4023 MESA_SHADER_VERTEX
),
4024 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
4025 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
4026 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
4027 key(key
), prog_data(&prog_data
->base
.base
),
4028 dispatch_width(dispatch_width
)
4030 this->mem_ctx
= mem_ctx
;
4037 this->failed
= false;
4038 this->simd16_unsupported
= false;
4039 this->no16_msg
= NULL
;
4040 this->variable_ht
= hash_table_ctor(0,
4041 hash_table_pointer_hash
,
4042 hash_table_pointer_compare
);
4044 this->nir_locals
= NULL
;
4045 this->nir_globals
= NULL
;
4047 memset(&this->payload
, 0, sizeof(this->payload
));
4048 memset(this->outputs
, 0, sizeof(this->outputs
));
4049 memset(this->output_components
, 0, sizeof(this->output_components
));
4050 this->source_depth_to_render_target
= false;
4051 this->runtime_check_aads_emit
= false;
4052 this->first_non_payload_grf
= 0;
4053 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
4055 this->current_annotation
= NULL
;
4056 this->base_ir
= NULL
;
4058 this->virtual_grf_start
= NULL
;
4059 this->virtual_grf_end
= NULL
;
4060 this->live_intervals
= NULL
;
4061 this->regs_live_at_ip
= NULL
;
4064 this->last_scratch
= 0;
4065 this->pull_constant_loc
= NULL
;
4066 this->push_constant_loc
= NULL
;
4068 this->spilled_any_registers
= false;
4069 this->do_dual_src
= false;
4071 if (dispatch_width
== 8)
4072 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
4075 fs_visitor::~fs_visitor()
4077 hash_table_dtor(this->variable_ht
);