2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "util/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 assert(ir
->data
.location
!= -1);
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation();
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->data
.mode
== ir_var_shader_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
74 if (ir
->data
.index
> 0) {
75 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
76 assert(ir
->data
.index
== 1);
77 this->dual_src_output
= *reg
;
78 this->do_dual_src
= true;
79 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
80 /* Writing gl_FragColor outputs to all color regions. */
81 assert(stage
== MESA_SHADER_FRAGMENT
);
82 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
83 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
84 this->outputs
[i
] = *reg
;
85 this->output_components
[i
] = 4;
87 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
88 this->frag_depth
= *reg
;
89 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
90 this->sample_mask
= *reg
;
92 /* gl_FragData or a user-defined FS output */
93 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
94 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
97 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
98 : ir
->type
->vector_elements
;
100 /* General color output. */
101 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
102 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
103 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
104 this->output_components
[output
] = vector_elements
;
107 } else if (ir
->data
.mode
== ir_var_uniform
) {
108 int param_index
= uniforms
;
110 /* Thanks to the lower_ubo_reference pass, we will see only
111 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
112 * variables, so no need for them to be in variable_ht.
114 * Some uniforms, such as samplers and atomic counters, have no actual
115 * storage, so we should ignore them.
117 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
120 if (dispatch_width
== 16) {
121 if (!variable_storage(ir
)) {
122 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
127 param_size
[param_index
] = type_size(ir
->type
);
128 if (!strncmp(ir
->name
, "gl_", 3)) {
129 setup_builtin_uniform_values(ir
);
131 setup_uniform_values(ir
);
134 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
135 reg
->type
= brw_type_for_base_type(ir
->type
);
137 } else if (ir
->data
.mode
== ir_var_system_value
) {
138 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
139 reg
= emit_samplepos_setup();
140 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
141 reg
= emit_sampleid_setup();
142 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
143 assert(brw
->gen
>= 7);
145 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
146 BRW_REGISTER_TYPE_D
));
151 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
153 hash_table_insert(this->variable_ht
, reg
, ir
);
157 fs_visitor::visit(ir_dereference_variable
*ir
)
159 fs_reg
*reg
= variable_storage(ir
->var
);
162 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
163 this->result
= fs_reg(reg_null_d
);
170 fs_visitor::visit(ir_dereference_record
*ir
)
172 const glsl_type
*struct_type
= ir
->record
->type
;
174 ir
->record
->accept(this);
176 unsigned int off
= 0;
177 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
178 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
180 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
182 this->result
= offset(this->result
, off
);
183 this->result
.type
= brw_type_for_base_type(ir
->type
);
187 fs_visitor::visit(ir_dereference_array
*ir
)
189 ir_constant
*constant_index
;
191 int element_size
= type_size(ir
->type
);
193 constant_index
= ir
->array_index
->as_constant();
195 ir
->array
->accept(this);
197 src
.type
= brw_type_for_base_type(ir
->type
);
199 if (constant_index
) {
200 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
201 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
203 /* Variable index array dereference. We attach the variable index
204 * component to the reg as a pointer to a register containing the
205 * offset. Currently only uniform arrays are supported in this patch,
206 * and that reladdr pointer is resolved by
207 * move_uniform_array_access_to_pull_constants(). All other array types
208 * are lowered by lower_variable_index_to_cond_assign().
210 ir
->array_index
->accept(this);
213 index_reg
= fs_reg(this, glsl_type::int_type
);
214 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
217 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
220 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
221 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
227 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
231 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
232 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
233 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
234 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
236 emit(MUL(y_times_a
, y
, a
));
238 fs_reg negative_a
= a
;
239 negative_a
.negate
= !a
.negate
;
240 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
241 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
243 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
245 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
246 * we need to reorder the operands.
248 emit(LRP(dst
, a
, y
, x
));
253 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
254 const fs_reg
&src0
, const fs_reg
&src1
)
259 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
260 inst
->conditional_mod
= conditionalmod
;
262 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
264 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
265 inst
->predicate
= BRW_PREDICATE_NORMAL
;
270 fs_visitor::try_emit_saturate(ir_expression
*ir
)
272 if (ir
->operation
!= ir_unop_saturate
)
275 ir_rvalue
*sat_val
= ir
->operands
[0];
277 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
279 sat_val
->accept(this);
280 fs_reg src
= this->result
;
282 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
284 /* If the last instruction from our accept() generated our
285 * src, just set the saturate flag instead of emmitting a separate mov.
287 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
288 if (modify
&& modify
->regs_written
== modify
->dst
.width
/ 8 &&
289 modify
->can_do_saturate()) {
290 modify
->saturate
= true;
299 fs_visitor::try_emit_line(ir_expression
*ir
)
301 /* LINE's src0 must be of type float. */
302 if (ir
->type
!= glsl_type::float_type
)
305 ir_rvalue
*nonmul
= ir
->operands
[1];
306 ir_expression
*mul
= ir
->operands
[0]->as_expression();
308 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
309 nonmul
= ir
->operands
[0];
310 mul
= ir
->operands
[1]->as_expression();
312 if (!mul
|| mul
->operation
!= ir_binop_mul
)
316 ir_constant
*const_add
= nonmul
->as_constant();
320 int add_operand_vf
= brw_float_to_vf(const_add
->value
.f
[0]);
321 if (add_operand_vf
== -1)
324 ir_rvalue
*non_const_mul
= mul
->operands
[1];
325 ir_constant
*const_mul
= mul
->operands
[0]->as_constant();
327 const_mul
= mul
->operands
[1]->as_constant();
332 non_const_mul
= mul
->operands
[0];
335 int mul_operand_vf
= brw_float_to_vf(const_mul
->value
.f
[0]);
336 if (mul_operand_vf
== -1)
339 non_const_mul
->accept(this);
340 fs_reg src1
= this->result
;
342 fs_reg src0
= fs_reg(this, ir
->type
);
343 emit(BRW_OPCODE_MOV
, src0
,
344 fs_reg((uint8_t)mul_operand_vf
, 0, 0, (uint8_t)add_operand_vf
));
346 this->result
= fs_reg(this, ir
->type
);
347 emit(BRW_OPCODE_LINE
, this->result
, src0
, src1
);
352 fs_visitor::try_emit_mad(ir_expression
*ir
)
354 /* 3-src instructions were introduced in gen6. */
358 /* MAD can only handle floating-point data. */
359 if (ir
->type
!= glsl_type::float_type
)
362 ir_rvalue
*nonmul
= ir
->operands
[1];
363 ir_expression
*mul
= ir
->operands
[0]->as_expression();
365 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
366 nonmul
= ir
->operands
[0];
367 mul
= ir
->operands
[1]->as_expression();
369 if (!mul
|| mul
->operation
!= ir_binop_mul
)
373 if (nonmul
->as_constant() ||
374 mul
->operands
[0]->as_constant() ||
375 mul
->operands
[1]->as_constant())
378 nonmul
->accept(this);
379 fs_reg src0
= this->result
;
381 mul
->operands
[0]->accept(this);
382 fs_reg src1
= this->result
;
384 mul
->operands
[1]->accept(this);
385 fs_reg src2
= this->result
;
387 this->result
= fs_reg(this, ir
->type
);
388 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
394 pack_pixel_offset(float x
)
396 /* Clamp upper end of the range to +7/16. See explanation in non-constant
397 * offset case below. */
398 int n
= MIN2((int)(x
* 16), 7);
403 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
405 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
406 * 8 channels at a time, same as the barycentric coords presented in
407 * the FS payload. this requires a bit of extra work to support.
409 no16("interpolate_at_* not yet supported in SIMD16 mode.");
411 assert(stage
== MESA_SHADER_FRAGMENT
);
412 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
414 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
415 ir_swizzle
* swiz
= NULL
;
417 /* the api does not allow a swizzle here, but the varying packing code
418 * may have pushed one into here.
420 swiz
= ir
->operands
[0]->as_swizzle();
422 deref
= swiz
->val
->as_dereference();
425 ir_variable
* var
= deref
->variable_referenced();
428 /* 1. collect interpolation factors */
430 fs_reg dst_x
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
431 fs_reg dst_y
= offset(dst_x
, 1);
433 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
434 * even when there is no payload. in the per-slot offset case, we'll replace this with
435 * the proper source data. */
436 fs_reg src
= fs_reg(this, glsl_type::float_type
);
437 int mlen
= 1; /* one reg unless overriden */
438 int reg_width
= dispatch_width
/ 8;
441 switch (ir
->operation
) {
442 case ir_unop_interpolate_at_centroid
:
443 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
446 case ir_binop_interpolate_at_sample
: {
447 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
448 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
450 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
451 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
455 case ir_binop_interpolate_at_offset
: {
456 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
458 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
459 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
460 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
463 /* pack the operands: hw wants offsets as 4 bit signed ints */
464 ir
->operands
[1]->accept(this);
465 src
= fs_reg(this, glsl_type::ivec2_type
);
467 for (int i
= 0; i
< 2; i
++) {
468 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
469 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
470 emit(MOV(src2
, temp
)); /* float to int */
472 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
473 * that we support a maximum offset of +0.5, which isn't representable
474 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
475 * which is the opposite of what the shader author wanted.
477 * This is legal due to ARB_gpu_shader5's quantization rules:
479 * "Not all values of <offset> may be supported; x and y offsets may
480 * be rounded to fixed-point values with the number of fraction bits
481 * given by the implementation-dependent constant
482 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
485 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
486 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
488 src2
= offset(src2
, 1);
489 this->result
= offset(this->result
, 1);
492 mlen
= 2 * reg_width
;
493 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
500 unreachable("not reached");
504 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
505 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
506 INTERP_QUALIFIER_NOPERSPECTIVE
;
508 /* 2. emit linterp */
510 fs_reg
res(this, ir
->type
);
513 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
514 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
515 emit(FS_OPCODE_LINTERP
, res
,
517 fs_reg(interp_reg(var
->data
.location
, ch
)));
518 res
= offset(res
, 1);
523 fs_visitor::visit(ir_expression
*ir
)
525 unsigned int operand
;
528 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
530 assert(ir
->get_num_operands() <= 3);
532 if (try_emit_saturate(ir
))
535 /* Deal with the real oddball stuff first */
536 switch (ir
->operation
) {
538 if (brw
->gen
<= 5 && try_emit_line(ir
))
540 if (try_emit_mad(ir
))
545 ir
->operands
[1]->accept(this);
546 op
[1] = this->result
;
547 ir
->operands
[2]->accept(this);
548 op
[2] = this->result
;
550 emit_bool_to_cond_code(ir
->operands
[0]);
552 this->result
= fs_reg(this, ir
->type
);
553 inst
= emit(SEL(this->result
, op
[1], op
[2]));
554 inst
->predicate
= BRW_PREDICATE_NORMAL
;
557 case ir_unop_interpolate_at_centroid
:
558 case ir_binop_interpolate_at_offset
:
559 case ir_binop_interpolate_at_sample
:
560 emit_interpolate_expression(ir
);
567 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
568 ir
->operands
[operand
]->accept(this);
569 if (this->result
.file
== BAD_FILE
) {
570 fail("Failed to get tree for expression operand:\n");
571 ir
->operands
[operand
]->fprint(stderr
);
572 fprintf(stderr
, "\n");
574 assert(this->result
.file
== GRF
|| this->result
.file
== UNIFORM
);
575 op
[operand
] = this->result
;
577 /* Matrix expression operands should have been broken down to vector
578 * operations already.
580 assert(!ir
->operands
[operand
]->type
->is_matrix());
581 /* And then those vector operands should have been broken down to scalar.
583 assert(!ir
->operands
[operand
]->type
->is_vector());
586 /* Storage for our result. If our result goes into an assignment, it will
587 * just get copy-propagated out, so no worries.
589 this->result
= fs_reg(this, ir
->type
);
591 switch (ir
->operation
) {
592 case ir_unop_logic_not
:
593 emit(NOT(this->result
, op
[0]));
596 op
[0].negate
= !op
[0].negate
;
597 emit(MOV(this->result
, op
[0]));
601 op
[0].negate
= false;
602 emit(MOV(this->result
, op
[0]));
605 if (ir
->type
->is_float()) {
606 /* AND(val, 0x80000000) gives the sign bit.
608 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
611 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
613 op
[0].type
= BRW_REGISTER_TYPE_UD
;
614 this->result
.type
= BRW_REGISTER_TYPE_UD
;
615 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
617 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
618 inst
->predicate
= BRW_PREDICATE_NORMAL
;
620 this->result
.type
= BRW_REGISTER_TYPE_F
;
622 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
623 * -> non-negative val generates 0x00000000.
624 * Predicated OR sets 1 if val is positive.
626 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
628 emit(ASR(this->result
, op
[0], fs_reg(31)));
630 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
631 inst
->predicate
= BRW_PREDICATE_NORMAL
;
635 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
639 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
642 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
646 unreachable("not reached: should be handled by ir_explog_to_explog2");
648 case ir_unop_sin_reduced
:
649 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
652 case ir_unop_cos_reduced
:
653 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
657 /* Select one of the two opcodes based on the glHint value. */
658 if (fs_key
->high_quality_derivatives
)
659 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
661 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
664 case ir_unop_dFdx_coarse
:
665 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
668 case ir_unop_dFdx_fine
:
669 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
673 /* Select one of the two opcodes based on the glHint value. */
674 if (fs_key
->high_quality_derivatives
)
675 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
677 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
680 case ir_unop_dFdy_coarse
:
681 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
684 case ir_unop_dFdy_fine
:
685 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
689 emit(ADD(this->result
, op
[0], op
[1]));
692 unreachable("not reached: should be handled by ir_sub_to_add_neg");
695 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
696 /* For integer multiplication, the MUL uses the low 16 bits
697 * of one of the operands (src0 on gen6, src1 on gen7). The
698 * MACH accumulates in the contribution of the upper 16 bits
701 if (ir
->operands
[0]->is_uint16_constant()) {
703 emit(MUL(this->result
, op
[0], op
[1]));
705 emit(MUL(this->result
, op
[1], op
[0]));
706 } else if (ir
->operands
[1]->is_uint16_constant()) {
708 emit(MUL(this->result
, op
[1], op
[0]));
710 emit(MUL(this->result
, op
[0], op
[1]));
713 no16("SIMD16 explicit accumulator operands unsupported\n");
715 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
718 emit(MUL(acc
, op
[0], op
[1]));
719 emit(MACH(reg_null_d
, op
[0], op
[1]));
720 emit(MOV(this->result
, fs_reg(acc
)));
723 emit(MUL(this->result
, op
[0], op
[1]));
726 case ir_binop_imul_high
: {
728 no16("SIMD16 explicit accumulator operands unsupported\n");
730 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
733 fs_inst
*mul
= emit(MUL(acc
, op
[0], op
[1]));
734 emit(MACH(this->result
, op
[0], op
[1]));
736 /* Until Gen8, integer multiplies read 32-bits from one source, and
737 * 16-bits from the other, and relying on the MACH instruction to
738 * generate the high bits of the result.
740 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
741 * but in order to do a 64x64-bit multiply we have to simulate the
742 * previous behavior and then use a MACH instruction.
744 * FINISHME: Don't use source modifiers on src1.
747 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
748 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
749 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
750 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
752 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
759 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
760 assert(ir
->type
->is_integer());
761 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
763 case ir_binop_carry
: {
765 no16("SIMD16 explicit accumulator operands unsupported\n");
767 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
768 BRW_REGISTER_TYPE_UD
);
770 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
771 emit(MOV(this->result
, fs_reg(acc
)));
774 case ir_binop_borrow
: {
776 no16("SIMD16 explicit accumulator operands unsupported\n");
778 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
779 BRW_REGISTER_TYPE_UD
);
781 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
782 emit(MOV(this->result
, fs_reg(acc
)));
786 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
787 assert(ir
->type
->is_integer());
788 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
792 case ir_binop_greater
:
793 case ir_binop_lequal
:
794 case ir_binop_gequal
:
796 case ir_binop_all_equal
:
797 case ir_binop_nequal
:
798 case ir_binop_any_nequal
:
800 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
801 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
804 emit(CMP(this->result
, op
[0], op
[1],
805 brw_conditional_for_comparison(ir
->operation
)));
808 case ir_binop_logic_xor
:
809 emit(XOR(this->result
, op
[0], op
[1]));
812 case ir_binop_logic_or
:
813 emit(OR(this->result
, op
[0], op
[1]));
816 case ir_binop_logic_and
:
817 emit(AND(this->result
, op
[0], op
[1]));
822 unreachable("not reached: should be handled by brw_fs_channel_expressions");
825 unreachable("not reached: should be handled by lower_noise");
827 case ir_quadop_vector
:
828 unreachable("not reached: should be handled by lower_quadop_vector");
830 case ir_binop_vector_extract
:
831 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
833 case ir_triop_vector_insert
:
834 unreachable("not reached: should be handled by lower_vector_insert()");
837 unreachable("not reached: should be handled by ldexp_to_arith()");
840 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
844 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
847 case ir_unop_bitcast_i2f
:
848 case ir_unop_bitcast_u2f
:
849 op
[0].type
= BRW_REGISTER_TYPE_F
;
850 this->result
= op
[0];
853 case ir_unop_bitcast_f2u
:
854 op
[0].type
= BRW_REGISTER_TYPE_UD
;
855 this->result
= op
[0];
858 case ir_unop_bitcast_f2i
:
859 op
[0].type
= BRW_REGISTER_TYPE_D
;
860 this->result
= op
[0];
866 emit(MOV(this->result
, op
[0]));
870 emit(AND(this->result
, op
[0], fs_reg(1)));
874 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
876 op
[0].type
= BRW_REGISTER_TYPE_D
;
877 this->result
.type
= BRW_REGISTER_TYPE_D
;
878 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
879 this->result
.type
= BRW_REGISTER_TYPE_F
;
883 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
886 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
890 emit(RNDZ(this->result
, op
[0]));
893 op
[0].negate
= !op
[0].negate
;
894 emit(RNDD(this->result
, op
[0]));
895 this->result
.negate
= true;
898 emit(RNDD(this->result
, op
[0]));
901 emit(FRC(this->result
, op
[0]));
903 case ir_unop_round_even
:
904 emit(RNDE(this->result
, op
[0]));
909 resolve_ud_negate(&op
[0]);
910 resolve_ud_negate(&op
[1]);
911 emit_minmax(ir
->operation
== ir_binop_min
?
912 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
913 this->result
, op
[0], op
[1]);
915 case ir_unop_pack_snorm_2x16
:
916 case ir_unop_pack_snorm_4x8
:
917 case ir_unop_pack_unorm_2x16
:
918 case ir_unop_pack_unorm_4x8
:
919 case ir_unop_unpack_snorm_2x16
:
920 case ir_unop_unpack_snorm_4x8
:
921 case ir_unop_unpack_unorm_2x16
:
922 case ir_unop_unpack_unorm_4x8
:
923 case ir_unop_unpack_half_2x16
:
924 case ir_unop_pack_half_2x16
:
925 unreachable("not reached: should be handled by lower_packing_builtins");
926 case ir_unop_unpack_half_2x16_split_x
:
927 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
929 case ir_unop_unpack_half_2x16_split_y
:
930 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
933 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
936 case ir_unop_bitfield_reverse
:
937 emit(BFREV(this->result
, op
[0]));
939 case ir_unop_bit_count
:
940 emit(CBIT(this->result
, op
[0]));
942 case ir_unop_find_msb
:
943 temp
= fs_reg(this, glsl_type::uint_type
);
944 emit(FBH(temp
, op
[0]));
946 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
947 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
948 * subtract the result from 31 to convert the MSB count into an LSB count.
951 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
952 emit(MOV(this->result
, temp
));
953 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
956 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
957 inst
->predicate
= BRW_PREDICATE_NORMAL
;
959 case ir_unop_find_lsb
:
960 emit(FBL(this->result
, op
[0]));
962 case ir_unop_saturate
:
963 inst
= emit(MOV(this->result
, op
[0]));
964 inst
->saturate
= true;
966 case ir_triop_bitfield_extract
:
967 /* Note that the instruction's argument order is reversed from GLSL
970 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
973 emit(BFI1(this->result
, op
[0], op
[1]));
976 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
978 case ir_quadop_bitfield_insert
:
979 unreachable("not reached: should be handled by "
980 "lower_instructions::bitfield_insert_to_bfm_bfi");
982 case ir_unop_bit_not
:
983 emit(NOT(this->result
, op
[0]));
985 case ir_binop_bit_and
:
986 emit(AND(this->result
, op
[0], op
[1]));
988 case ir_binop_bit_xor
:
989 emit(XOR(this->result
, op
[0], op
[1]));
991 case ir_binop_bit_or
:
992 emit(OR(this->result
, op
[0], op
[1]));
995 case ir_binop_lshift
:
996 emit(SHL(this->result
, op
[0], op
[1]));
999 case ir_binop_rshift
:
1000 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1001 emit(ASR(this->result
, op
[0], op
[1]));
1003 emit(SHR(this->result
, op
[0], op
[1]));
1005 case ir_binop_pack_half_2x16_split
:
1006 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
1008 case ir_binop_ubo_load
: {
1009 /* This IR node takes a constant uniform block and a constant or
1010 * variable byte offset within the block and loads a vector from that.
1012 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1013 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
1016 if (const_uniform_block
) {
1017 /* The block index is a constant, so just emit the binding table entry
1020 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1021 const_uniform_block
->value
.u
[0]);
1023 /* The block index is not a constant. Evaluate the index expression
1024 * per-channel and add the base UBO index; the generator will select
1025 * a value from any live channel.
1027 surf_index
= fs_reg(this, glsl_type::uint_type
);
1028 emit(ADD(surf_index
, op
[0],
1029 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1030 ->force_writemask_all
= true;
1032 /* Assume this may touch any UBO. It would be nice to provide
1033 * a tighter bound, but the array information is already lowered away.
1035 brw_mark_surface_used(prog_data
,
1036 stage_prog_data
->binding_table
.ubo_start
+
1037 shader_prog
->NumUniformBlocks
- 1);
1041 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
1042 packed_consts
.type
= result
.type
;
1044 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
1045 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
1046 packed_consts
, surf_index
, const_offset_reg
));
1048 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1049 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
1051 /* The std140 packing rules don't allow vectors to cross 16-byte
1052 * boundaries, and a reg is 32 bytes.
1054 assert(packed_consts
.subreg_offset
< 32);
1056 /* UBO bools are any nonzero value. We consider bools to be
1057 * values with the low bit set to 1. Convert them using CMP.
1059 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1060 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
1062 emit(MOV(result
, packed_consts
));
1065 result
= offset(result
, 1);
1068 /* Turn the byte offset into a dword offset. */
1069 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
1070 emit(SHR(base_offset
, op
[1], fs_reg(2)));
1072 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1073 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
1076 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
1077 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
1079 result
= offset(result
, 1);
1083 result
.reg_offset
= 0;
1088 /* Note that the instruction's argument order is reversed from GLSL
1091 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
1095 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1099 case ir_unop_interpolate_at_centroid
:
1100 case ir_binop_interpolate_at_offset
:
1101 case ir_binop_interpolate_at_sample
:
1102 unreachable("already handled above");
1108 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1109 const glsl_type
*type
, bool predicated
)
1111 switch (type
->base_type
) {
1112 case GLSL_TYPE_FLOAT
:
1113 case GLSL_TYPE_UINT
:
1115 case GLSL_TYPE_BOOL
:
1116 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1117 l
.type
= brw_type_for_base_type(type
);
1118 r
.type
= brw_type_for_base_type(type
);
1120 if (predicated
|| !l
.equals(r
)) {
1121 fs_inst
*inst
= emit(MOV(l
, r
));
1122 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1129 case GLSL_TYPE_ARRAY
:
1130 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1131 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1135 case GLSL_TYPE_STRUCT
:
1136 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1137 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1142 case GLSL_TYPE_SAMPLER
:
1143 case GLSL_TYPE_IMAGE
:
1144 case GLSL_TYPE_ATOMIC_UINT
:
1147 case GLSL_TYPE_VOID
:
1148 case GLSL_TYPE_ERROR
:
1149 case GLSL_TYPE_INTERFACE
:
1150 unreachable("not reached");
1154 /* If the RHS processing resulted in an instruction generating a
1155 * temporary value, and it would be easy to rewrite the instruction to
1156 * generate its result right into the LHS instead, do so. This ends
1157 * up reliably removing instructions where it can be tricky to do so
1158 * later without real UD chain information.
1161 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1164 fs_inst
*pre_rhs_inst
,
1165 fs_inst
*last_rhs_inst
)
1167 /* Only attempt if we're doing a direct assignment. */
1168 if (ir
->condition
||
1169 !(ir
->lhs
->type
->is_scalar() ||
1170 (ir
->lhs
->type
->is_vector() &&
1171 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1174 /* Make sure the last instruction generated our source reg. */
1175 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1181 /* If last_rhs_inst wrote a different number of components than our LHS,
1182 * we can't safely rewrite it.
1184 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
1187 /* Success! Rewrite the instruction. */
1194 fs_visitor::visit(ir_assignment
*ir
)
1199 /* FINISHME: arrays on the lhs */
1200 ir
->lhs
->accept(this);
1203 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1205 ir
->rhs
->accept(this);
1208 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1210 assert(l
.file
!= BAD_FILE
);
1211 assert(r
.file
!= BAD_FILE
);
1213 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1216 if (ir
->condition
) {
1217 emit_bool_to_cond_code(ir
->condition
);
1220 if (ir
->lhs
->type
->is_scalar() ||
1221 ir
->lhs
->type
->is_vector()) {
1222 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1223 if (ir
->write_mask
& (1 << i
)) {
1224 inst
= emit(MOV(l
, r
));
1226 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1232 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1237 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
1238 fs_reg coordinate
, int coord_components
,
1240 fs_reg lod
, fs_reg dPdy
, int grad_components
,
1245 bool simd16
= false;
1251 if (shadow_c
.file
!= BAD_FILE
) {
1252 for (int i
= 0; i
< coord_components
; i
++) {
1253 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1254 coordinate
= offset(coordinate
, 1);
1257 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1258 * the unused slots must be zeroed.
1260 for (int i
= coord_components
; i
< 3; i
++) {
1261 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1266 /* There's no plain shadow compare message, so we use shadow
1267 * compare with a bias of 0.0.
1269 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1271 } else if (op
== ir_txb
|| op
== ir_txl
) {
1272 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1275 unreachable("Should not get here.");
1278 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1280 } else if (op
== ir_tex
) {
1281 for (int i
= 0; i
< coord_components
; i
++) {
1282 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1283 coordinate
= offset(coordinate
, 1);
1285 /* zero the others. */
1286 for (int i
= coord_components
; i
<3; i
++) {
1287 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1289 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1291 } else if (op
== ir_txd
) {
1294 for (int i
= 0; i
< coord_components
; i
++) {
1295 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1296 coordinate
= offset(coordinate
, 1);
1298 /* the slots for u and v are always present, but r is optional */
1299 mlen
+= MAX2(coord_components
, 2);
1302 * dPdx = dudx, dvdx, drdx
1303 * dPdy = dudy, dvdy, drdy
1305 * 1-arg: Does not exist.
1307 * 2-arg: dudx dvdx dudy dvdy
1308 * dPdx.x dPdx.y dPdy.x dPdy.y
1311 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1312 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1313 * m5 m6 m7 m8 m9 m10
1315 for (int i
= 0; i
< grad_components
; i
++) {
1316 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1317 dPdx
= offset(dPdx
, 1);
1319 mlen
+= MAX2(grad_components
, 2);
1321 for (int i
= 0; i
< grad_components
; i
++) {
1322 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1323 dPdy
= offset(dPdy
, 1);
1325 mlen
+= MAX2(grad_components
, 2);
1326 } else if (op
== ir_txs
) {
1327 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1329 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1332 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1333 * instructions. We'll need to do SIMD16 here.
1336 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
1338 for (int i
= 0; i
< coord_components
; i
++) {
1339 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1341 coordinate
= offset(coordinate
, 1);
1344 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1345 * be necessary for TXF (ld), but seems wise to do for all messages.
1347 for (int i
= coord_components
; i
< 3; i
++) {
1348 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1351 /* lod/bias appears after u/v/r. */
1354 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1357 /* The unused upper half. */
1362 /* Now, since we're doing simd16, the return is 2 interleaved
1363 * vec4s where the odd-indexed ones are junk. We'll need to move
1364 * this weirdness around to the expected layout.
1367 dst
= fs_reg(GRF
, virtual_grf_alloc(8), orig_dst
.type
);
1372 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1373 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1374 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1375 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1376 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1377 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1379 unreachable("not reached");
1382 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1383 inst
->base_mrf
= base_mrf
;
1385 inst
->header_present
= true;
1386 inst
->regs_written
= simd16
? 8 : 4;
1389 for (int i
= 0; i
< 4; i
++) {
1390 emit(MOV(orig_dst
, dst
));
1391 orig_dst
= offset(orig_dst
, 1);
1392 dst
= offset(dst
, 2);
1399 /* gen5's sampler has slots for u, v, r, array index, then optional
1400 * parameters like shadow comparitor or LOD bias. If optional
1401 * parameters aren't present, those base slots are optional and don't
1402 * need to be included in the message.
1404 * We don't fill in the unnecessary slots regardless, which may look
1405 * surprising in the disassembly.
1408 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
1409 fs_reg coordinate
, int vector_elements
,
1411 fs_reg lod
, fs_reg lod2
, int grad_components
,
1412 fs_reg sample_index
, uint32_t sampler
,
1415 int reg_width
= dispatch_width
/ 8;
1416 bool header_present
= false;
1418 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1419 fs_reg msg_coords
= message
;
1422 /* The offsets set up by the ir_texture visitor are in the
1423 * m1 header, so we can't go headerless.
1425 header_present
= true;
1429 for (int i
= 0; i
< vector_elements
; i
++) {
1430 emit(MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
));
1431 coordinate
= offset(coordinate
, 1);
1433 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
1434 fs_reg msg_lod
= offset(msg_coords
, 4);
1436 if (shadow_c
.file
!= BAD_FILE
) {
1437 fs_reg msg_shadow
= msg_lod
;
1438 emit(MOV(msg_shadow
, shadow_c
));
1439 msg_lod
= offset(msg_shadow
, 1);
1446 opcode
= SHADER_OPCODE_TEX
;
1449 emit(MOV(msg_lod
, lod
));
1450 msg_end
= offset(msg_lod
, 1);
1452 opcode
= FS_OPCODE_TXB
;
1455 emit(MOV(msg_lod
, lod
));
1456 msg_end
= offset(msg_lod
, 1);
1458 opcode
= SHADER_OPCODE_TXL
;
1463 * dPdx = dudx, dvdx, drdx
1464 * dPdy = dudy, dvdy, drdy
1466 * Load up these values:
1467 * - dudx dudy dvdx dvdy drdx drdy
1468 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1471 for (int i
= 0; i
< grad_components
; i
++) {
1472 emit(MOV(msg_end
, lod
));
1473 lod
= offset(lod
, 1);
1474 msg_end
= offset(msg_end
, 1);
1476 emit(MOV(msg_end
, lod2
));
1477 lod2
= offset(lod2
, 1);
1478 msg_end
= offset(msg_end
, 1);
1481 opcode
= SHADER_OPCODE_TXD
;
1485 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
1486 emit(MOV(msg_lod
, lod
));
1487 msg_end
= offset(msg_lod
, 1);
1489 opcode
= SHADER_OPCODE_TXS
;
1491 case ir_query_levels
:
1493 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1494 msg_end
= offset(msg_lod
, 1);
1496 opcode
= SHADER_OPCODE_TXS
;
1499 msg_lod
= offset(msg_coords
, 3);
1500 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
));
1501 msg_end
= offset(msg_lod
, 1);
1503 opcode
= SHADER_OPCODE_TXF
;
1506 msg_lod
= offset(msg_coords
, 3);
1508 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1510 emit(MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
));
1511 msg_end
= offset(msg_lod
, 2);
1513 opcode
= SHADER_OPCODE_TXF_CMS
;
1516 opcode
= SHADER_OPCODE_LOD
;
1519 opcode
= SHADER_OPCODE_TG4
;
1522 unreachable("not reached");
1525 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1526 inst
->base_mrf
= message
.reg
;
1527 inst
->mlen
= msg_end
.reg
- message
.reg
;
1528 inst
->header_present
= header_present
;
1529 inst
->regs_written
= 4 * reg_width
;
1531 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1532 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1533 " disallowed by hardware\n");
1540 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1542 if (brw
->gen
< 8 && !brw
->is_haswell
)
1545 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1549 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
1550 fs_reg coordinate
, int coord_components
,
1552 fs_reg lod
, fs_reg lod2
, int grad_components
,
1553 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
1554 fs_reg offset_value
)
1556 int reg_width
= dispatch_width
/ 8;
1557 bool header_present
= false;
1559 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1560 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1561 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1565 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
1566 is_high_sampler(brw
, sampler
)) {
1567 /* For general texture offsets (no txf workaround), we need a header to
1568 * put them in. Note that for SIMD16 we're making space for two actual
1569 * hardware registers here, so the emit will have to fix up for this.
1571 * * ir4_tg4 needs to place its channel select in the header,
1572 * for interaction with ARB_texture_swizzle
1574 * The sampler index is only 4-bits, so for larger sampler numbers we
1575 * need to offset the Sampler State Pointer in the header.
1577 header_present
= true;
1578 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
1582 if (shadow_c
.file
!= BAD_FILE
) {
1583 emit(MOV(sources
[length
], shadow_c
));
1587 bool has_nonconstant_offset
=
1588 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
1589 bool coordinate_done
= false;
1591 /* Set up the LOD info */
1597 emit(MOV(sources
[length
], lod
));
1601 emit(MOV(sources
[length
], lod
));
1605 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1607 /* Load dPdx and the coordinate together:
1608 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1610 for (int i
= 0; i
< coord_components
; i
++) {
1611 emit(MOV(sources
[length
], coordinate
));
1612 coordinate
= offset(coordinate
, 1);
1615 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1616 * only derivatives for (u, v, r).
1618 if (i
< grad_components
) {
1619 emit(MOV(sources
[length
], lod
));
1620 lod
= offset(lod
, 1);
1623 emit(MOV(sources
[length
], lod2
));
1624 lod2
= offset(lod2
, 1);
1629 coordinate_done
= true;
1633 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1636 case ir_query_levels
:
1637 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1641 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1642 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1643 coordinate
= offset(coordinate
, 1);
1646 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1649 for (int i
= 1; i
< coord_components
; i
++) {
1650 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1651 coordinate
= offset(coordinate
, 1);
1655 coordinate_done
= true;
1658 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1661 /* data from the multisample control surface */
1662 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1665 /* there is no offsetting for this message; just copy in the integer
1666 * texture coordinates
1668 for (int i
= 0; i
< coord_components
; i
++) {
1669 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1670 coordinate
= offset(coordinate
, 1);
1674 coordinate_done
= true;
1677 if (has_nonconstant_offset
) {
1678 if (shadow_c
.file
!= BAD_FILE
)
1679 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1681 /* More crazy intermixing */
1682 for (int i
= 0; i
< 2; i
++) { /* u, v */
1683 emit(MOV(sources
[length
], coordinate
));
1684 coordinate
= offset(coordinate
, 1);
1688 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1689 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1690 offset_value
= offset(offset_value
, 1);
1694 if (coord_components
== 3) { /* r if present */
1695 emit(MOV(sources
[length
], coordinate
));
1696 coordinate
= offset(coordinate
, 1);
1700 coordinate_done
= true;
1705 /* Set up the coordinate (except for cases where it was done above) */
1706 if (!coordinate_done
) {
1707 for (int i
= 0; i
< coord_components
; i
++) {
1708 emit(MOV(sources
[length
], coordinate
));
1709 coordinate
= offset(coordinate
, 1);
1716 mlen
= length
* reg_width
- header_present
;
1718 mlen
= length
* reg_width
;
1720 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
1721 BRW_REGISTER_TYPE_F
);
1722 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1724 /* Generate the SEND */
1727 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1728 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1729 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1730 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1731 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1732 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1733 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1734 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1735 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1737 if (has_nonconstant_offset
)
1738 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1740 opcode
= SHADER_OPCODE_TG4
;
1743 unreachable("not reached");
1745 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1746 inst
->base_mrf
= -1;
1748 inst
->header_present
= header_present
;
1749 inst
->regs_written
= 4 * reg_width
;
1751 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1752 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1753 " disallowed by hardware\n");
1759 static struct brw_sampler_prog_key_data
*
1760 get_tex(gl_shader_stage stage
, const void *key
)
1763 case MESA_SHADER_FRAGMENT
:
1764 return &((brw_wm_prog_key
*) key
)->tex
;
1766 unreachable("unhandled shader stage");
1771 fs_visitor::rescale_texcoord(fs_reg coordinate
, const glsl_type
*coord_type
,
1772 bool is_rect
, uint32_t sampler
, int texunit
)
1774 fs_inst
*inst
= NULL
;
1775 bool needs_gl_clamp
= true;
1776 fs_reg scale_x
, scale_y
;
1777 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
1779 /* The 965 requires the EU to do the normalization of GL rectangle
1780 * texture coordinates. We use the program parameter state
1781 * tracking to get the scaling factor.
1785 (brw
->gen
>= 6 && (tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
1786 tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
1787 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1788 int tokens
[STATE_LENGTH
] = {
1790 STATE_TEXRECT_SCALE
,
1796 no16("rectangle scale uniform setup not supported on SIMD16\n");
1797 if (dispatch_width
== 16) {
1801 GLuint index
= _mesa_add_state_reference(params
,
1802 (gl_state_index
*)tokens
);
1803 /* Try to find existing copies of the texrect scale uniforms. */
1804 for (unsigned i
= 0; i
< uniforms
; i
++) {
1805 if (stage_prog_data
->param
[i
] ==
1806 &prog
->Parameters
->ParameterValues
[index
][0]) {
1807 scale_x
= fs_reg(UNIFORM
, i
);
1808 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1813 /* If we didn't already set them up, do so now. */
1814 if (scale_x
.file
== BAD_FILE
) {
1815 scale_x
= fs_reg(UNIFORM
, uniforms
);
1816 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1818 stage_prog_data
->param
[uniforms
++] =
1819 &prog
->Parameters
->ParameterValues
[index
][0];
1820 stage_prog_data
->param
[uniforms
++] =
1821 &prog
->Parameters
->ParameterValues
[index
][1];
1825 /* The 965 requires the EU to do the normalization of GL rectangle
1826 * texture coordinates. We use the program parameter state
1827 * tracking to get the scaling factor.
1829 if (brw
->gen
< 6 && is_rect
) {
1830 fs_reg dst
= fs_reg(this, coord_type
);
1831 fs_reg src
= coordinate
;
1834 emit(MUL(dst
, src
, scale_x
));
1835 dst
= offset(dst
, 1);
1836 src
= offset(src
, 1);
1837 emit(MUL(dst
, src
, scale_y
));
1838 } else if (is_rect
) {
1839 /* On gen6+, the sampler handles the rectangle coordinates
1840 * natively, without needing rescaling. But that means we have
1841 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1842 * not [0, 1] like the default case below.
1844 needs_gl_clamp
= false;
1846 for (int i
= 0; i
< 2; i
++) {
1847 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1848 fs_reg chan
= coordinate
;
1849 chan
= offset(chan
, i
);
1851 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1852 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1854 /* Our parameter comes in as 1.0/width or 1.0/height,
1855 * because that's what people normally want for doing
1856 * texture rectangle handling. We need width or height
1857 * for clamping, but we don't care enough to make a new
1858 * parameter type, so just invert back.
1860 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1861 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1862 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1864 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1865 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1870 if (coord_type
&& needs_gl_clamp
) {
1871 for (unsigned int i
= 0; i
< MIN2(coord_type
->vector_elements
, 3); i
++) {
1872 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1873 fs_reg chan
= coordinate
;
1874 chan
= offset(chan
, i
);
1876 fs_inst
*inst
= emit(MOV(chan
, chan
));
1877 inst
->saturate
= true;
1884 /* Sample from the MCS surface attached to this multisample texture. */
1886 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
1888 int reg_width
= dispatch_width
/ 8;
1889 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(components
* reg_width
),
1890 BRW_REGISTER_TYPE_F
);
1891 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1892 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
1894 /* parameters are: u, v, r; missing parameters are treated as zero */
1895 for (int i
= 0; i
< components
; i
++) {
1896 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1897 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1898 coordinate
= offset(coordinate
, 1);
1901 emit(LOAD_PAYLOAD(payload
, sources
, components
));
1903 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
1904 inst
->base_mrf
= -1;
1905 inst
->mlen
= components
* reg_width
;
1906 inst
->header_present
= false;
1907 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
1908 * response, but the sampler always
1916 fs_visitor::emit_texture(ir_texture_opcode op
,
1917 const glsl_type
*dest_type
,
1918 fs_reg coordinate
, const struct glsl_type
*coord_type
,
1920 fs_reg lod
, fs_reg lod2
, int grad_components
,
1921 fs_reg sample_index
,
1922 fs_reg offset_value
, unsigned offset_components
,
1924 int gather_component
,
1928 fs_reg sampler_reg
, int texunit
)
1930 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
1931 fs_inst
*inst
= NULL
;
1934 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1935 * emitting anything other than setting up the constant result.
1937 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], gather_component
);
1938 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1940 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1943 for (int i
=0; i
<4; i
++) {
1944 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1945 res
= offset(res
, 1);
1951 if (coordinate
.file
!= BAD_FILE
) {
1952 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
1953 * samplers. This should only be a problem with GL_CLAMP on Gen7.
1955 coordinate
= rescale_texcoord(coordinate
, coord_type
, is_rect
,
1959 /* Writemasking doesn't eliminate channels on SIMD8 texture
1960 * samples, so don't worry about them.
1962 fs_reg
dst(this, glsl_type::get_instance(dest_type
->base_type
, 4, 1));
1964 int coord_components
= coord_type
? coord_type
->vector_elements
: 0;
1966 if (brw
->gen
>= 7) {
1967 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
1968 shadow_c
, lod
, lod2
, grad_components
,
1969 sample_index
, mcs
, sampler_reg
,
1971 } else if (brw
->gen
>= 5) {
1972 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
1973 shadow_c
, lod
, lod2
, grad_components
,
1974 sample_index
, sampler
,
1975 offset_value
.file
!= BAD_FILE
);
1977 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
1978 shadow_c
, lod
, lod2
, grad_components
,
1982 if (shadow_c
.file
!= BAD_FILE
)
1983 inst
->shadow_compare
= true;
1985 if (offset_value
.file
== IMM
)
1986 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
1990 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
1993 emit_gen6_gather_wa(tex
->gen6_gather_wa
[sampler
], dst
);
1996 /* fixup #layers for cube map arrays */
1997 if (op
== ir_txs
&& is_cube_array
) {
1998 fs_reg depth
= offset(dst
, 2);
1999 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
2000 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
2002 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
2003 int components
= inst
->regs_written
/ (dst
.width
/ 8);
2004 for (int i
= 0; i
< components
; i
++) {
2006 fixed_payload
[i
] = fixed_depth
;
2008 fixed_payload
[i
] = offset(dst
, i
);
2011 emit(LOAD_PAYLOAD(dst
, fixed_payload
, components
));
2014 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
2018 fs_visitor::visit(ir_texture
*ir
)
2020 const struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2022 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2024 ir_rvalue
*nonconst_sampler_index
=
2025 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2027 /* Handle non-constant sampler array indexing */
2029 if (nonconst_sampler_index
) {
2030 /* The highest sampler which may be used by this operation is
2031 * the last element of the array. Mark it here, because the generator
2032 * doesn't have enough information to determine the bound.
2034 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2035 ->array
->type
->array_size();
2037 uint32_t max_used
= sampler
+ array_size
- 1;
2038 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2039 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2041 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2044 brw_mark_surface_used(prog_data
, max_used
);
2046 /* Emit code to evaluate the actual indexing expression */
2047 nonconst_sampler_index
->accept(this);
2048 fs_reg
temp(this, glsl_type::uint_type
);
2049 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
2050 ->force_writemask_all
= true;
2053 /* Single sampler, or constant array index; the indexing expression
2054 * is just an immediate.
2056 sampler_reg
= fs_reg(sampler
);
2059 /* FINISHME: We're failing to recompile our programs when the sampler is
2060 * updated. This only matters for the texture rectangle scale parameters
2061 * (pre-gen6, or gen6+ with GL_CLAMP).
2063 int texunit
= prog
->SamplerUnits
[sampler
];
2065 /* Should be lowered by do_lower_texture_projection */
2066 assert(!ir
->projector
);
2068 /* Should be lowered */
2069 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2071 /* Generate code to compute all the subexpression trees. This has to be
2072 * done before loading any values into MRFs for the sampler message since
2073 * generating these values may involve SEND messages that need the MRFs.
2076 const glsl_type
*coord_type
= NULL
;
2077 if (ir
->coordinate
) {
2078 coord_type
= ir
->coordinate
->type
;
2079 ir
->coordinate
->accept(this);
2080 coordinate
= this->result
;
2083 fs_reg shadow_comparitor
;
2084 if (ir
->shadow_comparitor
) {
2085 ir
->shadow_comparitor
->accept(this);
2086 shadow_comparitor
= this->result
;
2089 fs_reg offset_value
;
2090 int offset_components
= 0;
2092 ir_constant
*const_offset
= ir
->offset
->as_constant();
2094 /* Store the header bitfield in an IMM register. This allows us to
2095 * use offset_value.file to distinguish between no offset, a constant
2096 * offset, and a non-constant offset.
2099 fs_reg(brw_texture_offset(ctx
, const_offset
->value
.i
,
2100 const_offset
->type
->vector_elements
));
2102 ir
->offset
->accept(this);
2103 offset_value
= this->result
;
2105 offset_components
= ir
->offset
->type
->vector_elements
;
2108 fs_reg lod
, lod2
, sample_index
, mcs
;
2109 int grad_components
= 0;
2114 case ir_query_levels
:
2117 ir
->lod_info
.bias
->accept(this);
2121 ir
->lod_info
.grad
.dPdx
->accept(this);
2124 ir
->lod_info
.grad
.dPdy
->accept(this);
2125 lod2
= this->result
;
2127 grad_components
= ir
->lod_info
.grad
.dPdx
->type
->vector_elements
;
2132 ir
->lod_info
.lod
->accept(this);
2136 ir
->lod_info
.sample_index
->accept(this);
2137 sample_index
= this->result
;
2139 if (brw
->gen
>= 7 && tex
->compressed_multisample_layout_mask
& (1<<sampler
))
2140 mcs
= emit_mcs_fetch(coordinate
, ir
->coordinate
->type
->vector_elements
,
2146 unreachable("Unrecognized texture opcode");
2149 int gather_component
= 0;
2150 if (ir
->op
== ir_tg4
)
2151 gather_component
= ir
->lod_info
.component
->as_constant()->value
.i
[0];
2154 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
;
2156 bool is_cube_array
=
2157 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2158 ir
->sampler
->type
->sampler_array
;
2160 emit_texture(ir
->op
, ir
->type
, coordinate
, coord_type
, shadow_comparitor
,
2161 lod
, lod2
, grad_components
, sample_index
, offset_value
,
2162 offset_components
, mcs
, gather_component
,
2163 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
2167 * Apply workarounds for Gen6 gather with UINT/SINT
2170 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2175 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2177 for (int i
= 0; i
< 4; i
++) {
2178 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2179 /* Convert from UNORM to UINT */
2180 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2181 emit(MOV(dst
, dst_f
));
2184 /* Reinterpret the UINT value as a signed INT value by
2185 * shifting the sign bit into place, then shifting back
2188 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2189 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2192 dst
= offset(dst
, 1);
2197 * Set up the gather channel based on the swizzle, for gather4.
2200 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
2202 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2203 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], orig_chan
);
2205 case SWIZZLE_X
: return 0;
2207 /* gather4 sampler is broken for green channel on RG32F --
2208 * we must ask for blue instead.
2210 if (tex
->gather_channel_quirk_mask
& (1<<sampler
))
2213 case SWIZZLE_Z
: return 2;
2214 case SWIZZLE_W
: return 3;
2216 unreachable("Not reached"); /* zero, one swizzles handled already */
2221 * Swizzle the result of a texture result. This is necessary for
2222 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2225 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
2226 fs_reg orig_val
, uint32_t sampler
)
2228 if (op
== ir_query_levels
) {
2229 /* # levels is in .w */
2230 this->result
= offset(orig_val
, 3);
2234 this->result
= orig_val
;
2236 /* txs,lod don't actually sample the texture, so swizzling the result
2239 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
2242 struct brw_sampler_prog_key_data
*tex
= get_tex(stage
, this->key
);
2244 if (dest_components
== 1) {
2245 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2246 } else if (tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2247 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
2248 swizzled_result
.type
= orig_val
.type
;
2250 for (int i
= 0; i
< 4; i
++) {
2251 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], i
);
2252 fs_reg l
= swizzled_result
;
2255 if (swiz
== SWIZZLE_ZERO
) {
2256 emit(MOV(l
, fs_reg(0.0f
)));
2257 } else if (swiz
== SWIZZLE_ONE
) {
2258 emit(MOV(l
, fs_reg(1.0f
)));
2260 emit(MOV(l
, offset(orig_val
,
2261 GET_SWZ(tex
->swizzles
[sampler
], i
))));
2264 this->result
= swizzled_result
;
2269 fs_visitor::visit(ir_swizzle
*ir
)
2271 ir
->val
->accept(this);
2272 fs_reg val
= this->result
;
2274 if (ir
->type
->vector_elements
== 1) {
2275 this->result
= offset(this->result
, ir
->mask
.x
);
2279 fs_reg result
= fs_reg(this, ir
->type
);
2280 this->result
= result
;
2282 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2283 fs_reg channel
= val
;
2301 emit(MOV(result
, offset(channel
, swiz
)));
2302 result
= offset(result
, 1);
2307 fs_visitor::visit(ir_discard
*ir
)
2309 assert(ir
->condition
== NULL
); /* FINISHME */
2311 /* We track our discarded pixels in f0.1. By predicating on it, we can
2312 * update just the flag bits that aren't yet discarded. By emitting a
2313 * CMP of g0 != g0, all our currently executing channels will get turned
2316 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2317 BRW_REGISTER_TYPE_UW
));
2318 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2319 BRW_CONDITIONAL_NZ
));
2320 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2321 cmp
->flag_subreg
= 1;
2323 if (brw
->gen
>= 6) {
2324 /* For performance, after a discard, jump to the end of the shader.
2325 * Only jump if all relevant channels have been discarded.
2327 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2328 discard_jump
->flag_subreg
= 1;
2330 discard_jump
->predicate
= (dispatch_width
== 8)
2331 ? BRW_PREDICATE_ALIGN1_ANY8H
2332 : BRW_PREDICATE_ALIGN1_ANY16H
;
2333 discard_jump
->predicate_inverse
= true;
2338 fs_visitor::visit(ir_constant
*ir
)
2340 /* Set this->result to reg at the bottom of the function because some code
2341 * paths will cause this visitor to be applied to other fields. This will
2342 * cause the value stored in this->result to be modified.
2344 * Make reg constant so that it doesn't get accidentally modified along the
2345 * way. Yes, I actually had this problem. :(
2347 const fs_reg
reg(this, ir
->type
);
2348 fs_reg dst_reg
= reg
;
2350 if (ir
->type
->is_array()) {
2351 const unsigned size
= type_size(ir
->type
->fields
.array
);
2353 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2354 ir
->array_elements
[i
]->accept(this);
2355 fs_reg src_reg
= this->result
;
2357 dst_reg
.type
= src_reg
.type
;
2358 for (unsigned j
= 0; j
< size
; j
++) {
2359 emit(MOV(dst_reg
, src_reg
));
2360 src_reg
= offset(src_reg
, 1);
2361 dst_reg
= offset(dst_reg
, 1);
2364 } else if (ir
->type
->is_record()) {
2365 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2366 const unsigned size
= type_size(field
->type
);
2368 field
->accept(this);
2369 fs_reg src_reg
= this->result
;
2371 dst_reg
.type
= src_reg
.type
;
2372 for (unsigned j
= 0; j
< size
; j
++) {
2373 emit(MOV(dst_reg
, src_reg
));
2374 src_reg
= offset(src_reg
, 1);
2375 dst_reg
= offset(dst_reg
, 1);
2379 const unsigned size
= type_size(ir
->type
);
2381 for (unsigned i
= 0; i
< size
; i
++) {
2382 switch (ir
->type
->base_type
) {
2383 case GLSL_TYPE_FLOAT
:
2384 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2386 case GLSL_TYPE_UINT
:
2387 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2390 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2392 case GLSL_TYPE_BOOL
:
2394 fs_reg(ir
->value
.b
[i
] != 0 ? (int)ctx
->Const
.UniformBooleanTrue
2398 unreachable("Non-float/uint/int/bool constant");
2400 dst_reg
= offset(dst_reg
, 1);
2408 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2410 ir_expression
*expr
= ir
->as_expression();
2412 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2415 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2416 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2423 assert(expr
->get_num_operands() <= 3);
2424 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2425 assert(expr
->operands
[i
]->type
->is_scalar());
2427 expr
->operands
[i
]->accept(this);
2428 op
[i
] = this->result
;
2430 resolve_ud_negate(&op
[i
]);
2433 switch (expr
->operation
) {
2434 case ir_unop_logic_not
:
2435 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2436 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2439 case ir_binop_logic_xor
:
2440 if (brw
->gen
<= 5) {
2441 fs_reg temp
= fs_reg(this, ir
->type
);
2442 emit(XOR(temp
, op
[0], op
[1]));
2443 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2445 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2447 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2450 case ir_binop_logic_or
:
2451 if (brw
->gen
<= 5) {
2452 fs_reg temp
= fs_reg(this, ir
->type
);
2453 emit(OR(temp
, op
[0], op
[1]));
2454 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2456 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2458 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2461 case ir_binop_logic_and
:
2462 if (brw
->gen
<= 5) {
2463 fs_reg temp
= fs_reg(this, ir
->type
);
2464 emit(AND(temp
, op
[0], op
[1]));
2465 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2467 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2469 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2473 if (brw
->gen
>= 6) {
2474 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2476 inst
= emit(MOV(reg_null_f
, op
[0]));
2477 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2482 if (brw
->gen
>= 6) {
2483 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2485 inst
= emit(MOV(reg_null_d
, op
[0]));
2486 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2490 case ir_binop_greater
:
2491 case ir_binop_gequal
:
2493 case ir_binop_lequal
:
2494 case ir_binop_equal
:
2495 case ir_binop_all_equal
:
2496 case ir_binop_nequal
:
2497 case ir_binop_any_nequal
:
2498 if (brw
->gen
<= 5) {
2499 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2500 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2503 emit(CMP(reg_null_d
, op
[0], op
[1],
2504 brw_conditional_for_comparison(expr
->operation
)));
2507 case ir_triop_csel
: {
2508 /* Expand the boolean condition into the flag register. */
2509 inst
= emit(MOV(reg_null_d
, op
[0]));
2510 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2512 /* Select which boolean to return. */
2513 fs_reg
temp(this, expr
->operands
[1]->type
);
2514 inst
= emit(SEL(temp
, op
[1], op
[2]));
2515 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2517 /* Expand the result to a condition code. */
2518 inst
= emit(MOV(reg_null_d
, temp
));
2519 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2524 unreachable("not reached");
2529 * Emit a gen6 IF statement with the comparison folded into the IF
2533 fs_visitor::emit_if_gen6(ir_if
*ir
)
2535 ir_expression
*expr
= ir
->condition
->as_expression();
2537 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2542 assert(expr
->get_num_operands() <= 3);
2543 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2544 assert(expr
->operands
[i
]->type
->is_scalar());
2546 expr
->operands
[i
]->accept(this);
2547 op
[i
] = this->result
;
2550 switch (expr
->operation
) {
2551 case ir_unop_logic_not
:
2552 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2555 case ir_binop_logic_xor
:
2556 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2559 case ir_binop_logic_or
:
2560 temp
= fs_reg(this, glsl_type::bool_type
);
2561 emit(OR(temp
, op
[0], op
[1]));
2562 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2565 case ir_binop_logic_and
:
2566 temp
= fs_reg(this, glsl_type::bool_type
);
2567 emit(AND(temp
, op
[0], op
[1]));
2568 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2572 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2573 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2577 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2580 case ir_binop_greater
:
2581 case ir_binop_gequal
:
2583 case ir_binop_lequal
:
2584 case ir_binop_equal
:
2585 case ir_binop_all_equal
:
2586 case ir_binop_nequal
:
2587 case ir_binop_any_nequal
:
2588 if (brw
->gen
<= 5) {
2589 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2590 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2593 emit(IF(op
[0], op
[1],
2594 brw_conditional_for_comparison(expr
->operation
)));
2597 case ir_triop_csel
: {
2598 /* Expand the boolean condition into the flag register. */
2599 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2600 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2602 /* Select which boolean to use as the result. */
2603 fs_reg
temp(this, expr
->operands
[1]->type
);
2604 inst
= emit(SEL(temp
, op
[1], op
[2]));
2605 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2607 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2612 unreachable("not reached");
2616 ir
->condition
->accept(this);
2617 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2621 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2623 * Many GLSL shaders contain the following pattern:
2625 * x = condition ? foo : bar
2627 * The compiler emits an ir_if tree for this, since each subexpression might be
2628 * a complex tree that could have side-effects or short-circuit logic.
2630 * However, the common case is to simply select one of two constants or
2631 * variable values---which is exactly what SEL is for. In this case, the
2632 * assembly looks like:
2640 * which can be easily translated into:
2642 * (+f0) SEL dst src0 src1
2644 * If src0 is an immediate value, we promote it to a temporary GRF.
2647 fs_visitor::try_replace_with_sel()
2649 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2650 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2652 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2654 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2657 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2658 for (int i
= 0; i
< 4; i
++) {
2659 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2661 match
= (fs_inst
*) match
->prev
;
2664 /* The opcodes match; it looks like the right sequence of instructions. */
2665 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2666 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2667 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2669 /* Check that the MOVs are the right form. */
2670 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2671 !then_mov
->is_partial_write() &&
2672 !else_mov
->is_partial_write()) {
2674 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2675 while (!if_inst
->next
->is_tail_sentinel())
2676 if_inst
->next
->exec_node::remove();
2677 if_inst
->exec_node::remove();
2679 /* Only the last source register can be a constant, so if the MOV in
2680 * the "then" clause uses a constant, we need to put it in a temporary.
2682 fs_reg
src0(then_mov
->src
[0]);
2683 if (src0
.file
== IMM
) {
2684 src0
= fs_reg(this, glsl_type::float_type
);
2685 src0
.type
= then_mov
->src
[0].type
;
2686 emit(MOV(src0
, then_mov
->src
[0]));
2690 if (if_inst
->conditional_mod
) {
2691 /* Sandybridge-specific IF with embedded comparison */
2692 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2693 if_inst
->conditional_mod
));
2694 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2695 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2697 /* Separate CMP and IF instructions */
2698 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2699 sel
->predicate
= if_inst
->predicate
;
2700 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2706 fs_visitor::visit(ir_if
*ir
)
2709 no16("Can't support (non-uniform) control flow on SIMD16\n");
2712 /* Don't point the annotation at the if statement, because then it plus
2713 * the then and else blocks get printed.
2715 this->base_ir
= ir
->condition
;
2717 if (brw
->gen
== 6) {
2720 emit_bool_to_cond_code(ir
->condition
);
2722 emit(IF(BRW_PREDICATE_NORMAL
));
2725 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2726 this->base_ir
= ir_
;
2730 if (!ir
->else_instructions
.is_empty()) {
2731 emit(BRW_OPCODE_ELSE
);
2733 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2734 this->base_ir
= ir_
;
2739 emit(BRW_OPCODE_ENDIF
);
2741 try_replace_with_sel();
2745 fs_visitor::visit(ir_loop
*ir
)
2748 no16("Can't support (non-uniform) control flow on SIMD16\n");
2751 this->base_ir
= NULL
;
2752 emit(BRW_OPCODE_DO
);
2754 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2755 this->base_ir
= ir_
;
2759 this->base_ir
= NULL
;
2760 emit(BRW_OPCODE_WHILE
);
2764 fs_visitor::visit(ir_loop_jump
*ir
)
2767 case ir_loop_jump::jump_break
:
2768 emit(BRW_OPCODE_BREAK
);
2770 case ir_loop_jump::jump_continue
:
2771 emit(BRW_OPCODE_CONTINUE
);
2777 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2779 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2780 ir
->actual_parameters
.get_head());
2781 ir_variable
*location
= deref
->variable_referenced();
2782 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2783 location
->data
.binding
);
2785 /* Calculate the surface offset */
2786 fs_reg
offset(this, glsl_type::uint_type
);
2787 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2790 deref_array
->array_index
->accept(this);
2792 fs_reg
tmp(this, glsl_type::uint_type
);
2793 emit(MUL(tmp
, this->result
, fs_reg(ATOMIC_COUNTER_SIZE
)));
2794 emit(ADD(offset
, tmp
, fs_reg(location
->data
.atomic
.offset
)));
2796 offset
= fs_reg(location
->data
.atomic
.offset
);
2799 /* Emit the appropriate machine instruction */
2800 const char *callee
= ir
->callee
->function_name();
2801 ir
->return_deref
->accept(this);
2802 fs_reg dst
= this->result
;
2804 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2805 emit_untyped_surface_read(surf_index
, dst
, offset
);
2807 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2808 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2809 fs_reg(), fs_reg());
2811 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2812 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2813 fs_reg(), fs_reg());
2818 fs_visitor::visit(ir_call
*ir
)
2820 const char *callee
= ir
->callee
->function_name();
2822 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2823 !strcmp("__intrinsic_atomic_increment", callee
) ||
2824 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2825 visit_atomic_counter_intrinsic(ir
);
2827 unreachable("Unsupported intrinsic.");
2832 fs_visitor::visit(ir_return
*)
2834 unreachable("FINISHME");
2838 fs_visitor::visit(ir_function
*ir
)
2840 /* Ignore function bodies other than main() -- we shouldn't see calls to
2841 * them since they should all be inlined before we get to ir_to_mesa.
2843 if (strcmp(ir
->name
, "main") == 0) {
2844 const ir_function_signature
*sig
;
2847 sig
= ir
->matching_signature(NULL
, &empty
, false);
2851 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2852 this->base_ir
= ir_
;
2859 fs_visitor::visit(ir_function_signature
*)
2861 unreachable("not reached");
2865 fs_visitor::visit(ir_emit_vertex
*)
2867 unreachable("not reached");
2871 fs_visitor::visit(ir_end_primitive
*)
2873 unreachable("not reached");
2877 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2878 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2882 (stage
== MESA_SHADER_FRAGMENT
) &&
2883 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2884 int reg_width
= dispatch_width
/ 8;
2887 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
2889 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2890 /* Initialize the sample mask in the message header. */
2891 emit(MOV(sources
[0], fs_reg(0u)))
2892 ->force_writemask_all
= true;
2895 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2896 ->force_writemask_all
= true;
2898 emit(MOV(component(sources
[0], 7),
2899 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2900 ->force_writemask_all
= true;
2904 /* Set the atomic operation offset. */
2905 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2906 emit(MOV(sources
[1], offset
));
2909 /* Set the atomic operation arguments. */
2910 if (src0
.file
!= BAD_FILE
) {
2911 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2912 emit(MOV(sources
[length
], src0
));
2916 if (src1
.file
!= BAD_FILE
) {
2917 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2918 emit(MOV(sources
[length
], src1
));
2922 int mlen
= 1 + (length
- 1) * reg_width
;
2923 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2924 BRW_REGISTER_TYPE_UD
);
2925 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
2927 /* Emit the instruction. */
2928 fs_inst
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
2929 fs_reg(atomic_op
), fs_reg(surf_index
));
2934 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2938 (stage
== MESA_SHADER_FRAGMENT
) &&
2939 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2940 int reg_width
= dispatch_width
/ 8;
2942 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
2944 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2945 /* Initialize the sample mask in the message header. */
2946 emit(MOV(sources
[0], fs_reg(0u)))
2947 ->force_writemask_all
= true;
2950 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2951 ->force_writemask_all
= true;
2953 emit(MOV(component(sources
[0], 7),
2954 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2955 ->force_writemask_all
= true;
2958 /* Set the surface read offset. */
2959 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2960 emit(MOV(sources
[1], offset
));
2962 int mlen
= 1 + reg_width
;
2963 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2964 BRW_REGISTER_TYPE_UD
);
2965 fs_inst
*inst
= emit(LOAD_PAYLOAD(src_payload
, sources
, 2));
2967 /* Emit the instruction. */
2968 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
2969 fs_reg(surf_index
));
2974 fs_visitor::emit(fs_inst
*inst
)
2976 if (dispatch_width
== 16 && inst
->exec_size
== 8)
2977 inst
->force_uncompressed
= true;
2979 inst
->annotation
= this->current_annotation
;
2980 inst
->ir
= this->base_ir
;
2982 this->instructions
.push_tail(inst
);
2988 fs_visitor::emit(exec_list list
)
2990 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2991 inst
->exec_node::remove();
2996 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2998 fs_visitor::emit_dummy_fs()
3000 int reg_width
= dispatch_width
/ 8;
3002 /* Everyone's favorite color. */
3003 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
3004 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
3005 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
3006 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
3009 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
3010 write
->base_mrf
= 2;
3011 write
->mlen
= 4 * reg_width
;
3015 /* The register location here is relative to the start of the URB
3016 * data. It will get adjusted to be a real location before
3017 * generate_code() time.
3020 fs_visitor::interp_reg(int location
, int channel
)
3022 assert(stage
== MESA_SHADER_FRAGMENT
);
3023 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3024 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
3025 int stride
= (channel
& 1) * 4;
3027 assert(prog_data
->urb_setup
[location
] != -1);
3029 return brw_vec1_grf(regnr
, stride
);
3032 /** Emits the interpolation for the varying inputs. */
3034 fs_visitor::emit_interpolation_setup_gen4()
3036 this->current_annotation
= "compute pixel centers";
3037 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
3038 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
3039 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3040 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3042 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
3043 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
3045 this->current_annotation
= "compute pixel deltas from v0";
3047 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3048 fs_reg(this, glsl_type::vec2_type
);
3049 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3050 offset(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
], 1);
3052 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3053 fs_reg(this, glsl_type::float_type
);
3054 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3055 fs_reg(this, glsl_type::float_type
);
3057 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3058 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
3059 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3060 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
3062 this->current_annotation
= "compute pos.w and 1/pos.w";
3063 /* Compute wpos.w. It's always in our setup, since it's needed to
3064 * interpolate the other attributes.
3066 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
3067 emit(FS_OPCODE_LINTERP
, wpos_w
,
3068 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3069 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3070 interp_reg(VARYING_SLOT_POS
, 3));
3071 /* Compute the pixel 1/W value from wpos.w. */
3072 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
3073 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
3074 this->current_annotation
= NULL
;
3077 /** Emits the interpolation for the varying inputs. */
3079 fs_visitor::emit_interpolation_setup_gen6()
3081 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
3083 /* If the pixel centers end up used, the setup is the same as for gen4. */
3084 this->current_annotation
= "compute pixel centers";
3085 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
3086 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
3087 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3088 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3089 emit(ADD(int_pixel_x
,
3090 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
3091 fs_reg(brw_imm_v(0x10101010))));
3092 emit(ADD(int_pixel_y
,
3093 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
3094 fs_reg(brw_imm_v(0x11001100))));
3096 /* As of gen6, we can no longer mix float and int sources. We have
3097 * to turn the integer pixel centers into floats for their actual
3100 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
3101 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
3102 emit(MOV(this->pixel_x
, int_pixel_x
));
3103 emit(MOV(this->pixel_y
, int_pixel_y
));
3105 this->current_annotation
= "compute pos.w";
3106 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
3107 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
3108 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
3110 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3111 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
3112 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
3113 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
3116 this->current_annotation
= NULL
;
3120 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
)
3122 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3125 if (color
.file
== BAD_FILE
) {
3126 return 4 * (dispatch_width
/ 8);
3129 uint8_t colors_enabled
;
3130 if (components
== 0) {
3131 /* We want to write one component to the alpha channel */
3132 colors_enabled
= 0x8;
3134 /* Enable the first components-many channels */
3135 colors_enabled
= (1 << components
) - 1;
3138 if (dispatch_width
== 8 || brw
->gen
>= 6) {
3139 /* SIMD8 write looks like:
3145 * gen6 SIMD16 DP write looks like:
3156 for (unsigned i
= 0; i
< 4; ++i
) {
3157 if (colors_enabled
& (1 << i
)) {
3158 dst
[len
] = fs_reg(GRF
, virtual_grf_alloc(color
.width
/ 8),
3159 color
.type
, color
.width
);
3160 inst
= emit(MOV(dst
[len
], offset(color
, i
)));
3161 inst
->saturate
= key
->clamp_fragment_color
;
3162 } else if (color
.width
== 16) {
3163 /* We need two BAD_FILE slots for a 16-wide color */
3170 /* pre-gen6 SIMD16 single source DP write looks like:
3180 for (unsigned i
= 0; i
< 4; ++i
) {
3181 if (colors_enabled
& (1 << i
)) {
3182 dst
[i
] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3183 inst
= emit(MOV(dst
[i
], half(offset(color
, i
), 0)));
3184 inst
->saturate
= key
->clamp_fragment_color
;
3186 dst
[i
+ 4] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3187 inst
= emit(MOV(dst
[i
+ 4], half(offset(color
, i
), 1)));
3188 inst
->saturate
= key
->clamp_fragment_color
;
3189 inst
->force_sechalf
= true;
3196 static enum brw_conditional_mod
3197 cond_for_alpha_func(GLenum func
)
3201 return BRW_CONDITIONAL_G
;
3203 return BRW_CONDITIONAL_GE
;
3205 return BRW_CONDITIONAL_L
;
3207 return BRW_CONDITIONAL_LE
;
3209 return BRW_CONDITIONAL_EQ
;
3211 return BRW_CONDITIONAL_NEQ
;
3213 unreachable("Not reached");
3218 * Alpha test support for when we compile it into the shader instead
3219 * of using the normal fixed-function alpha test.
3222 fs_visitor::emit_alpha_test()
3224 assert(stage
== MESA_SHADER_FRAGMENT
);
3225 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3226 this->current_annotation
= "Alpha test";
3229 if (key
->alpha_test_func
== GL_ALWAYS
)
3232 if (key
->alpha_test_func
== GL_NEVER
) {
3234 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3235 BRW_REGISTER_TYPE_UW
));
3236 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3237 BRW_CONDITIONAL_NEQ
));
3240 fs_reg color
= offset(outputs
[0], 3);
3242 /* f0.1 &= func(color, ref) */
3243 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3244 cond_for_alpha_func(key
->alpha_test_func
)));
3246 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3247 cmp
->flag_subreg
= 1;
3251 fs_visitor::emit_single_fb_write(fs_reg color0
, fs_reg color1
,
3252 fs_reg src0_alpha
, unsigned components
)
3254 assert(stage
== MESA_SHADER_FRAGMENT
);
3255 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3256 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3258 this->current_annotation
= "FB write header";
3259 bool header_present
= true;
3260 int reg_size
= dispatch_width
/ 8;
3262 /* We can potentially have a message length of up to 15, so we have to set
3263 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3265 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
3268 /* From the Sandy Bridge PRM, volume 4, page 198:
3270 * "Dispatched Pixel Enables. One bit per pixel indicating
3271 * which pixels were originally enabled when the thread was
3272 * dispatched. This field is only required for the end-of-
3273 * thread message and on all dual-source messages."
3275 if (brw
->gen
>= 6 &&
3276 (brw
->is_haswell
|| brw
->gen
>= 8 || !prog_data
->uses_kill
) &&
3277 color1
.file
== BAD_FILE
&&
3278 key
->nr_color_regions
== 1) {
3279 header_present
= false;
3283 /* Allocate 2 registers for a header */
3286 if (payload
.aa_dest_stencil_reg
) {
3287 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1));
3288 emit(MOV(sources
[length
],
3289 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3293 prog_data
->uses_omask
=
3294 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3295 if (prog_data
->uses_omask
) {
3296 this->current_annotation
= "FB write oMask";
3297 assert(this->sample_mask
.file
!= BAD_FILE
);
3298 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
3299 * it's unsinged single words, one vgrf is always 16-wide.
3301 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1),
3302 BRW_REGISTER_TYPE_UW
, 16);
3303 emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
3307 if (color0
.file
== BAD_FILE
) {
3308 /* Even if there's no color buffers enabled, we still need to send
3309 * alpha out the pipeline to our null renderbuffer to support
3310 * alpha-testing, alpha-to-coverage, and so on.
3312 length
+= setup_color_payload(sources
+ length
, this->outputs
[0], 0);
3313 } else if (color1
.file
== BAD_FILE
) {
3314 if (src0_alpha
.file
!= BAD_FILE
) {
3315 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(reg_size
),
3316 src0_alpha
.type
, src0_alpha
.width
);
3317 fs_inst
*inst
= emit(MOV(sources
[length
], src0_alpha
));
3318 inst
->saturate
= key
->clamp_fragment_color
;
3322 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3324 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3325 length
+= setup_color_payload(sources
+ length
, color1
, components
);
3328 if (source_depth_to_render_target
) {
3329 if (brw
->gen
== 6) {
3330 /* For outputting oDepth on gen6, SIMD8 writes have to be
3331 * used. This would require SIMD8 moves of each half to
3332 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3333 * Just bail on doing so for now.
3335 no16("Missing support for simd16 depth writes on gen6\n");
3338 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3339 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3340 /* Hand over gl_FragDepth. */
3341 assert(this->frag_depth
.file
!= BAD_FILE
);
3342 emit(MOV(sources
[length
], this->frag_depth
));
3344 /* Pass through the payload depth. */
3345 emit(MOV(sources
[length
],
3346 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3351 if (payload
.dest_depth_reg
) {
3352 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3353 emit(MOV(sources
[length
],
3354 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3360 if (brw
->gen
>= 7) {
3361 /* Send from the GRF */
3362 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3363 load
= emit(LOAD_PAYLOAD(payload
, sources
, length
));
3364 payload
.reg
= virtual_grf_alloc(load
->regs_written
);
3365 load
->dst
= payload
;
3366 write
= emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
3367 write
->base_mrf
= -1;
3369 /* Send from the MRF */
3370 load
= emit(LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3372 write
= emit(FS_OPCODE_FB_WRITE
);
3373 write
->base_mrf
= 1;
3376 write
->mlen
= load
->regs_written
;
3377 write
->header_present
= header_present
;
3378 if (prog_data
->uses_kill
) {
3379 write
->predicate
= BRW_PREDICATE_NORMAL
;
3380 write
->flag_subreg
= 1;
3386 fs_visitor::emit_fb_writes()
3388 assert(stage
== MESA_SHADER_FRAGMENT
);
3389 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3390 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3393 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
3394 if (dispatch_width
== 16)
3395 do_dual_src
= false;
3400 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3401 emit_shader_time_end();
3403 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3404 "FB dual-source write");
3405 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3408 prog_data
->dual_src_blend
= true;
3409 } else if (key
->nr_color_regions
> 0) {
3410 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3411 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3412 "FB write target %d",
3415 if (brw
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
3416 src0_alpha
= offset(outputs
[0], 3);
3418 if (target
== key
->nr_color_regions
- 1 &&
3419 (INTEL_DEBUG
& DEBUG_SHADER_TIME
))
3420 emit_shader_time_end();
3422 inst
= emit_single_fb_write(this->outputs
[target
], reg_undef
,
3424 this->output_components
[target
]);
3425 inst
->target
= target
;
3428 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3429 emit_shader_time_end();
3431 /* Even if there's no color buffers enabled, we still need to send
3432 * alpha out the pipeline to our null renderbuffer to support
3433 * alpha-testing, alpha-to-coverage, and so on.
3435 inst
= emit_single_fb_write(reg_undef
, reg_undef
, reg_undef
, 0);
3440 this->current_annotation
= NULL
;
3444 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3446 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3450 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
3451 emit(MOV(temp
, *reg
));
3456 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3458 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3459 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3462 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3464 assert(brw
->gen
<= 5);
3466 if (rvalue
->type
!= glsl_type::bool_type
)
3469 fs_reg and_result
= fs_reg(this, glsl_type::bool_type
);
3470 fs_reg neg_result
= fs_reg(this, glsl_type::bool_type
);
3471 emit(AND(and_result
, *reg
, fs_reg(1)));
3472 emit(MOV(neg_result
, negate(and_result
)));
3476 fs_visitor::fs_visitor(struct brw_context
*brw
,
3478 const struct brw_wm_prog_key
*key
,
3479 struct brw_wm_prog_data
*prog_data
,
3480 struct gl_shader_program
*shader_prog
,
3481 struct gl_fragment_program
*fp
,
3482 unsigned dispatch_width
)
3483 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3484 MESA_SHADER_FRAGMENT
),
3485 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
3486 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
3487 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
3488 key(key
), prog_data(&prog_data
->base
),
3489 dispatch_width(dispatch_width
)
3491 this->mem_ctx
= mem_ctx
;
3498 this->failed
= false;
3499 this->simd16_unsupported
= false;
3500 this->no16_msg
= NULL
;
3501 this->variable_ht
= hash_table_ctor(0,
3502 hash_table_pointer_hash
,
3503 hash_table_pointer_compare
);
3505 memset(&this->payload
, 0, sizeof(this->payload
));
3506 memset(this->outputs
, 0, sizeof(this->outputs
));
3507 memset(this->output_components
, 0, sizeof(this->output_components
));
3508 this->source_depth_to_render_target
= false;
3509 this->runtime_check_aads_emit
= false;
3510 this->first_non_payload_grf
= 0;
3511 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3513 this->current_annotation
= NULL
;
3514 this->base_ir
= NULL
;
3516 this->virtual_grf_sizes
= NULL
;
3517 this->virtual_grf_count
= 0;
3518 this->virtual_grf_array_size
= 0;
3519 this->virtual_grf_start
= NULL
;
3520 this->virtual_grf_end
= NULL
;
3521 this->live_intervals
= NULL
;
3522 this->regs_live_at_ip
= NULL
;
3525 this->last_scratch
= 0;
3526 this->pull_constant_loc
= NULL
;
3527 this->push_constant_loc
= NULL
;
3529 this->spilled_any_registers
= false;
3530 this->do_dual_src
= false;
3532 if (dispatch_width
== 8)
3533 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3536 fs_visitor::~fs_visitor()
3538 hash_table_dtor(this->variable_ht
);