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i965/fs: Simplify computation of key.input_slots_valid during precompile.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_visitor.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "brw_fs.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50
51 void
52 fs_visitor::visit(ir_variable *ir)
53 {
54 fs_reg *reg = NULL;
55
56 if (variable_storage(ir))
57 return;
58
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
64 } else {
65 reg = emit_general_interpolation(ir);
66 }
67 assert(reg);
68 hash_table_insert(this->variable_ht, reg, ir);
69 return;
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
72
73 if (ir->index > 0) {
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
82 }
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
85 } else {
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
89
90 int vector_elements =
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
93
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
100 }
101 }
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
104
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
108 */
109 if (ir->is_in_uniform_block())
110 return;
111
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
115 }
116 return;
117 }
118
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
122 } else {
123 setup_uniform_values(ir);
124 }
125
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
128 }
129
130 if (!reg)
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
132
133 hash_table_insert(this->variable_ht, reg, ir);
134 }
135
136 void
137 fs_visitor::visit(ir_dereference_variable *ir)
138 {
139 fs_reg *reg = variable_storage(ir->var);
140 this->result = *reg;
141 }
142
143 void
144 fs_visitor::visit(ir_dereference_record *ir)
145 {
146 const glsl_type *struct_type = ir->record->type;
147
148 ir->record->accept(this);
149
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
153 break;
154 offset += type_size(struct_type->fields.structure[i].type);
155 }
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
158 }
159
160 void
161 fs_visitor::visit(ir_dereference_array *ir)
162 {
163 ir_constant *constant_index;
164 fs_reg src;
165 int element_size = type_size(ir->type);
166
167 constant_index = ir->array_index->as_constant();
168
169 ir->array->accept(this);
170 src = this->result;
171 src.type = brw_type_for_base_type(ir->type);
172
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
176 } else {
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
183 */
184 ir->array_index->accept(this);
185
186 fs_reg index_reg;
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
189
190 if (src.reladdr) {
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
192 }
193
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
196 }
197 this->result = src;
198 }
199
200 void
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
202 {
203 if (brw->gen < 6 ||
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
211
212 emit(MUL(y_times_a, y, a));
213
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
217
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
219 } else {
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
222 */
223 emit(LRP(dst, a, y, x));
224 }
225 }
226
227 void
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
230 {
231 fs_inst *inst;
232
233 if (brw->gen >= 6) {
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
236 } else {
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
238
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
241 }
242 }
243
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
246 */
247 bool
248 fs_visitor::try_emit_saturate(ir_expression *ir)
249 {
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
251
252 if (!sat_val)
253 return false;
254
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
256
257 sat_val->accept(this);
258 fs_reg src = this->result;
259
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
261
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
264 */
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
270 } else {
271 modify->saturate = true;
272 this->result = src;
273 }
274
275
276 return true;
277 }
278
279 bool
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
281 {
282 /* 3-src instructions were introduced in gen6. */
283 if (brw->gen < 6)
284 return false;
285
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
288 return false;
289
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
292
293 if (!mul || mul->operation != ir_binop_mul)
294 return false;
295
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
299 return false;
300
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
303
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
306
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
309
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
312
313 return true;
314 }
315
316 void
317 fs_visitor::visit(ir_expression *ir)
318 {
319 unsigned int operand;
320 fs_reg op[3], temp;
321 fs_inst *inst;
322
323 assert(ir->get_num_operands() <= 3);
324
325 if (try_emit_saturate(ir))
326 return;
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
329 return;
330 }
331
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
337 printf("\n");
338 }
339 assert(this->result.is_valid_3src());
340 op[operand] = this->result;
341
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
344 */
345 assert(!ir->operands[operand]->type->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
347 */
348 assert(!ir->operands[operand]->type->is_vector());
349 }
350
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
353 */
354 this->result = fs_reg(this, ir->type);
355
356 switch (ir->operation) {
357 case ir_unop_logic_not:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
360 */
361 emit(XOR(this->result, op[0], fs_reg(1)));
362 break;
363 case ir_unop_neg:
364 op[0].negate = !op[0].negate;
365 emit(MOV(this->result, op[0]));
366 break;
367 case ir_unop_abs:
368 op[0].abs = true;
369 op[0].negate = false;
370 emit(MOV(this->result, op[0]));
371 break;
372 case ir_unop_sign:
373 temp = fs_reg(this, ir->type);
374
375 emit(MOV(this->result, fs_reg(0.0f)));
376
377 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
378 inst = emit(MOV(this->result, fs_reg(1.0f)));
379 inst->predicate = BRW_PREDICATE_NORMAL;
380
381 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
382 inst = emit(MOV(this->result, fs_reg(-1.0f)));
383 inst->predicate = BRW_PREDICATE_NORMAL;
384
385 break;
386 case ir_unop_rcp:
387 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
388 break;
389
390 case ir_unop_exp2:
391 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
392 break;
393 case ir_unop_log2:
394 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
395 break;
396 case ir_unop_exp:
397 case ir_unop_log:
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
399 break;
400 case ir_unop_sin:
401 case ir_unop_sin_reduced:
402 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
403 break;
404 case ir_unop_cos:
405 case ir_unop_cos_reduced:
406 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
407 break;
408
409 case ir_unop_dFdx:
410 emit(FS_OPCODE_DDX, this->result, op[0]);
411 break;
412 case ir_unop_dFdy:
413 emit(FS_OPCODE_DDY, this->result, op[0]);
414 break;
415
416 case ir_binop_add:
417 emit(ADD(this->result, op[0], op[1]));
418 break;
419 case ir_binop_sub:
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 break;
422
423 case ir_binop_mul:
424 if (ir->type->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
428 * of that operand.
429 *
430 * FINISHME: Emit just the MUL if we know an operand is small
431 * enough.
432 */
433 if (brw->gen >= 7 && dispatch_width == 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
435
436 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
437
438 emit(MUL(acc, op[0], op[1]));
439 emit(MACH(reg_null_d, op[0], op[1]));
440 emit(MOV(this->result, fs_reg(acc)));
441 } else {
442 emit(MUL(this->result, op[0], op[1]));
443 }
444 break;
445 case ir_binop_div:
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir->type->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
449 break;
450 case ir_binop_mod:
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir->type->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
454 break;
455
456 case ir_binop_less:
457 case ir_binop_greater:
458 case ir_binop_lequal:
459 case ir_binop_gequal:
460 case ir_binop_equal:
461 case ir_binop_all_equal:
462 case ir_binop_nequal:
463 case ir_binop_any_nequal:
464 resolve_bool_comparison(ir->operands[0], &op[0]);
465 resolve_bool_comparison(ir->operands[1], &op[1]);
466
467 emit(CMP(this->result, op[0], op[1],
468 brw_conditional_for_comparison(ir->operation)));
469 break;
470
471 case ir_binop_logic_xor:
472 emit(XOR(this->result, op[0], op[1]));
473 break;
474
475 case ir_binop_logic_or:
476 emit(OR(this->result, op[0], op[1]));
477 break;
478
479 case ir_binop_logic_and:
480 emit(AND(this->result, op[0], op[1]));
481 break;
482
483 case ir_binop_dot:
484 case ir_unop_any:
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 break;
487
488 case ir_unop_noise:
489 assert(!"not reached: should be handled by lower_noise");
490 break;
491
492 case ir_quadop_vector:
493 assert(!"not reached: should be handled by lower_quadop_vector");
494 break;
495
496 case ir_binop_vector_extract:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
498 break;
499
500 case ir_triop_vector_insert:
501 assert(!"not reached: should be handled by lower_vector_insert()");
502 break;
503
504 case ir_unop_sqrt:
505 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
506 break;
507
508 case ir_unop_rsq:
509 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
510 break;
511
512 case ir_unop_bitcast_i2f:
513 case ir_unop_bitcast_u2f:
514 op[0].type = BRW_REGISTER_TYPE_F;
515 this->result = op[0];
516 break;
517 case ir_unop_i2u:
518 case ir_unop_bitcast_f2u:
519 op[0].type = BRW_REGISTER_TYPE_UD;
520 this->result = op[0];
521 break;
522 case ir_unop_u2i:
523 case ir_unop_bitcast_f2i:
524 op[0].type = BRW_REGISTER_TYPE_D;
525 this->result = op[0];
526 break;
527 case ir_unop_i2f:
528 case ir_unop_u2f:
529 case ir_unop_f2i:
530 case ir_unop_f2u:
531 emit(MOV(this->result, op[0]));
532 break;
533
534 case ir_unop_b2i:
535 emit(AND(this->result, op[0], fs_reg(1)));
536 break;
537 case ir_unop_b2f:
538 temp = fs_reg(this, glsl_type::int_type);
539 emit(AND(temp, op[0], fs_reg(1)));
540 emit(MOV(this->result, temp));
541 break;
542
543 case ir_unop_f2b:
544 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
545 break;
546 case ir_unop_i2b:
547 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
548 break;
549
550 case ir_unop_trunc:
551 emit(RNDZ(this->result, op[0]));
552 break;
553 case ir_unop_ceil:
554 op[0].negate = !op[0].negate;
555 emit(RNDD(this->result, op[0]));
556 this->result.negate = true;
557 break;
558 case ir_unop_floor:
559 emit(RNDD(this->result, op[0]));
560 break;
561 case ir_unop_fract:
562 emit(FRC(this->result, op[0]));
563 break;
564 case ir_unop_round_even:
565 emit(RNDE(this->result, op[0]));
566 break;
567
568 case ir_binop_min:
569 case ir_binop_max:
570 resolve_ud_negate(&op[0]);
571 resolve_ud_negate(&op[1]);
572 emit_minmax(ir->operation == ir_binop_min ?
573 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
574 this->result, op[0], op[1]);
575 break;
576 case ir_unop_pack_snorm_2x16:
577 case ir_unop_pack_snorm_4x8:
578 case ir_unop_pack_unorm_2x16:
579 case ir_unop_pack_unorm_4x8:
580 case ir_unop_unpack_snorm_2x16:
581 case ir_unop_unpack_snorm_4x8:
582 case ir_unop_unpack_unorm_2x16:
583 case ir_unop_unpack_unorm_4x8:
584 case ir_unop_unpack_half_2x16:
585 case ir_unop_pack_half_2x16:
586 assert(!"not reached: should be handled by lower_packing_builtins");
587 break;
588 case ir_unop_unpack_half_2x16_split_x:
589 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
590 break;
591 case ir_unop_unpack_half_2x16_split_y:
592 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
593 break;
594 case ir_binop_pow:
595 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
596 break;
597
598 case ir_unop_bitfield_reverse:
599 emit(BFREV(this->result, op[0]));
600 break;
601 case ir_unop_bit_count:
602 emit(CBIT(this->result, op[0]));
603 break;
604 case ir_unop_find_msb:
605 temp = fs_reg(this, glsl_type::uint_type);
606 emit(FBH(temp, op[0]));
607
608 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
609 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
610 * subtract the result from 31 to convert the MSB count into an LSB count.
611 */
612
613 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
614 emit(MOV(this->result, temp));
615 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
616
617 temp.negate = true;
618 inst = emit(ADD(this->result, temp, fs_reg(31)));
619 inst->predicate = BRW_PREDICATE_NORMAL;
620 break;
621 case ir_unop_find_lsb:
622 emit(FBL(this->result, op[0]));
623 break;
624 case ir_triop_bitfield_extract:
625 /* Note that the instruction's argument order is reversed from GLSL
626 * and the IR.
627 */
628 emit(BFE(this->result, op[2], op[1], op[0]));
629 break;
630 case ir_binop_bfm:
631 emit(BFI1(this->result, op[0], op[1]));
632 break;
633 case ir_triop_bfi:
634 emit(BFI2(this->result, op[0], op[1], op[2]));
635 break;
636 case ir_quadop_bitfield_insert:
637 assert(!"not reached: should be handled by "
638 "lower_instructions::bitfield_insert_to_bfm_bfi");
639 break;
640
641 case ir_unop_bit_not:
642 emit(NOT(this->result, op[0]));
643 break;
644 case ir_binop_bit_and:
645 emit(AND(this->result, op[0], op[1]));
646 break;
647 case ir_binop_bit_xor:
648 emit(XOR(this->result, op[0], op[1]));
649 break;
650 case ir_binop_bit_or:
651 emit(OR(this->result, op[0], op[1]));
652 break;
653
654 case ir_binop_lshift:
655 emit(SHL(this->result, op[0], op[1]));
656 break;
657
658 case ir_binop_rshift:
659 if (ir->type->base_type == GLSL_TYPE_INT)
660 emit(ASR(this->result, op[0], op[1]));
661 else
662 emit(SHR(this->result, op[0], op[1]));
663 break;
664 case ir_binop_pack_half_2x16_split:
665 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
666 break;
667 case ir_binop_ubo_load: {
668 /* This IR node takes a constant uniform block and a constant or
669 * variable byte offset within the block and loads a vector from that.
670 */
671 ir_constant *uniform_block = ir->operands[0]->as_constant();
672 ir_constant *const_offset = ir->operands[1]->as_constant();
673 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
674 if (const_offset) {
675 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
676 packed_consts.type = result.type;
677
678 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
679 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
680 packed_consts, surf_index, const_offset_reg));
681
682 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
683 for (int i = 0; i < ir->type->vector_elements; i++) {
684 /* UBO bools are any nonzero value. We consider bools to be
685 * values with the low bit set to 1. Convert them using CMP.
686 */
687 if (ir->type->base_type == GLSL_TYPE_BOOL) {
688 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
689 } else {
690 emit(MOV(result, packed_consts));
691 }
692
693 packed_consts.smear++;
694 result.reg_offset++;
695
696 /* The std140 packing rules don't allow vectors to cross 16-byte
697 * boundaries, and a reg is 32 bytes.
698 */
699 assert(packed_consts.smear < 8);
700 }
701 } else {
702 /* Turn the byte offset into a dword offset. */
703 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
704 emit(SHR(base_offset, op[1], fs_reg(2)));
705
706 for (int i = 0; i < ir->type->vector_elements; i++) {
707 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
708 base_offset, i));
709
710 if (ir->type->base_type == GLSL_TYPE_BOOL)
711 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
712
713 result.reg_offset++;
714 }
715 }
716
717 result.reg_offset = 0;
718 break;
719 }
720
721 case ir_triop_fma:
722 /* Note that the instruction's argument order is reversed from GLSL
723 * and the IR.
724 */
725 emit(MAD(this->result, op[2], op[1], op[0]));
726 break;
727
728 case ir_triop_lrp:
729 emit_lrp(this->result, op[0], op[1], op[2]);
730 break;
731
732 case ir_triop_csel:
733 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
734 inst = emit(BRW_OPCODE_SEL, this->result, op[1], op[2]);
735 inst->predicate = BRW_PREDICATE_NORMAL;
736 break;
737 }
738 }
739
740 void
741 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
742 const glsl_type *type, bool predicated)
743 {
744 switch (type->base_type) {
745 case GLSL_TYPE_FLOAT:
746 case GLSL_TYPE_UINT:
747 case GLSL_TYPE_INT:
748 case GLSL_TYPE_BOOL:
749 for (unsigned int i = 0; i < type->components(); i++) {
750 l.type = brw_type_for_base_type(type);
751 r.type = brw_type_for_base_type(type);
752
753 if (predicated || !l.equals(r)) {
754 fs_inst *inst = emit(MOV(l, r));
755 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
756 }
757
758 l.reg_offset++;
759 r.reg_offset++;
760 }
761 break;
762 case GLSL_TYPE_ARRAY:
763 for (unsigned int i = 0; i < type->length; i++) {
764 emit_assignment_writes(l, r, type->fields.array, predicated);
765 }
766 break;
767
768 case GLSL_TYPE_STRUCT:
769 for (unsigned int i = 0; i < type->length; i++) {
770 emit_assignment_writes(l, r, type->fields.structure[i].type,
771 predicated);
772 }
773 break;
774
775 case GLSL_TYPE_SAMPLER:
776 break;
777
778 case GLSL_TYPE_VOID:
779 case GLSL_TYPE_ERROR:
780 case GLSL_TYPE_INTERFACE:
781 assert(!"not reached");
782 break;
783 }
784 }
785
786 /* If the RHS processing resulted in an instruction generating a
787 * temporary value, and it would be easy to rewrite the instruction to
788 * generate its result right into the LHS instead, do so. This ends
789 * up reliably removing instructions where it can be tricky to do so
790 * later without real UD chain information.
791 */
792 bool
793 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
794 fs_reg dst,
795 fs_reg src,
796 fs_inst *pre_rhs_inst,
797 fs_inst *last_rhs_inst)
798 {
799 /* Only attempt if we're doing a direct assignment. */
800 if (ir->condition ||
801 !(ir->lhs->type->is_scalar() ||
802 (ir->lhs->type->is_vector() &&
803 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
804 return false;
805
806 /* Make sure the last instruction generated our source reg. */
807 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
808 last_rhs_inst,
809 src);
810 if (!modify)
811 return false;
812
813 /* If last_rhs_inst wrote a different number of components than our LHS,
814 * we can't safely rewrite it.
815 */
816 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
817 return false;
818
819 /* Success! Rewrite the instruction. */
820 modify->dst = dst;
821
822 return true;
823 }
824
825 void
826 fs_visitor::visit(ir_assignment *ir)
827 {
828 fs_reg l, r;
829 fs_inst *inst;
830
831 /* FINISHME: arrays on the lhs */
832 ir->lhs->accept(this);
833 l = this->result;
834
835 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
836
837 ir->rhs->accept(this);
838 r = this->result;
839
840 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
841
842 assert(l.file != BAD_FILE);
843 assert(r.file != BAD_FILE);
844
845 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
846 return;
847
848 if (ir->condition) {
849 emit_bool_to_cond_code(ir->condition);
850 }
851
852 if (ir->lhs->type->is_scalar() ||
853 ir->lhs->type->is_vector()) {
854 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
855 if (ir->write_mask & (1 << i)) {
856 inst = emit(MOV(l, r));
857 if (ir->condition)
858 inst->predicate = BRW_PREDICATE_NORMAL;
859 r.reg_offset++;
860 }
861 l.reg_offset++;
862 }
863 } else {
864 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
865 }
866 }
867
868 fs_inst *
869 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
870 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
871 {
872 int mlen;
873 int base_mrf = 1;
874 bool simd16 = false;
875 fs_reg orig_dst;
876
877 /* g0 header. */
878 mlen = 1;
879
880 if (ir->shadow_comparitor) {
881 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
882 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
883 coordinate.reg_offset++;
884 }
885
886 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
887 * the unused slots must be zeroed.
888 */
889 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
890 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
891 }
892 mlen += 3;
893
894 if (ir->op == ir_tex) {
895 /* There's no plain shadow compare message, so we use shadow
896 * compare with a bias of 0.0.
897 */
898 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
899 mlen++;
900 } else if (ir->op == ir_txb || ir->op == ir_txl) {
901 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
902 mlen++;
903 } else {
904 assert(!"Should not get here.");
905 }
906
907 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
908 mlen++;
909 } else if (ir->op == ir_tex) {
910 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
911 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
912 coordinate.reg_offset++;
913 }
914 /* zero the others. */
915 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
916 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
917 }
918 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
919 mlen += 3;
920 } else if (ir->op == ir_txd) {
921 fs_reg &dPdx = lod;
922
923 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
924 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
925 coordinate.reg_offset++;
926 }
927 /* the slots for u and v are always present, but r is optional */
928 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
929
930 /* P = u, v, r
931 * dPdx = dudx, dvdx, drdx
932 * dPdy = dudy, dvdy, drdy
933 *
934 * 1-arg: Does not exist.
935 *
936 * 2-arg: dudx dvdx dudy dvdy
937 * dPdx.x dPdx.y dPdy.x dPdy.y
938 * m4 m5 m6 m7
939 *
940 * 3-arg: dudx dvdx drdx dudy dvdy drdy
941 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
942 * m5 m6 m7 m8 m9 m10
943 */
944 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
945 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
946 dPdx.reg_offset++;
947 }
948 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
949
950 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
951 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
952 dPdy.reg_offset++;
953 }
954 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
955 } else if (ir->op == ir_txs) {
956 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
957 simd16 = true;
958 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
959 mlen += 2;
960 } else {
961 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
962 * instructions. We'll need to do SIMD16 here.
963 */
964 simd16 = true;
965 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
966
967 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
968 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
969 coordinate));
970 coordinate.reg_offset++;
971 }
972
973 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
974 * be necessary for TXF (ld), but seems wise to do for all messages.
975 */
976 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
977 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
978 }
979
980 /* lod/bias appears after u/v/r. */
981 mlen += 6;
982
983 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
984 mlen++;
985
986 /* The unused upper half. */
987 mlen++;
988 }
989
990 if (simd16) {
991 /* Now, since we're doing simd16, the return is 2 interleaved
992 * vec4s where the odd-indexed ones are junk. We'll need to move
993 * this weirdness around to the expected layout.
994 */
995 orig_dst = dst;
996 dst = fs_reg(GRF, virtual_grf_alloc(8),
997 (brw->is_g4x ?
998 brw_type_for_base_type(ir->type) :
999 BRW_REGISTER_TYPE_F));
1000 }
1001
1002 fs_inst *inst = NULL;
1003 switch (ir->op) {
1004 case ir_tex:
1005 inst = emit(SHADER_OPCODE_TEX, dst);
1006 break;
1007 case ir_txb:
1008 inst = emit(FS_OPCODE_TXB, dst);
1009 break;
1010 case ir_txl:
1011 inst = emit(SHADER_OPCODE_TXL, dst);
1012 break;
1013 case ir_txd:
1014 inst = emit(SHADER_OPCODE_TXD, dst);
1015 break;
1016 case ir_txs:
1017 inst = emit(SHADER_OPCODE_TXS, dst);
1018 break;
1019 case ir_txf:
1020 inst = emit(SHADER_OPCODE_TXF, dst);
1021 break;
1022 default:
1023 fail("unrecognized texture opcode");
1024 }
1025 inst->base_mrf = base_mrf;
1026 inst->mlen = mlen;
1027 inst->header_present = true;
1028 inst->regs_written = simd16 ? 8 : 4;
1029
1030 if (simd16) {
1031 for (int i = 0; i < 4; i++) {
1032 emit(MOV(orig_dst, dst));
1033 orig_dst.reg_offset++;
1034 dst.reg_offset += 2;
1035 }
1036 }
1037
1038 return inst;
1039 }
1040
1041 /* gen5's sampler has slots for u, v, r, array index, then optional
1042 * parameters like shadow comparitor or LOD bias. If optional
1043 * parameters aren't present, those base slots are optional and don't
1044 * need to be included in the message.
1045 *
1046 * We don't fill in the unnecessary slots regardless, which may look
1047 * surprising in the disassembly.
1048 */
1049 fs_inst *
1050 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1051 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1052 fs_reg sample_index)
1053 {
1054 int mlen = 0;
1055 int base_mrf = 2;
1056 int reg_width = dispatch_width / 8;
1057 bool header_present = false;
1058 const int vector_elements =
1059 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1060
1061 if (ir->offset != NULL && ir->op == ir_txf) {
1062 /* It appears that the ld instruction used for txf does its
1063 * address bounds check before adding in the offset. To work
1064 * around this, just add the integer offset to the integer texel
1065 * coordinate, and don't put the offset in the header.
1066 */
1067 ir_constant *offset = ir->offset->as_constant();
1068 for (int i = 0; i < vector_elements; i++) {
1069 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1070 coordinate,
1071 offset->value.i[i]));
1072 coordinate.reg_offset++;
1073 }
1074 } else {
1075 if (ir->offset) {
1076 /* The offsets set up by the ir_texture visitor are in the
1077 * m1 header, so we can't go headerless.
1078 */
1079 header_present = true;
1080 mlen++;
1081 base_mrf--;
1082 }
1083
1084 for (int i = 0; i < vector_elements; i++) {
1085 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1086 coordinate));
1087 coordinate.reg_offset++;
1088 }
1089 }
1090 mlen += vector_elements * reg_width;
1091
1092 if (ir->shadow_comparitor) {
1093 mlen = MAX2(mlen, header_present + 4 * reg_width);
1094
1095 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1096 mlen += reg_width;
1097 }
1098
1099 fs_inst *inst = NULL;
1100 switch (ir->op) {
1101 case ir_tex:
1102 inst = emit(SHADER_OPCODE_TEX, dst);
1103 break;
1104 case ir_txb:
1105 mlen = MAX2(mlen, header_present + 4 * reg_width);
1106 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1107 mlen += reg_width;
1108
1109 inst = emit(FS_OPCODE_TXB, dst);
1110 break;
1111 case ir_txl:
1112 mlen = MAX2(mlen, header_present + 4 * reg_width);
1113 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1114 mlen += reg_width;
1115
1116 inst = emit(SHADER_OPCODE_TXL, dst);
1117 break;
1118 case ir_txd: {
1119 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1120
1121 /**
1122 * P = u, v, r
1123 * dPdx = dudx, dvdx, drdx
1124 * dPdy = dudy, dvdy, drdy
1125 *
1126 * Load up these values:
1127 * - dudx dudy dvdx dvdy drdx drdy
1128 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1129 */
1130 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1131 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1132 lod.reg_offset++;
1133 mlen += reg_width;
1134
1135 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1136 lod2.reg_offset++;
1137 mlen += reg_width;
1138 }
1139
1140 inst = emit(SHADER_OPCODE_TXD, dst);
1141 break;
1142 }
1143 case ir_txs:
1144 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1145 mlen += reg_width;
1146 inst = emit(SHADER_OPCODE_TXS, dst);
1147 break;
1148 case ir_txf:
1149 mlen = header_present + 4 * reg_width;
1150 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1151 inst = emit(SHADER_OPCODE_TXF, dst);
1152 break;
1153 case ir_txf_ms:
1154 mlen = header_present + 4 * reg_width;
1155
1156 /* lod */
1157 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1158 /* sample index */
1159 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1160 mlen += reg_width;
1161 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1162 break;
1163 case ir_lod:
1164 inst = emit(SHADER_OPCODE_LOD, dst);
1165 break;
1166 }
1167 inst->base_mrf = base_mrf;
1168 inst->mlen = mlen;
1169 inst->header_present = header_present;
1170 inst->regs_written = 4;
1171
1172 if (mlen > 11) {
1173 fail("Message length >11 disallowed by hardware\n");
1174 }
1175
1176 return inst;
1177 }
1178
1179 fs_inst *
1180 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1181 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1182 fs_reg sample_index)
1183 {
1184 int mlen = 0;
1185 int base_mrf = 2;
1186 int reg_width = dispatch_width / 8;
1187 bool header_present = false;
1188 int offsets[3];
1189
1190 if (ir->offset && ir->op != ir_txf) {
1191 /* The offsets set up by the ir_texture visitor are in the
1192 * m1 header, so we can't go headerless.
1193 */
1194 header_present = true;
1195 mlen++;
1196 base_mrf--;
1197 }
1198
1199 if (ir->shadow_comparitor) {
1200 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1201 mlen += reg_width;
1202 }
1203
1204 /* Set up the LOD info */
1205 switch (ir->op) {
1206 case ir_tex:
1207 case ir_lod:
1208 break;
1209 case ir_txb:
1210 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1211 mlen += reg_width;
1212 break;
1213 case ir_txl:
1214 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1215 mlen += reg_width;
1216 break;
1217 case ir_txd: {
1218 if (dispatch_width == 16)
1219 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1220
1221 /* Load dPdx and the coordinate together:
1222 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1223 */
1224 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1225 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1226 coordinate.reg_offset++;
1227 mlen += reg_width;
1228
1229 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1230 * only derivatives for (u, v, r).
1231 */
1232 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1233 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1234 lod.reg_offset++;
1235 mlen += reg_width;
1236
1237 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1238 lod2.reg_offset++;
1239 mlen += reg_width;
1240 }
1241 }
1242 break;
1243 }
1244 case ir_txs:
1245 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1246 mlen += reg_width;
1247 break;
1248 case ir_txf:
1249 /* It appears that the ld instruction used for txf does its
1250 * address bounds check before adding in the offset. To work
1251 * around this, just add the integer offset to the integer texel
1252 * coordinate, and don't put the offset in the header.
1253 */
1254 if (ir->offset) {
1255 ir_constant *offset = ir->offset->as_constant();
1256 offsets[0] = offset->value.i[0];
1257 offsets[1] = offset->value.i[1];
1258 offsets[2] = offset->value.i[2];
1259 } else {
1260 memset(offsets, 0, sizeof(offsets));
1261 }
1262
1263 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1264 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1265 coordinate, offsets[0]));
1266 coordinate.reg_offset++;
1267 mlen += reg_width;
1268
1269 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1270 mlen += reg_width;
1271
1272 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1273 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1274 coordinate, offsets[i]));
1275 coordinate.reg_offset++;
1276 mlen += reg_width;
1277 }
1278 break;
1279 case ir_txf_ms:
1280 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1281 mlen += reg_width;
1282
1283 /* constant zero MCS; we arrange to never actually have a compressed
1284 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1285 * if we ever support texturing from compressed multisample surfaces
1286 */
1287 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1288 mlen += reg_width;
1289
1290 /* there is no offsetting for this message; just copy in the integer
1291 * texture coordinates
1292 */
1293 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1294 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1295 coordinate));
1296 coordinate.reg_offset++;
1297 mlen += reg_width;
1298 }
1299 break;
1300 }
1301
1302 /* Set up the coordinate (except for cases where it was done above) */
1303 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
1304 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1305 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1306 coordinate.reg_offset++;
1307 mlen += reg_width;
1308 }
1309 }
1310
1311 /* Generate the SEND */
1312 fs_inst *inst = NULL;
1313 switch (ir->op) {
1314 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1315 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1316 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1317 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1318 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1319 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1320 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1321 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1322 }
1323 inst->base_mrf = base_mrf;
1324 inst->mlen = mlen;
1325 inst->header_present = header_present;
1326 inst->regs_written = 4;
1327
1328 if (mlen > 11) {
1329 fail("Message length >11 disallowed by hardware\n");
1330 }
1331
1332 return inst;
1333 }
1334
1335 fs_reg
1336 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1337 bool is_rect, int sampler, int texunit)
1338 {
1339 fs_inst *inst = NULL;
1340 bool needs_gl_clamp = true;
1341 fs_reg scale_x, scale_y;
1342
1343 /* The 965 requires the EU to do the normalization of GL rectangle
1344 * texture coordinates. We use the program parameter state
1345 * tracking to get the scaling factor.
1346 */
1347 if (is_rect &&
1348 (brw->gen < 6 ||
1349 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1350 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1351 struct gl_program_parameter_list *params = fp->Base.Parameters;
1352 int tokens[STATE_LENGTH] = {
1353 STATE_INTERNAL,
1354 STATE_TEXRECT_SCALE,
1355 texunit,
1356 0,
1357 0
1358 };
1359
1360 if (dispatch_width == 16) {
1361 fail("rectangle scale uniform setup not supported on 16-wide\n");
1362 return coordinate;
1363 }
1364
1365 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1366 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1367
1368 GLuint index = _mesa_add_state_reference(params,
1369 (gl_state_index *)tokens);
1370 c->prog_data.param[c->prog_data.nr_params++] =
1371 &fp->Base.Parameters->ParameterValues[index][0].f;
1372 c->prog_data.param[c->prog_data.nr_params++] =
1373 &fp->Base.Parameters->ParameterValues[index][1].f;
1374 }
1375
1376 /* The 965 requires the EU to do the normalization of GL rectangle
1377 * texture coordinates. We use the program parameter state
1378 * tracking to get the scaling factor.
1379 */
1380 if (brw->gen < 6 && is_rect) {
1381 fs_reg dst = fs_reg(this, ir->coordinate->type);
1382 fs_reg src = coordinate;
1383 coordinate = dst;
1384
1385 emit(MUL(dst, src, scale_x));
1386 dst.reg_offset++;
1387 src.reg_offset++;
1388 emit(MUL(dst, src, scale_y));
1389 } else if (is_rect) {
1390 /* On gen6+, the sampler handles the rectangle coordinates
1391 * natively, without needing rescaling. But that means we have
1392 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1393 * not [0, 1] like the default case below.
1394 */
1395 needs_gl_clamp = false;
1396
1397 for (int i = 0; i < 2; i++) {
1398 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1399 fs_reg chan = coordinate;
1400 chan.reg_offset += i;
1401
1402 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1403 inst->conditional_mod = BRW_CONDITIONAL_G;
1404
1405 /* Our parameter comes in as 1.0/width or 1.0/height,
1406 * because that's what people normally want for doing
1407 * texture rectangle handling. We need width or height
1408 * for clamping, but we don't care enough to make a new
1409 * parameter type, so just invert back.
1410 */
1411 fs_reg limit = fs_reg(this, glsl_type::float_type);
1412 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1413 emit(SHADER_OPCODE_RCP, limit, limit);
1414
1415 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1416 inst->conditional_mod = BRW_CONDITIONAL_L;
1417 }
1418 }
1419 }
1420
1421 if (ir->coordinate && needs_gl_clamp) {
1422 for (unsigned int i = 0;
1423 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1424 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1425 fs_reg chan = coordinate;
1426 chan.reg_offset += i;
1427
1428 fs_inst *inst = emit(MOV(chan, chan));
1429 inst->saturate = true;
1430 }
1431 }
1432 }
1433 return coordinate;
1434 }
1435
1436 void
1437 fs_visitor::visit(ir_texture *ir)
1438 {
1439 fs_inst *inst = NULL;
1440
1441 int sampler =
1442 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1443 /* FINISHME: We're failing to recompile our programs when the sampler is
1444 * updated. This only matters for the texture rectangle scale parameters
1445 * (pre-gen6, or gen6+ with GL_CLAMP).
1446 */
1447 int texunit = fp->Base.SamplerUnits[sampler];
1448
1449 /* Should be lowered by do_lower_texture_projection */
1450 assert(!ir->projector);
1451
1452 /* Generate code to compute all the subexpression trees. This has to be
1453 * done before loading any values into MRFs for the sampler message since
1454 * generating these values may involve SEND messages that need the MRFs.
1455 */
1456 fs_reg coordinate;
1457 if (ir->coordinate) {
1458 ir->coordinate->accept(this);
1459
1460 coordinate = rescale_texcoord(ir, this->result,
1461 ir->sampler->type->sampler_dimensionality ==
1462 GLSL_SAMPLER_DIM_RECT,
1463 sampler, texunit);
1464 }
1465
1466 fs_reg shadow_comparitor;
1467 if (ir->shadow_comparitor) {
1468 ir->shadow_comparitor->accept(this);
1469 shadow_comparitor = this->result;
1470 }
1471
1472 fs_reg lod, lod2, sample_index;
1473 switch (ir->op) {
1474 case ir_tex:
1475 case ir_lod:
1476 break;
1477 case ir_txb:
1478 ir->lod_info.bias->accept(this);
1479 lod = this->result;
1480 break;
1481 case ir_txd:
1482 ir->lod_info.grad.dPdx->accept(this);
1483 lod = this->result;
1484
1485 ir->lod_info.grad.dPdy->accept(this);
1486 lod2 = this->result;
1487 break;
1488 case ir_txf:
1489 case ir_txl:
1490 case ir_txs:
1491 ir->lod_info.lod->accept(this);
1492 lod = this->result;
1493 break;
1494 case ir_txf_ms:
1495 ir->lod_info.sample_index->accept(this);
1496 sample_index = this->result;
1497 break;
1498 };
1499
1500 /* Writemasking doesn't eliminate channels on SIMD8 texture
1501 * samples, so don't worry about them.
1502 */
1503 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1504
1505 if (brw->gen >= 7) {
1506 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1507 lod, lod2, sample_index);
1508 } else if (brw->gen >= 5) {
1509 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1510 lod, lod2, sample_index);
1511 } else {
1512 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1513 lod, lod2);
1514 }
1515
1516 /* The header is set up by generate_tex() when necessary. */
1517 inst->src[0] = reg_undef;
1518
1519 if (ir->offset != NULL && ir->op != ir_txf)
1520 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1521
1522 inst->sampler = sampler;
1523
1524 if (ir->shadow_comparitor)
1525 inst->shadow_compare = true;
1526
1527 /* fixup #layers for cube map arrays */
1528 if (ir->op == ir_txs) {
1529 glsl_type const *type = ir->sampler->type;
1530 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1531 type->sampler_array) {
1532 fs_reg depth = dst;
1533 depth.reg_offset = 2;
1534 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1535 }
1536 }
1537
1538 swizzle_result(ir, dst, sampler);
1539 }
1540
1541 /**
1542 * Swizzle the result of a texture result. This is necessary for
1543 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1544 */
1545 void
1546 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1547 {
1548 this->result = orig_val;
1549
1550 if (ir->op == ir_txs || ir->op == ir_lod)
1551 return;
1552
1553 if (ir->type == glsl_type::float_type) {
1554 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1555 assert(ir->sampler->type->sampler_shadow);
1556 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1557 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1558
1559 for (int i = 0; i < 4; i++) {
1560 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1561 fs_reg l = swizzled_result;
1562 l.reg_offset += i;
1563
1564 if (swiz == SWIZZLE_ZERO) {
1565 emit(MOV(l, fs_reg(0.0f)));
1566 } else if (swiz == SWIZZLE_ONE) {
1567 emit(MOV(l, fs_reg(1.0f)));
1568 } else {
1569 fs_reg r = orig_val;
1570 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1571 emit(MOV(l, r));
1572 }
1573 }
1574 this->result = swizzled_result;
1575 }
1576 }
1577
1578 void
1579 fs_visitor::visit(ir_swizzle *ir)
1580 {
1581 ir->val->accept(this);
1582 fs_reg val = this->result;
1583
1584 if (ir->type->vector_elements == 1) {
1585 this->result.reg_offset += ir->mask.x;
1586 return;
1587 }
1588
1589 fs_reg result = fs_reg(this, ir->type);
1590 this->result = result;
1591
1592 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1593 fs_reg channel = val;
1594 int swiz = 0;
1595
1596 switch (i) {
1597 case 0:
1598 swiz = ir->mask.x;
1599 break;
1600 case 1:
1601 swiz = ir->mask.y;
1602 break;
1603 case 2:
1604 swiz = ir->mask.z;
1605 break;
1606 case 3:
1607 swiz = ir->mask.w;
1608 break;
1609 }
1610
1611 channel.reg_offset += swiz;
1612 emit(MOV(result, channel));
1613 result.reg_offset++;
1614 }
1615 }
1616
1617 void
1618 fs_visitor::visit(ir_discard *ir)
1619 {
1620 assert(ir->condition == NULL); /* FINISHME */
1621
1622 /* We track our discarded pixels in f0.1. By predicating on it, we can
1623 * update just the flag bits that aren't yet discarded. By emitting a
1624 * CMP of g0 != g0, all our currently executing channels will get turned
1625 * off.
1626 */
1627 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1628 BRW_REGISTER_TYPE_UW));
1629 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1630 BRW_CONDITIONAL_NZ));
1631 cmp->predicate = BRW_PREDICATE_NORMAL;
1632 cmp->flag_subreg = 1;
1633
1634 if (brw->gen >= 6) {
1635 /* For performance, after a discard, jump to the end of the shader.
1636 * However, many people will do foliage by discarding based on a
1637 * texture's alpha mask, and then continue on to texture with the
1638 * remaining pixels. To avoid trashing the derivatives for those
1639 * texture samples, we'll only jump if all of the pixels in the subspan
1640 * have been discarded.
1641 */
1642 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1643 discard_jump->flag_subreg = 1;
1644 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1645 discard_jump->predicate_inverse = true;
1646 }
1647 }
1648
1649 void
1650 fs_visitor::visit(ir_constant *ir)
1651 {
1652 /* Set this->result to reg at the bottom of the function because some code
1653 * paths will cause this visitor to be applied to other fields. This will
1654 * cause the value stored in this->result to be modified.
1655 *
1656 * Make reg constant so that it doesn't get accidentally modified along the
1657 * way. Yes, I actually had this problem. :(
1658 */
1659 const fs_reg reg(this, ir->type);
1660 fs_reg dst_reg = reg;
1661
1662 if (ir->type->is_array()) {
1663 const unsigned size = type_size(ir->type->fields.array);
1664
1665 for (unsigned i = 0; i < ir->type->length; i++) {
1666 ir->array_elements[i]->accept(this);
1667 fs_reg src_reg = this->result;
1668
1669 dst_reg.type = src_reg.type;
1670 for (unsigned j = 0; j < size; j++) {
1671 emit(MOV(dst_reg, src_reg));
1672 src_reg.reg_offset++;
1673 dst_reg.reg_offset++;
1674 }
1675 }
1676 } else if (ir->type->is_record()) {
1677 foreach_list(node, &ir->components) {
1678 ir_constant *const field = (ir_constant *) node;
1679 const unsigned size = type_size(field->type);
1680
1681 field->accept(this);
1682 fs_reg src_reg = this->result;
1683
1684 dst_reg.type = src_reg.type;
1685 for (unsigned j = 0; j < size; j++) {
1686 emit(MOV(dst_reg, src_reg));
1687 src_reg.reg_offset++;
1688 dst_reg.reg_offset++;
1689 }
1690 }
1691 } else {
1692 const unsigned size = type_size(ir->type);
1693
1694 for (unsigned i = 0; i < size; i++) {
1695 switch (ir->type->base_type) {
1696 case GLSL_TYPE_FLOAT:
1697 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1698 break;
1699 case GLSL_TYPE_UINT:
1700 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1701 break;
1702 case GLSL_TYPE_INT:
1703 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1704 break;
1705 case GLSL_TYPE_BOOL:
1706 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1707 break;
1708 default:
1709 assert(!"Non-float/uint/int/bool constant");
1710 }
1711 dst_reg.reg_offset++;
1712 }
1713 }
1714
1715 this->result = reg;
1716 }
1717
1718 void
1719 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1720 {
1721 ir_expression *expr = ir->as_expression();
1722
1723 if (expr) {
1724 fs_reg op[2];
1725 fs_inst *inst;
1726
1727 assert(expr->get_num_operands() <= 2);
1728 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1729 assert(expr->operands[i]->type->is_scalar());
1730
1731 expr->operands[i]->accept(this);
1732 op[i] = this->result;
1733
1734 resolve_ud_negate(&op[i]);
1735 }
1736
1737 switch (expr->operation) {
1738 case ir_unop_logic_not:
1739 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1740 inst->conditional_mod = BRW_CONDITIONAL_Z;
1741 break;
1742
1743 case ir_binop_logic_xor:
1744 case ir_binop_logic_or:
1745 case ir_binop_logic_and:
1746 goto out;
1747
1748 case ir_unop_f2b:
1749 if (brw->gen >= 6) {
1750 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1751 } else {
1752 inst = emit(MOV(reg_null_f, op[0]));
1753 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1754 }
1755 break;
1756
1757 case ir_unop_i2b:
1758 if (brw->gen >= 6) {
1759 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1760 } else {
1761 inst = emit(MOV(reg_null_d, op[0]));
1762 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1763 }
1764 break;
1765
1766 case ir_binop_greater:
1767 case ir_binop_gequal:
1768 case ir_binop_less:
1769 case ir_binop_lequal:
1770 case ir_binop_equal:
1771 case ir_binop_all_equal:
1772 case ir_binop_nequal:
1773 case ir_binop_any_nequal:
1774 resolve_bool_comparison(expr->operands[0], &op[0]);
1775 resolve_bool_comparison(expr->operands[1], &op[1]);
1776
1777 emit(CMP(reg_null_d, op[0], op[1],
1778 brw_conditional_for_comparison(expr->operation)));
1779 break;
1780
1781 default:
1782 assert(!"not reached");
1783 fail("bad cond code\n");
1784 break;
1785 }
1786 return;
1787 }
1788
1789 out:
1790 ir->accept(this);
1791
1792 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1793 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1794 }
1795
1796 /**
1797 * Emit a gen6 IF statement with the comparison folded into the IF
1798 * instruction.
1799 */
1800 void
1801 fs_visitor::emit_if_gen6(ir_if *ir)
1802 {
1803 ir_expression *expr = ir->condition->as_expression();
1804
1805 if (expr) {
1806 fs_reg op[2];
1807 fs_inst *inst;
1808 fs_reg temp;
1809
1810 assert(expr->get_num_operands() <= 2);
1811 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1812 assert(expr->operands[i]->type->is_scalar());
1813
1814 expr->operands[i]->accept(this);
1815 op[i] = this->result;
1816 }
1817
1818 switch (expr->operation) {
1819 case ir_unop_logic_not:
1820 case ir_binop_logic_xor:
1821 case ir_binop_logic_or:
1822 case ir_binop_logic_and:
1823 /* For operations on bool arguments, only the low bit of the bool is
1824 * valid, and the others are undefined. Fall back to the condition
1825 * code path.
1826 */
1827 break;
1828
1829 case ir_unop_f2b:
1830 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1831 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1832 return;
1833
1834 case ir_unop_i2b:
1835 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1836 return;
1837
1838 case ir_binop_greater:
1839 case ir_binop_gequal:
1840 case ir_binop_less:
1841 case ir_binop_lequal:
1842 case ir_binop_equal:
1843 case ir_binop_all_equal:
1844 case ir_binop_nequal:
1845 case ir_binop_any_nequal:
1846 resolve_bool_comparison(expr->operands[0], &op[0]);
1847 resolve_bool_comparison(expr->operands[1], &op[1]);
1848
1849 emit(IF(op[0], op[1],
1850 brw_conditional_for_comparison(expr->operation)));
1851 return;
1852 default:
1853 assert(!"not reached");
1854 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1855 fail("bad condition\n");
1856 return;
1857 }
1858 }
1859
1860 emit_bool_to_cond_code(ir->condition);
1861 fs_inst *inst = emit(BRW_OPCODE_IF);
1862 inst->predicate = BRW_PREDICATE_NORMAL;
1863 }
1864
1865 /**
1866 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1867 *
1868 * Many GLSL shaders contain the following pattern:
1869 *
1870 * x = condition ? foo : bar
1871 *
1872 * The compiler emits an ir_if tree for this, since each subexpression might be
1873 * a complex tree that could have side-effects or short-circuit logic.
1874 *
1875 * However, the common case is to simply select one of two constants or
1876 * variable values---which is exactly what SEL is for. In this case, the
1877 * assembly looks like:
1878 *
1879 * (+f0) IF
1880 * MOV dst src0
1881 * ELSE
1882 * MOV dst src1
1883 * ENDIF
1884 *
1885 * which can be easily translated into:
1886 *
1887 * (+f0) SEL dst src0 src1
1888 *
1889 * If src0 is an immediate value, we promote it to a temporary GRF.
1890 */
1891 void
1892 fs_visitor::try_replace_with_sel()
1893 {
1894 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1895 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1896
1897 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1898 int opcodes[] = {
1899 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1900 };
1901
1902 fs_inst *match = (fs_inst *) endif_inst->prev;
1903 for (int i = 0; i < 4; i++) {
1904 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1905 return;
1906 match = (fs_inst *) match->prev;
1907 }
1908
1909 /* The opcodes match; it looks like the right sequence of instructions. */
1910 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1911 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1912 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1913
1914 /* Check that the MOVs are the right form. */
1915 if (then_mov->dst.equals(else_mov->dst) &&
1916 !then_mov->is_partial_write() &&
1917 !else_mov->is_partial_write()) {
1918
1919 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1920 while (!if_inst->next->is_tail_sentinel())
1921 if_inst->next->remove();
1922 if_inst->remove();
1923
1924 /* Only the last source register can be a constant, so if the MOV in
1925 * the "then" clause uses a constant, we need to put it in a temporary.
1926 */
1927 fs_reg src0(then_mov->src[0]);
1928 if (src0.file == IMM) {
1929 src0 = fs_reg(this, glsl_type::float_type);
1930 src0.type = then_mov->src[0].type;
1931 emit(MOV(src0, then_mov->src[0]));
1932 }
1933
1934 fs_inst *sel;
1935 if (if_inst->conditional_mod) {
1936 /* Sandybridge-specific IF with embedded comparison */
1937 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
1938 if_inst->conditional_mod));
1939 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1940 sel->predicate = BRW_PREDICATE_NORMAL;
1941 } else {
1942 /* Separate CMP and IF instructions */
1943 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1944 sel->predicate = if_inst->predicate;
1945 sel->predicate_inverse = if_inst->predicate_inverse;
1946 }
1947 }
1948 }
1949
1950 void
1951 fs_visitor::visit(ir_if *ir)
1952 {
1953 if (brw->gen < 6 && dispatch_width == 16) {
1954 fail("Can't support (non-uniform) control flow on 16-wide\n");
1955 }
1956
1957 /* Don't point the annotation at the if statement, because then it plus
1958 * the then and else blocks get printed.
1959 */
1960 this->base_ir = ir->condition;
1961
1962 if (brw->gen == 6) {
1963 emit_if_gen6(ir);
1964 } else {
1965 emit_bool_to_cond_code(ir->condition);
1966
1967 emit(IF(BRW_PREDICATE_NORMAL));
1968 }
1969
1970 foreach_list(node, &ir->then_instructions) {
1971 ir_instruction *ir = (ir_instruction *)node;
1972 this->base_ir = ir;
1973
1974 ir->accept(this);
1975 }
1976
1977 if (!ir->else_instructions.is_empty()) {
1978 emit(BRW_OPCODE_ELSE);
1979
1980 foreach_list(node, &ir->else_instructions) {
1981 ir_instruction *ir = (ir_instruction *)node;
1982 this->base_ir = ir;
1983
1984 ir->accept(this);
1985 }
1986 }
1987
1988 emit(BRW_OPCODE_ENDIF);
1989
1990 try_replace_with_sel();
1991 }
1992
1993 void
1994 fs_visitor::visit(ir_loop *ir)
1995 {
1996 fs_reg counter = reg_undef;
1997
1998 if (brw->gen < 6 && dispatch_width == 16) {
1999 fail("Can't support (non-uniform) control flow on 16-wide\n");
2000 }
2001
2002 if (ir->counter) {
2003 this->base_ir = ir->counter;
2004 ir->counter->accept(this);
2005 counter = *(variable_storage(ir->counter));
2006
2007 if (ir->from) {
2008 this->base_ir = ir->from;
2009 ir->from->accept(this);
2010
2011 emit(MOV(counter, this->result));
2012 }
2013 }
2014
2015 this->base_ir = NULL;
2016 emit(BRW_OPCODE_DO);
2017
2018 if (ir->to) {
2019 this->base_ir = ir->to;
2020 ir->to->accept(this);
2021
2022 emit(CMP(reg_null_d, counter, this->result,
2023 brw_conditional_for_comparison(ir->cmp)));
2024
2025 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2026 inst->predicate = BRW_PREDICATE_NORMAL;
2027 }
2028
2029 foreach_list(node, &ir->body_instructions) {
2030 ir_instruction *ir = (ir_instruction *)node;
2031
2032 this->base_ir = ir;
2033 ir->accept(this);
2034 }
2035
2036 if (ir->increment) {
2037 this->base_ir = ir->increment;
2038 ir->increment->accept(this);
2039 emit(ADD(counter, counter, this->result));
2040 }
2041
2042 this->base_ir = NULL;
2043 emit(BRW_OPCODE_WHILE);
2044 }
2045
2046 void
2047 fs_visitor::visit(ir_loop_jump *ir)
2048 {
2049 switch (ir->mode) {
2050 case ir_loop_jump::jump_break:
2051 emit(BRW_OPCODE_BREAK);
2052 break;
2053 case ir_loop_jump::jump_continue:
2054 emit(BRW_OPCODE_CONTINUE);
2055 break;
2056 }
2057 }
2058
2059 void
2060 fs_visitor::visit(ir_call *ir)
2061 {
2062 assert(!"FINISHME");
2063 }
2064
2065 void
2066 fs_visitor::visit(ir_return *ir)
2067 {
2068 assert(!"FINISHME");
2069 }
2070
2071 void
2072 fs_visitor::visit(ir_function *ir)
2073 {
2074 /* Ignore function bodies other than main() -- we shouldn't see calls to
2075 * them since they should all be inlined before we get to ir_to_mesa.
2076 */
2077 if (strcmp(ir->name, "main") == 0) {
2078 const ir_function_signature *sig;
2079 exec_list empty;
2080
2081 sig = ir->matching_signature(NULL, &empty);
2082
2083 assert(sig);
2084
2085 foreach_list(node, &sig->body) {
2086 ir_instruction *ir = (ir_instruction *)node;
2087 this->base_ir = ir;
2088
2089 ir->accept(this);
2090 }
2091 }
2092 }
2093
2094 void
2095 fs_visitor::visit(ir_function_signature *ir)
2096 {
2097 assert(!"not reached");
2098 (void)ir;
2099 }
2100
2101 void
2102 fs_visitor::visit(ir_emit_vertex *)
2103 {
2104 assert(!"not reached");
2105 }
2106
2107 void
2108 fs_visitor::visit(ir_end_primitive *)
2109 {
2110 assert(!"not reached");
2111 }
2112
2113 fs_inst *
2114 fs_visitor::emit(fs_inst inst)
2115 {
2116 fs_inst *list_inst = new(mem_ctx) fs_inst;
2117 *list_inst = inst;
2118 emit(list_inst);
2119 return list_inst;
2120 }
2121
2122 fs_inst *
2123 fs_visitor::emit(fs_inst *inst)
2124 {
2125 if (force_uncompressed_stack > 0)
2126 inst->force_uncompressed = true;
2127 else if (force_sechalf_stack > 0)
2128 inst->force_sechalf = true;
2129
2130 inst->annotation = this->current_annotation;
2131 inst->ir = this->base_ir;
2132
2133 this->instructions.push_tail(inst);
2134
2135 return inst;
2136 }
2137
2138 void
2139 fs_visitor::emit(exec_list list)
2140 {
2141 foreach_list_safe(node, &list) {
2142 fs_inst *inst = (fs_inst *)node;
2143 inst->remove();
2144 emit(inst);
2145 }
2146 }
2147
2148 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2149 void
2150 fs_visitor::emit_dummy_fs()
2151 {
2152 int reg_width = dispatch_width / 8;
2153
2154 /* Everyone's favorite color. */
2155 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2156 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2157 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2158 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2159
2160 fs_inst *write;
2161 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2162 write->base_mrf = 2;
2163 write->mlen = 4 * reg_width;
2164 write->eot = true;
2165 }
2166
2167 /* The register location here is relative to the start of the URB
2168 * data. It will get adjusted to be a real location before
2169 * generate_code() time.
2170 */
2171 struct brw_reg
2172 fs_visitor::interp_reg(int location, int channel)
2173 {
2174 int regnr = c->prog_data.urb_setup[location] * 2 + channel / 2;
2175 int stride = (channel & 1) * 4;
2176
2177 assert(c->prog_data.urb_setup[location] != -1);
2178
2179 return brw_vec1_grf(regnr, stride);
2180 }
2181
2182 /** Emits the interpolation for the varying inputs. */
2183 void
2184 fs_visitor::emit_interpolation_setup_gen4()
2185 {
2186 this->current_annotation = "compute pixel centers";
2187 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2188 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2189 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2190 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2191
2192 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2193 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2194
2195 this->current_annotation = "compute pixel deltas from v0";
2196 if (brw->has_pln) {
2197 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2198 fs_reg(this, glsl_type::vec2_type);
2199 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2200 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2201 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2202 } else {
2203 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2204 fs_reg(this, glsl_type::float_type);
2205 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2206 fs_reg(this, glsl_type::float_type);
2207 }
2208 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2209 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2210 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2211 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2212
2213 this->current_annotation = "compute pos.w and 1/pos.w";
2214 /* Compute wpos.w. It's always in our setup, since it's needed to
2215 * interpolate the other attributes.
2216 */
2217 this->wpos_w = fs_reg(this, glsl_type::float_type);
2218 emit(FS_OPCODE_LINTERP, wpos_w,
2219 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2220 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2221 interp_reg(VARYING_SLOT_POS, 3));
2222 /* Compute the pixel 1/W value from wpos.w. */
2223 this->pixel_w = fs_reg(this, glsl_type::float_type);
2224 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2225 this->current_annotation = NULL;
2226 }
2227
2228 /** Emits the interpolation for the varying inputs. */
2229 void
2230 fs_visitor::emit_interpolation_setup_gen6()
2231 {
2232 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2233
2234 /* If the pixel centers end up used, the setup is the same as for gen4. */
2235 this->current_annotation = "compute pixel centers";
2236 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2237 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2238 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2239 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2240 emit(ADD(int_pixel_x,
2241 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2242 fs_reg(brw_imm_v(0x10101010))));
2243 emit(ADD(int_pixel_y,
2244 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2245 fs_reg(brw_imm_v(0x11001100))));
2246
2247 /* As of gen6, we can no longer mix float and int sources. We have
2248 * to turn the integer pixel centers into floats for their actual
2249 * use.
2250 */
2251 this->pixel_x = fs_reg(this, glsl_type::float_type);
2252 this->pixel_y = fs_reg(this, glsl_type::float_type);
2253 emit(MOV(this->pixel_x, int_pixel_x));
2254 emit(MOV(this->pixel_y, int_pixel_y));
2255
2256 this->current_annotation = "compute pos.w";
2257 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2258 this->wpos_w = fs_reg(this, glsl_type::float_type);
2259 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2260
2261 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2262 uint8_t reg = c->barycentric_coord_reg[i];
2263 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2264 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2265 }
2266
2267 this->current_annotation = NULL;
2268 }
2269
2270 void
2271 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2272 {
2273 int reg_width = dispatch_width / 8;
2274 fs_inst *inst;
2275 fs_reg color = outputs[target];
2276 fs_reg mrf;
2277
2278 /* If there's no color data to be written, skip it. */
2279 if (color.file == BAD_FILE)
2280 return;
2281
2282 color.reg_offset += index;
2283
2284 if (dispatch_width == 8 || brw->gen >= 6) {
2285 /* SIMD8 write looks like:
2286 * m + 0: r0
2287 * m + 1: r1
2288 * m + 2: g0
2289 * m + 3: g1
2290 *
2291 * gen6 SIMD16 DP write looks like:
2292 * m + 0: r0
2293 * m + 1: r1
2294 * m + 2: g0
2295 * m + 3: g1
2296 * m + 4: b0
2297 * m + 5: b1
2298 * m + 6: a0
2299 * m + 7: a1
2300 */
2301 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2302 color.type),
2303 color));
2304 inst->saturate = c->key.clamp_fragment_color;
2305 } else {
2306 /* pre-gen6 SIMD16 single source DP write looks like:
2307 * m + 0: r0
2308 * m + 1: g0
2309 * m + 2: b0
2310 * m + 3: a0
2311 * m + 4: r1
2312 * m + 5: g1
2313 * m + 6: b1
2314 * m + 7: a1
2315 */
2316 if (brw->has_compr4) {
2317 /* By setting the high bit of the MRF register number, we
2318 * indicate that we want COMPR4 mode - instead of doing the
2319 * usual destination + 1 for the second half we get
2320 * destination + 4.
2321 */
2322 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2323 color.type),
2324 color));
2325 inst->saturate = c->key.clamp_fragment_color;
2326 } else {
2327 push_force_uncompressed();
2328 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2329 color));
2330 inst->saturate = c->key.clamp_fragment_color;
2331 pop_force_uncompressed();
2332
2333 push_force_sechalf();
2334 color.sechalf = true;
2335 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2336 color));
2337 inst->saturate = c->key.clamp_fragment_color;
2338 pop_force_sechalf();
2339 color.sechalf = false;
2340 }
2341 }
2342 }
2343
2344 void
2345 fs_visitor::emit_fb_writes()
2346 {
2347 this->current_annotation = "FB write header";
2348 bool header_present = true;
2349 /* We can potentially have a message length of up to 15, so we have to set
2350 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2351 */
2352 int base_mrf = 1;
2353 int nr = base_mrf;
2354 int reg_width = dispatch_width / 8;
2355 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2356 bool src0_alpha_to_render_target = false;
2357
2358 if (dispatch_width == 16 && do_dual_src) {
2359 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2360 do_dual_src = false;
2361 }
2362
2363 /* From the Sandy Bridge PRM, volume 4, page 198:
2364 *
2365 * "Dispatched Pixel Enables. One bit per pixel indicating
2366 * which pixels were originally enabled when the thread was
2367 * dispatched. This field is only required for the end-of-
2368 * thread message and on all dual-source messages."
2369 */
2370 if (brw->gen >= 6 &&
2371 !this->fp->UsesKill &&
2372 !do_dual_src &&
2373 c->key.nr_color_regions == 1) {
2374 header_present = false;
2375 }
2376
2377 if (header_present) {
2378 src0_alpha_to_render_target = brw->gen >= 6 &&
2379 !do_dual_src &&
2380 c->key.replicate_alpha;
2381 /* m2, m3 header */
2382 nr += 2;
2383 }
2384
2385 if (c->aa_dest_stencil_reg) {
2386 push_force_uncompressed();
2387 emit(MOV(fs_reg(MRF, nr++),
2388 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2389 pop_force_uncompressed();
2390 }
2391
2392 /* Reserve space for color. It'll be filled in per MRT below. */
2393 int color_mrf = nr;
2394 nr += 4 * reg_width;
2395 if (do_dual_src)
2396 nr += 4;
2397 if (src0_alpha_to_render_target)
2398 nr += reg_width;
2399
2400 if (c->source_depth_to_render_target) {
2401 if (brw->gen == 6 && dispatch_width == 16) {
2402 /* For outputting oDepth on gen6, SIMD8 writes have to be
2403 * used. This would require 8-wide moves of each half to
2404 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2405 * Just bail on doing so for now.
2406 */
2407 fail("Missing support for simd16 depth writes on gen6\n");
2408 }
2409
2410 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2411 /* Hand over gl_FragDepth. */
2412 assert(this->frag_depth.file != BAD_FILE);
2413 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2414 } else {
2415 /* Pass through the payload depth. */
2416 emit(MOV(fs_reg(MRF, nr),
2417 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2418 }
2419 nr += reg_width;
2420 }
2421
2422 if (c->dest_depth_reg) {
2423 emit(MOV(fs_reg(MRF, nr),
2424 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2425 nr += reg_width;
2426 }
2427
2428 if (do_dual_src) {
2429 fs_reg src0 = this->outputs[0];
2430 fs_reg src1 = this->dual_src_output;
2431
2432 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2433 "FB write src0");
2434 for (int i = 0; i < 4; i++) {
2435 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2436 src0.reg_offset++;
2437 inst->saturate = c->key.clamp_fragment_color;
2438 }
2439
2440 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2441 "FB write src1");
2442 for (int i = 0; i < 4; i++) {
2443 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2444 src1));
2445 src1.reg_offset++;
2446 inst->saturate = c->key.clamp_fragment_color;
2447 }
2448
2449 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2450 emit_shader_time_end();
2451
2452 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2453 inst->target = 0;
2454 inst->base_mrf = base_mrf;
2455 inst->mlen = nr - base_mrf;
2456 inst->eot = true;
2457 inst->header_present = header_present;
2458
2459 c->prog_data.dual_src_blend = true;
2460 this->current_annotation = NULL;
2461 return;
2462 }
2463
2464 for (int target = 0; target < c->key.nr_color_regions; target++) {
2465 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2466 "FB write target %d",
2467 target);
2468 /* If src0_alpha_to_render_target is true, include source zero alpha
2469 * data in RenderTargetWrite message for targets > 0.
2470 */
2471 int write_color_mrf = color_mrf;
2472 if (src0_alpha_to_render_target && target != 0) {
2473 fs_inst *inst;
2474 fs_reg color = outputs[0];
2475 color.reg_offset += 3;
2476
2477 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2478 color));
2479 inst->saturate = c->key.clamp_fragment_color;
2480 write_color_mrf = color_mrf + reg_width;
2481 }
2482
2483 for (unsigned i = 0; i < this->output_components[target]; i++)
2484 emit_color_write(target, i, write_color_mrf);
2485
2486 bool eot = false;
2487 if (target == c->key.nr_color_regions - 1) {
2488 eot = true;
2489
2490 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2491 emit_shader_time_end();
2492 }
2493
2494 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2495 inst->target = target;
2496 inst->base_mrf = base_mrf;
2497 if (src0_alpha_to_render_target && target == 0)
2498 inst->mlen = nr - base_mrf - reg_width;
2499 else
2500 inst->mlen = nr - base_mrf;
2501 inst->eot = eot;
2502 inst->header_present = header_present;
2503 }
2504
2505 if (c->key.nr_color_regions == 0) {
2506 /* Even if there's no color buffers enabled, we still need to send
2507 * alpha out the pipeline to our null renderbuffer to support
2508 * alpha-testing, alpha-to-coverage, and so on.
2509 */
2510 emit_color_write(0, 3, color_mrf);
2511
2512 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2513 emit_shader_time_end();
2514
2515 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2516 inst->base_mrf = base_mrf;
2517 inst->mlen = nr - base_mrf;
2518 inst->eot = true;
2519 inst->header_present = header_present;
2520 }
2521
2522 this->current_annotation = NULL;
2523 }
2524
2525 void
2526 fs_visitor::resolve_ud_negate(fs_reg *reg)
2527 {
2528 if (reg->type != BRW_REGISTER_TYPE_UD ||
2529 !reg->negate)
2530 return;
2531
2532 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2533 emit(MOV(temp, *reg));
2534 *reg = temp;
2535 }
2536
2537 void
2538 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2539 {
2540 if (rvalue->type != glsl_type::bool_type)
2541 return;
2542
2543 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2544 emit(AND(temp, *reg, fs_reg(1)));
2545 *reg = temp;
2546 }
2547
2548 fs_visitor::fs_visitor(struct brw_context *brw,
2549 struct brw_wm_compile *c,
2550 struct gl_shader_program *shader_prog,
2551 struct gl_fragment_program *fp,
2552 unsigned dispatch_width)
2553 : dispatch_width(dispatch_width)
2554 {
2555 this->c = c;
2556 this->brw = brw;
2557 this->fp = fp;
2558 this->shader_prog = shader_prog;
2559 this->ctx = &brw->ctx;
2560 this->mem_ctx = ralloc_context(NULL);
2561 if (shader_prog)
2562 shader = (struct brw_shader *)
2563 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2564 else
2565 shader = NULL;
2566 this->failed = false;
2567 this->variable_ht = hash_table_ctor(0,
2568 hash_table_pointer_hash,
2569 hash_table_pointer_compare);
2570
2571 memset(this->outputs, 0, sizeof(this->outputs));
2572 memset(this->output_components, 0, sizeof(this->output_components));
2573 this->first_non_payload_grf = 0;
2574 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2575
2576 this->current_annotation = NULL;
2577 this->base_ir = NULL;
2578
2579 this->virtual_grf_sizes = NULL;
2580 this->virtual_grf_count = 0;
2581 this->virtual_grf_array_size = 0;
2582 this->virtual_grf_start = NULL;
2583 this->virtual_grf_end = NULL;
2584 this->live_intervals_valid = false;
2585
2586 this->params_remap = NULL;
2587 this->nr_params_remap = 0;
2588
2589 this->force_uncompressed_stack = 0;
2590 this->force_sechalf_stack = 0;
2591
2592 memset(&this->param_size, 0, sizeof(this->param_size));
2593 }
2594
2595 fs_visitor::~fs_visitor()
2596 {
2597 ralloc_free(this->mem_ctx);
2598 hash_table_dtor(this->variable_ht);
2599 }