2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation(ir
);
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
86 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
87 this->sample_mask
= *reg
;
89 /* gl_FragData or a user-defined FS output */
90 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
91 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
94 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
95 : ir
->type
->vector_elements
;
97 /* General color output. */
98 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
99 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
100 this->outputs
[output
] = *reg
;
101 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
102 this->output_components
[output
] = vector_elements
;
105 } else if (ir
->data
.mode
== ir_var_uniform
) {
106 int param_index
= uniforms
;
108 /* Thanks to the lower_ubo_reference pass, we will see only
109 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
110 * variables, so no need for them to be in variable_ht.
112 * Atomic counters take no uniform storage, no need to do
115 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
118 if (dispatch_width
== 16) {
119 if (!variable_storage(ir
)) {
120 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
125 param_size
[param_index
] = type_size(ir
->type
);
126 if (!strncmp(ir
->name
, "gl_", 3)) {
127 setup_builtin_uniform_values(ir
);
129 setup_uniform_values(ir
);
132 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
133 reg
->type
= brw_type_for_base_type(ir
->type
);
135 } else if (ir
->data
.mode
== ir_var_system_value
) {
136 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
137 reg
= emit_samplepos_setup(ir
);
138 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
139 reg
= emit_sampleid_setup(ir
);
140 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
141 assert(brw
->gen
>= 7);
143 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
144 BRW_REGISTER_TYPE_D
));
149 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
151 hash_table_insert(this->variable_ht
, reg
, ir
);
155 fs_visitor::visit(ir_dereference_variable
*ir
)
157 fs_reg
*reg
= variable_storage(ir
->var
);
160 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
161 this->result
= fs_reg(reg_null_d
);
168 fs_visitor::visit(ir_dereference_record
*ir
)
170 const glsl_type
*struct_type
= ir
->record
->type
;
172 ir
->record
->accept(this);
174 unsigned int offset
= 0;
175 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
176 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
178 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
180 this->result
.reg_offset
+= offset
;
181 this->result
.type
= brw_type_for_base_type(ir
->type
);
185 fs_visitor::visit(ir_dereference_array
*ir
)
187 ir_constant
*constant_index
;
189 int element_size
= type_size(ir
->type
);
191 constant_index
= ir
->array_index
->as_constant();
193 ir
->array
->accept(this);
195 src
.type
= brw_type_for_base_type(ir
->type
);
197 if (constant_index
) {
198 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
199 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
201 /* Variable index array dereference. We attach the variable index
202 * component to the reg as a pointer to a register containing the
203 * offset. Currently only uniform arrays are supported in this patch,
204 * and that reladdr pointer is resolved by
205 * move_uniform_array_access_to_pull_constants(). All other array types
206 * are lowered by lower_variable_index_to_cond_assign().
208 ir
->array_index
->accept(this);
211 index_reg
= fs_reg(this, glsl_type::int_type
);
212 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
215 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
218 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
219 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
225 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
229 !x
.is_valid_3src() ||
230 !y
.is_valid_3src() ||
231 !a
.is_valid_3src()) {
232 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
233 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
234 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
235 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
237 emit(MUL(y_times_a
, y
, a
));
239 fs_reg negative_a
= a
;
240 negative_a
.negate
= !a
.negate
;
241 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
242 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
244 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
246 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
247 * we need to reorder the operands.
249 emit(LRP(dst
, a
, y
, x
));
254 fs_visitor::emit_minmax(uint32_t conditionalmod
, const fs_reg
&dst
,
255 const fs_reg
&src0
, const fs_reg
&src1
)
260 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
261 inst
->conditional_mod
= conditionalmod
;
263 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
265 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
266 inst
->predicate
= BRW_PREDICATE_NORMAL
;
270 /* Instruction selection: Produce a MOV.sat instead of
271 * MIN(MAX(val, 0), 1) when possible.
274 fs_visitor::try_emit_saturate(ir_expression
*ir
)
276 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
281 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
283 sat_val
->accept(this);
284 fs_reg src
= this->result
;
286 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
288 /* If the last instruction from our accept() didn't generate our
289 * src, generate a saturated MOV
291 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
292 if (!modify
|| modify
->regs_written
!= 1) {
293 this->result
= fs_reg(this, ir
->type
);
294 fs_inst
*inst
= emit(MOV(this->result
, src
));
295 inst
->saturate
= true;
297 modify
->saturate
= true;
306 fs_visitor::try_emit_mad(ir_expression
*ir
)
308 /* 3-src instructions were introduced in gen6. */
312 /* MAD can only handle floating-point data. */
313 if (ir
->type
!= glsl_type::float_type
)
316 ir_rvalue
*nonmul
= ir
->operands
[1];
317 ir_expression
*mul
= ir
->operands
[0]->as_expression();
319 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
320 nonmul
= ir
->operands
[0];
321 mul
= ir
->operands
[1]->as_expression();
323 if (!mul
|| mul
->operation
!= ir_binop_mul
)
327 if (nonmul
->as_constant() ||
328 mul
->operands
[0]->as_constant() ||
329 mul
->operands
[1]->as_constant())
332 nonmul
->accept(this);
333 fs_reg src0
= this->result
;
335 mul
->operands
[0]->accept(this);
336 fs_reg src1
= this->result
;
338 mul
->operands
[1]->accept(this);
339 fs_reg src2
= this->result
;
341 this->result
= fs_reg(this, ir
->type
);
342 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
348 fs_visitor::visit(ir_expression
*ir
)
350 unsigned int operand
;
354 assert(ir
->get_num_operands() <= 3);
356 if (try_emit_saturate(ir
))
358 if (ir
->operation
== ir_binop_add
) {
359 if (try_emit_mad(ir
))
363 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
364 ir
->operands
[operand
]->accept(this);
365 if (this->result
.file
== BAD_FILE
) {
366 fail("Failed to get tree for expression operand:\n");
367 ir
->operands
[operand
]->fprint(stderr
);
368 fprintf(stderr
, "\n");
370 assert(this->result
.is_valid_3src());
371 op
[operand
] = this->result
;
373 /* Matrix expression operands should have been broken down to vector
374 * operations already.
376 assert(!ir
->operands
[operand
]->type
->is_matrix());
377 /* And then those vector operands should have been broken down to scalar.
379 assert(!ir
->operands
[operand
]->type
->is_vector());
382 /* Storage for our result. If our result goes into an assignment, it will
383 * just get copy-propagated out, so no worries.
385 this->result
= fs_reg(this, ir
->type
);
387 switch (ir
->operation
) {
388 case ir_unop_logic_not
:
389 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
390 * ones complement of the whole register, not just bit 0.
392 emit(XOR(this->result
, op
[0], fs_reg(1)));
395 op
[0].negate
= !op
[0].negate
;
396 emit(MOV(this->result
, op
[0]));
400 op
[0].negate
= false;
401 emit(MOV(this->result
, op
[0]));
404 if (ir
->type
->is_float()) {
405 /* AND(val, 0x80000000) gives the sign bit.
407 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
410 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
412 op
[0].type
= BRW_REGISTER_TYPE_UD
;
413 this->result
.type
= BRW_REGISTER_TYPE_UD
;
414 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
416 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
417 inst
->predicate
= BRW_PREDICATE_NORMAL
;
419 this->result
.type
= BRW_REGISTER_TYPE_F
;
421 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
422 * -> non-negative val generates 0x00000000.
423 * Predicated OR sets 1 if val is positive.
425 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
427 emit(ASR(this->result
, op
[0], fs_reg(31)));
429 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
430 inst
->predicate
= BRW_PREDICATE_NORMAL
;
434 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
438 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
441 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
445 assert(!"not reached: should be handled by ir_explog_to_explog2");
448 case ir_unop_sin_reduced
:
449 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
452 case ir_unop_cos_reduced
:
453 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
457 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
460 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
464 emit(ADD(this->result
, op
[0], op
[1]));
467 assert(!"not reached: should be handled by ir_sub_to_add_neg");
471 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
472 /* For integer multiplication, the MUL uses the low 16 bits
473 * of one of the operands (src0 on gen6, src1 on gen7). The
474 * MACH accumulates in the contribution of the upper 16 bits
477 if (ir
->operands
[0]->is_uint16_constant()) {
479 emit(MUL(this->result
, op
[0], op
[1]));
481 emit(MUL(this->result
, op
[1], op
[0]));
482 } else if (ir
->operands
[1]->is_uint16_constant()) {
484 emit(MUL(this->result
, op
[1], op
[0]));
486 emit(MUL(this->result
, op
[0], op
[1]));
489 no16("SIMD16 explicit accumulator operands unsupported\n");
491 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
493 emit(MUL(acc
, op
[0], op
[1]));
494 emit(MACH(reg_null_d
, op
[0], op
[1]));
495 emit(MOV(this->result
, fs_reg(acc
)));
498 emit(MUL(this->result
, op
[0], op
[1]));
501 case ir_binop_imul_high
: {
503 no16("SIMD16 explicit accumulator operands unsupported\n");
505 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
507 emit(MUL(acc
, op
[0], op
[1]));
508 emit(MACH(this->result
, op
[0], op
[1]));
512 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
513 assert(ir
->type
->is_integer());
514 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
516 case ir_binop_carry
: {
518 no16("SIMD16 explicit accumulator operands unsupported\n");
520 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
522 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
523 emit(MOV(this->result
, fs_reg(acc
)));
526 case ir_binop_borrow
: {
528 no16("SIMD16 explicit accumulator operands unsupported\n");
530 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
532 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
533 emit(MOV(this->result
, fs_reg(acc
)));
537 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
538 assert(ir
->type
->is_integer());
539 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
543 case ir_binop_greater
:
544 case ir_binop_lequal
:
545 case ir_binop_gequal
:
547 case ir_binop_all_equal
:
548 case ir_binop_nequal
:
549 case ir_binop_any_nequal
:
550 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
551 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
553 emit(CMP(this->result
, op
[0], op
[1],
554 brw_conditional_for_comparison(ir
->operation
)));
557 case ir_binop_logic_xor
:
558 emit(XOR(this->result
, op
[0], op
[1]));
561 case ir_binop_logic_or
:
562 emit(OR(this->result
, op
[0], op
[1]));
565 case ir_binop_logic_and
:
566 emit(AND(this->result
, op
[0], op
[1]));
571 assert(!"not reached: should be handled by brw_fs_channel_expressions");
575 assert(!"not reached: should be handled by lower_noise");
578 case ir_quadop_vector
:
579 assert(!"not reached: should be handled by lower_quadop_vector");
582 case ir_binop_vector_extract
:
583 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
586 case ir_triop_vector_insert
:
587 assert(!"not reached: should be handled by lower_vector_insert()");
591 assert(!"not reached: should be handled by ldexp_to_arith()");
595 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
599 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
602 case ir_unop_bitcast_i2f
:
603 case ir_unop_bitcast_u2f
:
604 op
[0].type
= BRW_REGISTER_TYPE_F
;
605 this->result
= op
[0];
608 case ir_unop_bitcast_f2u
:
609 op
[0].type
= BRW_REGISTER_TYPE_UD
;
610 this->result
= op
[0];
613 case ir_unop_bitcast_f2i
:
614 op
[0].type
= BRW_REGISTER_TYPE_D
;
615 this->result
= op
[0];
621 emit(MOV(this->result
, op
[0]));
625 emit(AND(this->result
, op
[0], fs_reg(1)));
628 temp
= fs_reg(this, glsl_type::int_type
);
629 emit(AND(temp
, op
[0], fs_reg(1)));
630 emit(MOV(this->result
, temp
));
634 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
637 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
641 emit(RNDZ(this->result
, op
[0]));
644 op
[0].negate
= !op
[0].negate
;
645 emit(RNDD(this->result
, op
[0]));
646 this->result
.negate
= true;
649 emit(RNDD(this->result
, op
[0]));
652 emit(FRC(this->result
, op
[0]));
654 case ir_unop_round_even
:
655 emit(RNDE(this->result
, op
[0]));
660 resolve_ud_negate(&op
[0]);
661 resolve_ud_negate(&op
[1]);
662 emit_minmax(ir
->operation
== ir_binop_min
?
663 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
664 this->result
, op
[0], op
[1]);
666 case ir_unop_pack_snorm_2x16
:
667 case ir_unop_pack_snorm_4x8
:
668 case ir_unop_pack_unorm_2x16
:
669 case ir_unop_pack_unorm_4x8
:
670 case ir_unop_unpack_snorm_2x16
:
671 case ir_unop_unpack_snorm_4x8
:
672 case ir_unop_unpack_unorm_2x16
:
673 case ir_unop_unpack_unorm_4x8
:
674 case ir_unop_unpack_half_2x16
:
675 case ir_unop_pack_half_2x16
:
676 assert(!"not reached: should be handled by lower_packing_builtins");
678 case ir_unop_unpack_half_2x16_split_x
:
679 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
681 case ir_unop_unpack_half_2x16_split_y
:
682 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
685 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
688 case ir_unop_bitfield_reverse
:
689 emit(BFREV(this->result
, op
[0]));
691 case ir_unop_bit_count
:
692 emit(CBIT(this->result
, op
[0]));
694 case ir_unop_find_msb
:
695 temp
= fs_reg(this, glsl_type::uint_type
);
696 emit(FBH(temp
, op
[0]));
698 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
699 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
700 * subtract the result from 31 to convert the MSB count into an LSB count.
703 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
704 emit(MOV(this->result
, temp
));
705 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
708 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
709 inst
->predicate
= BRW_PREDICATE_NORMAL
;
711 case ir_unop_find_lsb
:
712 emit(FBL(this->result
, op
[0]));
714 case ir_triop_bitfield_extract
:
715 /* Note that the instruction's argument order is reversed from GLSL
718 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
721 emit(BFI1(this->result
, op
[0], op
[1]));
724 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
726 case ir_quadop_bitfield_insert
:
727 assert(!"not reached: should be handled by "
728 "lower_instructions::bitfield_insert_to_bfm_bfi");
731 case ir_unop_bit_not
:
732 emit(NOT(this->result
, op
[0]));
734 case ir_binop_bit_and
:
735 emit(AND(this->result
, op
[0], op
[1]));
737 case ir_binop_bit_xor
:
738 emit(XOR(this->result
, op
[0], op
[1]));
740 case ir_binop_bit_or
:
741 emit(OR(this->result
, op
[0], op
[1]));
744 case ir_binop_lshift
:
745 emit(SHL(this->result
, op
[0], op
[1]));
748 case ir_binop_rshift
:
749 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
750 emit(ASR(this->result
, op
[0], op
[1]));
752 emit(SHR(this->result
, op
[0], op
[1]));
754 case ir_binop_pack_half_2x16_split
:
755 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
757 case ir_binop_ubo_load
: {
758 /* This IR node takes a constant uniform block and a constant or
759 * variable byte offset within the block and loads a vector from that.
761 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
762 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
763 fs_reg surf_index
= fs_reg(prog_data
->base
.binding_table
.ubo_start
+
764 uniform_block
->value
.u
[0]);
766 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
767 packed_consts
.type
= result
.type
;
769 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
770 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
771 packed_consts
, surf_index
, const_offset_reg
));
773 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
774 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
776 /* The std140 packing rules don't allow vectors to cross 16-byte
777 * boundaries, and a reg is 32 bytes.
779 assert(packed_consts
.subreg_offset
< 32);
781 /* UBO bools are any nonzero value. We consider bools to be
782 * values with the low bit set to 1. Convert them using CMP.
784 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
785 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
787 emit(MOV(result
, packed_consts
));
793 /* Turn the byte offset into a dword offset. */
794 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
795 emit(SHR(base_offset
, op
[1], fs_reg(2)));
797 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
798 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
801 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
802 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
808 result
.reg_offset
= 0;
813 /* Note that the instruction's argument order is reversed from GLSL
816 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
820 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
824 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
825 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
826 inst
->predicate
= BRW_PREDICATE_NORMAL
;
832 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
833 const glsl_type
*type
, bool predicated
)
835 switch (type
->base_type
) {
836 case GLSL_TYPE_FLOAT
:
840 for (unsigned int i
= 0; i
< type
->components(); i
++) {
841 l
.type
= brw_type_for_base_type(type
);
842 r
.type
= brw_type_for_base_type(type
);
844 if (predicated
|| !l
.equals(r
)) {
845 fs_inst
*inst
= emit(MOV(l
, r
));
846 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
853 case GLSL_TYPE_ARRAY
:
854 for (unsigned int i
= 0; i
< type
->length
; i
++) {
855 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
859 case GLSL_TYPE_STRUCT
:
860 for (unsigned int i
= 0; i
< type
->length
; i
++) {
861 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
866 case GLSL_TYPE_SAMPLER
:
867 case GLSL_TYPE_IMAGE
:
868 case GLSL_TYPE_ATOMIC_UINT
:
872 case GLSL_TYPE_ERROR
:
873 case GLSL_TYPE_INTERFACE
:
874 assert(!"not reached");
879 /* If the RHS processing resulted in an instruction generating a
880 * temporary value, and it would be easy to rewrite the instruction to
881 * generate its result right into the LHS instead, do so. This ends
882 * up reliably removing instructions where it can be tricky to do so
883 * later without real UD chain information.
886 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
889 fs_inst
*pre_rhs_inst
,
890 fs_inst
*last_rhs_inst
)
892 /* Only attempt if we're doing a direct assignment. */
894 !(ir
->lhs
->type
->is_scalar() ||
895 (ir
->lhs
->type
->is_vector() &&
896 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
899 /* Make sure the last instruction generated our source reg. */
900 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
906 /* If last_rhs_inst wrote a different number of components than our LHS,
907 * we can't safely rewrite it.
909 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
912 /* Success! Rewrite the instruction. */
919 fs_visitor::visit(ir_assignment
*ir
)
924 /* FINISHME: arrays on the lhs */
925 ir
->lhs
->accept(this);
928 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
930 ir
->rhs
->accept(this);
933 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
935 assert(l
.file
!= BAD_FILE
);
936 assert(r
.file
!= BAD_FILE
);
938 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
942 emit_bool_to_cond_code(ir
->condition
);
945 if (ir
->lhs
->type
->is_scalar() ||
946 ir
->lhs
->type
->is_vector()) {
947 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
948 if (ir
->write_mask
& (1 << i
)) {
949 inst
= emit(MOV(l
, r
));
951 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
962 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
963 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
973 if (ir
->shadow_comparitor
) {
974 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
975 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
976 coordinate
.reg_offset
++;
979 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
980 * the unused slots must be zeroed.
982 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
983 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
987 if (ir
->op
== ir_tex
) {
988 /* There's no plain shadow compare message, so we use shadow
989 * compare with a bias of 0.0.
991 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
993 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
994 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
997 assert(!"Should not get here.");
1000 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1002 } else if (ir
->op
== ir_tex
) {
1003 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1004 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1005 coordinate
.reg_offset
++;
1007 /* zero the others. */
1008 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
1009 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1011 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1013 } else if (ir
->op
== ir_txd
) {
1016 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1017 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1018 coordinate
.reg_offset
++;
1020 /* the slots for u and v are always present, but r is optional */
1021 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
1024 * dPdx = dudx, dvdx, drdx
1025 * dPdy = dudy, dvdy, drdy
1027 * 1-arg: Does not exist.
1029 * 2-arg: dudx dvdx dudy dvdy
1030 * dPdx.x dPdx.y dPdy.x dPdy.y
1033 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1034 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1035 * m5 m6 m7 m8 m9 m10
1037 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1038 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1041 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1043 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1044 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1047 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1048 } else if (ir
->op
== ir_txs
) {
1049 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1051 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1054 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1055 * instructions. We'll need to do SIMD16 here.
1058 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1060 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1061 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1063 coordinate
.reg_offset
++;
1066 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1067 * be necessary for TXF (ld), but seems wise to do for all messages.
1069 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1070 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1073 /* lod/bias appears after u/v/r. */
1076 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1079 /* The unused upper half. */
1084 /* Now, since we're doing simd16, the return is 2 interleaved
1085 * vec4s where the odd-indexed ones are junk. We'll need to move
1086 * this weirdness around to the expected layout.
1089 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1091 brw_type_for_base_type(ir
->type
) :
1092 BRW_REGISTER_TYPE_F
));
1095 fs_inst
*inst
= NULL
;
1098 inst
= emit(SHADER_OPCODE_TEX
, dst
, reg_undef
);
1101 inst
= emit(FS_OPCODE_TXB
, dst
, reg_undef
);
1104 inst
= emit(SHADER_OPCODE_TXL
, dst
, reg_undef
);
1107 inst
= emit(SHADER_OPCODE_TXD
, dst
, reg_undef
);
1110 inst
= emit(SHADER_OPCODE_TXS
, dst
, reg_undef
);
1113 inst
= emit(SHADER_OPCODE_TXF
, dst
, reg_undef
);
1116 fail("unrecognized texture opcode");
1118 inst
->base_mrf
= base_mrf
;
1120 inst
->header_present
= true;
1121 inst
->regs_written
= simd16
? 8 : 4;
1124 for (int i
= 0; i
< 4; i
++) {
1125 emit(MOV(orig_dst
, dst
));
1126 orig_dst
.reg_offset
++;
1127 dst
.reg_offset
+= 2;
1134 /* gen5's sampler has slots for u, v, r, array index, then optional
1135 * parameters like shadow comparitor or LOD bias. If optional
1136 * parameters aren't present, those base slots are optional and don't
1137 * need to be included in the message.
1139 * We don't fill in the unnecessary slots regardless, which may look
1140 * surprising in the disassembly.
1143 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1144 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1145 fs_reg sample_index
)
1149 int reg_width
= dispatch_width
/ 8;
1150 bool header_present
= false;
1151 const int vector_elements
=
1152 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1155 /* The offsets set up by the ir_texture visitor are in the
1156 * m1 header, so we can't go headerless.
1158 header_present
= true;
1163 for (int i
= 0; i
< vector_elements
; i
++) {
1164 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1166 coordinate
.reg_offset
++;
1168 mlen
+= vector_elements
* reg_width
;
1170 if (ir
->shadow_comparitor
) {
1171 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1173 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1177 fs_inst
*inst
= NULL
;
1180 inst
= emit(SHADER_OPCODE_TEX
, dst
, reg_undef
);
1183 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1184 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1187 inst
= emit(FS_OPCODE_TXB
, dst
, reg_undef
);
1190 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1191 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1194 inst
= emit(SHADER_OPCODE_TXL
, dst
, reg_undef
);
1197 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1201 * dPdx = dudx, dvdx, drdx
1202 * dPdy = dudy, dvdy, drdy
1204 * Load up these values:
1205 * - dudx dudy dvdx dvdy drdx drdy
1206 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1208 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1209 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1213 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1218 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1222 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1224 inst
= emit(SHADER_OPCODE_TXS
, dst
, reg_undef
);
1226 case ir_query_levels
:
1227 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1229 inst
= emit(SHADER_OPCODE_TXS
, dst
, reg_undef
);
1232 mlen
= header_present
+ 4 * reg_width
;
1233 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1234 inst
= emit(SHADER_OPCODE_TXF
, dst
, reg_undef
);
1237 mlen
= header_present
+ 4 * reg_width
;
1240 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1242 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1244 inst
= emit(SHADER_OPCODE_TXF_CMS
, dst
, reg_undef
);
1247 inst
= emit(SHADER_OPCODE_LOD
, dst
, reg_undef
);
1250 inst
= emit(SHADER_OPCODE_TG4
, dst
, reg_undef
);
1253 fail("unrecognized texture opcode");
1256 inst
->base_mrf
= base_mrf
;
1258 inst
->header_present
= header_present
;
1259 inst
->regs_written
= 4;
1261 if (mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1262 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1263 " disallowed by hardware\n");
1270 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1271 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1272 fs_reg sample_index
, fs_reg mcs
, int sampler
)
1274 int reg_width
= dispatch_width
/ 8;
1275 bool header_present
= false;
1277 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1278 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1279 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1283 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
) || sampler
>= 16) {
1284 /* For general texture offsets (no txf workaround), we need a header to
1285 * put them in. Note that for SIMD16 we're making space for two actual
1286 * hardware registers here, so the emit will have to fix up for this.
1288 * * ir4_tg4 needs to place its channel select in the header,
1289 * for interaction with ARB_texture_swizzle
1291 * The sampler index is only 4-bits, so for larger sampler numbers we
1292 * need to offset the Sampler State Pointer in the header.
1294 header_present
= true;
1295 sources
[length
] = reg_undef
;
1299 if (ir
->shadow_comparitor
) {
1300 emit(MOV(sources
[length
], shadow_c
));
1304 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
1305 bool coordinate_done
= false;
1307 /* Set up the LOD info */
1313 emit(MOV(sources
[length
], lod
));
1317 emit(MOV(sources
[length
], lod
));
1321 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1323 /* Load dPdx and the coordinate together:
1324 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1326 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1327 emit(MOV(sources
[length
], coordinate
));
1328 coordinate
.reg_offset
++;
1331 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1332 * only derivatives for (u, v, r).
1334 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1335 emit(MOV(sources
[length
], lod
));
1339 emit(MOV(sources
[length
], lod2
));
1345 coordinate_done
= true;
1349 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1352 case ir_query_levels
:
1353 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1357 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1358 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1359 coordinate
.reg_offset
++;
1362 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1365 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1366 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1367 coordinate
.reg_offset
++;
1371 coordinate_done
= true;
1374 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1377 /* data from the multisample control surface */
1378 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1381 /* there is no offsetting for this message; just copy in the integer
1382 * texture coordinates
1384 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1385 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1386 coordinate
.reg_offset
++;
1390 coordinate_done
= true;
1393 if (has_nonconstant_offset
) {
1394 if (ir
->shadow_comparitor
)
1395 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1397 /* More crazy intermixing */
1398 ir
->offset
->accept(this);
1399 fs_reg offset_value
= this->result
;
1401 for (int i
= 0; i
< 2; i
++) { /* u, v */
1402 emit(MOV(sources
[length
], coordinate
));
1403 coordinate
.reg_offset
++;
1407 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1408 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1409 offset_value
.reg_offset
++;
1413 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1414 emit(MOV(sources
[length
], coordinate
));
1415 coordinate
.reg_offset
++;
1419 coordinate_done
= true;
1424 /* Set up the coordinate (except for cases where it was done above) */
1425 if (ir
->coordinate
&& !coordinate_done
) {
1426 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1427 emit(MOV(sources
[length
], coordinate
));
1428 coordinate
.reg_offset
++;
1433 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1434 BRW_REGISTER_TYPE_F
);
1435 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1437 /* Generate the SEND */
1440 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1441 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1442 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1443 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1444 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1445 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1446 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1447 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1448 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1450 if (has_nonconstant_offset
)
1451 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1453 opcode
= SHADER_OPCODE_TG4
;
1456 fs_inst
*inst
= emit(opcode
, dst
, src_payload
);
1457 inst
->base_mrf
= -1;
1459 inst
->mlen
= length
* reg_width
- header_present
;
1461 inst
->mlen
= length
* reg_width
;
1462 inst
->header_present
= header_present
;
1463 inst
->regs_written
= 4;
1465 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1466 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1467 " disallowed by hardware\n");
1474 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1475 bool is_rect
, int sampler
, int texunit
)
1477 fs_inst
*inst
= NULL
;
1478 bool needs_gl_clamp
= true;
1479 fs_reg scale_x
, scale_y
;
1481 /* The 965 requires the EU to do the normalization of GL rectangle
1482 * texture coordinates. We use the program parameter state
1483 * tracking to get the scaling factor.
1487 (brw
->gen
>= 6 && (key
->tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1488 key
->tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1489 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1490 int tokens
[STATE_LENGTH
] = {
1492 STATE_TEXRECT_SCALE
,
1498 no16("rectangle scale uniform setup not supported on SIMD16\n");
1499 if (dispatch_width
== 16) {
1503 GLuint index
= _mesa_add_state_reference(params
,
1504 (gl_state_index
*)tokens
);
1505 /* Try to find existing copies of the texrect scale uniforms. */
1506 for (unsigned i
= 0; i
< uniforms
; i
++) {
1507 if (stage_prog_data
->param
[i
] ==
1508 &prog
->Parameters
->ParameterValues
[index
][0].f
) {
1509 scale_x
= fs_reg(UNIFORM
, i
);
1510 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1515 /* If we didn't already set them up, do so now. */
1516 if (scale_x
.file
== BAD_FILE
) {
1517 scale_x
= fs_reg(UNIFORM
, uniforms
);
1518 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1520 stage_prog_data
->param
[uniforms
++] =
1521 &prog
->Parameters
->ParameterValues
[index
][0].f
;
1522 stage_prog_data
->param
[uniforms
++] =
1523 &prog
->Parameters
->ParameterValues
[index
][1].f
;
1527 /* The 965 requires the EU to do the normalization of GL rectangle
1528 * texture coordinates. We use the program parameter state
1529 * tracking to get the scaling factor.
1531 if (brw
->gen
< 6 && is_rect
) {
1532 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1533 fs_reg src
= coordinate
;
1536 emit(MUL(dst
, src
, scale_x
));
1539 emit(MUL(dst
, src
, scale_y
));
1540 } else if (is_rect
) {
1541 /* On gen6+, the sampler handles the rectangle coordinates
1542 * natively, without needing rescaling. But that means we have
1543 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1544 * not [0, 1] like the default case below.
1546 needs_gl_clamp
= false;
1548 for (int i
= 0; i
< 2; i
++) {
1549 if (key
->tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1550 fs_reg chan
= coordinate
;
1551 chan
.reg_offset
+= i
;
1553 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1554 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1556 /* Our parameter comes in as 1.0/width or 1.0/height,
1557 * because that's what people normally want for doing
1558 * texture rectangle handling. We need width or height
1559 * for clamping, but we don't care enough to make a new
1560 * parameter type, so just invert back.
1562 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1563 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1564 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1566 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1567 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1572 if (ir
->coordinate
&& needs_gl_clamp
) {
1573 for (unsigned int i
= 0;
1574 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1575 if (key
->tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1576 fs_reg chan
= coordinate
;
1577 chan
.reg_offset
+= i
;
1579 fs_inst
*inst
= emit(MOV(chan
, chan
));
1580 inst
->saturate
= true;
1587 /* Sample from the MCS surface attached to this multisample texture. */
1589 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
)
1591 int reg_width
= dispatch_width
/ 8;
1592 int length
= ir
->coordinate
->type
->vector_elements
;
1593 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1594 BRW_REGISTER_TYPE_F
);
1595 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1596 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, length
);
1598 /* parameters are: u, v, r; missing parameters are treated as zero */
1599 for (int i
= 0; i
< length
; i
++) {
1600 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1601 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1602 coordinate
.reg_offset
++;
1605 emit(LOAD_PAYLOAD(payload
, sources
, length
));
1607 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
);
1608 inst
->base_mrf
= -1;
1609 inst
->mlen
= length
* reg_width
;
1610 inst
->header_present
= false;
1611 inst
->regs_written
= 4; /* we only care about one reg of response,
1612 * but the sampler always writes 4/8
1614 inst
->sampler
= sampler
;
1620 fs_visitor::visit(ir_texture
*ir
)
1622 fs_inst
*inst
= NULL
;
1625 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1626 /* FINISHME: We're failing to recompile our programs when the sampler is
1627 * updated. This only matters for the texture rectangle scale parameters
1628 * (pre-gen6, or gen6+ with GL_CLAMP).
1630 int texunit
= prog
->SamplerUnits
[sampler
];
1632 if (ir
->op
== ir_tg4
) {
1633 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1634 * emitting anything other than setting up the constant result.
1636 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1637 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1638 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1640 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1643 for (int i
=0; i
<4; i
++) {
1644 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1651 /* Should be lowered by do_lower_texture_projection */
1652 assert(!ir
->projector
);
1654 /* Should be lowered */
1655 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1657 /* Generate code to compute all the subexpression trees. This has to be
1658 * done before loading any values into MRFs for the sampler message since
1659 * generating these values may involve SEND messages that need the MRFs.
1662 if (ir
->coordinate
) {
1663 ir
->coordinate
->accept(this);
1665 coordinate
= rescale_texcoord(ir
, this->result
,
1666 ir
->sampler
->type
->sampler_dimensionality
==
1667 GLSL_SAMPLER_DIM_RECT
,
1671 fs_reg shadow_comparitor
;
1672 if (ir
->shadow_comparitor
) {
1673 ir
->shadow_comparitor
->accept(this);
1674 shadow_comparitor
= this->result
;
1677 fs_reg lod
, lod2
, sample_index
, mcs
;
1682 case ir_query_levels
:
1685 ir
->lod_info
.bias
->accept(this);
1689 ir
->lod_info
.grad
.dPdx
->accept(this);
1692 ir
->lod_info
.grad
.dPdy
->accept(this);
1693 lod2
= this->result
;
1698 ir
->lod_info
.lod
->accept(this);
1702 ir
->lod_info
.sample_index
->accept(this);
1703 sample_index
= this->result
;
1705 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1706 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
1711 assert(!"Unrecognized texture opcode");
1714 /* Writemasking doesn't eliminate channels on SIMD8 texture
1715 * samples, so don't worry about them.
1717 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1719 if (brw
->gen
>= 7) {
1720 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1721 lod
, lod2
, sample_index
, mcs
, sampler
);
1722 } else if (brw
->gen
>= 5) {
1723 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1724 lod
, lod2
, sample_index
);
1726 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1730 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1731 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
1733 if (ir
->op
== ir_tg4
)
1734 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1736 inst
->sampler
= sampler
;
1738 if (ir
->shadow_comparitor
)
1739 inst
->shadow_compare
= true;
1741 /* fixup #layers for cube map arrays */
1742 if (ir
->op
== ir_txs
) {
1743 glsl_type
const *type
= ir
->sampler
->type
;
1744 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1745 type
->sampler_array
) {
1747 depth
.reg_offset
= 2;
1748 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
1749 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
1751 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
1753 for (int i
= 0; i
< inst
->regs_written
; i
++) {
1755 fixed_payload
[i
] = fixed_depth
;
1758 fixed_payload
[i
] = d
;
1761 emit(LOAD_PAYLOAD(dst
, fixed_payload
, inst
->regs_written
));
1765 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
1766 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], dst
);
1769 swizzle_result(ir
, dst
, sampler
);
1773 * Apply workarounds for Gen6 gather with UINT/SINT
1776 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
1781 int width
= (wa
& WA_8BIT
) ? 8 : 16;
1783 for (int i
= 0; i
< 4; i
++) {
1784 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
1785 /* Convert from UNORM to UINT */
1786 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
1787 emit(MOV(dst
, dst_f
));
1790 /* Reinterpret the UINT value as a signed INT value by
1791 * shifting the sign bit into place, then shifting back
1794 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
1795 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
1803 * Set up the gather channel based on the swizzle, for gather4.
1806 fs_visitor::gather_channel(ir_texture
*ir
, int sampler
)
1808 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1809 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1811 case SWIZZLE_X
: return 0;
1813 /* gather4 sampler is broken for green channel on RG32F --
1814 * we must ask for blue instead.
1816 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
1819 case SWIZZLE_Z
: return 2;
1820 case SWIZZLE_W
: return 3;
1822 assert(!"Not reached"); /* zero, one swizzles handled already */
1828 * Swizzle the result of a texture result. This is necessary for
1829 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1832 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1834 if (ir
->op
== ir_query_levels
) {
1835 /* # levels is in .w */
1836 orig_val
.reg_offset
+= 3;
1837 this->result
= orig_val
;
1841 this->result
= orig_val
;
1843 /* txs,lod don't actually sample the texture, so swizzling the result
1846 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
1849 if (ir
->type
== glsl_type::float_type
) {
1850 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1851 assert(ir
->sampler
->type
->sampler_shadow
);
1852 } else if (key
->tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1853 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1855 for (int i
= 0; i
< 4; i
++) {
1856 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], i
);
1857 fs_reg l
= swizzled_result
;
1860 if (swiz
== SWIZZLE_ZERO
) {
1861 emit(MOV(l
, fs_reg(0.0f
)));
1862 } else if (swiz
== SWIZZLE_ONE
) {
1863 emit(MOV(l
, fs_reg(1.0f
)));
1865 fs_reg r
= orig_val
;
1866 r
.reg_offset
+= GET_SWZ(key
->tex
.swizzles
[sampler
], i
);
1870 this->result
= swizzled_result
;
1875 fs_visitor::visit(ir_swizzle
*ir
)
1877 ir
->val
->accept(this);
1878 fs_reg val
= this->result
;
1880 if (ir
->type
->vector_elements
== 1) {
1881 this->result
.reg_offset
+= ir
->mask
.x
;
1885 fs_reg result
= fs_reg(this, ir
->type
);
1886 this->result
= result
;
1888 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1889 fs_reg channel
= val
;
1907 channel
.reg_offset
+= swiz
;
1908 emit(MOV(result
, channel
));
1909 result
.reg_offset
++;
1914 fs_visitor::visit(ir_discard
*ir
)
1916 assert(ir
->condition
== NULL
); /* FINISHME */
1918 /* We track our discarded pixels in f0.1. By predicating on it, we can
1919 * update just the flag bits that aren't yet discarded. By emitting a
1920 * CMP of g0 != g0, all our currently executing channels will get turned
1923 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1924 BRW_REGISTER_TYPE_UW
));
1925 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1926 BRW_CONDITIONAL_NZ
));
1927 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1928 cmp
->flag_subreg
= 1;
1930 if (brw
->gen
>= 6) {
1931 /* For performance, after a discard, jump to the end of the shader.
1932 * However, many people will do foliage by discarding based on a
1933 * texture's alpha mask, and then continue on to texture with the
1934 * remaining pixels. To avoid trashing the derivatives for those
1935 * texture samples, we'll only jump if all of the pixels in the subspan
1936 * have been discarded.
1938 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1939 discard_jump
->flag_subreg
= 1;
1940 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1941 discard_jump
->predicate_inverse
= true;
1946 fs_visitor::visit(ir_constant
*ir
)
1948 /* Set this->result to reg at the bottom of the function because some code
1949 * paths will cause this visitor to be applied to other fields. This will
1950 * cause the value stored in this->result to be modified.
1952 * Make reg constant so that it doesn't get accidentally modified along the
1953 * way. Yes, I actually had this problem. :(
1955 const fs_reg
reg(this, ir
->type
);
1956 fs_reg dst_reg
= reg
;
1958 if (ir
->type
->is_array()) {
1959 const unsigned size
= type_size(ir
->type
->fields
.array
);
1961 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1962 ir
->array_elements
[i
]->accept(this);
1963 fs_reg src_reg
= this->result
;
1965 dst_reg
.type
= src_reg
.type
;
1966 for (unsigned j
= 0; j
< size
; j
++) {
1967 emit(MOV(dst_reg
, src_reg
));
1968 src_reg
.reg_offset
++;
1969 dst_reg
.reg_offset
++;
1972 } else if (ir
->type
->is_record()) {
1973 foreach_in_list(ir_constant
, field
, &ir
->components
) {
1974 const unsigned size
= type_size(field
->type
);
1976 field
->accept(this);
1977 fs_reg src_reg
= this->result
;
1979 dst_reg
.type
= src_reg
.type
;
1980 for (unsigned j
= 0; j
< size
; j
++) {
1981 emit(MOV(dst_reg
, src_reg
));
1982 src_reg
.reg_offset
++;
1983 dst_reg
.reg_offset
++;
1987 const unsigned size
= type_size(ir
->type
);
1989 for (unsigned i
= 0; i
< size
; i
++) {
1990 switch (ir
->type
->base_type
) {
1991 case GLSL_TYPE_FLOAT
:
1992 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1994 case GLSL_TYPE_UINT
:
1995 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1998 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2000 case GLSL_TYPE_BOOL
:
2001 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
2004 assert(!"Non-float/uint/int/bool constant");
2006 dst_reg
.reg_offset
++;
2014 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2016 ir_expression
*expr
= ir
->as_expression();
2019 expr
->operation
!= ir_binop_logic_and
&&
2020 expr
->operation
!= ir_binop_logic_or
&&
2021 expr
->operation
!= ir_binop_logic_xor
) {
2025 assert(expr
->get_num_operands() <= 2);
2026 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2027 assert(expr
->operands
[i
]->type
->is_scalar());
2029 expr
->operands
[i
]->accept(this);
2030 op
[i
] = this->result
;
2032 resolve_ud_negate(&op
[i
]);
2035 switch (expr
->operation
) {
2036 case ir_unop_logic_not
:
2037 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2038 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2042 if (brw
->gen
>= 6) {
2043 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2045 inst
= emit(MOV(reg_null_f
, op
[0]));
2046 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2051 if (brw
->gen
>= 6) {
2052 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2054 inst
= emit(MOV(reg_null_d
, op
[0]));
2055 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2059 case ir_binop_greater
:
2060 case ir_binop_gequal
:
2062 case ir_binop_lequal
:
2063 case ir_binop_equal
:
2064 case ir_binop_all_equal
:
2065 case ir_binop_nequal
:
2066 case ir_binop_any_nequal
:
2067 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2068 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2070 emit(CMP(reg_null_d
, op
[0], op
[1],
2071 brw_conditional_for_comparison(expr
->operation
)));
2075 assert(!"not reached");
2076 fail("bad cond code\n");
2084 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2085 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2089 * Emit a gen6 IF statement with the comparison folded into the IF
2093 fs_visitor::emit_if_gen6(ir_if
*ir
)
2095 ir_expression
*expr
= ir
->condition
->as_expression();
2102 assert(expr
->get_num_operands() <= 2);
2103 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2104 assert(expr
->operands
[i
]->type
->is_scalar());
2106 expr
->operands
[i
]->accept(this);
2107 op
[i
] = this->result
;
2110 switch (expr
->operation
) {
2111 case ir_unop_logic_not
:
2112 case ir_binop_logic_xor
:
2113 case ir_binop_logic_or
:
2114 case ir_binop_logic_and
:
2115 /* For operations on bool arguments, only the low bit of the bool is
2116 * valid, and the others are undefined. Fall back to the condition
2122 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2123 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2127 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2130 case ir_binop_greater
:
2131 case ir_binop_gequal
:
2133 case ir_binop_lequal
:
2134 case ir_binop_equal
:
2135 case ir_binop_all_equal
:
2136 case ir_binop_nequal
:
2137 case ir_binop_any_nequal
:
2138 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2139 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2141 emit(IF(op
[0], op
[1],
2142 brw_conditional_for_comparison(expr
->operation
)));
2145 assert(!"not reached");
2146 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2147 fail("bad condition\n");
2152 emit_bool_to_cond_code(ir
->condition
);
2153 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
2154 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2158 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2160 * Many GLSL shaders contain the following pattern:
2162 * x = condition ? foo : bar
2164 * The compiler emits an ir_if tree for this, since each subexpression might be
2165 * a complex tree that could have side-effects or short-circuit logic.
2167 * However, the common case is to simply select one of two constants or
2168 * variable values---which is exactly what SEL is for. In this case, the
2169 * assembly looks like:
2177 * which can be easily translated into:
2179 * (+f0) SEL dst src0 src1
2181 * If src0 is an immediate value, we promote it to a temporary GRF.
2184 fs_visitor::try_replace_with_sel()
2186 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2187 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2189 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2191 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2194 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2195 for (int i
= 0; i
< 4; i
++) {
2196 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2198 match
= (fs_inst
*) match
->prev
;
2201 /* The opcodes match; it looks like the right sequence of instructions. */
2202 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2203 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2204 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2206 /* Check that the MOVs are the right form. */
2207 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2208 !then_mov
->is_partial_write() &&
2209 !else_mov
->is_partial_write()) {
2211 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2212 while (!if_inst
->next
->is_tail_sentinel())
2213 if_inst
->next
->remove();
2216 /* Only the last source register can be a constant, so if the MOV in
2217 * the "then" clause uses a constant, we need to put it in a temporary.
2219 fs_reg
src0(then_mov
->src
[0]);
2220 if (src0
.file
== IMM
) {
2221 src0
= fs_reg(this, glsl_type::float_type
);
2222 src0
.type
= then_mov
->src
[0].type
;
2223 emit(MOV(src0
, then_mov
->src
[0]));
2227 if (if_inst
->conditional_mod
) {
2228 /* Sandybridge-specific IF with embedded comparison */
2229 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2230 if_inst
->conditional_mod
));
2231 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2232 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2234 /* Separate CMP and IF instructions */
2235 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2236 sel
->predicate
= if_inst
->predicate
;
2237 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2243 fs_visitor::visit(ir_if
*ir
)
2246 no16("Can't support (non-uniform) control flow on SIMD16\n");
2249 /* Don't point the annotation at the if statement, because then it plus
2250 * the then and else blocks get printed.
2252 this->base_ir
= ir
->condition
;
2254 if (brw
->gen
== 6) {
2257 emit_bool_to_cond_code(ir
->condition
);
2259 emit(IF(BRW_PREDICATE_NORMAL
));
2262 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2263 this->base_ir
= ir_
;
2267 if (!ir
->else_instructions
.is_empty()) {
2268 emit(BRW_OPCODE_ELSE
);
2270 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2271 this->base_ir
= ir_
;
2276 emit(BRW_OPCODE_ENDIF
);
2278 try_replace_with_sel();
2282 fs_visitor::visit(ir_loop
*ir
)
2285 no16("Can't support (non-uniform) control flow on SIMD16\n");
2288 this->base_ir
= NULL
;
2289 emit(BRW_OPCODE_DO
);
2291 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2292 this->base_ir
= ir_
;
2296 this->base_ir
= NULL
;
2297 emit(BRW_OPCODE_WHILE
);
2301 fs_visitor::visit(ir_loop_jump
*ir
)
2304 case ir_loop_jump::jump_break
:
2305 emit(BRW_OPCODE_BREAK
);
2307 case ir_loop_jump::jump_continue
:
2308 emit(BRW_OPCODE_CONTINUE
);
2314 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2316 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2317 ir
->actual_parameters
.get_head());
2318 ir_variable
*location
= deref
->variable_referenced();
2319 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2320 location
->data
.atomic
.buffer_index
);
2322 /* Calculate the surface offset */
2323 fs_reg
offset(this, glsl_type::uint_type
);
2324 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2327 deref_array
->array_index
->accept(this);
2329 fs_reg
tmp(this, glsl_type::uint_type
);
2330 emit(MUL(tmp
, this->result
, ATOMIC_COUNTER_SIZE
));
2331 emit(ADD(offset
, tmp
, location
->data
.atomic
.offset
));
2333 offset
= location
->data
.atomic
.offset
;
2336 /* Emit the appropriate machine instruction */
2337 const char *callee
= ir
->callee
->function_name();
2338 ir
->return_deref
->accept(this);
2339 fs_reg dst
= this->result
;
2341 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2342 emit_untyped_surface_read(surf_index
, dst
, offset
);
2344 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2345 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2346 fs_reg(), fs_reg());
2348 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2349 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2350 fs_reg(), fs_reg());
2355 fs_visitor::visit(ir_call
*ir
)
2357 const char *callee
= ir
->callee
->function_name();
2359 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2360 !strcmp("__intrinsic_atomic_increment", callee
) ||
2361 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2362 visit_atomic_counter_intrinsic(ir
);
2364 assert(!"Unsupported intrinsic.");
2369 fs_visitor::visit(ir_return
*ir
)
2371 assert(!"FINISHME");
2375 fs_visitor::visit(ir_function
*ir
)
2377 /* Ignore function bodies other than main() -- we shouldn't see calls to
2378 * them since they should all be inlined before we get to ir_to_mesa.
2380 if (strcmp(ir
->name
, "main") == 0) {
2381 const ir_function_signature
*sig
;
2384 sig
= ir
->matching_signature(NULL
, &empty
);
2388 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2389 this->base_ir
= ir_
;
2396 fs_visitor::visit(ir_function_signature
*ir
)
2398 assert(!"not reached");
2403 fs_visitor::visit(ir_emit_vertex
*)
2405 assert(!"not reached");
2409 fs_visitor::visit(ir_end_primitive
*)
2411 assert(!"not reached");
2415 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2416 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2419 const unsigned operand_len
= dispatch_width
/ 8;
2422 /* Initialize the sample mask in the message header. */
2423 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2424 ->force_writemask_all
= true;
2427 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2428 ->force_writemask_all
= true;
2430 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2431 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2432 ->force_writemask_all
= true;
2437 /* Set the atomic operation offset. */
2438 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2439 mlen
+= operand_len
;
2441 /* Set the atomic operation arguments. */
2442 if (src0
.file
!= BAD_FILE
) {
2443 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src0
));
2444 mlen
+= operand_len
;
2447 if (src1
.file
!= BAD_FILE
) {
2448 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src1
));
2449 mlen
+= operand_len
;
2452 /* Emit the instruction. */
2453 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2454 atomic_op
, surf_index
);
2457 inst
->header_present
= true;
2462 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2465 const unsigned operand_len
= dispatch_width
/ 8;
2468 /* Initialize the sample mask in the message header. */
2469 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2470 ->force_writemask_all
= true;
2473 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2474 ->force_writemask_all
= true;
2476 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2477 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2478 ->force_writemask_all
= true;
2483 /* Set the surface read offset. */
2484 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2485 mlen
+= operand_len
;
2487 /* Emit the instruction. */
2488 fs_inst
*inst
= new(mem_ctx
)
2489 fs_inst(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, surf_index
);
2492 inst
->header_present
= true;
2497 fs_visitor::emit(fs_inst
*inst
)
2499 if (force_uncompressed_stack
> 0)
2500 inst
->force_uncompressed
= true;
2502 inst
->annotation
= this->current_annotation
;
2503 inst
->ir
= this->base_ir
;
2505 this->instructions
.push_tail(inst
);
2511 fs_visitor::emit(exec_list list
)
2513 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2519 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2521 fs_visitor::emit_dummy_fs()
2523 int reg_width
= dispatch_width
/ 8;
2525 /* Everyone's favorite color. */
2526 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2527 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2528 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2529 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2532 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2533 write
->base_mrf
= 2;
2534 write
->mlen
= 4 * reg_width
;
2538 /* The register location here is relative to the start of the URB
2539 * data. It will get adjusted to be a real location before
2540 * generate_code() time.
2543 fs_visitor::interp_reg(int location
, int channel
)
2545 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
2546 int stride
= (channel
& 1) * 4;
2548 assert(prog_data
->urb_setup
[location
] != -1);
2550 return brw_vec1_grf(regnr
, stride
);
2553 /** Emits the interpolation for the varying inputs. */
2555 fs_visitor::emit_interpolation_setup_gen4()
2557 this->current_annotation
= "compute pixel centers";
2558 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2559 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2560 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2561 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2563 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2564 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2566 this->current_annotation
= "compute pixel deltas from v0";
2568 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2569 fs_reg(this, glsl_type::vec2_type
);
2570 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2571 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2572 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2574 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2575 fs_reg(this, glsl_type::float_type
);
2576 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2577 fs_reg(this, glsl_type::float_type
);
2579 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2580 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2581 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2582 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2584 this->current_annotation
= "compute pos.w and 1/pos.w";
2585 /* Compute wpos.w. It's always in our setup, since it's needed to
2586 * interpolate the other attributes.
2588 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2589 emit(FS_OPCODE_LINTERP
, wpos_w
,
2590 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2591 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2592 interp_reg(VARYING_SLOT_POS
, 3));
2593 /* Compute the pixel 1/W value from wpos.w. */
2594 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2595 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2596 this->current_annotation
= NULL
;
2599 /** Emits the interpolation for the varying inputs. */
2601 fs_visitor::emit_interpolation_setup_gen6()
2603 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2605 /* If the pixel centers end up used, the setup is the same as for gen4. */
2606 this->current_annotation
= "compute pixel centers";
2607 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2608 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2609 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2610 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2611 emit(ADD(int_pixel_x
,
2612 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2613 fs_reg(brw_imm_v(0x10101010))));
2614 emit(ADD(int_pixel_y
,
2615 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2616 fs_reg(brw_imm_v(0x11001100))));
2618 /* As of gen6, we can no longer mix float and int sources. We have
2619 * to turn the integer pixel centers into floats for their actual
2622 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2623 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2624 emit(MOV(this->pixel_x
, int_pixel_x
));
2625 emit(MOV(this->pixel_y
, int_pixel_y
));
2627 this->current_annotation
= "compute pos.w";
2628 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
2629 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2630 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2632 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2633 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
2634 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2635 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2638 this->current_annotation
= NULL
;
2642 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2644 int reg_width
= dispatch_width
/ 8;
2646 fs_reg color
= outputs
[target
];
2649 /* If there's no color data to be written, skip it. */
2650 if (color
.file
== BAD_FILE
)
2653 color
.reg_offset
+= index
;
2655 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2656 /* SIMD8 write looks like:
2662 * gen6 SIMD16 DP write looks like:
2672 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2675 inst
->saturate
= key
->clamp_fragment_color
;
2677 /* pre-gen6 SIMD16 single source DP write looks like:
2687 if (brw
->has_compr4
) {
2688 /* By setting the high bit of the MRF register number, we
2689 * indicate that we want COMPR4 mode - instead of doing the
2690 * usual destination + 1 for the second half we get
2693 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2696 inst
->saturate
= key
->clamp_fragment_color
;
2698 push_force_uncompressed();
2699 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2701 inst
->saturate
= key
->clamp_fragment_color
;
2702 pop_force_uncompressed();
2704 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2706 inst
->force_sechalf
= true;
2707 inst
->saturate
= key
->clamp_fragment_color
;
2713 cond_for_alpha_func(GLenum func
)
2717 return BRW_CONDITIONAL_G
;
2719 return BRW_CONDITIONAL_GE
;
2721 return BRW_CONDITIONAL_L
;
2723 return BRW_CONDITIONAL_LE
;
2725 return BRW_CONDITIONAL_EQ
;
2727 return BRW_CONDITIONAL_NEQ
;
2729 assert(!"Not reached");
2735 * Alpha test support for when we compile it into the shader instead
2736 * of using the normal fixed-function alpha test.
2739 fs_visitor::emit_alpha_test()
2741 this->current_annotation
= "Alpha test";
2744 if (key
->alpha_test_func
== GL_ALWAYS
)
2747 if (key
->alpha_test_func
== GL_NEVER
) {
2749 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2750 BRW_REGISTER_TYPE_UW
));
2751 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2752 BRW_CONDITIONAL_NEQ
));
2755 fs_reg color
= outputs
[0];
2756 color
.reg_offset
+= 3;
2758 /* f0.1 &= func(color, ref) */
2759 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
2760 cond_for_alpha_func(key
->alpha_test_func
)));
2762 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2763 cmp
->flag_subreg
= 1;
2767 fs_visitor::emit_fb_writes()
2769 this->current_annotation
= "FB write header";
2770 bool header_present
= true;
2771 /* We can potentially have a message length of up to 15, so we have to set
2772 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2776 int reg_width
= dispatch_width
/ 8;
2777 bool src0_alpha_to_render_target
= false;
2780 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
2781 if (dispatch_width
== 16)
2782 do_dual_src
= false;
2785 /* From the Sandy Bridge PRM, volume 4, page 198:
2787 * "Dispatched Pixel Enables. One bit per pixel indicating
2788 * which pixels were originally enabled when the thread was
2789 * dispatched. This field is only required for the end-of-
2790 * thread message and on all dual-source messages."
2792 if (brw
->gen
>= 6 &&
2793 (brw
->is_haswell
|| brw
->gen
>= 8 || !this->fp
->UsesKill
) &&
2795 key
->nr_color_regions
== 1) {
2796 header_present
= false;
2799 if (header_present
) {
2800 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
2802 key
->replicate_alpha
;
2807 if (payload
.aa_dest_stencil_reg
) {
2808 push_force_uncompressed();
2809 emit(MOV(fs_reg(MRF
, nr
++),
2810 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
2811 pop_force_uncompressed();
2814 prog_data
->uses_omask
=
2815 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
2816 if (prog_data
->uses_omask
) {
2817 this->current_annotation
= "FB write oMask";
2818 assert(this->sample_mask
.file
!= BAD_FILE
);
2819 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
2820 emit(FS_OPCODE_SET_OMASK
, fs_reg(MRF
, nr
, BRW_REGISTER_TYPE_UW
), this->sample_mask
);
2824 /* Reserve space for color. It'll be filled in per MRT below. */
2826 nr
+= 4 * reg_width
;
2829 if (src0_alpha_to_render_target
)
2832 if (source_depth_to_render_target
) {
2833 if (brw
->gen
== 6) {
2834 /* For outputting oDepth on gen6, SIMD8 writes have to be
2835 * used. This would require SIMD8 moves of each half to
2836 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2837 * Just bail on doing so for now.
2839 no16("Missing support for simd16 depth writes on gen6\n");
2842 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2843 /* Hand over gl_FragDepth. */
2844 assert(this->frag_depth
.file
!= BAD_FILE
);
2845 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2847 /* Pass through the payload depth. */
2848 emit(MOV(fs_reg(MRF
, nr
),
2849 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
2854 if (payload
.dest_depth_reg
) {
2855 emit(MOV(fs_reg(MRF
, nr
),
2856 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
2861 fs_reg src0
= this->outputs
[0];
2862 fs_reg src1
= this->dual_src_output
;
2864 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2866 for (int i
= 0; i
< 4; i
++) {
2867 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2869 inst
->saturate
= key
->clamp_fragment_color
;
2872 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2874 for (int i
= 0; i
< 4; i
++) {
2875 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2878 inst
->saturate
= key
->clamp_fragment_color
;
2881 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2882 emit_shader_time_end();
2884 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2886 inst
->base_mrf
= base_mrf
;
2887 inst
->mlen
= nr
- base_mrf
;
2889 inst
->header_present
= header_present
;
2890 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2891 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2892 inst
->flag_subreg
= 1;
2895 prog_data
->dual_src_blend
= true;
2896 this->current_annotation
= NULL
;
2900 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
2901 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2902 "FB write target %d",
2904 /* If src0_alpha_to_render_target is true, include source zero alpha
2905 * data in RenderTargetWrite message for targets > 0.
2907 int write_color_mrf
= color_mrf
;
2908 if (src0_alpha_to_render_target
&& target
!= 0) {
2910 fs_reg color
= outputs
[0];
2911 color
.reg_offset
+= 3;
2913 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2915 inst
->saturate
= key
->clamp_fragment_color
;
2916 write_color_mrf
= color_mrf
+ reg_width
;
2919 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2920 emit_color_write(target
, i
, write_color_mrf
);
2923 if (target
== key
->nr_color_regions
- 1) {
2926 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2927 emit_shader_time_end();
2930 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2931 inst
->target
= target
;
2932 inst
->base_mrf
= base_mrf
;
2933 if (src0_alpha_to_render_target
&& target
== 0)
2934 inst
->mlen
= nr
- base_mrf
- reg_width
;
2936 inst
->mlen
= nr
- base_mrf
;
2938 inst
->header_present
= header_present
;
2939 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2940 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2941 inst
->flag_subreg
= 1;
2945 if (key
->nr_color_regions
== 0) {
2946 /* Even if there's no color buffers enabled, we still need to send
2947 * alpha out the pipeline to our null renderbuffer to support
2948 * alpha-testing, alpha-to-coverage, and so on.
2950 emit_color_write(0, 3, color_mrf
);
2952 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2953 emit_shader_time_end();
2955 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2956 inst
->base_mrf
= base_mrf
;
2957 inst
->mlen
= nr
- base_mrf
;
2959 inst
->header_present
= header_present
;
2960 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
2961 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2962 inst
->flag_subreg
= 1;
2966 this->current_annotation
= NULL
;
2970 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2972 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2976 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2977 emit(MOV(temp
, *reg
));
2982 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2984 if (rvalue
->type
!= glsl_type::bool_type
)
2987 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2988 emit(AND(temp
, *reg
, fs_reg(1)));
2992 fs_visitor::fs_visitor(struct brw_context
*brw
,
2994 const struct brw_wm_prog_key
*key
,
2995 struct brw_wm_prog_data
*prog_data
,
2996 struct gl_shader_program
*shader_prog
,
2997 struct gl_fragment_program
*fp
,
2998 unsigned dispatch_width
)
2999 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3000 MESA_SHADER_FRAGMENT
),
3001 key(key
), prog_data(prog_data
),
3002 dispatch_width(dispatch_width
)
3005 this->mem_ctx
= mem_ctx
;
3006 this->failed
= false;
3007 this->simd16_unsupported
= false;
3008 this->no16_msg
= NULL
;
3009 this->variable_ht
= hash_table_ctor(0,
3010 hash_table_pointer_hash
,
3011 hash_table_pointer_compare
);
3013 memset(&this->payload
, 0, sizeof(this->payload
));
3014 memset(this->outputs
, 0, sizeof(this->outputs
));
3015 memset(this->output_components
, 0, sizeof(this->output_components
));
3016 this->source_depth_to_render_target
= false;
3017 this->runtime_check_aads_emit
= false;
3018 this->first_non_payload_grf
= 0;
3019 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3021 this->current_annotation
= NULL
;
3022 this->base_ir
= NULL
;
3024 this->virtual_grf_sizes
= NULL
;
3025 this->virtual_grf_count
= 0;
3026 this->virtual_grf_array_size
= 0;
3027 this->virtual_grf_start
= NULL
;
3028 this->virtual_grf_end
= NULL
;
3029 this->live_intervals
= NULL
;
3030 this->regs_live_at_ip
= NULL
;
3033 this->last_scratch
= 0;
3034 this->pull_constant_loc
= NULL
;
3035 this->push_constant_loc
= NULL
;
3037 this->force_uncompressed_stack
= 0;
3039 this->spilled_any_registers
= false;
3040 this->do_dual_src
= false;
3042 if (dispatch_width
== 8)
3043 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3046 fs_visitor::~fs_visitor()
3048 hash_table_dtor(this->variable_ht
);