projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965/gs: Add a case to brwNewProgram() for geometry shaders.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_visitor.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "brw_fs.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50
51 void
52 fs_visitor::visit(ir_variable *ir)
53 {
54 fs_reg *reg = NULL;
55
56 if (variable_storage(ir))
57 return;
58
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
64 } else {
65 reg = emit_general_interpolation(ir);
66 }
67 assert(reg);
68 hash_table_insert(this->variable_ht, reg, ir);
69 return;
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
72
73 if (ir->index > 0) {
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
82 }
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
85 } else {
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
89
90 int vector_elements =
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
93
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
100 }
101 }
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
104
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
108 */
109 if (ir->is_in_uniform_block())
110 return;
111
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
115 }
116 return;
117 }
118
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
122 } else {
123 setup_uniform_values(ir);
124 }
125
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
128 }
129
130 if (!reg)
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
132
133 hash_table_insert(this->variable_ht, reg, ir);
134 }
135
136 void
137 fs_visitor::visit(ir_dereference_variable *ir)
138 {
139 fs_reg *reg = variable_storage(ir->var);
140 this->result = *reg;
141 }
142
143 void
144 fs_visitor::visit(ir_dereference_record *ir)
145 {
146 const glsl_type *struct_type = ir->record->type;
147
148 ir->record->accept(this);
149
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
153 break;
154 offset += type_size(struct_type->fields.structure[i].type);
155 }
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
158 }
159
160 void
161 fs_visitor::visit(ir_dereference_array *ir)
162 {
163 ir_constant *constant_index;
164 fs_reg src;
165 int element_size = type_size(ir->type);
166
167 constant_index = ir->array_index->as_constant();
168
169 ir->array->accept(this);
170 src = this->result;
171 src.type = brw_type_for_base_type(ir->type);
172
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
176 } else {
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
183 */
184 ir->array_index->accept(this);
185
186 fs_reg index_reg;
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
189
190 if (src.reladdr) {
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
192 }
193
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
196 }
197 this->result = src;
198 }
199
200 void
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
202 {
203 if (brw->gen < 6 ||
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
211
212 emit(MUL(y_times_a, y, a));
213
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
217
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
219 } else {
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
222 */
223 emit(LRP(dst, a, y, x));
224 }
225 }
226
227 void
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
230 {
231 fs_inst *inst;
232
233 if (brw->gen >= 6) {
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
236 } else {
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
238
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
241 }
242 }
243
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
246 */
247 bool
248 fs_visitor::try_emit_saturate(ir_expression *ir)
249 {
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
251
252 if (!sat_val)
253 return false;
254
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
256
257 sat_val->accept(this);
258 fs_reg src = this->result;
259
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
261
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
264 */
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
270 } else {
271 modify->saturate = true;
272 this->result = src;
273 }
274
275
276 return true;
277 }
278
279 bool
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
281 {
282 /* 3-src instructions were introduced in gen6. */
283 if (brw->gen < 6)
284 return false;
285
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
288 return false;
289
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
292
293 if (!mul || mul->operation != ir_binop_mul)
294 return false;
295
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
299 return false;
300
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
303
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
306
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
309
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
312
313 return true;
314 }
315
316 void
317 fs_visitor::visit(ir_expression *ir)
318 {
319 unsigned int operand;
320 fs_reg op[3], temp;
321 fs_inst *inst;
322
323 assert(ir->get_num_operands() <= 3);
324
325 if (try_emit_saturate(ir))
326 return;
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
329 return;
330 }
331
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
337 printf("\n");
338 }
339 op[operand] = this->result;
340
341 /* Matrix expression operands should have been broken down to vector
342 * operations already.
343 */
344 assert(!ir->operands[operand]->type->is_matrix());
345 /* And then those vector operands should have been broken down to scalar.
346 */
347 assert(!ir->operands[operand]->type->is_vector());
348 }
349
350 /* Storage for our result. If our result goes into an assignment, it will
351 * just get copy-propagated out, so no worries.
352 */
353 this->result = fs_reg(this, ir->type);
354
355 switch (ir->operation) {
356 case ir_unop_logic_not:
357 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
358 * ones complement of the whole register, not just bit 0.
359 */
360 emit(XOR(this->result, op[0], fs_reg(1)));
361 break;
362 case ir_unop_neg:
363 op[0].negate = !op[0].negate;
364 emit(MOV(this->result, op[0]));
365 break;
366 case ir_unop_abs:
367 op[0].abs = true;
368 op[0].negate = false;
369 emit(MOV(this->result, op[0]));
370 break;
371 case ir_unop_sign:
372 temp = fs_reg(this, ir->type);
373
374 emit(MOV(this->result, fs_reg(0.0f)));
375
376 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
377 inst = emit(MOV(this->result, fs_reg(1.0f)));
378 inst->predicate = BRW_PREDICATE_NORMAL;
379
380 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
381 inst = emit(MOV(this->result, fs_reg(-1.0f)));
382 inst->predicate = BRW_PREDICATE_NORMAL;
383
384 break;
385 case ir_unop_rcp:
386 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
387 break;
388
389 case ir_unop_exp2:
390 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
391 break;
392 case ir_unop_log2:
393 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
394 break;
395 case ir_unop_exp:
396 case ir_unop_log:
397 assert(!"not reached: should be handled by ir_explog_to_explog2");
398 break;
399 case ir_unop_sin:
400 case ir_unop_sin_reduced:
401 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
402 break;
403 case ir_unop_cos:
404 case ir_unop_cos_reduced:
405 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
406 break;
407
408 case ir_unop_dFdx:
409 emit(FS_OPCODE_DDX, this->result, op[0]);
410 break;
411 case ir_unop_dFdy:
412 emit(FS_OPCODE_DDY, this->result, op[0]);
413 break;
414
415 case ir_binop_add:
416 emit(ADD(this->result, op[0], op[1]));
417 break;
418 case ir_binop_sub:
419 assert(!"not reached: should be handled by ir_sub_to_add_neg");
420 break;
421
422 case ir_binop_mul:
423 if (ir->type->is_integer()) {
424 /* For integer multiplication, the MUL uses the low 16 bits
425 * of one of the operands (src0 on gen6, src1 on gen7). The
426 * MACH accumulates in the contribution of the upper 16 bits
427 * of that operand.
428 *
429 * FINISHME: Emit just the MUL if we know an operand is small
430 * enough.
431 */
432 if (brw->gen >= 7 && dispatch_width == 16)
433 fail("16-wide explicit accumulator operands unsupported\n");
434
435 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
436
437 emit(MUL(acc, op[0], op[1]));
438 emit(MACH(reg_null_d, op[0], op[1]));
439 emit(MOV(this->result, fs_reg(acc)));
440 } else {
441 emit(MUL(this->result, op[0], op[1]));
442 }
443 break;
444 case ir_binop_div:
445 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
446 assert(ir->type->is_integer());
447 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
448 break;
449 case ir_binop_mod:
450 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
451 assert(ir->type->is_integer());
452 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
453 break;
454
455 case ir_binop_less:
456 case ir_binop_greater:
457 case ir_binop_lequal:
458 case ir_binop_gequal:
459 case ir_binop_equal:
460 case ir_binop_all_equal:
461 case ir_binop_nequal:
462 case ir_binop_any_nequal:
463 resolve_bool_comparison(ir->operands[0], &op[0]);
464 resolve_bool_comparison(ir->operands[1], &op[1]);
465
466 emit(CMP(this->result, op[0], op[1],
467 brw_conditional_for_comparison(ir->operation)));
468 break;
469
470 case ir_binop_logic_xor:
471 emit(XOR(this->result, op[0], op[1]));
472 break;
473
474 case ir_binop_logic_or:
475 emit(OR(this->result, op[0], op[1]));
476 break;
477
478 case ir_binop_logic_and:
479 emit(AND(this->result, op[0], op[1]));
480 break;
481
482 case ir_binop_dot:
483 case ir_unop_any:
484 assert(!"not reached: should be handled by brw_fs_channel_expressions");
485 break;
486
487 case ir_unop_noise:
488 assert(!"not reached: should be handled by lower_noise");
489 break;
490
491 case ir_quadop_vector:
492 assert(!"not reached: should be handled by lower_quadop_vector");
493 break;
494
495 case ir_binop_vector_extract:
496 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
497 break;
498
499 case ir_triop_vector_insert:
500 assert(!"not reached: should be handled by lower_vector_insert()");
501 break;
502
503 case ir_unop_sqrt:
504 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
505 break;
506
507 case ir_unop_rsq:
508 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
509 break;
510
511 case ir_unop_bitcast_i2f:
512 case ir_unop_bitcast_u2f:
513 op[0].type = BRW_REGISTER_TYPE_F;
514 this->result = op[0];
515 break;
516 case ir_unop_i2u:
517 case ir_unop_bitcast_f2u:
518 op[0].type = BRW_REGISTER_TYPE_UD;
519 this->result = op[0];
520 break;
521 case ir_unop_u2i:
522 case ir_unop_bitcast_f2i:
523 op[0].type = BRW_REGISTER_TYPE_D;
524 this->result = op[0];
525 break;
526 case ir_unop_i2f:
527 case ir_unop_u2f:
528 case ir_unop_f2i:
529 case ir_unop_f2u:
530 emit(MOV(this->result, op[0]));
531 break;
532
533 case ir_unop_b2i:
534 emit(AND(this->result, op[0], fs_reg(1)));
535 break;
536 case ir_unop_b2f:
537 temp = fs_reg(this, glsl_type::int_type);
538 emit(AND(temp, op[0], fs_reg(1)));
539 emit(MOV(this->result, temp));
540 break;
541
542 case ir_unop_f2b:
543 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
544 break;
545 case ir_unop_i2b:
546 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
547 break;
548
549 case ir_unop_trunc:
550 emit(RNDZ(this->result, op[0]));
551 break;
552 case ir_unop_ceil:
553 op[0].negate = !op[0].negate;
554 emit(RNDD(this->result, op[0]));
555 this->result.negate = true;
556 break;
557 case ir_unop_floor:
558 emit(RNDD(this->result, op[0]));
559 break;
560 case ir_unop_fract:
561 emit(FRC(this->result, op[0]));
562 break;
563 case ir_unop_round_even:
564 emit(RNDE(this->result, op[0]));
565 break;
566
567 case ir_binop_min:
568 case ir_binop_max:
569 resolve_ud_negate(&op[0]);
570 resolve_ud_negate(&op[1]);
571 emit_minmax(ir->operation == ir_binop_min ?
572 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
573 this->result, op[0], op[1]);
574 break;
575 case ir_unop_pack_snorm_2x16:
576 case ir_unop_pack_snorm_4x8:
577 case ir_unop_pack_unorm_2x16:
578 case ir_unop_pack_unorm_4x8:
579 case ir_unop_unpack_snorm_2x16:
580 case ir_unop_unpack_snorm_4x8:
581 case ir_unop_unpack_unorm_2x16:
582 case ir_unop_unpack_unorm_4x8:
583 case ir_unop_unpack_half_2x16:
584 case ir_unop_pack_half_2x16:
585 assert(!"not reached: should be handled by lower_packing_builtins");
586 break;
587 case ir_unop_unpack_half_2x16_split_x:
588 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
589 break;
590 case ir_unop_unpack_half_2x16_split_y:
591 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
592 break;
593 case ir_binop_pow:
594 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
595 break;
596
597 case ir_unop_bitfield_reverse:
598 emit(BFREV(this->result, op[0]));
599 break;
600 case ir_unop_bit_count:
601 emit(CBIT(this->result, op[0]));
602 break;
603 case ir_unop_find_msb:
604 temp = fs_reg(this, glsl_type::uint_type);
605 emit(FBH(temp, op[0]));
606
607 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
608 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
609 * subtract the result from 31 to convert the MSB count into an LSB count.
610 */
611
612 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
613 emit(MOV(this->result, temp));
614 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
615
616 temp.negate = true;
617 inst = emit(ADD(this->result, temp, fs_reg(31)));
618 inst->predicate = BRW_PREDICATE_NORMAL;
619 break;
620 case ir_unop_find_lsb:
621 emit(FBL(this->result, op[0]));
622 break;
623 case ir_triop_bitfield_extract:
624 /* Note that the instruction's argument order is reversed from GLSL
625 * and the IR.
626 */
627 emit(BFE(this->result, op[2], op[1], op[0]));
628 break;
629 case ir_binop_bfm:
630 emit(BFI1(this->result, op[0], op[1]));
631 break;
632 case ir_triop_bfi:
633 emit(BFI2(this->result, op[0], op[1], op[2]));
634 break;
635 case ir_quadop_bitfield_insert:
636 assert(!"not reached: should be handled by "
637 "lower_instructions::bitfield_insert_to_bfm_bfi");
638 break;
639
640 case ir_unop_bit_not:
641 emit(NOT(this->result, op[0]));
642 break;
643 case ir_binop_bit_and:
644 emit(AND(this->result, op[0], op[1]));
645 break;
646 case ir_binop_bit_xor:
647 emit(XOR(this->result, op[0], op[1]));
648 break;
649 case ir_binop_bit_or:
650 emit(OR(this->result, op[0], op[1]));
651 break;
652
653 case ir_binop_lshift:
654 emit(SHL(this->result, op[0], op[1]));
655 break;
656
657 case ir_binop_rshift:
658 if (ir->type->base_type == GLSL_TYPE_INT)
659 emit(ASR(this->result, op[0], op[1]));
660 else
661 emit(SHR(this->result, op[0], op[1]));
662 break;
663 case ir_binop_pack_half_2x16_split:
664 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
665 break;
666 case ir_binop_ubo_load: {
667 /* This IR node takes a constant uniform block and a constant or
668 * variable byte offset within the block and loads a vector from that.
669 */
670 ir_constant *uniform_block = ir->operands[0]->as_constant();
671 ir_constant *const_offset = ir->operands[1]->as_constant();
672 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
673 if (const_offset) {
674 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
675 packed_consts.type = result.type;
676
677 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
678 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
679 packed_consts, surf_index, const_offset_reg));
680
681 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
682 for (int i = 0; i < ir->type->vector_elements; i++) {
683 /* UBO bools are any nonzero value. We consider bools to be
684 * values with the low bit set to 1. Convert them using CMP.
685 */
686 if (ir->type->base_type == GLSL_TYPE_BOOL) {
687 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
688 } else {
689 emit(MOV(result, packed_consts));
690 }
691
692 packed_consts.smear++;
693 result.reg_offset++;
694
695 /* The std140 packing rules don't allow vectors to cross 16-byte
696 * boundaries, and a reg is 32 bytes.
697 */
698 assert(packed_consts.smear < 8);
699 }
700 } else {
701 /* Turn the byte offset into a dword offset. */
702 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
703 emit(SHR(base_offset, op[1], fs_reg(2)));
704
705 for (int i = 0; i < ir->type->vector_elements; i++) {
706 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
707 base_offset, i));
708
709 if (ir->type->base_type == GLSL_TYPE_BOOL)
710 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
711
712 result.reg_offset++;
713 }
714 }
715
716 result.reg_offset = 0;
717 break;
718 }
719
720 case ir_triop_lrp:
721 emit_lrp(this->result, op[0], op[1], op[2]);
722 break;
723 }
724 }
725
726 void
727 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
728 const glsl_type *type, bool predicated)
729 {
730 switch (type->base_type) {
731 case GLSL_TYPE_FLOAT:
732 case GLSL_TYPE_UINT:
733 case GLSL_TYPE_INT:
734 case GLSL_TYPE_BOOL:
735 for (unsigned int i = 0; i < type->components(); i++) {
736 l.type = brw_type_for_base_type(type);
737 r.type = brw_type_for_base_type(type);
738
739 if (predicated || !l.equals(r)) {
740 fs_inst *inst = emit(MOV(l, r));
741 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
742 }
743
744 l.reg_offset++;
745 r.reg_offset++;
746 }
747 break;
748 case GLSL_TYPE_ARRAY:
749 for (unsigned int i = 0; i < type->length; i++) {
750 emit_assignment_writes(l, r, type->fields.array, predicated);
751 }
752 break;
753
754 case GLSL_TYPE_STRUCT:
755 for (unsigned int i = 0; i < type->length; i++) {
756 emit_assignment_writes(l, r, type->fields.structure[i].type,
757 predicated);
758 }
759 break;
760
761 case GLSL_TYPE_SAMPLER:
762 break;
763
764 case GLSL_TYPE_VOID:
765 case GLSL_TYPE_ERROR:
766 case GLSL_TYPE_INTERFACE:
767 assert(!"not reached");
768 break;
769 }
770 }
771
772 /* If the RHS processing resulted in an instruction generating a
773 * temporary value, and it would be easy to rewrite the instruction to
774 * generate its result right into the LHS instead, do so. This ends
775 * up reliably removing instructions where it can be tricky to do so
776 * later without real UD chain information.
777 */
778 bool
779 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
780 fs_reg dst,
781 fs_reg src,
782 fs_inst *pre_rhs_inst,
783 fs_inst *last_rhs_inst)
784 {
785 /* Only attempt if we're doing a direct assignment. */
786 if (ir->condition ||
787 !(ir->lhs->type->is_scalar() ||
788 (ir->lhs->type->is_vector() &&
789 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
790 return false;
791
792 /* Make sure the last instruction generated our source reg. */
793 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
794 last_rhs_inst,
795 src);
796 if (!modify)
797 return false;
798
799 /* If last_rhs_inst wrote a different number of components than our LHS,
800 * we can't safely rewrite it.
801 */
802 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
803 return false;
804
805 /* Success! Rewrite the instruction. */
806 modify->dst = dst;
807
808 return true;
809 }
810
811 void
812 fs_visitor::visit(ir_assignment *ir)
813 {
814 fs_reg l, r;
815 fs_inst *inst;
816
817 /* FINISHME: arrays on the lhs */
818 ir->lhs->accept(this);
819 l = this->result;
820
821 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
822
823 ir->rhs->accept(this);
824 r = this->result;
825
826 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
827
828 assert(l.file != BAD_FILE);
829 assert(r.file != BAD_FILE);
830
831 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
832 return;
833
834 if (ir->condition) {
835 emit_bool_to_cond_code(ir->condition);
836 }
837
838 if (ir->lhs->type->is_scalar() ||
839 ir->lhs->type->is_vector()) {
840 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
841 if (ir->write_mask & (1 << i)) {
842 inst = emit(MOV(l, r));
843 if (ir->condition)
844 inst->predicate = BRW_PREDICATE_NORMAL;
845 r.reg_offset++;
846 }
847 l.reg_offset++;
848 }
849 } else {
850 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
851 }
852 }
853
854 fs_inst *
855 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
856 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
857 {
858 int mlen;
859 int base_mrf = 1;
860 bool simd16 = false;
861 fs_reg orig_dst;
862
863 /* g0 header. */
864 mlen = 1;
865
866 if (ir->shadow_comparitor) {
867 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
868 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
869 coordinate.reg_offset++;
870 }
871 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
872 mlen += 3;
873
874 if (ir->op == ir_tex) {
875 /* There's no plain shadow compare message, so we use shadow
876 * compare with a bias of 0.0.
877 */
878 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
879 mlen++;
880 } else if (ir->op == ir_txb || ir->op == ir_txl) {
881 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
882 mlen++;
883 } else {
884 assert(!"Should not get here.");
885 }
886
887 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
888 mlen++;
889 } else if (ir->op == ir_tex) {
890 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
891 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
892 coordinate.reg_offset++;
893 }
894 /* zero the others. */
895 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
896 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
897 }
898 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
899 mlen += 3;
900 } else if (ir->op == ir_txd) {
901 fs_reg &dPdx = lod;
902
903 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
904 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
905 coordinate.reg_offset++;
906 }
907 /* the slots for u and v are always present, but r is optional */
908 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
909
910 /* P = u, v, r
911 * dPdx = dudx, dvdx, drdx
912 * dPdy = dudy, dvdy, drdy
913 *
914 * 1-arg: Does not exist.
915 *
916 * 2-arg: dudx dvdx dudy dvdy
917 * dPdx.x dPdx.y dPdy.x dPdy.y
918 * m4 m5 m6 m7
919 *
920 * 3-arg: dudx dvdx drdx dudy dvdy drdy
921 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
922 * m5 m6 m7 m8 m9 m10
923 */
924 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
925 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
926 dPdx.reg_offset++;
927 }
928 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
929
930 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
931 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
932 dPdy.reg_offset++;
933 }
934 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
935 } else if (ir->op == ir_txs) {
936 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
937 simd16 = true;
938 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
939 mlen += 2;
940 } else {
941 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
942 * instructions. We'll need to do SIMD16 here.
943 */
944 simd16 = true;
945 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
946
947 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
948 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
949 coordinate));
950 coordinate.reg_offset++;
951 }
952
953 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
954 * be necessary for TXF (ld), but seems wise to do for all messages.
955 */
956 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
957 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
958 }
959
960 /* lod/bias appears after u/v/r. */
961 mlen += 6;
962
963 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
964 mlen++;
965
966 /* The unused upper half. */
967 mlen++;
968 }
969
970 if (simd16) {
971 /* Now, since we're doing simd16, the return is 2 interleaved
972 * vec4s where the odd-indexed ones are junk. We'll need to move
973 * this weirdness around to the expected layout.
974 */
975 orig_dst = dst;
976 dst = fs_reg(GRF, virtual_grf_alloc(8),
977 (brw->is_g4x ?
978 brw_type_for_base_type(ir->type) :
979 BRW_REGISTER_TYPE_F));
980 }
981
982 fs_inst *inst = NULL;
983 switch (ir->op) {
984 case ir_tex:
985 inst = emit(SHADER_OPCODE_TEX, dst);
986 break;
987 case ir_txb:
988 inst = emit(FS_OPCODE_TXB, dst);
989 break;
990 case ir_txl:
991 inst = emit(SHADER_OPCODE_TXL, dst);
992 break;
993 case ir_txd:
994 inst = emit(SHADER_OPCODE_TXD, dst);
995 break;
996 case ir_txs:
997 inst = emit(SHADER_OPCODE_TXS, dst);
998 break;
999 case ir_txf:
1000 inst = emit(SHADER_OPCODE_TXF, dst);
1001 break;
1002 default:
1003 fail("unrecognized texture opcode");
1004 }
1005 inst->base_mrf = base_mrf;
1006 inst->mlen = mlen;
1007 inst->header_present = true;
1008 inst->regs_written = simd16 ? 8 : 4;
1009
1010 if (simd16) {
1011 for (int i = 0; i < 4; i++) {
1012 emit(MOV(orig_dst, dst));
1013 orig_dst.reg_offset++;
1014 dst.reg_offset += 2;
1015 }
1016 }
1017
1018 return inst;
1019 }
1020
1021 /* gen5's sampler has slots for u, v, r, array index, then optional
1022 * parameters like shadow comparitor or LOD bias. If optional
1023 * parameters aren't present, those base slots are optional and don't
1024 * need to be included in the message.
1025 *
1026 * We don't fill in the unnecessary slots regardless, which may look
1027 * surprising in the disassembly.
1028 */
1029 fs_inst *
1030 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1031 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1032 fs_reg sample_index)
1033 {
1034 int mlen = 0;
1035 int base_mrf = 2;
1036 int reg_width = dispatch_width / 8;
1037 bool header_present = false;
1038 const int vector_elements =
1039 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1040
1041 if (ir->offset != NULL && ir->op == ir_txf) {
1042 /* It appears that the ld instruction used for txf does its
1043 * address bounds check before adding in the offset. To work
1044 * around this, just add the integer offset to the integer texel
1045 * coordinate, and don't put the offset in the header.
1046 */
1047 ir_constant *offset = ir->offset->as_constant();
1048 for (int i = 0; i < vector_elements; i++) {
1049 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1050 coordinate,
1051 offset->value.i[i]));
1052 coordinate.reg_offset++;
1053 }
1054 } else {
1055 if (ir->offset) {
1056 /* The offsets set up by the ir_texture visitor are in the
1057 * m1 header, so we can't go headerless.
1058 */
1059 header_present = true;
1060 mlen++;
1061 base_mrf--;
1062 }
1063
1064 for (int i = 0; i < vector_elements; i++) {
1065 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1066 coordinate));
1067 coordinate.reg_offset++;
1068 }
1069 }
1070 mlen += vector_elements * reg_width;
1071
1072 if (ir->shadow_comparitor) {
1073 mlen = MAX2(mlen, header_present + 4 * reg_width);
1074
1075 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1076 mlen += reg_width;
1077 }
1078
1079 fs_inst *inst = NULL;
1080 switch (ir->op) {
1081 case ir_tex:
1082 inst = emit(SHADER_OPCODE_TEX, dst);
1083 break;
1084 case ir_txb:
1085 mlen = MAX2(mlen, header_present + 4 * reg_width);
1086 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1087 mlen += reg_width;
1088
1089 inst = emit(FS_OPCODE_TXB, dst);
1090 break;
1091 case ir_txl:
1092 mlen = MAX2(mlen, header_present + 4 * reg_width);
1093 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1094 mlen += reg_width;
1095
1096 inst = emit(SHADER_OPCODE_TXL, dst);
1097 break;
1098 case ir_txd: {
1099 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1100
1101 /**
1102 * P = u, v, r
1103 * dPdx = dudx, dvdx, drdx
1104 * dPdy = dudy, dvdy, drdy
1105 *
1106 * Load up these values:
1107 * - dudx dudy dvdx dvdy drdx drdy
1108 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1109 */
1110 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1111 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1112 lod.reg_offset++;
1113 mlen += reg_width;
1114
1115 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1116 lod2.reg_offset++;
1117 mlen += reg_width;
1118 }
1119
1120 inst = emit(SHADER_OPCODE_TXD, dst);
1121 break;
1122 }
1123 case ir_txs:
1124 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1125 mlen += reg_width;
1126 inst = emit(SHADER_OPCODE_TXS, dst);
1127 break;
1128 case ir_txf:
1129 mlen = header_present + 4 * reg_width;
1130 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1131 inst = emit(SHADER_OPCODE_TXF, dst);
1132 break;
1133 case ir_txf_ms:
1134 mlen = header_present + 4 * reg_width;
1135
1136 /* lod */
1137 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1138 /* sample index */
1139 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1140 mlen += reg_width;
1141 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1142 break;
1143 case ir_lod:
1144 inst = emit(SHADER_OPCODE_LOD, dst);
1145 break;
1146 }
1147 inst->base_mrf = base_mrf;
1148 inst->mlen = mlen;
1149 inst->header_present = header_present;
1150 inst->regs_written = 4;
1151
1152 if (mlen > 11) {
1153 fail("Message length >11 disallowed by hardware\n");
1154 }
1155
1156 return inst;
1157 }
1158
1159 fs_inst *
1160 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1161 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1162 fs_reg sample_index)
1163 {
1164 int mlen = 0;
1165 int base_mrf = 2;
1166 int reg_width = dispatch_width / 8;
1167 bool header_present = false;
1168 int offsets[3];
1169
1170 if (ir->offset && ir->op != ir_txf) {
1171 /* The offsets set up by the ir_texture visitor are in the
1172 * m1 header, so we can't go headerless.
1173 */
1174 header_present = true;
1175 mlen++;
1176 base_mrf--;
1177 }
1178
1179 if (ir->shadow_comparitor) {
1180 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1181 mlen += reg_width;
1182 }
1183
1184 /* Set up the LOD info */
1185 switch (ir->op) {
1186 case ir_tex:
1187 case ir_lod:
1188 break;
1189 case ir_txb:
1190 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1191 mlen += reg_width;
1192 break;
1193 case ir_txl:
1194 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1195 mlen += reg_width;
1196 break;
1197 case ir_txd: {
1198 if (dispatch_width == 16)
1199 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1200
1201 /* Load dPdx and the coordinate together:
1202 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1203 */
1204 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1205 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1206 coordinate.reg_offset++;
1207 mlen += reg_width;
1208
1209 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1210 * only derivatives for (u, v, r).
1211 */
1212 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1213 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1214 lod.reg_offset++;
1215 mlen += reg_width;
1216
1217 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1218 lod2.reg_offset++;
1219 mlen += reg_width;
1220 }
1221 }
1222 break;
1223 }
1224 case ir_txs:
1225 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1226 mlen += reg_width;
1227 break;
1228 case ir_txf:
1229 /* It appears that the ld instruction used for txf does its
1230 * address bounds check before adding in the offset. To work
1231 * around this, just add the integer offset to the integer texel
1232 * coordinate, and don't put the offset in the header.
1233 */
1234 if (ir->offset) {
1235 ir_constant *offset = ir->offset->as_constant();
1236 offsets[0] = offset->value.i[0];
1237 offsets[1] = offset->value.i[1];
1238 offsets[2] = offset->value.i[2];
1239 } else {
1240 memset(offsets, 0, sizeof(offsets));
1241 }
1242
1243 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1244 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1245 coordinate, offsets[0]));
1246 coordinate.reg_offset++;
1247 mlen += reg_width;
1248
1249 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1250 mlen += reg_width;
1251
1252 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1253 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1254 coordinate, offsets[i]));
1255 coordinate.reg_offset++;
1256 mlen += reg_width;
1257 }
1258 break;
1259 case ir_txf_ms:
1260 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1261 mlen += reg_width;
1262
1263 /* constant zero MCS; we arrange to never actually have a compressed
1264 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1265 * if we ever support texturing from compressed multisample surfaces
1266 */
1267 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1268 mlen += reg_width;
1269
1270 /* there is no offsetting for this message; just copy in the integer
1271 * texture coordinates
1272 */
1273 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1274 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1275 coordinate));
1276 coordinate.reg_offset++;
1277 mlen += reg_width;
1278 }
1279 break;
1280 }
1281
1282 /* Set up the coordinate (except for cases where it was done above) */
1283 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
1284 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1285 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1286 coordinate.reg_offset++;
1287 mlen += reg_width;
1288 }
1289 }
1290
1291 /* Generate the SEND */
1292 fs_inst *inst = NULL;
1293 switch (ir->op) {
1294 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1295 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1296 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1297 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1298 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1299 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1300 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1301 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1302 }
1303 inst->base_mrf = base_mrf;
1304 inst->mlen = mlen;
1305 inst->header_present = header_present;
1306 inst->regs_written = 4;
1307
1308 if (mlen > 11) {
1309 fail("Message length >11 disallowed by hardware\n");
1310 }
1311
1312 return inst;
1313 }
1314
1315 fs_reg
1316 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1317 bool is_rect, int sampler, int texunit)
1318 {
1319 fs_inst *inst = NULL;
1320 bool needs_gl_clamp = true;
1321 fs_reg scale_x, scale_y;
1322
1323 /* The 965 requires the EU to do the normalization of GL rectangle
1324 * texture coordinates. We use the program parameter state
1325 * tracking to get the scaling factor.
1326 */
1327 if (is_rect &&
1328 (brw->gen < 6 ||
1329 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1330 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1331 struct gl_program_parameter_list *params = fp->Base.Parameters;
1332 int tokens[STATE_LENGTH] = {
1333 STATE_INTERNAL,
1334 STATE_TEXRECT_SCALE,
1335 texunit,
1336 0,
1337 0
1338 };
1339
1340 if (dispatch_width == 16) {
1341 fail("rectangle scale uniform setup not supported on 16-wide\n");
1342 return coordinate;
1343 }
1344
1345 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1346 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1347
1348 GLuint index = _mesa_add_state_reference(params,
1349 (gl_state_index *)tokens);
1350 c->prog_data.param[c->prog_data.nr_params++] =
1351 &fp->Base.Parameters->ParameterValues[index][0].f;
1352 c->prog_data.param[c->prog_data.nr_params++] =
1353 &fp->Base.Parameters->ParameterValues[index][1].f;
1354 }
1355
1356 /* The 965 requires the EU to do the normalization of GL rectangle
1357 * texture coordinates. We use the program parameter state
1358 * tracking to get the scaling factor.
1359 */
1360 if (brw->gen < 6 && is_rect) {
1361 fs_reg dst = fs_reg(this, ir->coordinate->type);
1362 fs_reg src = coordinate;
1363 coordinate = dst;
1364
1365 emit(MUL(dst, src, scale_x));
1366 dst.reg_offset++;
1367 src.reg_offset++;
1368 emit(MUL(dst, src, scale_y));
1369 } else if (is_rect) {
1370 /* On gen6+, the sampler handles the rectangle coordinates
1371 * natively, without needing rescaling. But that means we have
1372 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1373 * not [0, 1] like the default case below.
1374 */
1375 needs_gl_clamp = false;
1376
1377 for (int i = 0; i < 2; i++) {
1378 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1379 fs_reg chan = coordinate;
1380 chan.reg_offset += i;
1381
1382 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1383 inst->conditional_mod = BRW_CONDITIONAL_G;
1384
1385 /* Our parameter comes in as 1.0/width or 1.0/height,
1386 * because that's what people normally want for doing
1387 * texture rectangle handling. We need width or height
1388 * for clamping, but we don't care enough to make a new
1389 * parameter type, so just invert back.
1390 */
1391 fs_reg limit = fs_reg(this, glsl_type::float_type);
1392 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1393 emit(SHADER_OPCODE_RCP, limit, limit);
1394
1395 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1396 inst->conditional_mod = BRW_CONDITIONAL_L;
1397 }
1398 }
1399 }
1400
1401 if (ir->coordinate && needs_gl_clamp) {
1402 for (unsigned int i = 0;
1403 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1404 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1405 fs_reg chan = coordinate;
1406 chan.reg_offset += i;
1407
1408 fs_inst *inst = emit(MOV(chan, chan));
1409 inst->saturate = true;
1410 }
1411 }
1412 }
1413 return coordinate;
1414 }
1415
1416 void
1417 fs_visitor::visit(ir_texture *ir)
1418 {
1419 fs_inst *inst = NULL;
1420
1421 int sampler =
1422 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1423 /* FINISHME: We're failing to recompile our programs when the sampler is
1424 * updated. This only matters for the texture rectangle scale parameters
1425 * (pre-gen6, or gen6+ with GL_CLAMP).
1426 */
1427 int texunit = fp->Base.SamplerUnits[sampler];
1428
1429 /* Should be lowered by do_lower_texture_projection */
1430 assert(!ir->projector);
1431
1432 /* Generate code to compute all the subexpression trees. This has to be
1433 * done before loading any values into MRFs for the sampler message since
1434 * generating these values may involve SEND messages that need the MRFs.
1435 */
1436 fs_reg coordinate;
1437 if (ir->coordinate) {
1438 ir->coordinate->accept(this);
1439
1440 coordinate = rescale_texcoord(ir, this->result,
1441 ir->sampler->type->sampler_dimensionality ==
1442 GLSL_SAMPLER_DIM_RECT,
1443 sampler, texunit);
1444 }
1445
1446 fs_reg shadow_comparitor;
1447 if (ir->shadow_comparitor) {
1448 ir->shadow_comparitor->accept(this);
1449 shadow_comparitor = this->result;
1450 }
1451
1452 fs_reg lod, lod2, sample_index;
1453 switch (ir->op) {
1454 case ir_tex:
1455 case ir_lod:
1456 break;
1457 case ir_txb:
1458 ir->lod_info.bias->accept(this);
1459 lod = this->result;
1460 break;
1461 case ir_txd:
1462 ir->lod_info.grad.dPdx->accept(this);
1463 lod = this->result;
1464
1465 ir->lod_info.grad.dPdy->accept(this);
1466 lod2 = this->result;
1467 break;
1468 case ir_txf:
1469 case ir_txl:
1470 case ir_txs:
1471 ir->lod_info.lod->accept(this);
1472 lod = this->result;
1473 break;
1474 case ir_txf_ms:
1475 ir->lod_info.sample_index->accept(this);
1476 sample_index = this->result;
1477 break;
1478 };
1479
1480 /* Writemasking doesn't eliminate channels on SIMD8 texture
1481 * samples, so don't worry about them.
1482 */
1483 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1484
1485 if (brw->gen >= 7) {
1486 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1487 lod, lod2, sample_index);
1488 } else if (brw->gen >= 5) {
1489 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1490 lod, lod2, sample_index);
1491 } else {
1492 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1493 lod, lod2);
1494 }
1495
1496 /* The header is set up by generate_tex() when necessary. */
1497 inst->src[0] = reg_undef;
1498
1499 if (ir->offset != NULL && ir->op != ir_txf)
1500 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1501
1502 inst->sampler = sampler;
1503
1504 if (ir->shadow_comparitor)
1505 inst->shadow_compare = true;
1506
1507 /* fixup #layers for cube map arrays */
1508 if (ir->op == ir_txs) {
1509 glsl_type const *type = ir->sampler->type;
1510 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1511 type->sampler_array) {
1512 fs_reg depth = dst;
1513 depth.reg_offset = 2;
1514 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1515 }
1516 }
1517
1518 swizzle_result(ir, dst, sampler);
1519 }
1520
1521 /**
1522 * Swizzle the result of a texture result. This is necessary for
1523 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1524 */
1525 void
1526 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1527 {
1528 this->result = orig_val;
1529
1530 if (ir->op == ir_txs || ir->op == ir_lod)
1531 return;
1532
1533 if (ir->type == glsl_type::float_type) {
1534 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1535 assert(ir->sampler->type->sampler_shadow);
1536 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1537 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1538
1539 for (int i = 0; i < 4; i++) {
1540 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1541 fs_reg l = swizzled_result;
1542 l.reg_offset += i;
1543
1544 if (swiz == SWIZZLE_ZERO) {
1545 emit(MOV(l, fs_reg(0.0f)));
1546 } else if (swiz == SWIZZLE_ONE) {
1547 emit(MOV(l, fs_reg(1.0f)));
1548 } else {
1549 fs_reg r = orig_val;
1550 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1551 emit(MOV(l, r));
1552 }
1553 }
1554 this->result = swizzled_result;
1555 }
1556 }
1557
1558 void
1559 fs_visitor::visit(ir_swizzle *ir)
1560 {
1561 ir->val->accept(this);
1562 fs_reg val = this->result;
1563
1564 if (ir->type->vector_elements == 1) {
1565 this->result.reg_offset += ir->mask.x;
1566 return;
1567 }
1568
1569 fs_reg result = fs_reg(this, ir->type);
1570 this->result = result;
1571
1572 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1573 fs_reg channel = val;
1574 int swiz = 0;
1575
1576 switch (i) {
1577 case 0:
1578 swiz = ir->mask.x;
1579 break;
1580 case 1:
1581 swiz = ir->mask.y;
1582 break;
1583 case 2:
1584 swiz = ir->mask.z;
1585 break;
1586 case 3:
1587 swiz = ir->mask.w;
1588 break;
1589 }
1590
1591 channel.reg_offset += swiz;
1592 emit(MOV(result, channel));
1593 result.reg_offset++;
1594 }
1595 }
1596
1597 void
1598 fs_visitor::visit(ir_discard *ir)
1599 {
1600 assert(ir->condition == NULL); /* FINISHME */
1601
1602 /* We track our discarded pixels in f0.1. By predicating on it, we can
1603 * update just the flag bits that aren't yet discarded. By emitting a
1604 * CMP of g0 != g0, all our currently executing channels will get turned
1605 * off.
1606 */
1607 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1608 BRW_REGISTER_TYPE_UW));
1609 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1610 BRW_CONDITIONAL_NZ));
1611 cmp->predicate = BRW_PREDICATE_NORMAL;
1612 cmp->flag_subreg = 1;
1613
1614 if (brw->gen >= 6) {
1615 /* For performance, after a discard, jump to the end of the shader.
1616 * However, many people will do foliage by discarding based on a
1617 * texture's alpha mask, and then continue on to texture with the
1618 * remaining pixels. To avoid trashing the derivatives for those
1619 * texture samples, we'll only jump if all of the pixels in the subspan
1620 * have been discarded.
1621 */
1622 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1623 discard_jump->flag_subreg = 1;
1624 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1625 discard_jump->predicate_inverse = true;
1626 }
1627 }
1628
1629 void
1630 fs_visitor::visit(ir_constant *ir)
1631 {
1632 /* Set this->result to reg at the bottom of the function because some code
1633 * paths will cause this visitor to be applied to other fields. This will
1634 * cause the value stored in this->result to be modified.
1635 *
1636 * Make reg constant so that it doesn't get accidentally modified along the
1637 * way. Yes, I actually had this problem. :(
1638 */
1639 const fs_reg reg(this, ir->type);
1640 fs_reg dst_reg = reg;
1641
1642 if (ir->type->is_array()) {
1643 const unsigned size = type_size(ir->type->fields.array);
1644
1645 for (unsigned i = 0; i < ir->type->length; i++) {
1646 ir->array_elements[i]->accept(this);
1647 fs_reg src_reg = this->result;
1648
1649 dst_reg.type = src_reg.type;
1650 for (unsigned j = 0; j < size; j++) {
1651 emit(MOV(dst_reg, src_reg));
1652 src_reg.reg_offset++;
1653 dst_reg.reg_offset++;
1654 }
1655 }
1656 } else if (ir->type->is_record()) {
1657 foreach_list(node, &ir->components) {
1658 ir_constant *const field = (ir_constant *) node;
1659 const unsigned size = type_size(field->type);
1660
1661 field->accept(this);
1662 fs_reg src_reg = this->result;
1663
1664 dst_reg.type = src_reg.type;
1665 for (unsigned j = 0; j < size; j++) {
1666 emit(MOV(dst_reg, src_reg));
1667 src_reg.reg_offset++;
1668 dst_reg.reg_offset++;
1669 }
1670 }
1671 } else {
1672 const unsigned size = type_size(ir->type);
1673
1674 for (unsigned i = 0; i < size; i++) {
1675 switch (ir->type->base_type) {
1676 case GLSL_TYPE_FLOAT:
1677 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1678 break;
1679 case GLSL_TYPE_UINT:
1680 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1681 break;
1682 case GLSL_TYPE_INT:
1683 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1684 break;
1685 case GLSL_TYPE_BOOL:
1686 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1687 break;
1688 default:
1689 assert(!"Non-float/uint/int/bool constant");
1690 }
1691 dst_reg.reg_offset++;
1692 }
1693 }
1694
1695 this->result = reg;
1696 }
1697
1698 void
1699 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1700 {
1701 ir_expression *expr = ir->as_expression();
1702
1703 if (expr) {
1704 fs_reg op[2];
1705 fs_inst *inst;
1706
1707 assert(expr->get_num_operands() <= 2);
1708 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1709 assert(expr->operands[i]->type->is_scalar());
1710
1711 expr->operands[i]->accept(this);
1712 op[i] = this->result;
1713
1714 resolve_ud_negate(&op[i]);
1715 }
1716
1717 switch (expr->operation) {
1718 case ir_unop_logic_not:
1719 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1720 inst->conditional_mod = BRW_CONDITIONAL_Z;
1721 break;
1722
1723 case ir_binop_logic_xor:
1724 case ir_binop_logic_or:
1725 case ir_binop_logic_and:
1726 goto out;
1727
1728 case ir_unop_f2b:
1729 if (brw->gen >= 6) {
1730 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1731 } else {
1732 inst = emit(MOV(reg_null_f, op[0]));
1733 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1734 }
1735 break;
1736
1737 case ir_unop_i2b:
1738 if (brw->gen >= 6) {
1739 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1740 } else {
1741 inst = emit(MOV(reg_null_d, op[0]));
1742 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1743 }
1744 break;
1745
1746 case ir_binop_greater:
1747 case ir_binop_gequal:
1748 case ir_binop_less:
1749 case ir_binop_lequal:
1750 case ir_binop_equal:
1751 case ir_binop_all_equal:
1752 case ir_binop_nequal:
1753 case ir_binop_any_nequal:
1754 resolve_bool_comparison(expr->operands[0], &op[0]);
1755 resolve_bool_comparison(expr->operands[1], &op[1]);
1756
1757 emit(CMP(reg_null_d, op[0], op[1],
1758 brw_conditional_for_comparison(expr->operation)));
1759 break;
1760
1761 default:
1762 assert(!"not reached");
1763 fail("bad cond code\n");
1764 break;
1765 }
1766 return;
1767 }
1768
1769 out:
1770 ir->accept(this);
1771
1772 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1773 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1774 }
1775
1776 /**
1777 * Emit a gen6 IF statement with the comparison folded into the IF
1778 * instruction.
1779 */
1780 void
1781 fs_visitor::emit_if_gen6(ir_if *ir)
1782 {
1783 ir_expression *expr = ir->condition->as_expression();
1784
1785 if (expr) {
1786 fs_reg op[2];
1787 fs_inst *inst;
1788 fs_reg temp;
1789
1790 assert(expr->get_num_operands() <= 2);
1791 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1792 assert(expr->operands[i]->type->is_scalar());
1793
1794 expr->operands[i]->accept(this);
1795 op[i] = this->result;
1796 }
1797
1798 switch (expr->operation) {
1799 case ir_unop_logic_not:
1800 case ir_binop_logic_xor:
1801 case ir_binop_logic_or:
1802 case ir_binop_logic_and:
1803 /* For operations on bool arguments, only the low bit of the bool is
1804 * valid, and the others are undefined. Fall back to the condition
1805 * code path.
1806 */
1807 break;
1808
1809 case ir_unop_f2b:
1810 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1811 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1812 return;
1813
1814 case ir_unop_i2b:
1815 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1816 return;
1817
1818 case ir_binop_greater:
1819 case ir_binop_gequal:
1820 case ir_binop_less:
1821 case ir_binop_lequal:
1822 case ir_binop_equal:
1823 case ir_binop_all_equal:
1824 case ir_binop_nequal:
1825 case ir_binop_any_nequal:
1826 resolve_bool_comparison(expr->operands[0], &op[0]);
1827 resolve_bool_comparison(expr->operands[1], &op[1]);
1828
1829 emit(IF(op[0], op[1],
1830 brw_conditional_for_comparison(expr->operation)));
1831 return;
1832 default:
1833 assert(!"not reached");
1834 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1835 fail("bad condition\n");
1836 return;
1837 }
1838 }
1839
1840 emit_bool_to_cond_code(ir->condition);
1841 fs_inst *inst = emit(BRW_OPCODE_IF);
1842 inst->predicate = BRW_PREDICATE_NORMAL;
1843 }
1844
1845 /**
1846 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1847 *
1848 * Many GLSL shaders contain the following pattern:
1849 *
1850 * x = condition ? foo : bar
1851 *
1852 * The compiler emits an ir_if tree for this, since each subexpression might be
1853 * a complex tree that could have side-effects or short-circuit logic.
1854 *
1855 * However, the common case is to simply select one of two constants or
1856 * variable values---which is exactly what SEL is for. In this case, the
1857 * assembly looks like:
1858 *
1859 * (+f0) IF
1860 * MOV dst src0
1861 * ELSE
1862 * MOV dst src1
1863 * ENDIF
1864 *
1865 * which can be easily translated into:
1866 *
1867 * (+f0) SEL dst src0 src1
1868 *
1869 * If src0 is an immediate value, we promote it to a temporary GRF.
1870 */
1871 void
1872 fs_visitor::try_replace_with_sel()
1873 {
1874 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1875 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1876
1877 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1878 int opcodes[] = {
1879 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1880 };
1881
1882 fs_inst *match = (fs_inst *) endif_inst->prev;
1883 for (int i = 0; i < 4; i++) {
1884 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1885 return;
1886 match = (fs_inst *) match->prev;
1887 }
1888
1889 /* The opcodes match; it looks like the right sequence of instructions. */
1890 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1891 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1892 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1893
1894 /* Check that the MOVs are the right form. */
1895 if (then_mov->dst.equals(else_mov->dst) &&
1896 !then_mov->is_partial_write() &&
1897 !else_mov->is_partial_write()) {
1898
1899 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1900 while (!if_inst->next->is_tail_sentinel())
1901 if_inst->next->remove();
1902 if_inst->remove();
1903
1904 /* Only the last source register can be a constant, so if the MOV in
1905 * the "then" clause uses a constant, we need to put it in a temporary.
1906 */
1907 fs_reg src0(then_mov->src[0]);
1908 if (src0.file == IMM) {
1909 src0 = fs_reg(this, glsl_type::float_type);
1910 src0.type = then_mov->src[0].type;
1911 emit(MOV(src0, then_mov->src[0]));
1912 }
1913
1914 fs_inst *sel;
1915 if (if_inst->conditional_mod) {
1916 /* Sandybridge-specific IF with embedded comparison */
1917 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
1918 if_inst->conditional_mod));
1919 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1920 sel->predicate = BRW_PREDICATE_NORMAL;
1921 } else {
1922 /* Separate CMP and IF instructions */
1923 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1924 sel->predicate = if_inst->predicate;
1925 sel->predicate_inverse = if_inst->predicate_inverse;
1926 }
1927 }
1928 }
1929
1930 void
1931 fs_visitor::visit(ir_if *ir)
1932 {
1933 if (brw->gen < 6 && dispatch_width == 16) {
1934 fail("Can't support (non-uniform) control flow on 16-wide\n");
1935 }
1936
1937 /* Don't point the annotation at the if statement, because then it plus
1938 * the then and else blocks get printed.
1939 */
1940 this->base_ir = ir->condition;
1941
1942 if (brw->gen == 6) {
1943 emit_if_gen6(ir);
1944 } else {
1945 emit_bool_to_cond_code(ir->condition);
1946
1947 emit(IF(BRW_PREDICATE_NORMAL));
1948 }
1949
1950 foreach_list(node, &ir->then_instructions) {
1951 ir_instruction *ir = (ir_instruction *)node;
1952 this->base_ir = ir;
1953
1954 ir->accept(this);
1955 }
1956
1957 if (!ir->else_instructions.is_empty()) {
1958 emit(BRW_OPCODE_ELSE);
1959
1960 foreach_list(node, &ir->else_instructions) {
1961 ir_instruction *ir = (ir_instruction *)node;
1962 this->base_ir = ir;
1963
1964 ir->accept(this);
1965 }
1966 }
1967
1968 emit(BRW_OPCODE_ENDIF);
1969
1970 try_replace_with_sel();
1971 }
1972
1973 void
1974 fs_visitor::visit(ir_loop *ir)
1975 {
1976 fs_reg counter = reg_undef;
1977
1978 if (brw->gen < 6 && dispatch_width == 16) {
1979 fail("Can't support (non-uniform) control flow on 16-wide\n");
1980 }
1981
1982 if (ir->counter) {
1983 this->base_ir = ir->counter;
1984 ir->counter->accept(this);
1985 counter = *(variable_storage(ir->counter));
1986
1987 if (ir->from) {
1988 this->base_ir = ir->from;
1989 ir->from->accept(this);
1990
1991 emit(MOV(counter, this->result));
1992 }
1993 }
1994
1995 this->base_ir = NULL;
1996 emit(BRW_OPCODE_DO);
1997
1998 if (ir->to) {
1999 this->base_ir = ir->to;
2000 ir->to->accept(this);
2001
2002 emit(CMP(reg_null_d, counter, this->result,
2003 brw_conditional_for_comparison(ir->cmp)));
2004
2005 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2006 inst->predicate = BRW_PREDICATE_NORMAL;
2007 }
2008
2009 foreach_list(node, &ir->body_instructions) {
2010 ir_instruction *ir = (ir_instruction *)node;
2011
2012 this->base_ir = ir;
2013 ir->accept(this);
2014 }
2015
2016 if (ir->increment) {
2017 this->base_ir = ir->increment;
2018 ir->increment->accept(this);
2019 emit(ADD(counter, counter, this->result));
2020 }
2021
2022 this->base_ir = NULL;
2023 emit(BRW_OPCODE_WHILE);
2024 }
2025
2026 void
2027 fs_visitor::visit(ir_loop_jump *ir)
2028 {
2029 switch (ir->mode) {
2030 case ir_loop_jump::jump_break:
2031 emit(BRW_OPCODE_BREAK);
2032 break;
2033 case ir_loop_jump::jump_continue:
2034 emit(BRW_OPCODE_CONTINUE);
2035 break;
2036 }
2037 }
2038
2039 void
2040 fs_visitor::visit(ir_call *ir)
2041 {
2042 assert(!"FINISHME");
2043 }
2044
2045 void
2046 fs_visitor::visit(ir_return *ir)
2047 {
2048 assert(!"FINISHME");
2049 }
2050
2051 void
2052 fs_visitor::visit(ir_function *ir)
2053 {
2054 /* Ignore function bodies other than main() -- we shouldn't see calls to
2055 * them since they should all be inlined before we get to ir_to_mesa.
2056 */
2057 if (strcmp(ir->name, "main") == 0) {
2058 const ir_function_signature *sig;
2059 exec_list empty;
2060
2061 sig = ir->matching_signature(&empty);
2062
2063 assert(sig);
2064
2065 foreach_list(node, &sig->body) {
2066 ir_instruction *ir = (ir_instruction *)node;
2067 this->base_ir = ir;
2068
2069 ir->accept(this);
2070 }
2071 }
2072 }
2073
2074 void
2075 fs_visitor::visit(ir_function_signature *ir)
2076 {
2077 assert(!"not reached");
2078 (void)ir;
2079 }
2080
2081 void
2082 fs_visitor::visit(ir_emit_vertex *)
2083 {
2084 assert(!"not reached");
2085 }
2086
2087 void
2088 fs_visitor::visit(ir_end_primitive *)
2089 {
2090 assert(!"not reached");
2091 }
2092
2093 fs_inst *
2094 fs_visitor::emit(fs_inst inst)
2095 {
2096 fs_inst *list_inst = new(mem_ctx) fs_inst;
2097 *list_inst = inst;
2098 emit(list_inst);
2099 return list_inst;
2100 }
2101
2102 fs_inst *
2103 fs_visitor::emit(fs_inst *inst)
2104 {
2105 if (force_uncompressed_stack > 0)
2106 inst->force_uncompressed = true;
2107 else if (force_sechalf_stack > 0)
2108 inst->force_sechalf = true;
2109
2110 inst->annotation = this->current_annotation;
2111 inst->ir = this->base_ir;
2112
2113 this->instructions.push_tail(inst);
2114
2115 return inst;
2116 }
2117
2118 void
2119 fs_visitor::emit(exec_list list)
2120 {
2121 foreach_list_safe(node, &list) {
2122 fs_inst *inst = (fs_inst *)node;
2123 inst->remove();
2124 emit(inst);
2125 }
2126 }
2127
2128 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2129 void
2130 fs_visitor::emit_dummy_fs()
2131 {
2132 int reg_width = dispatch_width / 8;
2133
2134 /* Everyone's favorite color. */
2135 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2136 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2137 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2138 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2139
2140 fs_inst *write;
2141 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2142 write->base_mrf = 2;
2143 write->mlen = 4 * reg_width;
2144 write->eot = true;
2145 }
2146
2147 /* The register location here is relative to the start of the URB
2148 * data. It will get adjusted to be a real location before
2149 * generate_code() time.
2150 */
2151 struct brw_reg
2152 fs_visitor::interp_reg(int location, int channel)
2153 {
2154 int regnr = urb_setup[location] * 2 + channel / 2;
2155 int stride = (channel & 1) * 4;
2156
2157 assert(urb_setup[location] != -1);
2158
2159 return brw_vec1_grf(regnr, stride);
2160 }
2161
2162 /** Emits the interpolation for the varying inputs. */
2163 void
2164 fs_visitor::emit_interpolation_setup_gen4()
2165 {
2166 this->current_annotation = "compute pixel centers";
2167 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2168 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2169 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2170 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2171
2172 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2173 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2174
2175 this->current_annotation = "compute pixel deltas from v0";
2176 if (brw->has_pln) {
2177 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2178 fs_reg(this, glsl_type::vec2_type);
2179 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2180 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2181 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2182 } else {
2183 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2184 fs_reg(this, glsl_type::float_type);
2185 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2186 fs_reg(this, glsl_type::float_type);
2187 }
2188 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2189 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2190 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2191 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2192
2193 this->current_annotation = "compute pos.w and 1/pos.w";
2194 /* Compute wpos.w. It's always in our setup, since it's needed to
2195 * interpolate the other attributes.
2196 */
2197 this->wpos_w = fs_reg(this, glsl_type::float_type);
2198 emit(FS_OPCODE_LINTERP, wpos_w,
2199 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2200 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2201 interp_reg(VARYING_SLOT_POS, 3));
2202 /* Compute the pixel 1/W value from wpos.w. */
2203 this->pixel_w = fs_reg(this, glsl_type::float_type);
2204 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2205 this->current_annotation = NULL;
2206 }
2207
2208 /** Emits the interpolation for the varying inputs. */
2209 void
2210 fs_visitor::emit_interpolation_setup_gen6()
2211 {
2212 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2213
2214 /* If the pixel centers end up used, the setup is the same as for gen4. */
2215 this->current_annotation = "compute pixel centers";
2216 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2217 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2218 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2219 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2220 emit(ADD(int_pixel_x,
2221 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2222 fs_reg(brw_imm_v(0x10101010))));
2223 emit(ADD(int_pixel_y,
2224 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2225 fs_reg(brw_imm_v(0x11001100))));
2226
2227 /* As of gen6, we can no longer mix float and int sources. We have
2228 * to turn the integer pixel centers into floats for their actual
2229 * use.
2230 */
2231 this->pixel_x = fs_reg(this, glsl_type::float_type);
2232 this->pixel_y = fs_reg(this, glsl_type::float_type);
2233 emit(MOV(this->pixel_x, int_pixel_x));
2234 emit(MOV(this->pixel_y, int_pixel_y));
2235
2236 this->current_annotation = "compute pos.w";
2237 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2238 this->wpos_w = fs_reg(this, glsl_type::float_type);
2239 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2240
2241 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2242 uint8_t reg = c->barycentric_coord_reg[i];
2243 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2244 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2245 }
2246
2247 this->current_annotation = NULL;
2248 }
2249
2250 void
2251 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2252 {
2253 int reg_width = dispatch_width / 8;
2254 fs_inst *inst;
2255 fs_reg color = outputs[target];
2256 fs_reg mrf;
2257
2258 /* If there's no color data to be written, skip it. */
2259 if (color.file == BAD_FILE)
2260 return;
2261
2262 color.reg_offset += index;
2263
2264 if (dispatch_width == 8 || brw->gen >= 6) {
2265 /* SIMD8 write looks like:
2266 * m + 0: r0
2267 * m + 1: r1
2268 * m + 2: g0
2269 * m + 3: g1
2270 *
2271 * gen6 SIMD16 DP write looks like:
2272 * m + 0: r0
2273 * m + 1: r1
2274 * m + 2: g0
2275 * m + 3: g1
2276 * m + 4: b0
2277 * m + 5: b1
2278 * m + 6: a0
2279 * m + 7: a1
2280 */
2281 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2282 color.type),
2283 color));
2284 inst->saturate = c->key.clamp_fragment_color;
2285 } else {
2286 /* pre-gen6 SIMD16 single source DP write looks like:
2287 * m + 0: r0
2288 * m + 1: g0
2289 * m + 2: b0
2290 * m + 3: a0
2291 * m + 4: r1
2292 * m + 5: g1
2293 * m + 6: b1
2294 * m + 7: a1
2295 */
2296 if (brw->has_compr4) {
2297 /* By setting the high bit of the MRF register number, we
2298 * indicate that we want COMPR4 mode - instead of doing the
2299 * usual destination + 1 for the second half we get
2300 * destination + 4.
2301 */
2302 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2303 color.type),
2304 color));
2305 inst->saturate = c->key.clamp_fragment_color;
2306 } else {
2307 push_force_uncompressed();
2308 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2309 color));
2310 inst->saturate = c->key.clamp_fragment_color;
2311 pop_force_uncompressed();
2312
2313 push_force_sechalf();
2314 color.sechalf = true;
2315 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2316 color));
2317 inst->saturate = c->key.clamp_fragment_color;
2318 pop_force_sechalf();
2319 color.sechalf = false;
2320 }
2321 }
2322 }
2323
2324 void
2325 fs_visitor::emit_fb_writes()
2326 {
2327 this->current_annotation = "FB write header";
2328 bool header_present = true;
2329 /* We can potentially have a message length of up to 15, so we have to set
2330 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2331 */
2332 int base_mrf = 1;
2333 int nr = base_mrf;
2334 int reg_width = dispatch_width / 8;
2335 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2336 bool src0_alpha_to_render_target = false;
2337
2338 if (dispatch_width == 16 && do_dual_src) {
2339 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2340 do_dual_src = false;
2341 }
2342
2343 /* From the Sandy Bridge PRM, volume 4, page 198:
2344 *
2345 * "Dispatched Pixel Enables. One bit per pixel indicating
2346 * which pixels were originally enabled when the thread was
2347 * dispatched. This field is only required for the end-of-
2348 * thread message and on all dual-source messages."
2349 */
2350 if (brw->gen >= 6 &&
2351 !this->fp->UsesKill &&
2352 !do_dual_src &&
2353 c->key.nr_color_regions == 1) {
2354 header_present = false;
2355 }
2356
2357 if (header_present) {
2358 src0_alpha_to_render_target = brw->gen >= 6 &&
2359 !do_dual_src &&
2360 c->key.replicate_alpha;
2361 /* m2, m3 header */
2362 nr += 2;
2363 }
2364
2365 if (c->aa_dest_stencil_reg) {
2366 push_force_uncompressed();
2367 emit(MOV(fs_reg(MRF, nr++),
2368 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2369 pop_force_uncompressed();
2370 }
2371
2372 /* Reserve space for color. It'll be filled in per MRT below. */
2373 int color_mrf = nr;
2374 nr += 4 * reg_width;
2375 if (do_dual_src)
2376 nr += 4;
2377 if (src0_alpha_to_render_target)
2378 nr += reg_width;
2379
2380 if (c->source_depth_to_render_target) {
2381 if (brw->gen == 6 && dispatch_width == 16) {
2382 /* For outputting oDepth on gen6, SIMD8 writes have to be
2383 * used. This would require 8-wide moves of each half to
2384 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2385 * Just bail on doing so for now.
2386 */
2387 fail("Missing support for simd16 depth writes on gen6\n");
2388 }
2389
2390 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2391 /* Hand over gl_FragDepth. */
2392 assert(this->frag_depth.file != BAD_FILE);
2393 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2394 } else {
2395 /* Pass through the payload depth. */
2396 emit(MOV(fs_reg(MRF, nr),
2397 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2398 }
2399 nr += reg_width;
2400 }
2401
2402 if (c->dest_depth_reg) {
2403 emit(MOV(fs_reg(MRF, nr),
2404 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2405 nr += reg_width;
2406 }
2407
2408 if (do_dual_src) {
2409 fs_reg src0 = this->outputs[0];
2410 fs_reg src1 = this->dual_src_output;
2411
2412 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2413 "FB write src0");
2414 for (int i = 0; i < 4; i++) {
2415 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2416 src0.reg_offset++;
2417 inst->saturate = c->key.clamp_fragment_color;
2418 }
2419
2420 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2421 "FB write src1");
2422 for (int i = 0; i < 4; i++) {
2423 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2424 src1));
2425 src1.reg_offset++;
2426 inst->saturate = c->key.clamp_fragment_color;
2427 }
2428
2429 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2430 emit_shader_time_end();
2431
2432 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2433 inst->target = 0;
2434 inst->base_mrf = base_mrf;
2435 inst->mlen = nr - base_mrf;
2436 inst->eot = true;
2437 inst->header_present = header_present;
2438
2439 c->prog_data.dual_src_blend = true;
2440 this->current_annotation = NULL;
2441 return;
2442 }
2443
2444 for (int target = 0; target < c->key.nr_color_regions; target++) {
2445 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2446 "FB write target %d",
2447 target);
2448 /* If src0_alpha_to_render_target is true, include source zero alpha
2449 * data in RenderTargetWrite message for targets > 0.
2450 */
2451 int write_color_mrf = color_mrf;
2452 if (src0_alpha_to_render_target && target != 0) {
2453 fs_inst *inst;
2454 fs_reg color = outputs[0];
2455 color.reg_offset += 3;
2456
2457 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2458 color));
2459 inst->saturate = c->key.clamp_fragment_color;
2460 write_color_mrf = color_mrf + reg_width;
2461 }
2462
2463 for (unsigned i = 0; i < this->output_components[target]; i++)
2464 emit_color_write(target, i, write_color_mrf);
2465
2466 bool eot = false;
2467 if (target == c->key.nr_color_regions - 1) {
2468 eot = true;
2469
2470 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2471 emit_shader_time_end();
2472 }
2473
2474 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2475 inst->target = target;
2476 inst->base_mrf = base_mrf;
2477 if (src0_alpha_to_render_target && target == 0)
2478 inst->mlen = nr - base_mrf - reg_width;
2479 else
2480 inst->mlen = nr - base_mrf;
2481 inst->eot = eot;
2482 inst->header_present = header_present;
2483 }
2484
2485 if (c->key.nr_color_regions == 0) {
2486 /* Even if there's no color buffers enabled, we still need to send
2487 * alpha out the pipeline to our null renderbuffer to support
2488 * alpha-testing, alpha-to-coverage, and so on.
2489 */
2490 emit_color_write(0, 3, color_mrf);
2491
2492 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2493 emit_shader_time_end();
2494
2495 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2496 inst->base_mrf = base_mrf;
2497 inst->mlen = nr - base_mrf;
2498 inst->eot = true;
2499 inst->header_present = header_present;
2500 }
2501
2502 this->current_annotation = NULL;
2503 }
2504
2505 void
2506 fs_visitor::resolve_ud_negate(fs_reg *reg)
2507 {
2508 if (reg->type != BRW_REGISTER_TYPE_UD ||
2509 !reg->negate)
2510 return;
2511
2512 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2513 emit(MOV(temp, *reg));
2514 *reg = temp;
2515 }
2516
2517 void
2518 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2519 {
2520 if (rvalue->type != glsl_type::bool_type)
2521 return;
2522
2523 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2524 emit(AND(temp, *reg, fs_reg(1)));
2525 *reg = temp;
2526 }
2527
2528 fs_visitor::fs_visitor(struct brw_context *brw,
2529 struct brw_wm_compile *c,
2530 struct gl_shader_program *shader_prog,
2531 struct gl_fragment_program *fp,
2532 unsigned dispatch_width)
2533 : dispatch_width(dispatch_width)
2534 {
2535 this->c = c;
2536 this->brw = brw;
2537 this->fp = fp;
2538 this->shader_prog = shader_prog;
2539 this->ctx = &brw->ctx;
2540 this->mem_ctx = ralloc_context(NULL);
2541 if (shader_prog)
2542 shader = (struct brw_shader *)
2543 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2544 else
2545 shader = NULL;
2546 this->failed = false;
2547 this->variable_ht = hash_table_ctor(0,
2548 hash_table_pointer_hash,
2549 hash_table_pointer_compare);
2550
2551 memset(this->outputs, 0, sizeof(this->outputs));
2552 memset(this->output_components, 0, sizeof(this->output_components));
2553 this->first_non_payload_grf = 0;
2554 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2555
2556 this->current_annotation = NULL;
2557 this->base_ir = NULL;
2558
2559 this->virtual_grf_sizes = NULL;
2560 this->virtual_grf_count = 0;
2561 this->virtual_grf_array_size = 0;
2562 this->virtual_grf_start = NULL;
2563 this->virtual_grf_end = NULL;
2564 this->live_intervals_valid = false;
2565
2566 this->params_remap = NULL;
2567 this->nr_params_remap = 0;
2568
2569 this->force_uncompressed_stack = 0;
2570 this->force_sechalf_stack = 0;
2571
2572 memset(&this->param_size, 0, sizeof(this->param_size));
2573 }
2574
2575 fs_visitor::~fs_visitor()
2576 {
2577 ralloc_free(this->mem_ctx);
2578 hash_table_dtor(this->variable_ht);
2579 }