2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_optimization.h"
51 #include "glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (ir
->mode
== ir_var_in
) {
62 if (!strcmp(ir
->name
, "gl_FragCoord")) {
63 reg
= emit_fragcoord_interpolation(ir
);
64 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
65 reg
= emit_frontfacing_interpolation(ir
);
67 reg
= emit_general_interpolation(ir
);
70 hash_table_insert(this->variable_ht
, reg
, ir
);
72 } else if (ir
->mode
== ir_var_out
) {
73 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 if (ir
->location
== FRAG_RESULT_COLOR
) {
76 /* Writing gl_FragColor outputs to all color regions. */
77 for (int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
78 this->outputs
[i
] = *reg
;
80 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
81 this->frag_depth
= ir
;
83 /* gl_FragData or a user-defined FS output */
84 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
85 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
87 /* General color output. */
88 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
89 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
90 this->outputs
[output
] = *reg
;
91 this->outputs
[output
].reg_offset
+= 4 * i
;
94 } else if (ir
->mode
== ir_var_uniform
) {
95 int param_index
= c
->prog_data
.nr_params
;
97 if (c
->dispatch_width
== 16) {
98 if (!variable_storage(ir
)) {
99 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
104 if (!strncmp(ir
->name
, "gl_", 3)) {
105 setup_builtin_uniform_values(ir
);
107 setup_uniform_values(ir
->location
, ir
->type
);
110 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
111 reg
->type
= brw_type_for_base_type(ir
->type
);
115 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
117 hash_table_insert(this->variable_ht
, reg
, ir
);
121 fs_visitor::visit(ir_dereference_variable
*ir
)
123 fs_reg
*reg
= variable_storage(ir
->var
);
128 fs_visitor::visit(ir_dereference_record
*ir
)
130 const glsl_type
*struct_type
= ir
->record
->type
;
132 ir
->record
->accept(this);
134 unsigned int offset
= 0;
135 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
136 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
138 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
140 this->result
.reg_offset
+= offset
;
141 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 fs_visitor::visit(ir_dereference_array
*ir
)
150 ir
->array
->accept(this);
151 index
= ir
->array_index
->as_constant();
153 element_size
= type_size(ir
->type
);
154 this->result
.type
= brw_type_for_base_type(ir
->type
);
157 assert(this->result
.file
== UNIFORM
|| this->result
.file
== GRF
);
158 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
160 assert(!"FINISHME: non-constant array element");
164 /* Instruction selection: Produce a MOV.sat instead of
165 * MIN(MAX(val, 0), 1) when possible.
168 fs_visitor::try_emit_saturate(ir_expression
*ir
)
170 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
175 sat_val
->accept(this);
176 fs_reg src
= this->result
;
178 this->result
= fs_reg(this, ir
->type
);
179 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
180 inst
->saturate
= true;
186 fs_visitor::visit(ir_expression
*ir
)
188 unsigned int operand
;
192 assert(ir
->get_num_operands() <= 2);
194 if (try_emit_saturate(ir
))
197 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
198 ir
->operands
[operand
]->accept(this);
199 if (this->result
.file
== BAD_FILE
) {
201 fail("Failed to get tree for expression operand:\n");
202 ir
->operands
[operand
]->accept(&v
);
204 op
[operand
] = this->result
;
206 /* Matrix expression operands should have been broken down to vector
207 * operations already.
209 assert(!ir
->operands
[operand
]->type
->is_matrix());
210 /* And then those vector operands should have been broken down to scalar.
212 assert(!ir
->operands
[operand
]->type
->is_vector());
215 /* Storage for our result. If our result goes into an assignment, it will
216 * just get copy-propagated out, so no worries.
218 this->result
= fs_reg(this, ir
->type
);
220 switch (ir
->operation
) {
221 case ir_unop_logic_not
:
222 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
223 * ones complement of the whole register, not just bit 0.
225 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
228 op
[0].negate
= !op
[0].negate
;
229 this->result
= op
[0];
233 op
[0].negate
= false;
234 this->result
= op
[0];
237 temp
= fs_reg(this, ir
->type
);
239 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
241 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
242 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
243 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
244 inst
->predicated
= true;
246 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
247 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
248 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
249 inst
->predicated
= true;
253 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
257 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
260 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
264 assert(!"not reached: should be handled by ir_explog_to_explog2");
267 case ir_unop_sin_reduced
:
268 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
271 case ir_unop_cos_reduced
:
272 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
276 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
279 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
283 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
286 assert(!"not reached: should be handled by ir_sub_to_add_neg");
290 if (ir
->type
->is_integer()) {
291 /* For integer multiplication, the MUL uses the low 16 bits
292 * of one of the operands (src0 on gen6, src1 on gen7). The
293 * MACH accumulates in the contribution of the upper 16 bits
296 * FINISHME: Emit just the MUL if we know an operand is small
299 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
301 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
302 emit(BRW_OPCODE_MACH
, reg_null_d
, op
[0], op
[1]);
303 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(acc
));
305 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
309 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
310 assert(ir
->type
->is_integer());
311 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
314 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
315 assert(ir
->type
->is_integer());
316 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
320 case ir_binop_greater
:
321 case ir_binop_lequal
:
322 case ir_binop_gequal
:
324 case ir_binop_all_equal
:
325 case ir_binop_nequal
:
326 case ir_binop_any_nequal
:
328 /* original gen4 does implicit conversion before comparison. */
330 temp
.type
= op
[0].type
;
332 resolve_ud_negate(&op
[0]);
333 resolve_ud_negate(&op
[1]);
335 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
336 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
337 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
340 case ir_binop_logic_xor
:
341 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
344 case ir_binop_logic_or
:
345 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
348 case ir_binop_logic_and
:
349 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
354 assert(!"not reached: should be handled by brw_fs_channel_expressions");
358 assert(!"not reached: should be handled by lower_noise");
361 case ir_quadop_vector
:
362 assert(!"not reached: should be handled by lower_quadop_vector");
366 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
370 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
374 op
[0].type
= BRW_REGISTER_TYPE_UD
;
375 this->result
= op
[0];
378 op
[0].type
= BRW_REGISTER_TYPE_D
;
379 this->result
= op
[0];
386 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
391 /* original gen4 does implicit conversion before comparison. */
393 temp
.type
= op
[0].type
;
395 resolve_ud_negate(&op
[0]);
397 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
398 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
399 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
403 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
406 op
[0].negate
= !op
[0].negate
;
407 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
408 this->result
.negate
= true;
411 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
414 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
416 case ir_unop_round_even
:
417 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
421 resolve_ud_negate(&op
[0]);
422 resolve_ud_negate(&op
[1]);
424 if (intel
->gen
>= 6) {
425 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
426 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
428 /* Unalias the destination */
429 this->result
= fs_reg(this, ir
->type
);
431 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
432 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
434 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
435 inst
->predicated
= true;
439 resolve_ud_negate(&op
[0]);
440 resolve_ud_negate(&op
[1]);
442 if (intel
->gen
>= 6) {
443 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
444 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
446 /* Unalias the destination */
447 this->result
= fs_reg(this, ir
->type
);
449 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
450 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
452 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
453 inst
->predicated
= true;
458 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
461 case ir_unop_bit_not
:
462 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
464 case ir_binop_bit_and
:
465 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
467 case ir_binop_bit_xor
:
468 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
470 case ir_binop_bit_or
:
471 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
474 case ir_binop_lshift
:
475 inst
= emit(BRW_OPCODE_SHL
, this->result
, op
[0], op
[1]);
478 case ir_binop_rshift
:
479 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
480 inst
= emit(BRW_OPCODE_ASR
, this->result
, op
[0], op
[1]);
482 inst
= emit(BRW_OPCODE_SHR
, this->result
, op
[0], op
[1]);
488 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
489 const glsl_type
*type
, bool predicated
)
491 switch (type
->base_type
) {
492 case GLSL_TYPE_FLOAT
:
496 for (unsigned int i
= 0; i
< type
->components(); i
++) {
497 l
.type
= brw_type_for_base_type(type
);
498 r
.type
= brw_type_for_base_type(type
);
500 if (predicated
|| !l
.equals(&r
)) {
501 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
502 inst
->predicated
= predicated
;
509 case GLSL_TYPE_ARRAY
:
510 for (unsigned int i
= 0; i
< type
->length
; i
++) {
511 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
515 case GLSL_TYPE_STRUCT
:
516 for (unsigned int i
= 0; i
< type
->length
; i
++) {
517 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
522 case GLSL_TYPE_SAMPLER
:
526 assert(!"not reached");
531 /* If the RHS processing resulted in an instruction generating a
532 * temporary value, and it would be easy to rewrite the instruction to
533 * generate its result right into the LHS instead, do so. This ends
534 * up reliably removing instructions where it can be tricky to do so
535 * later without real UD chain information.
538 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
541 fs_inst
*pre_rhs_inst
,
542 fs_inst
*last_rhs_inst
)
544 if (pre_rhs_inst
== last_rhs_inst
)
545 return false; /* No instructions generated to work with. */
547 /* Only attempt if we're doing a direct assignment. */
549 !(ir
->lhs
->type
->is_scalar() ||
550 (ir
->lhs
->type
->is_vector() &&
551 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
554 /* Make sure the last instruction generated our source reg. */
555 if (last_rhs_inst
->predicated
||
556 last_rhs_inst
->force_uncompressed
||
557 last_rhs_inst
->force_sechalf
||
558 !src
.equals(&last_rhs_inst
->dst
))
561 /* Success! Rewrite the instruction. */
562 last_rhs_inst
->dst
= dst
;
568 fs_visitor::visit(ir_assignment
*ir
)
573 /* FINISHME: arrays on the lhs */
574 ir
->lhs
->accept(this);
577 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
579 ir
->rhs
->accept(this);
582 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
584 assert(l
.file
!= BAD_FILE
);
585 assert(r
.file
!= BAD_FILE
);
587 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
591 emit_bool_to_cond_code(ir
->condition
);
594 if (ir
->lhs
->type
->is_scalar() ||
595 ir
->lhs
->type
->is_vector()) {
596 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
597 if (ir
->write_mask
& (1 << i
)) {
598 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
600 inst
->predicated
= true;
606 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
611 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
622 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
623 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
624 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
625 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
626 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
627 inst
->saturate
= true;
629 coordinate
.reg_offset
++;
631 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
634 if (ir
->op
== ir_tex
) {
635 /* There's no plain shadow compare message, so we use shadow
636 * compare with a bias of 0.0.
638 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
640 } else if (ir
->op
== ir_txb
) {
641 ir
->lod_info
.bias
->accept(this);
642 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
645 assert(ir
->op
== ir_txl
);
646 ir
->lod_info
.lod
->accept(this);
647 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
651 ir
->shadow_comparitor
->accept(this);
652 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
654 } else if (ir
->op
== ir_tex
) {
655 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
656 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
658 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
659 inst
->saturate
= true;
660 coordinate
.reg_offset
++;
662 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
664 } else if (ir
->op
== ir_txd
) {
665 ir
->lod_info
.grad
.dPdx
->accept(this);
666 fs_reg dPdx
= this->result
;
668 ir
->lod_info
.grad
.dPdy
->accept(this);
669 fs_reg dPdy
= this->result
;
671 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
672 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
673 coordinate
.reg_offset
++;
675 /* the slots for u and v are always present, but r is optional */
676 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
679 * dPdx = dudx, dvdx, drdx
680 * dPdy = dudy, dvdy, drdy
682 * 1-arg: Does not exist.
684 * 2-arg: dudx dvdx dudy dvdy
685 * dPdx.x dPdx.y dPdy.x dPdy.y
688 * 3-arg: dudx dvdx drdx dudy dvdy drdy
689 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
692 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
693 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
696 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
698 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
699 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
702 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
703 } else if (ir
->op
== ir_txs
) {
704 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
706 ir
->lod_info
.lod
->accept(this);
707 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
710 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
711 * instructions. We'll need to do SIMD16 here.
714 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
716 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
717 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
718 base_mrf
+ mlen
+ i
* 2,
721 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
722 inst
->saturate
= true;
723 coordinate
.reg_offset
++;
726 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
727 * be necessary for TXF (ld), but seems wise to do for all messages.
729 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
730 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
733 /* lod/bias appears after u/v/r. */
736 if (ir
->op
== ir_txb
) {
737 ir
->lod_info
.bias
->accept(this);
738 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
741 ir
->lod_info
.lod
->accept(this);
742 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, this->result
.type
),
747 /* The unused upper half. */
752 /* Now, since we're doing simd16, the return is 2 interleaved
753 * vec4s where the odd-indexed ones are junk. We'll need to move
754 * this weirdness around to the expected layout.
757 const glsl_type
*vec_type
=
758 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
759 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
760 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
761 : BRW_REGISTER_TYPE_F
;
764 fs_inst
*inst
= NULL
;
767 inst
= emit(SHADER_OPCODE_TEX
, dst
);
770 inst
= emit(FS_OPCODE_TXB
, dst
);
773 inst
= emit(SHADER_OPCODE_TXL
, dst
);
776 inst
= emit(SHADER_OPCODE_TXD
, dst
);
779 inst
= emit(SHADER_OPCODE_TXS
, dst
);
782 inst
= emit(SHADER_OPCODE_TXF
, dst
);
785 inst
->base_mrf
= base_mrf
;
787 inst
->header_present
= true;
790 for (int i
= 0; i
< 4; i
++) {
791 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
792 orig_dst
.reg_offset
++;
800 /* gen5's sampler has slots for u, v, r, array index, then optional
801 * parameters like shadow comparitor or LOD bias. If optional
802 * parameters aren't present, those base slots are optional and don't
803 * need to be included in the message.
805 * We don't fill in the unnecessary slots regardless, which may look
806 * surprising in the disassembly.
809 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
814 int reg_width
= c
->dispatch_width
/ 8;
815 bool header_present
= false;
816 const int vector_elements
=
817 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
820 /* The offsets set up by the ir_texture visitor are in the
821 * m1 header, so we can't go headerless.
823 header_present
= true;
828 for (int i
= 0; i
< vector_elements
; i
++) {
829 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
830 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
,
833 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
834 inst
->saturate
= true;
835 coordinate
.reg_offset
++;
837 mlen
+= vector_elements
* reg_width
;
839 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
840 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
842 ir
->shadow_comparitor
->accept(this);
843 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
847 fs_inst
*inst
= NULL
;
850 inst
= emit(SHADER_OPCODE_TEX
, dst
);
853 ir
->lod_info
.bias
->accept(this);
854 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
855 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
858 inst
= emit(FS_OPCODE_TXB
, dst
);
862 ir
->lod_info
.lod
->accept(this);
863 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
864 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
867 inst
= emit(SHADER_OPCODE_TXL
, dst
);
870 ir
->lod_info
.grad
.dPdx
->accept(this);
871 fs_reg dPdx
= this->result
;
873 ir
->lod_info
.grad
.dPdy
->accept(this);
874 fs_reg dPdy
= this->result
;
876 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
880 * dPdx = dudx, dvdx, drdx
881 * dPdy = dudy, dvdy, drdy
883 * Load up these values:
884 * - dudx dudy dvdx dvdy drdx drdy
885 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
887 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
888 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
892 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
897 inst
= emit(SHADER_OPCODE_TXD
, dst
);
901 ir
->lod_info
.lod
->accept(this);
902 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
904 inst
= emit(SHADER_OPCODE_TXS
, dst
);
907 mlen
= header_present
+ 4 * reg_width
;
909 ir
->lod_info
.lod
->accept(this);
911 fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
913 inst
= emit(SHADER_OPCODE_TXF
, dst
);
916 inst
->base_mrf
= base_mrf
;
918 inst
->header_present
= header_present
;
921 fail("Message length >11 disallowed by hardware\n");
928 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
933 int reg_width
= c
->dispatch_width
/ 8;
934 bool header_present
= false;
937 /* The offsets set up by the ir_texture visitor are in the
938 * m1 header, so we can't go headerless.
940 header_present
= true;
945 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
946 ir
->shadow_comparitor
->accept(this);
947 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
951 /* Set up the LOD info */
956 ir
->lod_info
.bias
->accept(this);
957 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
961 ir
->lod_info
.lod
->accept(this);
962 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
966 if (c
->dispatch_width
== 16)
967 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
969 ir
->lod_info
.grad
.dPdx
->accept(this);
970 fs_reg dPdx
= this->result
;
972 ir
->lod_info
.grad
.dPdy
->accept(this);
973 fs_reg dPdy
= this->result
;
975 /* Load dPdx and the coordinate together:
976 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
978 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
979 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
981 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
982 inst
->saturate
= true;
983 coordinate
.reg_offset
++;
986 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
990 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
997 ir
->lod_info
.lod
->accept(this);
998 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
1002 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1003 emit(BRW_OPCODE_MOV
,
1004 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
);
1005 coordinate
.reg_offset
++;
1008 ir
->lod_info
.lod
->accept(this);
1009 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), this->result
);
1012 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1013 emit(BRW_OPCODE_MOV
,
1014 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
);
1015 coordinate
.reg_offset
++;
1021 /* Set up the coordinate (except for cases where it was done above) */
1022 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1023 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1024 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1026 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
1027 inst
->saturate
= true;
1028 coordinate
.reg_offset
++;
1033 /* Generate the SEND */
1034 fs_inst
*inst
= NULL
;
1036 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1037 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1038 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1039 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1040 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1041 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1043 inst
->base_mrf
= base_mrf
;
1045 inst
->header_present
= header_present
;
1048 fail("Message length >11 disallowed by hardware\n");
1055 fs_visitor::visit(ir_texture
*ir
)
1057 fs_inst
*inst
= NULL
;
1059 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1060 sampler
= fp
->Base
.SamplerUnits
[sampler
];
1062 /* Our hardware doesn't have a sample_d_c message, so shadow compares
1063 * for textureGrad/TXD need to be emulated with instructions.
1065 bool hw_compare_supported
= ir
->op
!= ir_txd
;
1066 if (ir
->shadow_comparitor
&& !hw_compare_supported
) {
1067 assert(c
->key
.compare_funcs
[sampler
] != GL_NONE
);
1068 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
1069 if (c
->key
.compare_funcs
[sampler
] == GL_ALWAYS
)
1070 return swizzle_result(ir
, fs_reg(1.0f
), sampler
);
1071 else if (c
->key
.compare_funcs
[sampler
] == GL_NEVER
)
1072 return swizzle_result(ir
, fs_reg(0.0f
), sampler
);
1076 ir
->coordinate
->accept(this);
1077 fs_reg coordinate
= this->result
;
1079 if (ir
->offset
!= NULL
) {
1080 ir_constant
*offset
= ir
->offset
->as_constant();
1081 assert(offset
!= NULL
);
1083 signed char offsets
[3];
1084 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
1085 offsets
[i
] = (signed char) offset
->value
.i
[i
];
1087 /* Combine all three offsets into a single unsigned dword:
1089 * bits 11:8 - U Offset (X component)
1090 * bits 7:4 - V Offset (Y component)
1091 * bits 3:0 - R Offset (Z component)
1093 unsigned offset_bits
= 0;
1094 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
1095 const unsigned shift
= 4 * (2 - i
);
1096 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
1099 /* Explicitly set up the message header by copying g0 to msg reg m1. */
1100 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
1101 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)));
1103 /* Then set the offset bits in DWord 2 of the message header. */
1104 emit(BRW_OPCODE_MOV
,
1105 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
1106 BRW_REGISTER_TYPE_UD
)),
1107 fs_reg(brw_imm_uw(offset_bits
)));
1110 /* Should be lowered by do_lower_texture_projection */
1111 assert(!ir
->projector
);
1113 /* The 965 requires the EU to do the normalization of GL rectangle
1114 * texture coordinates. We use the program parameter state
1115 * tracking to get the scaling factor.
1117 if (intel
->gen
< 6 &&
1118 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1119 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1120 int tokens
[STATE_LENGTH
] = {
1122 STATE_TEXRECT_SCALE
,
1128 if (c
->dispatch_width
== 16) {
1129 fail("rectangle scale uniform setup not supported on 16-wide\n");
1130 this->result
= fs_reg(this, ir
->type
);
1134 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1136 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1139 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1140 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1141 GLuint index
= _mesa_add_state_reference(params
,
1142 (gl_state_index
*)tokens
);
1144 this->param_index
[c
->prog_data
.nr_params
] = index
;
1145 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1146 c
->prog_data
.nr_params
++;
1147 this->param_index
[c
->prog_data
.nr_params
] = index
;
1148 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1149 c
->prog_data
.nr_params
++;
1151 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1152 fs_reg src
= coordinate
;
1155 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1158 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1161 /* Writemasking doesn't eliminate channels on SIMD8 texture
1162 * samples, so don't worry about them.
1164 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1166 if (intel
->gen
>= 7) {
1167 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1168 } else if (intel
->gen
>= 5) {
1169 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1171 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1174 /* If there's an offset, we already set up m1. To avoid the implied move,
1175 * use the null register. Otherwise, we want an implied move from g0.
1177 if (ir
->offset
!= NULL
|| !inst
->header_present
)
1178 inst
->src
[0] = reg_undef
;
1180 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1182 inst
->sampler
= sampler
;
1184 if (ir
->shadow_comparitor
) {
1185 if (hw_compare_supported
) {
1186 inst
->shadow_compare
= true;
1188 ir
->shadow_comparitor
->accept(this);
1189 fs_reg ref
= this->result
;
1192 dst
= fs_reg(this, glsl_type::vec4_type
);
1194 /* FINISHME: This needs to be done pre-filtering. */
1196 uint32_t conditional
= 0;
1197 switch (c
->key
.compare_funcs
[sampler
]) {
1198 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1199 case GL_LESS
: conditional
= BRW_CONDITIONAL_L
; break;
1200 case GL_GREATER
: conditional
= BRW_CONDITIONAL_G
; break;
1201 case GL_LEQUAL
: conditional
= BRW_CONDITIONAL_LE
; break;
1202 case GL_GEQUAL
: conditional
= BRW_CONDITIONAL_GE
; break;
1203 case GL_EQUAL
: conditional
= BRW_CONDITIONAL_EQ
; break;
1204 case GL_NOTEQUAL
: conditional
= BRW_CONDITIONAL_NEQ
; break;
1205 default: assert(!"Should not get here: bad shadow compare function");
1208 /* Use conditional moves to load 0 or 1 as the result */
1209 this->current_annotation
= "manual shadow comparison";
1210 for (int i
= 0; i
< 4; i
++) {
1211 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(0.0f
));
1213 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, ref
, value
);
1214 inst
->conditional_mod
= conditional
;
1216 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(1.0f
));
1217 inst
->predicated
= true;
1226 swizzle_result(ir
, dst
, sampler
);
1230 * Swizzle the result of a texture result. This is necessary for
1231 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1234 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1236 this->result
= orig_val
;
1238 if (ir
->op
== ir_txs
)
1241 if (ir
->type
== glsl_type::float_type
) {
1242 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1243 assert(ir
->sampler
->type
->sampler_shadow
);
1244 } else if (c
->key
.tex_swizzles
[sampler
] != SWIZZLE_NOOP
) {
1245 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1247 for (int i
= 0; i
< 4; i
++) {
1248 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1249 fs_reg l
= swizzled_result
;
1252 if (swiz
== SWIZZLE_ZERO
) {
1253 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1254 } else if (swiz
== SWIZZLE_ONE
) {
1255 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1257 fs_reg r
= orig_val
;
1258 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1259 emit(BRW_OPCODE_MOV
, l
, r
);
1262 this->result
= swizzled_result
;
1267 fs_visitor::visit(ir_swizzle
*ir
)
1269 ir
->val
->accept(this);
1270 fs_reg val
= this->result
;
1272 if (ir
->type
->vector_elements
== 1) {
1273 this->result
.reg_offset
+= ir
->mask
.x
;
1277 fs_reg result
= fs_reg(this, ir
->type
);
1278 this->result
= result
;
1280 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1281 fs_reg channel
= val
;
1299 channel
.reg_offset
+= swiz
;
1300 emit(BRW_OPCODE_MOV
, result
, channel
);
1301 result
.reg_offset
++;
1306 fs_visitor::visit(ir_discard
*ir
)
1308 assert(ir
->condition
== NULL
); /* FINISHME */
1310 emit(FS_OPCODE_DISCARD
);
1311 kill_emitted
= true;
1315 fs_visitor::visit(ir_constant
*ir
)
1317 /* Set this->result to reg at the bottom of the function because some code
1318 * paths will cause this visitor to be applied to other fields. This will
1319 * cause the value stored in this->result to be modified.
1321 * Make reg constant so that it doesn't get accidentally modified along the
1322 * way. Yes, I actually had this problem. :(
1324 const fs_reg
reg(this, ir
->type
);
1325 fs_reg dst_reg
= reg
;
1327 if (ir
->type
->is_array()) {
1328 const unsigned size
= type_size(ir
->type
->fields
.array
);
1330 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1331 ir
->array_elements
[i
]->accept(this);
1332 fs_reg src_reg
= this->result
;
1334 dst_reg
.type
= src_reg
.type
;
1335 for (unsigned j
= 0; j
< size
; j
++) {
1336 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1337 src_reg
.reg_offset
++;
1338 dst_reg
.reg_offset
++;
1341 } else if (ir
->type
->is_record()) {
1342 foreach_list(node
, &ir
->components
) {
1343 ir_instruction
*const field
= (ir_instruction
*) node
;
1344 const unsigned size
= type_size(field
->type
);
1346 field
->accept(this);
1347 fs_reg src_reg
= this->result
;
1349 dst_reg
.type
= src_reg
.type
;
1350 for (unsigned j
= 0; j
< size
; j
++) {
1351 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1352 src_reg
.reg_offset
++;
1353 dst_reg
.reg_offset
++;
1357 const unsigned size
= type_size(ir
->type
);
1359 for (unsigned i
= 0; i
< size
; i
++) {
1360 switch (ir
->type
->base_type
) {
1361 case GLSL_TYPE_FLOAT
:
1362 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1364 case GLSL_TYPE_UINT
:
1365 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1368 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1370 case GLSL_TYPE_BOOL
:
1371 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1374 assert(!"Non-float/uint/int/bool constant");
1376 dst_reg
.reg_offset
++;
1384 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1386 ir_expression
*expr
= ir
->as_expression();
1392 assert(expr
->get_num_operands() <= 2);
1393 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1394 assert(expr
->operands
[i
]->type
->is_scalar());
1396 expr
->operands
[i
]->accept(this);
1397 op
[i
] = this->result
;
1399 resolve_ud_negate(&op
[i
]);
1402 switch (expr
->operation
) {
1403 case ir_unop_logic_not
:
1404 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1405 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1408 case ir_binop_logic_xor
:
1409 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1410 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1413 case ir_binop_logic_or
:
1414 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1418 case ir_binop_logic_and
:
1419 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1420 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1424 if (intel
->gen
>= 6) {
1425 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1427 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1429 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1433 if (intel
->gen
>= 6) {
1434 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1436 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1438 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1441 case ir_binop_greater
:
1442 case ir_binop_gequal
:
1444 case ir_binop_lequal
:
1445 case ir_binop_equal
:
1446 case ir_binop_all_equal
:
1447 case ir_binop_nequal
:
1448 case ir_binop_any_nequal
:
1449 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1450 inst
->conditional_mod
=
1451 brw_conditional_for_comparison(expr
->operation
);
1455 assert(!"not reached");
1456 fail("bad cond code\n");
1464 if (intel
->gen
>= 6) {
1465 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1466 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1468 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1469 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1474 * Emit a gen6 IF statement with the comparison folded into the IF
1478 fs_visitor::emit_if_gen6(ir_if
*ir
)
1480 ir_expression
*expr
= ir
->condition
->as_expression();
1487 assert(expr
->get_num_operands() <= 2);
1488 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1489 assert(expr
->operands
[i
]->type
->is_scalar());
1491 expr
->operands
[i
]->accept(this);
1492 op
[i
] = this->result
;
1495 switch (expr
->operation
) {
1496 case ir_unop_logic_not
:
1497 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1498 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1501 case ir_binop_logic_xor
:
1502 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1503 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1506 case ir_binop_logic_or
:
1507 temp
= fs_reg(this, glsl_type::bool_type
);
1508 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1509 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1510 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1513 case ir_binop_logic_and
:
1514 temp
= fs_reg(this, glsl_type::bool_type
);
1515 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1516 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1517 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1521 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1522 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1526 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1527 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1530 case ir_binop_greater
:
1531 case ir_binop_gequal
:
1533 case ir_binop_lequal
:
1534 case ir_binop_equal
:
1535 case ir_binop_all_equal
:
1536 case ir_binop_nequal
:
1537 case ir_binop_any_nequal
:
1538 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1539 inst
->conditional_mod
=
1540 brw_conditional_for_comparison(expr
->operation
);
1543 assert(!"not reached");
1544 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1545 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1546 fail("bad condition\n");
1552 ir
->condition
->accept(this);
1554 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1555 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1559 fs_visitor::visit(ir_if
*ir
)
1563 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1564 fail("Can't support (non-uniform) control flow on 16-wide\n");
1567 /* Don't point the annotation at the if statement, because then it plus
1568 * the then and else blocks get printed.
1570 this->base_ir
= ir
->condition
;
1572 if (intel
->gen
== 6) {
1575 emit_bool_to_cond_code(ir
->condition
);
1577 inst
= emit(BRW_OPCODE_IF
);
1578 inst
->predicated
= true;
1581 foreach_list(node
, &ir
->then_instructions
) {
1582 ir_instruction
*ir
= (ir_instruction
*)node
;
1588 if (!ir
->else_instructions
.is_empty()) {
1589 emit(BRW_OPCODE_ELSE
);
1591 foreach_list(node
, &ir
->else_instructions
) {
1592 ir_instruction
*ir
= (ir_instruction
*)node
;
1599 emit(BRW_OPCODE_ENDIF
);
1603 fs_visitor::visit(ir_loop
*ir
)
1605 fs_reg counter
= reg_undef
;
1607 if (c
->dispatch_width
== 16) {
1608 fail("Can't support (non-uniform) control flow on 16-wide\n");
1612 this->base_ir
= ir
->counter
;
1613 ir
->counter
->accept(this);
1614 counter
= *(variable_storage(ir
->counter
));
1617 this->base_ir
= ir
->from
;
1618 ir
->from
->accept(this);
1620 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1624 emit(BRW_OPCODE_DO
);
1627 this->base_ir
= ir
->to
;
1628 ir
->to
->accept(this);
1630 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1631 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1633 inst
= emit(BRW_OPCODE_BREAK
);
1634 inst
->predicated
= true;
1637 foreach_list(node
, &ir
->body_instructions
) {
1638 ir_instruction
*ir
= (ir_instruction
*)node
;
1644 if (ir
->increment
) {
1645 this->base_ir
= ir
->increment
;
1646 ir
->increment
->accept(this);
1647 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1650 emit(BRW_OPCODE_WHILE
);
1654 fs_visitor::visit(ir_loop_jump
*ir
)
1657 case ir_loop_jump::jump_break
:
1658 emit(BRW_OPCODE_BREAK
);
1660 case ir_loop_jump::jump_continue
:
1661 emit(BRW_OPCODE_CONTINUE
);
1667 fs_visitor::visit(ir_call
*ir
)
1669 assert(!"FINISHME");
1673 fs_visitor::visit(ir_return
*ir
)
1675 assert(!"FINISHME");
1679 fs_visitor::visit(ir_function
*ir
)
1681 /* Ignore function bodies other than main() -- we shouldn't see calls to
1682 * them since they should all be inlined before we get to ir_to_mesa.
1684 if (strcmp(ir
->name
, "main") == 0) {
1685 const ir_function_signature
*sig
;
1688 sig
= ir
->matching_signature(&empty
);
1692 foreach_list(node
, &sig
->body
) {
1693 ir_instruction
*ir
= (ir_instruction
*)node
;
1702 fs_visitor::visit(ir_function_signature
*ir
)
1704 assert(!"not reached");
1709 fs_visitor::emit(fs_inst inst
)
1711 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1714 if (force_uncompressed_stack
> 0)
1715 list_inst
->force_uncompressed
= true;
1716 else if (force_sechalf_stack
> 0)
1717 list_inst
->force_sechalf
= true;
1719 list_inst
->annotation
= this->current_annotation
;
1720 list_inst
->ir
= this->base_ir
;
1722 this->instructions
.push_tail(list_inst
);
1727 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1729 fs_visitor::emit_dummy_fs()
1731 /* Everyone's favorite color. */
1732 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1733 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1734 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1735 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1738 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1739 write
->base_mrf
= 2;
1742 /* The register location here is relative to the start of the URB
1743 * data. It will get adjusted to be a real location before
1744 * generate_code() time.
1747 fs_visitor::interp_reg(int location
, int channel
)
1749 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1750 int stride
= (channel
& 1) * 4;
1752 assert(urb_setup
[location
] != -1);
1754 return brw_vec1_grf(regnr
, stride
);
1757 /** Emits the interpolation for the varying inputs. */
1759 fs_visitor::emit_interpolation_setup_gen4()
1761 this->current_annotation
= "compute pixel centers";
1762 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1763 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1764 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1765 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1767 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1768 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1770 this->current_annotation
= "compute pixel deltas from v0";
1772 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1773 fs_reg(this, glsl_type::vec2_type
);
1774 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1775 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1776 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1778 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1779 fs_reg(this, glsl_type::float_type
);
1780 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1781 fs_reg(this, glsl_type::float_type
);
1783 emit(BRW_OPCODE_ADD
, this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1784 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1785 emit(BRW_OPCODE_ADD
, this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1786 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1788 this->current_annotation
= "compute pos.w and 1/pos.w";
1789 /* Compute wpos.w. It's always in our setup, since it's needed to
1790 * interpolate the other attributes.
1792 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1793 emit(FS_OPCODE_LINTERP
, wpos_w
,
1794 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1795 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1796 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1797 /* Compute the pixel 1/W value from wpos.w. */
1798 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1799 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1800 this->current_annotation
= NULL
;
1803 /** Emits the interpolation for the varying inputs. */
1805 fs_visitor::emit_interpolation_setup_gen6()
1807 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1809 /* If the pixel centers end up used, the setup is the same as for gen4. */
1810 this->current_annotation
= "compute pixel centers";
1811 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1812 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1813 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1814 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1815 emit(BRW_OPCODE_ADD
,
1817 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1818 fs_reg(brw_imm_v(0x10101010)));
1819 emit(BRW_OPCODE_ADD
,
1821 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1822 fs_reg(brw_imm_v(0x11001100)));
1824 /* As of gen6, we can no longer mix float and int sources. We have
1825 * to turn the integer pixel centers into floats for their actual
1828 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1829 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1830 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1831 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1833 this->current_annotation
= "compute pos.w";
1834 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1835 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1836 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1838 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1839 uint8_t reg
= c
->barycentric_coord_reg
[i
];
1840 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
1841 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
1844 this->current_annotation
= NULL
;
1848 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
1850 int reg_width
= c
->dispatch_width
/ 8;
1852 fs_reg color
= outputs
[target
];
1855 /* If there's no color data to be written, skip it. */
1856 if (color
.file
== BAD_FILE
)
1859 color
.reg_offset
+= index
;
1861 if (c
->dispatch_width
== 8 || intel
->gen
>= 6) {
1862 /* SIMD8 write looks like:
1868 * gen6 SIMD16 DP write looks like:
1878 inst
= emit(BRW_OPCODE_MOV
,
1879 fs_reg(MRF
, first_color_mrf
+ index
* reg_width
, color
.type
),
1881 inst
->saturate
= c
->key
.clamp_fragment_color
;
1883 /* pre-gen6 SIMD16 single source DP write looks like:
1893 if (brw
->has_compr4
) {
1894 /* By setting the high bit of the MRF register number, we
1895 * indicate that we want COMPR4 mode - instead of doing the
1896 * usual destination + 1 for the second half we get
1899 inst
= emit(BRW_OPCODE_MOV
,
1900 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
1903 inst
->saturate
= c
->key
.clamp_fragment_color
;
1905 push_force_uncompressed();
1906 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
,
1909 inst
->saturate
= c
->key
.clamp_fragment_color
;
1910 pop_force_uncompressed();
1912 push_force_sechalf();
1913 color
.sechalf
= true;
1914 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4,
1917 inst
->saturate
= c
->key
.clamp_fragment_color
;
1918 pop_force_sechalf();
1919 color
.sechalf
= false;
1925 fs_visitor::emit_fb_writes()
1927 this->current_annotation
= "FB write header";
1928 bool header_present
= true;
1931 int reg_width
= c
->dispatch_width
/ 8;
1933 if (intel
->gen
>= 6 &&
1934 !this->kill_emitted
&&
1935 c
->key
.nr_color_regions
== 1) {
1936 header_present
= false;
1939 if (header_present
) {
1944 if (c
->aa_dest_stencil_reg
) {
1945 push_force_uncompressed();
1946 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1947 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1948 pop_force_uncompressed();
1951 /* Reserve space for color. It'll be filled in per MRT below. */
1953 nr
+= 4 * reg_width
;
1955 if (c
->source_depth_to_render_target
) {
1956 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1957 /* For outputting oDepth on gen6, SIMD8 writes have to be
1958 * used. This would require 8-wide moves of each half to
1959 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1960 * Just bail on doing so for now.
1962 fail("Missing support for simd16 depth writes on gen6\n");
1965 if (c
->computes_depth
) {
1966 /* Hand over gl_FragDepth. */
1967 assert(this->frag_depth
);
1968 fs_reg depth
= *(variable_storage(this->frag_depth
));
1970 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1972 /* Pass through the payload depth. */
1973 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1974 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1979 if (c
->dest_depth_reg
) {
1980 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1981 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1985 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1986 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1987 "FB write target %d",
1989 for (int i
= 0; i
< 4; i
++)
1990 emit_color_write(target
, i
, color_mrf
);
1992 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1993 inst
->target
= target
;
1994 inst
->base_mrf
= base_mrf
;
1995 inst
->mlen
= nr
- base_mrf
;
1996 if (target
== c
->key
.nr_color_regions
- 1)
1998 inst
->header_present
= header_present
;
2001 if (c
->key
.nr_color_regions
== 0) {
2002 if (c
->key
.alpha_test
) {
2003 /* If the alpha test is enabled but there's no color buffer,
2004 * we still need to send alpha out the pipeline to our null
2007 emit_color_write(0, 3, color_mrf
);
2010 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2011 inst
->base_mrf
= base_mrf
;
2012 inst
->mlen
= nr
- base_mrf
;
2014 inst
->header_present
= header_present
;
2017 this->current_annotation
= NULL
;
2021 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2023 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2027 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2028 emit(BRW_OPCODE_MOV
, temp
, *reg
);