2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation(ir
);
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
74 assert(ir
->location
== FRAG_RESULT_DATA0
);
75 assert(ir
->index
== 1);
76 this->dual_src_output
= *reg
;
77 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
80 this->outputs
[i
] = *reg
;
81 this->output_components
[i
] = 4;
83 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
84 this->frag_depth
= *reg
;
85 } else if (ir
->location
== FRAG_RESULT_SAMPLE_MASK
) {
86 this->sample_mask
= *reg
;
88 /* gl_FragData or a user-defined FS output */
89 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
90 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
93 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
94 : ir
->type
->vector_elements
;
96 /* General color output. */
97 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
98 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
99 this->outputs
[output
] = *reg
;
100 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
101 this->output_components
[output
] = vector_elements
;
104 } else if (ir
->mode
== ir_var_uniform
) {
105 int param_index
= c
->prog_data
.nr_params
;
107 /* Thanks to the lower_ubo_reference pass, we will see only
108 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
109 * variables, so no need for them to be in variable_ht.
111 * Atomic counters take no uniform storage, no need to do
114 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
117 if (dispatch_width
== 16) {
118 if (!variable_storage(ir
)) {
119 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
124 param_size
[param_index
] = type_size(ir
->type
);
125 if (!strncmp(ir
->name
, "gl_", 3)) {
126 setup_builtin_uniform_values(ir
);
128 setup_uniform_values(ir
);
131 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
132 reg
->type
= brw_type_for_base_type(ir
->type
);
134 } else if (ir
->mode
== ir_var_system_value
) {
135 if (ir
->location
== SYSTEM_VALUE_SAMPLE_POS
) {
136 reg
= emit_samplepos_setup(ir
);
137 } else if (ir
->location
== SYSTEM_VALUE_SAMPLE_ID
) {
138 reg
= emit_sampleid_setup(ir
);
143 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
145 hash_table_insert(this->variable_ht
, reg
, ir
);
149 fs_visitor::visit(ir_dereference_variable
*ir
)
151 fs_reg
*reg
= variable_storage(ir
->var
);
156 fs_visitor::visit(ir_dereference_record
*ir
)
158 const glsl_type
*struct_type
= ir
->record
->type
;
160 ir
->record
->accept(this);
162 unsigned int offset
= 0;
163 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
164 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
166 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
168 this->result
.reg_offset
+= offset
;
169 this->result
.type
= brw_type_for_base_type(ir
->type
);
173 fs_visitor::visit(ir_dereference_array
*ir
)
175 ir_constant
*constant_index
;
177 int element_size
= type_size(ir
->type
);
179 constant_index
= ir
->array_index
->as_constant();
181 ir
->array
->accept(this);
183 src
.type
= brw_type_for_base_type(ir
->type
);
185 if (constant_index
) {
186 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
187 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
189 /* Variable index array dereference. We attach the variable index
190 * component to the reg as a pointer to a register containing the
191 * offset. Currently only uniform arrays are supported in this patch,
192 * and that reladdr pointer is resolved by
193 * move_uniform_array_access_to_pull_constants(). All other array types
194 * are lowered by lower_variable_index_to_cond_assign().
196 ir
->array_index
->accept(this);
199 index_reg
= fs_reg(this, glsl_type::int_type
);
200 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
203 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
206 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
207 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
213 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
216 !x
.is_valid_3src() ||
217 !y
.is_valid_3src() ||
218 !a
.is_valid_3src()) {
219 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
220 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
221 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
222 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
224 emit(MUL(y_times_a
, y
, a
));
226 a
.negate
= !a
.negate
;
227 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
228 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
230 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
232 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
233 * we need to reorder the operands.
235 emit(LRP(dst
, a
, y
, x
));
240 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
241 fs_reg src0
, fs_reg src1
)
246 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
247 inst
->conditional_mod
= conditionalmod
;
249 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
251 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
252 inst
->predicate
= BRW_PREDICATE_NORMAL
;
256 /* Instruction selection: Produce a MOV.sat instead of
257 * MIN(MAX(val, 0), 1) when possible.
260 fs_visitor::try_emit_saturate(ir_expression
*ir
)
262 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
267 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
269 sat_val
->accept(this);
270 fs_reg src
= this->result
;
272 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
274 /* If the last instruction from our accept() didn't generate our
275 * src, generate a saturated MOV
277 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
278 if (!modify
|| modify
->regs_written
!= 1) {
279 this->result
= fs_reg(this, ir
->type
);
280 fs_inst
*inst
= emit(MOV(this->result
, src
));
281 inst
->saturate
= true;
283 modify
->saturate
= true;
292 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
294 /* 3-src instructions were introduced in gen6. */
298 /* MAD can only handle floating-point data. */
299 if (ir
->type
!= glsl_type::float_type
)
302 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
303 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
305 if (!mul
|| mul
->operation
!= ir_binop_mul
)
308 if (nonmul
->as_constant() ||
309 mul
->operands
[0]->as_constant() ||
310 mul
->operands
[1]->as_constant())
313 nonmul
->accept(this);
314 fs_reg src0
= this->result
;
316 mul
->operands
[0]->accept(this);
317 fs_reg src1
= this->result
;
319 mul
->operands
[1]->accept(this);
320 fs_reg src2
= this->result
;
322 this->result
= fs_reg(this, ir
->type
);
323 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
329 fs_visitor::visit(ir_expression
*ir
)
331 unsigned int operand
;
335 assert(ir
->get_num_operands() <= 3);
337 if (try_emit_saturate(ir
))
339 if (ir
->operation
== ir_binop_add
) {
340 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
344 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
345 ir
->operands
[operand
]->accept(this);
346 if (this->result
.file
== BAD_FILE
) {
347 fail("Failed to get tree for expression operand:\n");
348 ir
->operands
[operand
]->print();
351 assert(this->result
.is_valid_3src());
352 op
[operand
] = this->result
;
354 /* Matrix expression operands should have been broken down to vector
355 * operations already.
357 assert(!ir
->operands
[operand
]->type
->is_matrix());
358 /* And then those vector operands should have been broken down to scalar.
360 assert(!ir
->operands
[operand
]->type
->is_vector());
363 /* Storage for our result. If our result goes into an assignment, it will
364 * just get copy-propagated out, so no worries.
366 this->result
= fs_reg(this, ir
->type
);
368 switch (ir
->operation
) {
369 case ir_unop_logic_not
:
370 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
371 * ones complement of the whole register, not just bit 0.
373 emit(XOR(this->result
, op
[0], fs_reg(1)));
376 op
[0].negate
= !op
[0].negate
;
377 emit(MOV(this->result
, op
[0]));
381 op
[0].negate
= false;
382 emit(MOV(this->result
, op
[0]));
385 if (ir
->type
->is_float()) {
386 /* AND(val, 0x80000000) gives the sign bit.
388 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
391 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
393 op
[0].type
= BRW_REGISTER_TYPE_UD
;
394 this->result
.type
= BRW_REGISTER_TYPE_UD
;
395 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
397 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
398 inst
->predicate
= BRW_PREDICATE_NORMAL
;
400 this->result
.type
= BRW_REGISTER_TYPE_F
;
402 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
403 * -> non-negative val generates 0x00000000.
404 * Predicated OR sets 1 if val is positive.
406 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
408 emit(ASR(this->result
, op
[0], fs_reg(31)));
410 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
411 inst
->predicate
= BRW_PREDICATE_NORMAL
;
415 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
419 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
422 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
426 assert(!"not reached: should be handled by ir_explog_to_explog2");
429 case ir_unop_sin_reduced
:
430 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
433 case ir_unop_cos_reduced
:
434 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
438 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
441 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
445 emit(ADD(this->result
, op
[0], op
[1]));
448 assert(!"not reached: should be handled by ir_sub_to_add_neg");
452 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
453 /* For integer multiplication, the MUL uses the low 16 bits
454 * of one of the operands (src0 on gen6, src1 on gen7). The
455 * MACH accumulates in the contribution of the upper 16 bits
458 * FINISHME: Emit just the MUL if we know an operand is small
461 if (brw
->gen
>= 7 && dispatch_width
== 16)
462 fail("16-wide explicit accumulator operands unsupported\n");
464 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
466 emit(MUL(acc
, op
[0], op
[1]));
467 emit(MACH(reg_null_d
, op
[0], op
[1]));
468 emit(MOV(this->result
, fs_reg(acc
)));
470 emit(MUL(this->result
, op
[0], op
[1]));
473 case ir_binop_imul_high
: {
474 if (brw
->gen
>= 7 && dispatch_width
== 16)
475 fail("16-wide explicit accumulator operands unsupported\n");
477 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
479 emit(MUL(acc
, op
[0], op
[1]));
480 emit(MACH(this->result
, op
[0], op
[1]));
484 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
485 assert(ir
->type
->is_integer());
486 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
488 case ir_binop_carry
: {
489 if (brw
->gen
>= 7 && dispatch_width
== 16)
490 fail("16-wide explicit accumulator operands unsupported\n");
492 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
494 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
495 emit(MOV(this->result
, fs_reg(acc
)));
498 case ir_binop_borrow
: {
499 if (brw
->gen
>= 7 && dispatch_width
== 16)
500 fail("16-wide explicit accumulator operands unsupported\n");
502 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
504 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
505 emit(MOV(this->result
, fs_reg(acc
)));
509 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
510 assert(ir
->type
->is_integer());
511 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
515 case ir_binop_greater
:
516 case ir_binop_lequal
:
517 case ir_binop_gequal
:
519 case ir_binop_all_equal
:
520 case ir_binop_nequal
:
521 case ir_binop_any_nequal
:
522 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
523 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
525 emit(CMP(this->result
, op
[0], op
[1],
526 brw_conditional_for_comparison(ir
->operation
)));
529 case ir_binop_logic_xor
:
530 emit(XOR(this->result
, op
[0], op
[1]));
533 case ir_binop_logic_or
:
534 emit(OR(this->result
, op
[0], op
[1]));
537 case ir_binop_logic_and
:
538 emit(AND(this->result
, op
[0], op
[1]));
543 assert(!"not reached: should be handled by brw_fs_channel_expressions");
547 assert(!"not reached: should be handled by lower_noise");
550 case ir_quadop_vector
:
551 assert(!"not reached: should be handled by lower_quadop_vector");
554 case ir_binop_vector_extract
:
555 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
558 case ir_triop_vector_insert
:
559 assert(!"not reached: should be handled by lower_vector_insert()");
563 assert(!"not reached: should be handled by ldexp_to_arith()");
567 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
571 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
574 case ir_unop_bitcast_i2f
:
575 case ir_unop_bitcast_u2f
:
576 op
[0].type
= BRW_REGISTER_TYPE_F
;
577 this->result
= op
[0];
580 case ir_unop_bitcast_f2u
:
581 op
[0].type
= BRW_REGISTER_TYPE_UD
;
582 this->result
= op
[0];
585 case ir_unop_bitcast_f2i
:
586 op
[0].type
= BRW_REGISTER_TYPE_D
;
587 this->result
= op
[0];
593 emit(MOV(this->result
, op
[0]));
597 emit(AND(this->result
, op
[0], fs_reg(1)));
600 temp
= fs_reg(this, glsl_type::int_type
);
601 emit(AND(temp
, op
[0], fs_reg(1)));
602 emit(MOV(this->result
, temp
));
606 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
609 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
613 emit(RNDZ(this->result
, op
[0]));
616 op
[0].negate
= !op
[0].negate
;
617 emit(RNDD(this->result
, op
[0]));
618 this->result
.negate
= true;
621 emit(RNDD(this->result
, op
[0]));
624 emit(FRC(this->result
, op
[0]));
626 case ir_unop_round_even
:
627 emit(RNDE(this->result
, op
[0]));
632 resolve_ud_negate(&op
[0]);
633 resolve_ud_negate(&op
[1]);
634 emit_minmax(ir
->operation
== ir_binop_min
?
635 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
636 this->result
, op
[0], op
[1]);
638 case ir_unop_pack_snorm_2x16
:
639 case ir_unop_pack_snorm_4x8
:
640 case ir_unop_pack_unorm_2x16
:
641 case ir_unop_pack_unorm_4x8
:
642 case ir_unop_unpack_snorm_2x16
:
643 case ir_unop_unpack_snorm_4x8
:
644 case ir_unop_unpack_unorm_2x16
:
645 case ir_unop_unpack_unorm_4x8
:
646 case ir_unop_unpack_half_2x16
:
647 case ir_unop_pack_half_2x16
:
648 assert(!"not reached: should be handled by lower_packing_builtins");
650 case ir_unop_unpack_half_2x16_split_x
:
651 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
653 case ir_unop_unpack_half_2x16_split_y
:
654 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
657 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
660 case ir_unop_bitfield_reverse
:
661 emit(BFREV(this->result
, op
[0]));
663 case ir_unop_bit_count
:
664 emit(CBIT(this->result
, op
[0]));
666 case ir_unop_find_msb
:
667 temp
= fs_reg(this, glsl_type::uint_type
);
668 emit(FBH(temp
, op
[0]));
670 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
671 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
672 * subtract the result from 31 to convert the MSB count into an LSB count.
675 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
676 emit(MOV(this->result
, temp
));
677 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
680 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
681 inst
->predicate
= BRW_PREDICATE_NORMAL
;
683 case ir_unop_find_lsb
:
684 emit(FBL(this->result
, op
[0]));
686 case ir_triop_bitfield_extract
:
687 /* Note that the instruction's argument order is reversed from GLSL
690 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
693 emit(BFI1(this->result
, op
[0], op
[1]));
696 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
698 case ir_quadop_bitfield_insert
:
699 assert(!"not reached: should be handled by "
700 "lower_instructions::bitfield_insert_to_bfm_bfi");
703 case ir_unop_bit_not
:
704 emit(NOT(this->result
, op
[0]));
706 case ir_binop_bit_and
:
707 emit(AND(this->result
, op
[0], op
[1]));
709 case ir_binop_bit_xor
:
710 emit(XOR(this->result
, op
[0], op
[1]));
712 case ir_binop_bit_or
:
713 emit(OR(this->result
, op
[0], op
[1]));
716 case ir_binop_lshift
:
717 emit(SHL(this->result
, op
[0], op
[1]));
720 case ir_binop_rshift
:
721 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
722 emit(ASR(this->result
, op
[0], op
[1]));
724 emit(SHR(this->result
, op
[0], op
[1]));
726 case ir_binop_pack_half_2x16_split
:
727 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
729 case ir_binop_ubo_load
: {
730 /* This IR node takes a constant uniform block and a constant or
731 * variable byte offset within the block and loads a vector from that.
733 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
734 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
735 fs_reg surf_index
= fs_reg(c
->prog_data
.base
.binding_table
.ubo_start
+
736 uniform_block
->value
.u
[0]);
738 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
739 packed_consts
.type
= result
.type
;
741 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
742 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
743 packed_consts
, surf_index
, const_offset_reg
));
745 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
746 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
747 /* UBO bools are any nonzero value. We consider bools to be
748 * values with the low bit set to 1. Convert them using CMP.
750 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
751 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
753 emit(MOV(result
, packed_consts
));
756 packed_consts
.smear
++;
759 /* The std140 packing rules don't allow vectors to cross 16-byte
760 * boundaries, and a reg is 32 bytes.
762 assert(packed_consts
.smear
< 8);
765 /* Turn the byte offset into a dword offset. */
766 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
767 emit(SHR(base_offset
, op
[1], fs_reg(2)));
769 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
770 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
773 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
774 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
780 result
.reg_offset
= 0;
785 /* Note that the instruction's argument order is reversed from GLSL
788 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
792 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
796 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
797 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
798 inst
->predicate
= BRW_PREDICATE_NORMAL
;
804 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
805 const glsl_type
*type
, bool predicated
)
807 switch (type
->base_type
) {
808 case GLSL_TYPE_FLOAT
:
812 for (unsigned int i
= 0; i
< type
->components(); i
++) {
813 l
.type
= brw_type_for_base_type(type
);
814 r
.type
= brw_type_for_base_type(type
);
816 if (predicated
|| !l
.equals(r
)) {
817 fs_inst
*inst
= emit(MOV(l
, r
));
818 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
825 case GLSL_TYPE_ARRAY
:
826 for (unsigned int i
= 0; i
< type
->length
; i
++) {
827 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
831 case GLSL_TYPE_STRUCT
:
832 for (unsigned int i
= 0; i
< type
->length
; i
++) {
833 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
838 case GLSL_TYPE_SAMPLER
:
839 case GLSL_TYPE_ATOMIC_UINT
:
843 case GLSL_TYPE_ERROR
:
844 case GLSL_TYPE_INTERFACE
:
845 assert(!"not reached");
850 /* If the RHS processing resulted in an instruction generating a
851 * temporary value, and it would be easy to rewrite the instruction to
852 * generate its result right into the LHS instead, do so. This ends
853 * up reliably removing instructions where it can be tricky to do so
854 * later without real UD chain information.
857 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
860 fs_inst
*pre_rhs_inst
,
861 fs_inst
*last_rhs_inst
)
863 /* Only attempt if we're doing a direct assignment. */
865 !(ir
->lhs
->type
->is_scalar() ||
866 (ir
->lhs
->type
->is_vector() &&
867 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
870 /* Make sure the last instruction generated our source reg. */
871 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
877 /* If last_rhs_inst wrote a different number of components than our LHS,
878 * we can't safely rewrite it.
880 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
883 /* Success! Rewrite the instruction. */
890 fs_visitor::visit(ir_assignment
*ir
)
895 /* FINISHME: arrays on the lhs */
896 ir
->lhs
->accept(this);
899 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
901 ir
->rhs
->accept(this);
904 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
906 assert(l
.file
!= BAD_FILE
);
907 assert(r
.file
!= BAD_FILE
);
909 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
913 emit_bool_to_cond_code(ir
->condition
);
916 if (ir
->lhs
->type
->is_scalar() ||
917 ir
->lhs
->type
->is_vector()) {
918 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
919 if (ir
->write_mask
& (1 << i
)) {
920 inst
= emit(MOV(l
, r
));
922 inst
->predicate
= BRW_PREDICATE_NORMAL
;
928 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
933 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
934 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
944 if (ir
->shadow_comparitor
) {
945 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
946 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
947 coordinate
.reg_offset
++;
950 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
951 * the unused slots must be zeroed.
953 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
954 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
958 if (ir
->op
== ir_tex
) {
959 /* There's no plain shadow compare message, so we use shadow
960 * compare with a bias of 0.0.
962 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
964 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
965 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
968 assert(!"Should not get here.");
971 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
973 } else if (ir
->op
== ir_tex
) {
974 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
975 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
976 coordinate
.reg_offset
++;
978 /* zero the others. */
979 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
980 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
982 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
984 } else if (ir
->op
== ir_txd
) {
987 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
988 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
989 coordinate
.reg_offset
++;
991 /* the slots for u and v are always present, but r is optional */
992 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
995 * dPdx = dudx, dvdx, drdx
996 * dPdy = dudy, dvdy, drdy
998 * 1-arg: Does not exist.
1000 * 2-arg: dudx dvdx dudy dvdy
1001 * dPdx.x dPdx.y dPdy.x dPdy.y
1004 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1005 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1006 * m5 m6 m7 m8 m9 m10
1008 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1009 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1012 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1014 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1015 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1018 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1019 } else if (ir
->op
== ir_txs
) {
1020 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1022 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1025 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1026 * instructions. We'll need to do SIMD16 here.
1029 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1031 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1032 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1034 coordinate
.reg_offset
++;
1037 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1038 * be necessary for TXF (ld), but seems wise to do for all messages.
1040 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1041 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1044 /* lod/bias appears after u/v/r. */
1047 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1050 /* The unused upper half. */
1055 /* Now, since we're doing simd16, the return is 2 interleaved
1056 * vec4s where the odd-indexed ones are junk. We'll need to move
1057 * this weirdness around to the expected layout.
1060 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1062 brw_type_for_base_type(ir
->type
) :
1063 BRW_REGISTER_TYPE_F
));
1066 fs_inst
*inst
= NULL
;
1069 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1072 inst
= emit(FS_OPCODE_TXB
, dst
);
1075 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1078 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1081 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1084 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1087 fail("unrecognized texture opcode");
1089 inst
->base_mrf
= base_mrf
;
1091 inst
->header_present
= true;
1092 inst
->regs_written
= simd16
? 8 : 4;
1095 for (int i
= 0; i
< 4; i
++) {
1096 emit(MOV(orig_dst
, dst
));
1097 orig_dst
.reg_offset
++;
1098 dst
.reg_offset
+= 2;
1105 /* gen5's sampler has slots for u, v, r, array index, then optional
1106 * parameters like shadow comparitor or LOD bias. If optional
1107 * parameters aren't present, those base slots are optional and don't
1108 * need to be included in the message.
1110 * We don't fill in the unnecessary slots regardless, which may look
1111 * surprising in the disassembly.
1114 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1115 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1116 fs_reg sample_index
)
1120 int reg_width
= dispatch_width
/ 8;
1121 bool header_present
= false;
1122 const int vector_elements
=
1123 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1126 /* The offsets set up by the ir_texture visitor are in the
1127 * m1 header, so we can't go headerless.
1129 header_present
= true;
1134 for (int i
= 0; i
< vector_elements
; i
++) {
1135 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1137 coordinate
.reg_offset
++;
1139 mlen
+= vector_elements
* reg_width
;
1141 if (ir
->shadow_comparitor
) {
1142 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1144 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1148 fs_inst
*inst
= NULL
;
1151 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1154 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1155 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1158 inst
= emit(FS_OPCODE_TXB
, dst
);
1161 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1162 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1165 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1168 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1172 * dPdx = dudx, dvdx, drdx
1173 * dPdy = dudy, dvdy, drdy
1175 * Load up these values:
1176 * - dudx dudy dvdx dvdy drdx drdy
1177 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1179 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1180 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1184 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1189 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1193 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1195 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1197 case ir_query_levels
:
1198 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1200 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1203 mlen
= header_present
+ 4 * reg_width
;
1204 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1205 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1208 mlen
= header_present
+ 4 * reg_width
;
1211 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1213 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1215 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1218 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1221 inst
= emit(SHADER_OPCODE_TG4
, dst
);
1224 fail("unrecognized texture opcode");
1227 inst
->base_mrf
= base_mrf
;
1229 inst
->header_present
= header_present
;
1230 inst
->regs_written
= 4;
1233 fail("Message length >11 disallowed by hardware\n");
1240 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1241 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1242 fs_reg sample_index
, fs_reg mcs
)
1244 int reg_width
= dispatch_width
/ 8;
1245 bool header_present
= false;
1247 fs_reg payload
= fs_reg(this, glsl_type::float_type
);
1248 fs_reg next
= payload
;
1250 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
)) {
1251 /* For general texture offsets (no txf workaround), we need a header to
1252 * put them in. Note that for 16-wide we're making space for two actual
1253 * hardware registers here, so the emit will have to fix up for this.
1255 * * ir4_tg4 needs to place its channel select in the header,
1256 * for interaction with ARB_texture_swizzle
1258 header_present
= true;
1262 if (ir
->shadow_comparitor
) {
1263 emit(MOV(next
, shadow_c
));
1267 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
1268 bool coordinate_done
= false;
1270 /* Set up the LOD info */
1276 emit(MOV(next
, lod
));
1280 emit(MOV(next
, lod
));
1284 if (dispatch_width
== 16)
1285 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1287 /* Load dPdx and the coordinate together:
1288 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1290 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1291 emit(MOV(next
, coordinate
));
1292 coordinate
.reg_offset
++;
1295 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1296 * only derivatives for (u, v, r).
1298 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1299 emit(MOV(next
, lod
));
1303 emit(MOV(next
, lod2
));
1309 coordinate_done
= true;
1313 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), lod
));
1316 case ir_query_levels
:
1317 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1321 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1322 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
));
1323 coordinate
.reg_offset
++;
1326 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), lod
));
1329 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1330 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
));
1331 coordinate
.reg_offset
++;
1335 coordinate_done
= true;
1338 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), sample_index
));
1341 /* data from the multisample control surface */
1342 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), mcs
));
1345 /* there is no offsetting for this message; just copy in the integer
1346 * texture coordinates
1348 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1349 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
));
1350 coordinate
.reg_offset
++;
1354 coordinate_done
= true;
1357 if (has_nonconstant_offset
) {
1358 if (ir
->shadow_comparitor
&& dispatch_width
== 16)
1359 fail("Gen7 does not support gather4_po_c in SIMD16 mode.");
1361 /* More crazy intermixing */
1362 ir
->offset
->accept(this);
1363 fs_reg offset_value
= this->result
;
1365 for (int i
= 0; i
< 2; i
++) { /* u, v */
1366 emit(MOV(next
, coordinate
));
1367 coordinate
.reg_offset
++;
1371 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1372 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), offset_value
));
1373 offset_value
.reg_offset
++;
1377 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1378 emit(MOV(next
, coordinate
));
1379 coordinate
.reg_offset
++;
1383 coordinate_done
= true;
1388 /* Set up the coordinate (except for cases where it was done above) */
1389 if (ir
->coordinate
&& !coordinate_done
) {
1390 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1391 emit(MOV(next
, coordinate
));
1392 coordinate
.reg_offset
++;
1397 /* Generate the SEND */
1398 fs_inst
*inst
= NULL
;
1400 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
, payload
); break;
1401 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
, payload
); break;
1402 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
, payload
); break;
1403 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
, payload
); break;
1404 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
, payload
); break;
1405 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
, payload
); break;
1406 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1407 case ir_query_levels
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1408 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
, payload
); break;
1410 if (has_nonconstant_offset
)
1411 inst
= emit(SHADER_OPCODE_TG4_OFFSET
, dst
, payload
);
1413 inst
= emit(SHADER_OPCODE_TG4
, dst
, payload
);
1416 inst
->base_mrf
= -1;
1418 inst
->mlen
= next
.reg_offset
* reg_width
- header_present
;
1420 inst
->mlen
= next
.reg_offset
* reg_width
;
1421 inst
->header_present
= header_present
;
1422 inst
->regs_written
= 4;
1424 virtual_grf_sizes
[payload
.reg
] = next
.reg_offset
;
1425 if (inst
->mlen
> 11) {
1426 fail("Message length >11 disallowed by hardware\n");
1433 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1434 bool is_rect
, int sampler
, int texunit
)
1436 fs_inst
*inst
= NULL
;
1437 bool needs_gl_clamp
= true;
1438 fs_reg scale_x
, scale_y
;
1440 /* The 965 requires the EU to do the normalization of GL rectangle
1441 * texture coordinates. We use the program parameter state
1442 * tracking to get the scaling factor.
1446 (brw
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1447 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1448 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1449 int tokens
[STATE_LENGTH
] = {
1451 STATE_TEXRECT_SCALE
,
1457 if (dispatch_width
== 16) {
1458 fail("rectangle scale uniform setup not supported on 16-wide\n");
1462 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1463 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1465 GLuint index
= _mesa_add_state_reference(params
,
1466 (gl_state_index
*)tokens
);
1467 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1468 &prog
->Parameters
->ParameterValues
[index
][0].f
;
1469 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1470 &prog
->Parameters
->ParameterValues
[index
][1].f
;
1473 /* The 965 requires the EU to do the normalization of GL rectangle
1474 * texture coordinates. We use the program parameter state
1475 * tracking to get the scaling factor.
1477 if (brw
->gen
< 6 && is_rect
) {
1478 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1479 fs_reg src
= coordinate
;
1482 emit(MUL(dst
, src
, scale_x
));
1485 emit(MUL(dst
, src
, scale_y
));
1486 } else if (is_rect
) {
1487 /* On gen6+, the sampler handles the rectangle coordinates
1488 * natively, without needing rescaling. But that means we have
1489 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1490 * not [0, 1] like the default case below.
1492 needs_gl_clamp
= false;
1494 for (int i
= 0; i
< 2; i
++) {
1495 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1496 fs_reg chan
= coordinate
;
1497 chan
.reg_offset
+= i
;
1499 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1500 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1502 /* Our parameter comes in as 1.0/width or 1.0/height,
1503 * because that's what people normally want for doing
1504 * texture rectangle handling. We need width or height
1505 * for clamping, but we don't care enough to make a new
1506 * parameter type, so just invert back.
1508 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1509 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1510 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1512 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1513 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1518 if (ir
->coordinate
&& needs_gl_clamp
) {
1519 for (unsigned int i
= 0;
1520 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1521 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1522 fs_reg chan
= coordinate
;
1523 chan
.reg_offset
+= i
;
1525 fs_inst
*inst
= emit(MOV(chan
, chan
));
1526 inst
->saturate
= true;
1533 /* Sample from the MCS surface attached to this multisample texture. */
1535 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
)
1537 int reg_width
= dispatch_width
/ 8;
1538 fs_reg payload
= fs_reg(this, glsl_type::float_type
);
1539 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1540 fs_reg next
= payload
;
1542 /* parameters are: u, v, r, lod; missing parameters are treated as zero */
1543 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1544 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
));
1545 coordinate
.reg_offset
++;
1549 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
);
1550 inst
->base_mrf
= -1;
1551 inst
->mlen
= next
.reg_offset
* reg_width
;
1552 inst
->header_present
= false;
1553 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of response,
1554 * but the sampler always writes 4/8
1556 inst
->sampler
= sampler
;
1562 fs_visitor::visit(ir_texture
*ir
)
1564 fs_inst
*inst
= NULL
;
1567 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1568 /* FINISHME: We're failing to recompile our programs when the sampler is
1569 * updated. This only matters for the texture rectangle scale parameters
1570 * (pre-gen6, or gen6+ with GL_CLAMP).
1572 int texunit
= prog
->SamplerUnits
[sampler
];
1574 if (ir
->op
== ir_tg4
) {
1575 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1576 * emitting anything other than setting up the constant result.
1578 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1579 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1580 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1582 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1585 for (int i
=0; i
<4; i
++) {
1586 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1593 /* Should be lowered by do_lower_texture_projection */
1594 assert(!ir
->projector
);
1596 /* Should be lowered */
1597 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1599 /* Generate code to compute all the subexpression trees. This has to be
1600 * done before loading any values into MRFs for the sampler message since
1601 * generating these values may involve SEND messages that need the MRFs.
1604 if (ir
->coordinate
) {
1605 ir
->coordinate
->accept(this);
1607 coordinate
= rescale_texcoord(ir
, this->result
,
1608 ir
->sampler
->type
->sampler_dimensionality
==
1609 GLSL_SAMPLER_DIM_RECT
,
1613 fs_reg shadow_comparitor
;
1614 if (ir
->shadow_comparitor
) {
1615 ir
->shadow_comparitor
->accept(this);
1616 shadow_comparitor
= this->result
;
1619 fs_reg lod
, lod2
, sample_index
, mcs
;
1624 case ir_query_levels
:
1627 ir
->lod_info
.bias
->accept(this);
1631 ir
->lod_info
.grad
.dPdx
->accept(this);
1634 ir
->lod_info
.grad
.dPdy
->accept(this);
1635 lod2
= this->result
;
1640 ir
->lod_info
.lod
->accept(this);
1644 ir
->lod_info
.sample_index
->accept(this);
1645 sample_index
= this->result
;
1647 if (brw
->gen
>= 7 && c
->key
.tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1648 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
1653 assert(!"Unrecognized texture opcode");
1656 /* Writemasking doesn't eliminate channels on SIMD8 texture
1657 * samples, so don't worry about them.
1659 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1661 if (brw
->gen
>= 7) {
1662 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1663 lod
, lod2
, sample_index
, mcs
);
1664 } else if (brw
->gen
>= 5) {
1665 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1666 lod
, lod2
, sample_index
);
1668 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1672 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1673 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
1675 if (ir
->op
== ir_tg4
)
1676 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1678 inst
->sampler
= sampler
;
1680 if (ir
->shadow_comparitor
)
1681 inst
->shadow_compare
= true;
1683 /* fixup #layers for cube map arrays */
1684 if (ir
->op
== ir_txs
) {
1685 glsl_type
const *type
= ir
->sampler
->type
;
1686 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1687 type
->sampler_array
) {
1689 depth
.reg_offset
= 2;
1690 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1694 swizzle_result(ir
, dst
, sampler
);
1698 * Set up the gather channel based on the swizzle, for gather4.
1701 fs_visitor::gather_channel(ir_texture
*ir
, int sampler
)
1703 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1704 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1706 case SWIZZLE_X
: return 0;
1708 /* gather4 sampler is broken for green channel on RG32F --
1709 * we must ask for blue instead.
1711 if (c
->key
.tex
.gather_channel_quirk_mask
& (1<<sampler
))
1714 case SWIZZLE_Z
: return 2;
1715 case SWIZZLE_W
: return 3;
1717 assert(!"Not reached"); /* zero, one swizzles handled already */
1723 * Swizzle the result of a texture result. This is necessary for
1724 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1727 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1729 if (ir
->op
== ir_query_levels
) {
1730 /* # levels is in .w */
1731 orig_val
.reg_offset
+= 3;
1732 this->result
= orig_val
;
1736 this->result
= orig_val
;
1738 /* txs,lod don't actually sample the texture, so swizzling the result
1741 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
1744 if (ir
->type
== glsl_type::float_type
) {
1745 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1746 assert(ir
->sampler
->type
->sampler_shadow
);
1747 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1748 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1750 for (int i
= 0; i
< 4; i
++) {
1751 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1752 fs_reg l
= swizzled_result
;
1755 if (swiz
== SWIZZLE_ZERO
) {
1756 emit(MOV(l
, fs_reg(0.0f
)));
1757 } else if (swiz
== SWIZZLE_ONE
) {
1758 emit(MOV(l
, fs_reg(1.0f
)));
1760 fs_reg r
= orig_val
;
1761 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1765 this->result
= swizzled_result
;
1770 fs_visitor::visit(ir_swizzle
*ir
)
1772 ir
->val
->accept(this);
1773 fs_reg val
= this->result
;
1775 if (ir
->type
->vector_elements
== 1) {
1776 this->result
.reg_offset
+= ir
->mask
.x
;
1780 fs_reg result
= fs_reg(this, ir
->type
);
1781 this->result
= result
;
1783 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1784 fs_reg channel
= val
;
1802 channel
.reg_offset
+= swiz
;
1803 emit(MOV(result
, channel
));
1804 result
.reg_offset
++;
1809 fs_visitor::visit(ir_discard
*ir
)
1811 assert(ir
->condition
== NULL
); /* FINISHME */
1813 /* We track our discarded pixels in f0.1. By predicating on it, we can
1814 * update just the flag bits that aren't yet discarded. By emitting a
1815 * CMP of g0 != g0, all our currently executing channels will get turned
1818 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1819 BRW_REGISTER_TYPE_UW
));
1820 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1821 BRW_CONDITIONAL_NZ
));
1822 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1823 cmp
->flag_subreg
= 1;
1825 if (brw
->gen
>= 6) {
1826 /* For performance, after a discard, jump to the end of the shader.
1827 * However, many people will do foliage by discarding based on a
1828 * texture's alpha mask, and then continue on to texture with the
1829 * remaining pixels. To avoid trashing the derivatives for those
1830 * texture samples, we'll only jump if all of the pixels in the subspan
1831 * have been discarded.
1833 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1834 discard_jump
->flag_subreg
= 1;
1835 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1836 discard_jump
->predicate_inverse
= true;
1841 fs_visitor::visit(ir_constant
*ir
)
1843 /* Set this->result to reg at the bottom of the function because some code
1844 * paths will cause this visitor to be applied to other fields. This will
1845 * cause the value stored in this->result to be modified.
1847 * Make reg constant so that it doesn't get accidentally modified along the
1848 * way. Yes, I actually had this problem. :(
1850 const fs_reg
reg(this, ir
->type
);
1851 fs_reg dst_reg
= reg
;
1853 if (ir
->type
->is_array()) {
1854 const unsigned size
= type_size(ir
->type
->fields
.array
);
1856 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1857 ir
->array_elements
[i
]->accept(this);
1858 fs_reg src_reg
= this->result
;
1860 dst_reg
.type
= src_reg
.type
;
1861 for (unsigned j
= 0; j
< size
; j
++) {
1862 emit(MOV(dst_reg
, src_reg
));
1863 src_reg
.reg_offset
++;
1864 dst_reg
.reg_offset
++;
1867 } else if (ir
->type
->is_record()) {
1868 foreach_list(node
, &ir
->components
) {
1869 ir_constant
*const field
= (ir_constant
*) node
;
1870 const unsigned size
= type_size(field
->type
);
1872 field
->accept(this);
1873 fs_reg src_reg
= this->result
;
1875 dst_reg
.type
= src_reg
.type
;
1876 for (unsigned j
= 0; j
< size
; j
++) {
1877 emit(MOV(dst_reg
, src_reg
));
1878 src_reg
.reg_offset
++;
1879 dst_reg
.reg_offset
++;
1883 const unsigned size
= type_size(ir
->type
);
1885 for (unsigned i
= 0; i
< size
; i
++) {
1886 switch (ir
->type
->base_type
) {
1887 case GLSL_TYPE_FLOAT
:
1888 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1890 case GLSL_TYPE_UINT
:
1891 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1894 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1896 case GLSL_TYPE_BOOL
:
1897 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1900 assert(!"Non-float/uint/int/bool constant");
1902 dst_reg
.reg_offset
++;
1910 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1912 ir_expression
*expr
= ir
->as_expression();
1915 expr
->operation
!= ir_binop_logic_and
&&
1916 expr
->operation
!= ir_binop_logic_or
&&
1917 expr
->operation
!= ir_binop_logic_xor
) {
1921 assert(expr
->get_num_operands() <= 2);
1922 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1923 assert(expr
->operands
[i
]->type
->is_scalar());
1925 expr
->operands
[i
]->accept(this);
1926 op
[i
] = this->result
;
1928 resolve_ud_negate(&op
[i
]);
1931 switch (expr
->operation
) {
1932 case ir_unop_logic_not
:
1933 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1934 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1938 if (brw
->gen
>= 6) {
1939 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1941 inst
= emit(MOV(reg_null_f
, op
[0]));
1942 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1947 if (brw
->gen
>= 6) {
1948 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1950 inst
= emit(MOV(reg_null_d
, op
[0]));
1951 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1955 case ir_binop_greater
:
1956 case ir_binop_gequal
:
1958 case ir_binop_lequal
:
1959 case ir_binop_equal
:
1960 case ir_binop_all_equal
:
1961 case ir_binop_nequal
:
1962 case ir_binop_any_nequal
:
1963 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1964 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1966 emit(CMP(reg_null_d
, op
[0], op
[1],
1967 brw_conditional_for_comparison(expr
->operation
)));
1971 assert(!"not reached");
1972 fail("bad cond code\n");
1980 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1981 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1985 * Emit a gen6 IF statement with the comparison folded into the IF
1989 fs_visitor::emit_if_gen6(ir_if
*ir
)
1991 ir_expression
*expr
= ir
->condition
->as_expression();
1998 assert(expr
->get_num_operands() <= 2);
1999 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2000 assert(expr
->operands
[i
]->type
->is_scalar());
2002 expr
->operands
[i
]->accept(this);
2003 op
[i
] = this->result
;
2006 switch (expr
->operation
) {
2007 case ir_unop_logic_not
:
2008 case ir_binop_logic_xor
:
2009 case ir_binop_logic_or
:
2010 case ir_binop_logic_and
:
2011 /* For operations on bool arguments, only the low bit of the bool is
2012 * valid, and the others are undefined. Fall back to the condition
2018 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2019 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2023 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2026 case ir_binop_greater
:
2027 case ir_binop_gequal
:
2029 case ir_binop_lequal
:
2030 case ir_binop_equal
:
2031 case ir_binop_all_equal
:
2032 case ir_binop_nequal
:
2033 case ir_binop_any_nequal
:
2034 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2035 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2037 emit(IF(op
[0], op
[1],
2038 brw_conditional_for_comparison(expr
->operation
)));
2041 assert(!"not reached");
2042 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2043 fail("bad condition\n");
2048 emit_bool_to_cond_code(ir
->condition
);
2049 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
2050 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2054 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2056 * Many GLSL shaders contain the following pattern:
2058 * x = condition ? foo : bar
2060 * The compiler emits an ir_if tree for this, since each subexpression might be
2061 * a complex tree that could have side-effects or short-circuit logic.
2063 * However, the common case is to simply select one of two constants or
2064 * variable values---which is exactly what SEL is for. In this case, the
2065 * assembly looks like:
2073 * which can be easily translated into:
2075 * (+f0) SEL dst src0 src1
2077 * If src0 is an immediate value, we promote it to a temporary GRF.
2080 fs_visitor::try_replace_with_sel()
2082 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2083 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2085 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2087 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2090 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2091 for (int i
= 0; i
< 4; i
++) {
2092 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2094 match
= (fs_inst
*) match
->prev
;
2097 /* The opcodes match; it looks like the right sequence of instructions. */
2098 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2099 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2100 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2102 /* Check that the MOVs are the right form. */
2103 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2104 !then_mov
->is_partial_write() &&
2105 !else_mov
->is_partial_write()) {
2107 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2108 while (!if_inst
->next
->is_tail_sentinel())
2109 if_inst
->next
->remove();
2112 /* Only the last source register can be a constant, so if the MOV in
2113 * the "then" clause uses a constant, we need to put it in a temporary.
2115 fs_reg
src0(then_mov
->src
[0]);
2116 if (src0
.file
== IMM
) {
2117 src0
= fs_reg(this, glsl_type::float_type
);
2118 src0
.type
= then_mov
->src
[0].type
;
2119 emit(MOV(src0
, then_mov
->src
[0]));
2123 if (if_inst
->conditional_mod
) {
2124 /* Sandybridge-specific IF with embedded comparison */
2125 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2126 if_inst
->conditional_mod
));
2127 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2128 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2130 /* Separate CMP and IF instructions */
2131 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2132 sel
->predicate
= if_inst
->predicate
;
2133 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2139 fs_visitor::visit(ir_if
*ir
)
2141 if (brw
->gen
< 6 && dispatch_width
== 16) {
2142 fail("Can't support (non-uniform) control flow on 16-wide\n");
2145 /* Don't point the annotation at the if statement, because then it plus
2146 * the then and else blocks get printed.
2148 this->base_ir
= ir
->condition
;
2150 if (brw
->gen
== 6) {
2153 emit_bool_to_cond_code(ir
->condition
);
2155 emit(IF(BRW_PREDICATE_NORMAL
));
2158 foreach_list(node
, &ir
->then_instructions
) {
2159 ir_instruction
*ir
= (ir_instruction
*)node
;
2165 if (!ir
->else_instructions
.is_empty()) {
2166 emit(BRW_OPCODE_ELSE
);
2168 foreach_list(node
, &ir
->else_instructions
) {
2169 ir_instruction
*ir
= (ir_instruction
*)node
;
2176 emit(BRW_OPCODE_ENDIF
);
2178 try_replace_with_sel();
2182 fs_visitor::visit(ir_loop
*ir
)
2184 fs_reg counter
= reg_undef
;
2186 if (brw
->gen
< 6 && dispatch_width
== 16) {
2187 fail("Can't support (non-uniform) control flow on 16-wide\n");
2191 this->base_ir
= ir
->counter
;
2192 ir
->counter
->accept(this);
2193 counter
= *(variable_storage(ir
->counter
));
2196 this->base_ir
= ir
->from
;
2197 ir
->from
->accept(this);
2199 emit(MOV(counter
, this->result
));
2203 this->base_ir
= NULL
;
2204 emit(BRW_OPCODE_DO
);
2207 this->base_ir
= ir
->to
;
2208 ir
->to
->accept(this);
2210 emit(CMP(reg_null_d
, counter
, this->result
,
2211 brw_conditional_for_comparison(ir
->cmp
)));
2213 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
2214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2217 foreach_list(node
, &ir
->body_instructions
) {
2218 ir_instruction
*ir
= (ir_instruction
*)node
;
2224 if (ir
->increment
) {
2225 this->base_ir
= ir
->increment
;
2226 ir
->increment
->accept(this);
2227 emit(ADD(counter
, counter
, this->result
));
2230 this->base_ir
= NULL
;
2231 emit(BRW_OPCODE_WHILE
);
2235 fs_visitor::visit(ir_loop_jump
*ir
)
2238 case ir_loop_jump::jump_break
:
2239 emit(BRW_OPCODE_BREAK
);
2241 case ir_loop_jump::jump_continue
:
2242 emit(BRW_OPCODE_CONTINUE
);
2248 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2250 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2251 ir
->actual_parameters
.get_head());
2252 ir_variable
*location
= deref
->variable_referenced();
2253 unsigned surf_index
= (c
->prog_data
.base
.binding_table
.abo_start
+
2254 location
->atomic
.buffer_index
);
2256 /* Calculate the surface offset */
2257 fs_reg
offset(this, glsl_type::uint_type
);
2258 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2261 deref_array
->array_index
->accept(this);
2263 fs_reg
tmp(this, glsl_type::uint_type
);
2264 emit(MUL(tmp
, this->result
, ATOMIC_COUNTER_SIZE
));
2265 emit(ADD(offset
, tmp
, location
->atomic
.offset
));
2267 offset
= location
->atomic
.offset
;
2270 /* Emit the appropriate machine instruction */
2271 const char *callee
= ir
->callee
->function_name();
2272 ir
->return_deref
->accept(this);
2273 fs_reg dst
= this->result
;
2275 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2276 emit_untyped_surface_read(surf_index
, dst
, offset
);
2278 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2279 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2280 fs_reg(), fs_reg());
2282 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2283 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2284 fs_reg(), fs_reg());
2289 fs_visitor::visit(ir_call
*ir
)
2291 const char *callee
= ir
->callee
->function_name();
2293 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2294 !strcmp("__intrinsic_atomic_increment", callee
) ||
2295 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2296 visit_atomic_counter_intrinsic(ir
);
2298 assert(!"Unsupported intrinsic.");
2303 fs_visitor::visit(ir_return
*ir
)
2305 assert(!"FINISHME");
2309 fs_visitor::visit(ir_function
*ir
)
2311 /* Ignore function bodies other than main() -- we shouldn't see calls to
2312 * them since they should all be inlined before we get to ir_to_mesa.
2314 if (strcmp(ir
->name
, "main") == 0) {
2315 const ir_function_signature
*sig
;
2318 sig
= ir
->matching_signature(NULL
, &empty
);
2322 foreach_list(node
, &sig
->body
) {
2323 ir_instruction
*ir
= (ir_instruction
*)node
;
2332 fs_visitor::visit(ir_function_signature
*ir
)
2334 assert(!"not reached");
2339 fs_visitor::visit(ir_emit_vertex
*)
2341 assert(!"not reached");
2345 fs_visitor::visit(ir_end_primitive
*)
2347 assert(!"not reached");
2351 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2352 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2355 const unsigned operand_len
= dispatch_width
/ 8;
2358 /* Initialize the sample mask in the message header. */
2359 emit(MOV(brw_uvec_mrf(8, mlen
, 0), brw_imm_ud(0)))
2360 ->force_writemask_all
= true;
2363 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2364 ->force_writemask_all
= true;
2366 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2367 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2368 ->force_writemask_all
= true;
2373 /* Set the atomic operation offset. */
2374 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2375 mlen
+= operand_len
;
2377 /* Set the atomic operation arguments. */
2378 if (src0
.file
!= BAD_FILE
) {
2379 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src0
));
2380 mlen
+= operand_len
;
2383 if (src1
.file
!= BAD_FILE
) {
2384 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src1
));
2385 mlen
+= operand_len
;
2388 /* Emit the instruction. */
2389 fs_inst
inst(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, atomic_op
, surf_index
);
2396 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2399 const unsigned operand_len
= dispatch_width
/ 8;
2402 /* Initialize the sample mask in the message header. */
2403 emit(MOV(brw_uvec_mrf(8, mlen
, 0), brw_imm_ud(0)))
2404 ->force_writemask_all
= true;
2407 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2408 ->force_writemask_all
= true;
2410 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2411 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2412 ->force_writemask_all
= true;
2417 /* Set the surface read offset. */
2418 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2419 mlen
+= operand_len
;
2421 /* Emit the instruction. */
2422 fs_inst
inst(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, surf_index
);
2429 fs_visitor::emit(fs_inst inst
)
2431 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
2438 fs_visitor::emit(fs_inst
*inst
)
2440 if (force_uncompressed_stack
> 0)
2441 inst
->force_uncompressed
= true;
2443 inst
->annotation
= this->current_annotation
;
2444 inst
->ir
= this->base_ir
;
2446 this->instructions
.push_tail(inst
);
2452 fs_visitor::emit(exec_list list
)
2454 foreach_list_safe(node
, &list
) {
2455 fs_inst
*inst
= (fs_inst
*)node
;
2461 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2463 fs_visitor::emit_dummy_fs()
2465 int reg_width
= dispatch_width
/ 8;
2467 /* Everyone's favorite color. */
2468 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2469 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2470 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2471 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2474 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2475 write
->base_mrf
= 2;
2476 write
->mlen
= 4 * reg_width
;
2480 /* The register location here is relative to the start of the URB
2481 * data. It will get adjusted to be a real location before
2482 * generate_code() time.
2485 fs_visitor::interp_reg(int location
, int channel
)
2487 int regnr
= c
->prog_data
.urb_setup
[location
] * 2 + channel
/ 2;
2488 int stride
= (channel
& 1) * 4;
2490 assert(c
->prog_data
.urb_setup
[location
] != -1);
2492 return brw_vec1_grf(regnr
, stride
);
2495 /** Emits the interpolation for the varying inputs. */
2497 fs_visitor::emit_interpolation_setup_gen4()
2499 this->current_annotation
= "compute pixel centers";
2500 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2501 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2502 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2503 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2505 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2506 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2508 this->current_annotation
= "compute pixel deltas from v0";
2510 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2511 fs_reg(this, glsl_type::vec2_type
);
2512 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2513 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2514 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2516 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2517 fs_reg(this, glsl_type::float_type
);
2518 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2519 fs_reg(this, glsl_type::float_type
);
2521 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2522 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2523 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2524 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2526 this->current_annotation
= "compute pos.w and 1/pos.w";
2527 /* Compute wpos.w. It's always in our setup, since it's needed to
2528 * interpolate the other attributes.
2530 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2531 emit(FS_OPCODE_LINTERP
, wpos_w
,
2532 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2533 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2534 interp_reg(VARYING_SLOT_POS
, 3));
2535 /* Compute the pixel 1/W value from wpos.w. */
2536 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2537 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2538 this->current_annotation
= NULL
;
2541 /** Emits the interpolation for the varying inputs. */
2543 fs_visitor::emit_interpolation_setup_gen6()
2545 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2547 /* If the pixel centers end up used, the setup is the same as for gen4. */
2548 this->current_annotation
= "compute pixel centers";
2549 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2550 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2551 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2552 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2553 emit(ADD(int_pixel_x
,
2554 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2555 fs_reg(brw_imm_v(0x10101010))));
2556 emit(ADD(int_pixel_y
,
2557 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2558 fs_reg(brw_imm_v(0x11001100))));
2560 /* As of gen6, we can no longer mix float and int sources. We have
2561 * to turn the integer pixel centers into floats for their actual
2564 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2565 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2566 emit(MOV(this->pixel_x
, int_pixel_x
));
2567 emit(MOV(this->pixel_y
, int_pixel_y
));
2569 this->current_annotation
= "compute pos.w";
2570 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2571 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2572 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2574 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2575 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2576 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2577 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2580 this->current_annotation
= NULL
;
2584 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2586 int reg_width
= dispatch_width
/ 8;
2588 fs_reg color
= outputs
[target
];
2591 /* If there's no color data to be written, skip it. */
2592 if (color
.file
== BAD_FILE
)
2595 color
.reg_offset
+= index
;
2597 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2598 /* SIMD8 write looks like:
2604 * gen6 SIMD16 DP write looks like:
2614 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2617 inst
->saturate
= c
->key
.clamp_fragment_color
;
2619 /* pre-gen6 SIMD16 single source DP write looks like:
2629 if (brw
->has_compr4
) {
2630 /* By setting the high bit of the MRF register number, we
2631 * indicate that we want COMPR4 mode - instead of doing the
2632 * usual destination + 1 for the second half we get
2635 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2638 inst
->saturate
= c
->key
.clamp_fragment_color
;
2640 push_force_uncompressed();
2641 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2643 inst
->saturate
= c
->key
.clamp_fragment_color
;
2644 pop_force_uncompressed();
2646 color
.sechalf
= true;
2647 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2649 inst
->force_sechalf
= true;
2650 inst
->saturate
= c
->key
.clamp_fragment_color
;
2651 color
.sechalf
= false;
2657 cond_for_alpha_func(GLenum func
)
2661 return BRW_CONDITIONAL_G
;
2663 return BRW_CONDITIONAL_GE
;
2665 return BRW_CONDITIONAL_L
;
2667 return BRW_CONDITIONAL_LE
;
2669 return BRW_CONDITIONAL_EQ
;
2671 return BRW_CONDITIONAL_NEQ
;
2673 assert(!"Not reached");
2679 * Alpha test support for when we compile it into the shader instead
2680 * of using the normal fixed-function alpha test.
2683 fs_visitor::emit_alpha_test()
2685 this->current_annotation
= "Alpha test";
2688 if (c
->key
.alpha_test_func
== GL_ALWAYS
)
2691 if (c
->key
.alpha_test_func
== GL_NEVER
) {
2693 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2694 BRW_REGISTER_TYPE_UW
));
2695 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2696 BRW_CONDITIONAL_NEQ
));
2699 fs_reg color
= outputs
[0];
2700 color
.reg_offset
+= 3;
2702 /* f0.1 &= func(color, ref) */
2703 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(c
->key
.alpha_test_ref
),
2704 cond_for_alpha_func(c
->key
.alpha_test_func
)));
2706 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2707 cmp
->flag_subreg
= 1;
2711 fs_visitor::emit_fb_writes()
2713 this->current_annotation
= "FB write header";
2714 bool header_present
= true;
2715 /* We can potentially have a message length of up to 15, so we have to set
2716 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2720 int reg_width
= dispatch_width
/ 8;
2721 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2722 bool src0_alpha_to_render_target
= false;
2724 if (dispatch_width
== 16 && do_dual_src
) {
2725 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2726 do_dual_src
= false;
2729 /* From the Sandy Bridge PRM, volume 4, page 198:
2731 * "Dispatched Pixel Enables. One bit per pixel indicating
2732 * which pixels were originally enabled when the thread was
2733 * dispatched. This field is only required for the end-of-
2734 * thread message and on all dual-source messages."
2736 if (brw
->gen
>= 6 &&
2737 !this->fp
->UsesKill
&&
2739 c
->key
.nr_color_regions
== 1) {
2740 header_present
= false;
2743 if (header_present
) {
2744 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
2746 c
->key
.replicate_alpha
;
2751 if (c
->aa_dest_stencil_reg
) {
2752 push_force_uncompressed();
2753 emit(MOV(fs_reg(MRF
, nr
++),
2754 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2755 pop_force_uncompressed();
2758 c
->prog_data
.uses_omask
=
2759 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
2760 if(c
->prog_data
.uses_omask
) {
2761 this->current_annotation
= "FB write oMask";
2762 assert(this->sample_mask
.file
!= BAD_FILE
);
2763 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
2764 emit(FS_OPCODE_SET_OMASK
, fs_reg(MRF
, nr
, BRW_REGISTER_TYPE_UW
), this->sample_mask
);
2768 /* Reserve space for color. It'll be filled in per MRT below. */
2770 nr
+= 4 * reg_width
;
2773 if (src0_alpha_to_render_target
)
2776 if (c
->source_depth_to_render_target
) {
2777 if (brw
->gen
== 6 && dispatch_width
== 16) {
2778 /* For outputting oDepth on gen6, SIMD8 writes have to be
2779 * used. This would require 8-wide moves of each half to
2780 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2781 * Just bail on doing so for now.
2783 fail("Missing support for simd16 depth writes on gen6\n");
2786 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2787 /* Hand over gl_FragDepth. */
2788 assert(this->frag_depth
.file
!= BAD_FILE
);
2789 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2791 /* Pass through the payload depth. */
2792 emit(MOV(fs_reg(MRF
, nr
),
2793 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2798 if (c
->dest_depth_reg
) {
2799 emit(MOV(fs_reg(MRF
, nr
),
2800 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2805 fs_reg src0
= this->outputs
[0];
2806 fs_reg src1
= this->dual_src_output
;
2808 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2810 for (int i
= 0; i
< 4; i
++) {
2811 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2813 inst
->saturate
= c
->key
.clamp_fragment_color
;
2816 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2818 for (int i
= 0; i
< 4; i
++) {
2819 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2822 inst
->saturate
= c
->key
.clamp_fragment_color
;
2825 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2826 emit_shader_time_end();
2828 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2830 inst
->base_mrf
= base_mrf
;
2831 inst
->mlen
= nr
- base_mrf
;
2833 inst
->header_present
= header_present
;
2835 c
->prog_data
.dual_src_blend
= true;
2836 this->current_annotation
= NULL
;
2840 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2841 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2842 "FB write target %d",
2844 /* If src0_alpha_to_render_target is true, include source zero alpha
2845 * data in RenderTargetWrite message for targets > 0.
2847 int write_color_mrf
= color_mrf
;
2848 if (src0_alpha_to_render_target
&& target
!= 0) {
2850 fs_reg color
= outputs
[0];
2851 color
.reg_offset
+= 3;
2853 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2855 inst
->saturate
= c
->key
.clamp_fragment_color
;
2856 write_color_mrf
= color_mrf
+ reg_width
;
2859 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2860 emit_color_write(target
, i
, write_color_mrf
);
2863 if (target
== c
->key
.nr_color_regions
- 1) {
2866 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2867 emit_shader_time_end();
2870 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2871 inst
->target
= target
;
2872 inst
->base_mrf
= base_mrf
;
2873 if (src0_alpha_to_render_target
&& target
== 0)
2874 inst
->mlen
= nr
- base_mrf
- reg_width
;
2876 inst
->mlen
= nr
- base_mrf
;
2878 inst
->header_present
= header_present
;
2881 if (c
->key
.nr_color_regions
== 0) {
2882 /* Even if there's no color buffers enabled, we still need to send
2883 * alpha out the pipeline to our null renderbuffer to support
2884 * alpha-testing, alpha-to-coverage, and so on.
2886 emit_color_write(0, 3, color_mrf
);
2888 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2889 emit_shader_time_end();
2891 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2892 inst
->base_mrf
= base_mrf
;
2893 inst
->mlen
= nr
- base_mrf
;
2895 inst
->header_present
= header_present
;
2898 this->current_annotation
= NULL
;
2902 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2904 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2908 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2909 emit(MOV(temp
, *reg
));
2914 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2916 if (rvalue
->type
!= glsl_type::bool_type
)
2919 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2920 emit(AND(temp
, *reg
, fs_reg(1)));
2924 fs_visitor::fs_visitor(struct brw_context
*brw
,
2925 struct brw_wm_compile
*c
,
2926 struct gl_shader_program
*shader_prog
,
2927 struct gl_fragment_program
*fp
,
2928 unsigned dispatch_width
)
2929 : dispatch_width(dispatch_width
)
2934 this->prog
= &fp
->Base
;
2935 this->shader_prog
= shader_prog
;
2936 this->prog
= &fp
->Base
;
2937 this->stage_prog_data
= &c
->prog_data
.base
;
2938 this->ctx
= &brw
->ctx
;
2939 this->mem_ctx
= ralloc_context(NULL
);
2941 shader
= (struct brw_shader
*)
2942 shader_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2945 this->failed
= false;
2946 this->variable_ht
= hash_table_ctor(0,
2947 hash_table_pointer_hash
,
2948 hash_table_pointer_compare
);
2950 memset(this->outputs
, 0, sizeof(this->outputs
));
2951 memset(this->output_components
, 0, sizeof(this->output_components
));
2952 this->first_non_payload_grf
= 0;
2953 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2955 this->current_annotation
= NULL
;
2956 this->base_ir
= NULL
;
2958 this->virtual_grf_sizes
= NULL
;
2959 this->virtual_grf_count
= 0;
2960 this->virtual_grf_array_size
= 0;
2961 this->virtual_grf_start
= NULL
;
2962 this->virtual_grf_end
= NULL
;
2963 this->live_intervals
= NULL
;
2965 this->params_remap
= NULL
;
2966 this->nr_params_remap
= 0;
2968 this->force_uncompressed_stack
= 0;
2970 this->spilled_any_registers
= false;
2972 memset(&this->param_size
, 0, sizeof(this->param_size
));
2975 fs_visitor::~fs_visitor()
2977 ralloc_free(this->mem_ctx
);
2978 hash_table_dtor(this->variable_ht
);