2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "compiler/glsl_types.h"
36 fs_visitor::emit_vs_system_value(int location
)
38 fs_reg
*reg
= new(this->mem_ctx
)
39 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
41 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
44 case SYSTEM_VALUE_BASE_VERTEX
:
46 vs_prog_data
->uses_basevertex
= true;
48 case SYSTEM_VALUE_BASE_INSTANCE
:
50 vs_prog_data
->uses_baseinstance
= true;
52 case SYSTEM_VALUE_VERTEX_ID
:
53 unreachable("should have been lowered");
54 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
56 vs_prog_data
->uses_vertexid
= true;
58 case SYSTEM_VALUE_INSTANCE_ID
:
60 vs_prog_data
->uses_instanceid
= true;
62 case SYSTEM_VALUE_DRAW_ID
:
63 if (nir
->info
.system_values_read
&
64 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
65 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
66 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
67 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
)))
70 vs_prog_data
->uses_drawid
= true;
73 unreachable("not reached");
79 /* Sample from the MCS surface attached to this multisample texture. */
81 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
82 const fs_reg
&sampler
)
84 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
85 const fs_reg srcs
[] = {
86 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
87 sampler
, fs_reg(), brw_imm_ud(components
), brw_imm_d(0)
89 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
92 /* We only care about one or two regs of response, but the sampler always
95 inst
->regs_written
= 4 * dispatch_width
/ 8;
101 fs_visitor::emit_texture(ir_texture_opcode op
,
102 const glsl_type
*dest_type
,
103 fs_reg coordinate
, int coord_components
,
105 fs_reg lod
, fs_reg lod2
, int grad_components
,
109 int gather_component
,
114 fs_inst
*inst
= NULL
;
116 if (op
== ir_query_levels
) {
117 /* textureQueryLevels() is implemented in terms of TXS so we need to
118 * pass a valid LOD argument.
120 assert(lod
.file
== BAD_FILE
);
121 lod
= brw_imm_ud(0u);
124 if (op
== ir_samples_identical
) {
125 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
127 /* If mcs is an immediate value, it means there is no MCS. In that case
130 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
131 bld
.MOV(dst
, brw_imm_ud(0u));
132 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
133 fs_reg tmp
= vgrf(glsl_type::uint_type
);
134 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
135 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
137 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
144 /* Writemasking doesn't eliminate channels on SIMD8 texture
145 * samples, so don't worry about them.
147 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
148 const fs_reg srcs
[] = {
149 coordinate
, shadow_c
, lod
, lod2
,
150 sample_index
, mcs
, sampler_reg
, offset_value
,
151 brw_imm_d(coord_components
), brw_imm_d(grad_components
)
157 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
160 opcode
= FS_OPCODE_TXB_LOGICAL
;
163 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
166 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
169 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
172 if ((key_tex
->msaa_16
& (1 << sampler
)))
173 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
175 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
178 case ir_query_levels
:
179 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
182 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
185 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
186 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
189 unreachable("Invalid texture opcode.");
192 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
193 inst
->regs_written
= 4 * dispatch_width
/ 8;
195 if (shadow_c
.file
!= BAD_FILE
)
196 inst
->shadow_compare
= true;
198 if (offset_value
.file
== IMM
)
199 inst
->offset
= offset_value
.ud
;
202 if (gather_component
== 1 &&
203 key_tex
->gather_channel_quirk_mask
& (1 << sampler
)) {
204 /* gather4 sampler is broken for green channel on RG32F --
205 * we must ask for blue instead.
207 inst
->offset
|= 2 << 16;
209 inst
->offset
|= gather_component
<< 16;
212 if (devinfo
->gen
== 6)
213 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
216 /* fixup #layers for cube map arrays */
217 if (op
== ir_txs
&& is_cube_array
) {
218 fs_reg depth
= offset(dst
, bld
, 2);
219 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
220 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
222 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
223 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
224 for (int i
= 0; i
< components
; i
++) {
226 fixed_payload
[i
] = fixed_depth
;
228 fixed_payload
[i
] = offset(dst
, bld
, i
);
231 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
234 if (op
== ir_query_levels
) {
235 /* # levels is in .w */
236 dst
= offset(dst
, bld
, 3);
243 * Apply workarounds for Gen6 gather with UINT/SINT
246 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
251 int width
= (wa
& WA_8BIT
) ? 8 : 16;
253 for (int i
= 0; i
< 4; i
++) {
254 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
255 /* Convert from UNORM to UINT */
256 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
260 /* Reinterpret the UINT value as a signed INT value by
261 * shifting the sign bit into place, then shifting back
264 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
265 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
268 dst
= offset(dst
, bld
, 1);
272 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
274 fs_visitor::emit_dummy_fs()
276 int reg_width
= dispatch_width
/ 8;
278 /* Everyone's favorite color. */
279 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
280 for (int i
= 0; i
< 4; i
++) {
281 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
282 brw_imm_f(color
[i
]));
286 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
288 if (devinfo
->gen
>= 6) {
290 write
->mlen
= 4 * reg_width
;
292 write
->header_size
= 2;
294 write
->mlen
= 2 + 4 * reg_width
;
297 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
298 * varying to avoid GPU hangs, so set that.
300 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
301 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
302 memset(wm_prog_data
->urb_setup
, -1,
303 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
305 /* We don't have any uniforms. */
306 stage_prog_data
->nr_params
= 0;
307 stage_prog_data
->nr_pull_params
= 0;
308 stage_prog_data
->curb_read_length
= 0;
309 stage_prog_data
->dispatch_grf_start_reg
= 2;
310 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
311 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
316 /* The register location here is relative to the start of the URB
317 * data. It will get adjusted to be a real location before
318 * generate_code() time.
321 fs_visitor::interp_reg(int location
, int channel
)
323 assert(stage
== MESA_SHADER_FRAGMENT
);
324 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
325 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
326 int stride
= (channel
& 1) * 4;
328 assert(prog_data
->urb_setup
[location
] != -1);
330 return brw_vec1_grf(regnr
, stride
);
333 /** Emits the interpolation for the varying inputs. */
335 fs_visitor::emit_interpolation_setup_gen4()
337 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
339 fs_builder abld
= bld
.annotate("compute pixel centers");
340 this->pixel_x
= vgrf(glsl_type::uint_type
);
341 this->pixel_y
= vgrf(glsl_type::uint_type
);
342 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
343 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
344 abld
.ADD(this->pixel_x
,
345 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
346 fs_reg(brw_imm_v(0x10101010)));
347 abld
.ADD(this->pixel_y
,
348 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
349 fs_reg(brw_imm_v(0x11001100)));
351 abld
= bld
.annotate("compute pixel deltas from v0");
353 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
354 vgrf(glsl_type::vec2_type
);
355 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
356 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
357 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
359 if (devinfo
->has_pln
&& dispatch_width
== 16) {
360 for (unsigned i
= 0; i
< 2; i
++) {
361 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
362 half(this->pixel_x
, i
), xstart
);
363 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
364 half(this->pixel_y
, i
), ystart
);
367 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
368 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
371 abld
= bld
.annotate("compute pos.w and 1/pos.w");
372 /* Compute wpos.w. It's always in our setup, since it's needed to
373 * interpolate the other attributes.
375 this->wpos_w
= vgrf(glsl_type::float_type
);
376 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
377 interp_reg(VARYING_SLOT_POS
, 3));
378 /* Compute the pixel 1/W value from wpos.w. */
379 this->pixel_w
= vgrf(glsl_type::float_type
);
380 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
383 /** Emits the interpolation for the varying inputs. */
385 fs_visitor::emit_interpolation_setup_gen6()
387 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
389 fs_builder abld
= bld
.annotate("compute pixel centers");
390 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
391 /* The "Register Region Restrictions" page says for BDW (and newer,
394 * "When destination spans two registers, the source may be one or
395 * two registers. The destination elements must be evenly split
396 * between the two registers."
398 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
399 * compute our pixel centers.
401 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
402 BRW_REGISTER_TYPE_UW
);
404 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
405 dbld
.ADD(int_pixel_xy
,
406 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
407 fs_reg(brw_imm_v(0x11001010)));
409 this->pixel_x
= vgrf(glsl_type::float_type
);
410 this->pixel_y
= vgrf(glsl_type::float_type
);
411 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
412 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
414 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
416 * "When destination spans two registers, the source MUST span two
419 * Since the GRF source of the ADD will only read a single register, we
420 * must do two separate ADDs in SIMD16.
422 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
423 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
424 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
425 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
426 abld
.ADD(int_pixel_x
,
427 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
428 fs_reg(brw_imm_v(0x10101010)));
429 abld
.ADD(int_pixel_y
,
430 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
431 fs_reg(brw_imm_v(0x11001100)));
433 /* As of gen6, we can no longer mix float and int sources. We have
434 * to turn the integer pixel centers into floats for their actual
437 this->pixel_x
= vgrf(glsl_type::float_type
);
438 this->pixel_y
= vgrf(glsl_type::float_type
);
439 abld
.MOV(this->pixel_x
, int_pixel_x
);
440 abld
.MOV(this->pixel_y
, int_pixel_y
);
443 abld
= bld
.annotate("compute pos.w");
444 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
445 this->wpos_w
= vgrf(glsl_type::float_type
);
446 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
448 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
449 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
450 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
454 static enum brw_conditional_mod
455 cond_for_alpha_func(GLenum func
)
459 return BRW_CONDITIONAL_G
;
461 return BRW_CONDITIONAL_GE
;
463 return BRW_CONDITIONAL_L
;
465 return BRW_CONDITIONAL_LE
;
467 return BRW_CONDITIONAL_EQ
;
469 return BRW_CONDITIONAL_NEQ
;
471 unreachable("Not reached");
476 * Alpha test support for when we compile it into the shader instead
477 * of using the normal fixed-function alpha test.
480 fs_visitor::emit_alpha_test()
482 assert(stage
== MESA_SHADER_FRAGMENT
);
483 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
484 const fs_builder abld
= bld
.annotate("Alpha test");
487 if (key
->alpha_test_func
== GL_ALWAYS
)
490 if (key
->alpha_test_func
== GL_NEVER
) {
492 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
493 BRW_REGISTER_TYPE_UW
));
494 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
495 BRW_CONDITIONAL_NEQ
);
498 fs_reg color
= offset(outputs
[0], bld
, 3);
500 /* f0.1 &= func(color, ref) */
501 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
502 cond_for_alpha_func(key
->alpha_test_func
));
504 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
505 cmp
->flag_subreg
= 1;
509 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
510 fs_reg color0
, fs_reg color1
,
511 fs_reg src0_alpha
, unsigned components
)
513 assert(stage
== MESA_SHADER_FRAGMENT
);
514 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
516 /* Hand over gl_FragDepth or the payload depth. */
517 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
518 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
520 fs_reg src_depth
, src_stencil
;
522 if (source_depth_to_render_target
) {
523 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
524 src_depth
= frag_depth
;
526 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
529 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
530 src_stencil
= frag_stencil
;
532 const fs_reg sources
[] = {
533 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
534 sample_mask
, brw_imm_ud(components
)
536 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
537 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
538 sources
, ARRAY_SIZE(sources
));
540 if (prog_data
->uses_kill
) {
541 write
->predicate
= BRW_PREDICATE_NORMAL
;
542 write
->flag_subreg
= 1;
549 fs_visitor::emit_fb_writes()
551 assert(stage
== MESA_SHADER_FRAGMENT
);
552 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
553 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
555 fs_inst
*inst
= NULL
;
557 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
558 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
559 * would require SIMD8 moves of each half to message regs, e.g. by using
560 * the SIMD lowering pass. Unfortunately this is more difficult than it
561 * sounds because the SIMD8 single-source message lacks channel selects
562 * for the second and third subspans.
564 no16("Missing support for simd16 depth writes on gen6\n");
567 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
568 /* From the 'Render Target Write message' section of the docs:
569 * "Output Stencil is not supported with SIMD16 Render Target Write
572 * FINISHME: split 16 into 2 8s
574 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
578 const fs_builder abld
= bld
.annotate("FB dual-source write");
580 inst
= emit_single_fb_write(abld
, this->outputs
[0],
581 this->dual_src_output
, reg_undef
, 4);
584 prog_data
->dual_src_blend
= true;
586 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
587 /* Skip over outputs that weren't written. */
588 if (this->outputs
[target
].file
== BAD_FILE
)
591 const fs_builder abld
= bld
.annotate(
592 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
595 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
596 src0_alpha
= offset(outputs
[0], bld
, 3);
598 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
600 this->output_components
[target
]);
601 inst
->target
= target
;
606 /* Even if there's no color buffers enabled, we still need to send
607 * alpha out the pipeline to our null renderbuffer to support
608 * alpha-testing, alpha-to-coverage, and so on.
610 /* FINISHME: Factor out this frequently recurring pattern into a
613 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
614 reg_undef
, offset(this->outputs
[0], bld
, 3) };
615 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
616 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
618 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
626 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
628 const struct brw_vs_prog_key
*key
=
629 (const struct brw_vs_prog_key
*) this->key
;
631 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
632 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
633 for (int j
= 0; j
< 4; ++j
) {
634 stage_prog_data
->param
[uniforms
+ j
] =
635 (gl_constant_value
*) &clip_planes
[i
][j
];
642 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
644 * This does nothing if the shader uses gl_ClipDistance or user clipping is
645 * disabled altogether.
647 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
649 struct brw_vue_prog_data
*vue_prog_data
=
650 (struct brw_vue_prog_data
*) prog_data
;
651 const struct brw_vs_prog_key
*key
=
652 (const struct brw_vs_prog_key
*) this->key
;
654 /* Bail unless some sort of legacy clipping is enabled */
655 if (key
->nr_userclip_plane_consts
== 0)
658 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
660 * "If a linked set of shaders forming the vertex stage contains no
661 * static write to gl_ClipVertex or gl_ClipDistance, but the
662 * application has requested clipping against user clip planes through
663 * the API, then the coordinate written to gl_Position is used for
664 * comparison against the user clip planes."
666 * This function is only called if the shader didn't write to
667 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
668 * if the user wrote to it; otherwise we use gl_Position.
671 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
672 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
673 clip_vertex
= VARYING_SLOT_POS
;
675 /* If the clip vertex isn't written, skip this. Typically this means
676 * the GS will set up clipping. */
677 if (outputs
[clip_vertex
].file
== BAD_FILE
)
680 setup_uniform_clipplane_values(clip_planes
);
682 const fs_builder abld
= bld
.annotate("user clip distances");
684 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
685 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
686 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
687 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
689 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
690 fs_reg u
= userplane
[i
];
691 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
692 output
.reg_offset
= i
& 3;
694 abld
.MUL(output
, outputs
[clip_vertex
], u
);
695 for (int j
= 1; j
< 4; j
++) {
696 u
.nr
= userplane
[i
].nr
+ j
;
697 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
703 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
705 int slot
, urb_offset
, length
;
706 int starting_urb_offset
= 0;
707 const struct brw_vue_prog_data
*vue_prog_data
=
708 (const struct brw_vue_prog_data
*) this->prog_data
;
709 const struct brw_vs_prog_key
*vs_key
=
710 (const struct brw_vs_prog_key
*) this->key
;
711 const GLbitfield64 psiz_mask
=
712 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
713 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
718 if (stage
== MESA_SHADER_TESS_EVAL
)
719 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
721 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
723 /* If we don't have any valid slots to write, just do a minimal urb write
724 * send to terminate the shader. This includes 1 slot of undefined data,
725 * because it's invalid to write 0 data:
727 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
728 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
729 * Write Data Payload:
731 * "The write data payload can be between 1 and 8 message phases long."
733 if (vue_map
->slots_valid
== 0) {
734 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
735 bld
.exec_all().MOV(payload
, urb_handle
);
737 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
744 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
746 fs_reg per_slot_offsets
;
748 if (stage
== MESA_SHADER_GEOMETRY
) {
749 const struct brw_gs_prog_data
*gs_prog_data
=
750 (const struct brw_gs_prog_data
*) this->prog_data
;
752 /* We need to increment the Global Offset to skip over the control data
753 * header and the extra "Vertex Count" field (1 HWord) at the beginning
754 * of the VUE. We're counting in OWords, so the units are doubled.
756 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
757 if (gs_prog_data
->static_vertex_count
== -1)
758 starting_urb_offset
+= 2;
760 /* We also need to use per-slot offsets. The per-slot offset is the
761 * Vertex Count. SIMD8 mode processes 8 different primitives at a
762 * time; each may output a different number of vertices.
764 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
767 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
768 const int output_vertex_size_owords
=
769 gs_prog_data
->output_vertex_size_hwords
* 2;
771 if (gs_vertex_count
.file
== IMM
) {
772 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
775 per_slot_offsets
= vgrf(glsl_type::int_type
);
776 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
777 brw_imm_ud(output_vertex_size_owords
));
782 urb_offset
= starting_urb_offset
;
784 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
785 int varying
= vue_map
->slot_to_varying
[slot
];
787 case VARYING_SLOT_PSIZ
: {
788 /* The point size varying slot is the vue header and is always in the
789 * vue map. But often none of the special varyings that live there
790 * are written and in that case we can skip writing to the vue
791 * header, provided the corresponding state properly clamps the
792 * values further down the pipeline. */
793 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
799 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
800 bld
.MOV(zero
, brw_imm_ud(0u));
802 sources
[length
++] = zero
;
803 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
804 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
806 sources
[length
++] = zero
;
808 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
809 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
811 sources
[length
++] = zero
;
813 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
814 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
816 sources
[length
++] = zero
;
819 case BRW_VARYING_SLOT_NDC
:
820 case VARYING_SLOT_EDGE
:
821 unreachable("unexpected scalar vs output");
825 /* gl_Position is always in the vue map, but isn't always written by
826 * the shader. Other varyings (clip distances) get added to the vue
827 * map but don't always get written. In those cases, the
828 * corresponding this->output[] slot will be invalid we and can skip
829 * the urb write for the varying. If we've already queued up a vue
830 * slot for writing we flush a mlen 5 urb write, otherwise we just
831 * advance the urb_offset.
833 if (varying
== BRW_VARYING_SLOT_PAD
||
834 this->outputs
[varying
].file
== BAD_FILE
) {
842 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
843 (varying
== VARYING_SLOT_COL0
||
844 varying
== VARYING_SLOT_COL1
||
845 varying
== VARYING_SLOT_BFC0
||
846 varying
== VARYING_SLOT_BFC1
)) {
847 /* We need to clamp these guys, so do a saturating MOV into a
848 * temp register and use that for the payload.
850 for (int i
= 0; i
< 4; i
++) {
851 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
852 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
853 set_saturate(true, bld
.MOV(reg
, src
));
854 sources
[length
++] = reg
;
857 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
858 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
859 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
860 sources
[length
++] = brw_imm_d(0);
865 const fs_builder abld
= bld
.annotate("URB write");
867 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
868 * the last slot or if we need to flush (see BAD_FILE varying case
869 * above), emit a URB write send now to flush out the data.
871 int last
= slot
== vue_map
->num_slots
- 1;
872 if (length
== 8 || last
)
875 fs_reg
*payload_sources
=
876 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
877 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
878 BRW_REGISTER_TYPE_F
);
879 payload_sources
[0] = urb_handle
;
881 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
882 payload_sources
[1] = per_slot_offsets
;
884 memcpy(&payload_sources
[header_size
], sources
,
885 length
* sizeof sources
[0]);
887 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
890 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
891 inst
->eot
= last
&& stage
!= MESA_SHADER_GEOMETRY
;
892 inst
->mlen
= length
+ header_size
;
893 inst
->offset
= urb_offset
;
894 urb_offset
= starting_urb_offset
+ slot
+ 1;
902 fs_visitor::emit_cs_terminate()
904 assert(devinfo
->gen
>= 7);
906 /* We are getting the thread ID from the compute shader header */
907 assert(stage
== MESA_SHADER_COMPUTE
);
909 /* We can't directly send from g0, since sends with EOT have to use
910 * g112-127. So, copy it to a virtual register, The register allocator will
911 * make sure it uses the appropriate register range.
913 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
914 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
915 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
917 /* Send a message to the thread spawner to terminate the thread. */
918 fs_inst
*inst
= bld
.exec_all()
919 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
924 fs_visitor::emit_barrier()
926 assert(devinfo
->gen
>= 7);
928 /* We are getting the barrier ID from the compute shader header */
929 assert(stage
== MESA_SHADER_COMPUTE
);
931 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
933 const fs_builder pbld
= bld
.exec_all().group(8, 0);
935 /* Clear the message payload */
936 pbld
.MOV(payload
, brw_imm_ud(0u));
938 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
939 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
940 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(0x0f000000u
));
942 /* Emit a gateway "barrier" message using the payload we set up, followed
943 * by a wait instruction.
945 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
948 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
951 struct brw_stage_prog_data
*prog_data
,
952 struct gl_program
*prog
,
953 const nir_shader
*shader
,
954 unsigned dispatch_width
,
955 int shader_time_index
,
956 const struct brw_vue_map
*input_vue_map
)
957 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
958 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
959 input_vue_map(input_vue_map
),
960 dispatch_width(dispatch_width
),
961 shader_time_index(shader_time_index
),
962 bld(fs_builder(this, dispatch_width
).at_end())
967 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
969 struct brw_gs_compile
*c
,
970 struct brw_gs_prog_data
*prog_data
,
971 const nir_shader
*shader
,
972 int shader_time_index
)
973 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
974 &prog_data
->base
.base
),
975 key(&c
->key
), gs_compile(c
),
976 prog_data(&prog_data
->base
.base
), prog(NULL
),
978 shader_time_index(shader_time_index
),
979 bld(fs_builder(this, dispatch_width
).at_end())
989 case MESA_SHADER_FRAGMENT
:
990 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
992 case MESA_SHADER_VERTEX
:
993 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
995 case MESA_SHADER_TESS_EVAL
:
996 key_tex
= &((const brw_tes_prog_key
*) key
)->tex
;
998 case MESA_SHADER_GEOMETRY
:
999 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
1001 case MESA_SHADER_COMPUTE
:
1002 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1005 unreachable("unhandled shader stage");
1008 this->prog_data
= this->stage_prog_data
;
1010 this->failed
= false;
1011 this->simd16_unsupported
= false;
1012 this->no16_msg
= NULL
;
1014 this->nir_locals
= NULL
;
1015 this->nir_ssa_values
= NULL
;
1017 memset(&this->payload
, 0, sizeof(this->payload
));
1018 memset(this->output_components
, 0, sizeof(this->output_components
));
1019 this->source_depth_to_render_target
= false;
1020 this->runtime_check_aads_emit
= false;
1021 this->first_non_payload_grf
= 0;
1022 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1024 this->virtual_grf_start
= NULL
;
1025 this->virtual_grf_end
= NULL
;
1026 this->live_intervals
= NULL
;
1027 this->regs_live_at_ip
= NULL
;
1030 this->last_scratch
= 0;
1031 this->pull_constant_loc
= NULL
;
1032 this->push_constant_loc
= NULL
;
1034 this->promoted_constants
= 0,
1036 this->spilled_any_registers
= false;
1037 this->do_dual_src
= false;
1039 if (dispatch_width
== 8)
1040 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1043 fs_visitor::~fs_visitor()