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i965/fs: Add support for translating ir_triop_fma into MAD.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_visitor.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "brw_fs.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50
51 void
52 fs_visitor::visit(ir_variable *ir)
53 {
54 fs_reg *reg = NULL;
55
56 if (variable_storage(ir))
57 return;
58
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
64 } else {
65 reg = emit_general_interpolation(ir);
66 }
67 assert(reg);
68 hash_table_insert(this->variable_ht, reg, ir);
69 return;
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
72
73 if (ir->index > 0) {
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
82 }
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
85 } else {
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
89
90 int vector_elements =
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
93
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
100 }
101 }
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
104
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
108 */
109 if (ir->is_in_uniform_block())
110 return;
111
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
115 }
116 return;
117 }
118
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
122 } else {
123 setup_uniform_values(ir);
124 }
125
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
128 }
129
130 if (!reg)
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
132
133 hash_table_insert(this->variable_ht, reg, ir);
134 }
135
136 void
137 fs_visitor::visit(ir_dereference_variable *ir)
138 {
139 fs_reg *reg = variable_storage(ir->var);
140 this->result = *reg;
141 }
142
143 void
144 fs_visitor::visit(ir_dereference_record *ir)
145 {
146 const glsl_type *struct_type = ir->record->type;
147
148 ir->record->accept(this);
149
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
153 break;
154 offset += type_size(struct_type->fields.structure[i].type);
155 }
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
158 }
159
160 void
161 fs_visitor::visit(ir_dereference_array *ir)
162 {
163 ir_constant *constant_index;
164 fs_reg src;
165 int element_size = type_size(ir->type);
166
167 constant_index = ir->array_index->as_constant();
168
169 ir->array->accept(this);
170 src = this->result;
171 src.type = brw_type_for_base_type(ir->type);
172
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
176 } else {
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
183 */
184 ir->array_index->accept(this);
185
186 fs_reg index_reg;
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
189
190 if (src.reladdr) {
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
192 }
193
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
196 }
197 this->result = src;
198 }
199
200 void
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
202 {
203 if (brw->gen < 6 ||
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
211
212 emit(MUL(y_times_a, y, a));
213
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
217
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
219 } else {
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
222 */
223 emit(LRP(dst, a, y, x));
224 }
225 }
226
227 void
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
230 {
231 fs_inst *inst;
232
233 if (brw->gen >= 6) {
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
236 } else {
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
238
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
241 }
242 }
243
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
246 */
247 bool
248 fs_visitor::try_emit_saturate(ir_expression *ir)
249 {
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
251
252 if (!sat_val)
253 return false;
254
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
256
257 sat_val->accept(this);
258 fs_reg src = this->result;
259
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
261
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
264 */
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
270 } else {
271 modify->saturate = true;
272 this->result = src;
273 }
274
275
276 return true;
277 }
278
279 bool
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
281 {
282 /* 3-src instructions were introduced in gen6. */
283 if (brw->gen < 6)
284 return false;
285
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
288 return false;
289
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
292
293 if (!mul || mul->operation != ir_binop_mul)
294 return false;
295
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
299 return false;
300
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
303
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
306
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
309
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
312
313 return true;
314 }
315
316 void
317 fs_visitor::visit(ir_expression *ir)
318 {
319 unsigned int operand;
320 fs_reg op[3], temp;
321 fs_inst *inst;
322
323 assert(ir->get_num_operands() <= 3);
324
325 if (try_emit_saturate(ir))
326 return;
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
329 return;
330 }
331
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
337 printf("\n");
338 }
339 assert(this->result.is_valid_3src());
340 op[operand] = this->result;
341
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
344 */
345 assert(!ir->operands[operand]->type->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
347 */
348 assert(!ir->operands[operand]->type->is_vector());
349 }
350
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
353 */
354 this->result = fs_reg(this, ir->type);
355
356 switch (ir->operation) {
357 case ir_unop_logic_not:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
360 */
361 emit(XOR(this->result, op[0], fs_reg(1)));
362 break;
363 case ir_unop_neg:
364 op[0].negate = !op[0].negate;
365 emit(MOV(this->result, op[0]));
366 break;
367 case ir_unop_abs:
368 op[0].abs = true;
369 op[0].negate = false;
370 emit(MOV(this->result, op[0]));
371 break;
372 case ir_unop_sign:
373 temp = fs_reg(this, ir->type);
374
375 emit(MOV(this->result, fs_reg(0.0f)));
376
377 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
378 inst = emit(MOV(this->result, fs_reg(1.0f)));
379 inst->predicate = BRW_PREDICATE_NORMAL;
380
381 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
382 inst = emit(MOV(this->result, fs_reg(-1.0f)));
383 inst->predicate = BRW_PREDICATE_NORMAL;
384
385 break;
386 case ir_unop_rcp:
387 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
388 break;
389
390 case ir_unop_exp2:
391 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
392 break;
393 case ir_unop_log2:
394 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
395 break;
396 case ir_unop_exp:
397 case ir_unop_log:
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
399 break;
400 case ir_unop_sin:
401 case ir_unop_sin_reduced:
402 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
403 break;
404 case ir_unop_cos:
405 case ir_unop_cos_reduced:
406 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
407 break;
408
409 case ir_unop_dFdx:
410 emit(FS_OPCODE_DDX, this->result, op[0]);
411 break;
412 case ir_unop_dFdy:
413 emit(FS_OPCODE_DDY, this->result, op[0]);
414 break;
415
416 case ir_binop_add:
417 emit(ADD(this->result, op[0], op[1]));
418 break;
419 case ir_binop_sub:
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 break;
422
423 case ir_binop_mul:
424 if (ir->type->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
428 * of that operand.
429 *
430 * FINISHME: Emit just the MUL if we know an operand is small
431 * enough.
432 */
433 if (brw->gen >= 7 && dispatch_width == 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
435
436 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
437
438 emit(MUL(acc, op[0], op[1]));
439 emit(MACH(reg_null_d, op[0], op[1]));
440 emit(MOV(this->result, fs_reg(acc)));
441 } else {
442 emit(MUL(this->result, op[0], op[1]));
443 }
444 break;
445 case ir_binop_div:
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir->type->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
449 break;
450 case ir_binop_mod:
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir->type->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
454 break;
455
456 case ir_binop_less:
457 case ir_binop_greater:
458 case ir_binop_lequal:
459 case ir_binop_gequal:
460 case ir_binop_equal:
461 case ir_binop_all_equal:
462 case ir_binop_nequal:
463 case ir_binop_any_nequal:
464 resolve_bool_comparison(ir->operands[0], &op[0]);
465 resolve_bool_comparison(ir->operands[1], &op[1]);
466
467 emit(CMP(this->result, op[0], op[1],
468 brw_conditional_for_comparison(ir->operation)));
469 break;
470
471 case ir_binop_logic_xor:
472 emit(XOR(this->result, op[0], op[1]));
473 break;
474
475 case ir_binop_logic_or:
476 emit(OR(this->result, op[0], op[1]));
477 break;
478
479 case ir_binop_logic_and:
480 emit(AND(this->result, op[0], op[1]));
481 break;
482
483 case ir_binop_dot:
484 case ir_unop_any:
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 break;
487
488 case ir_unop_noise:
489 assert(!"not reached: should be handled by lower_noise");
490 break;
491
492 case ir_quadop_vector:
493 assert(!"not reached: should be handled by lower_quadop_vector");
494 break;
495
496 case ir_binop_vector_extract:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
498 break;
499
500 case ir_triop_vector_insert:
501 assert(!"not reached: should be handled by lower_vector_insert()");
502 break;
503
504 case ir_unop_sqrt:
505 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
506 break;
507
508 case ir_unop_rsq:
509 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
510 break;
511
512 case ir_unop_bitcast_i2f:
513 case ir_unop_bitcast_u2f:
514 op[0].type = BRW_REGISTER_TYPE_F;
515 this->result = op[0];
516 break;
517 case ir_unop_i2u:
518 case ir_unop_bitcast_f2u:
519 op[0].type = BRW_REGISTER_TYPE_UD;
520 this->result = op[0];
521 break;
522 case ir_unop_u2i:
523 case ir_unop_bitcast_f2i:
524 op[0].type = BRW_REGISTER_TYPE_D;
525 this->result = op[0];
526 break;
527 case ir_unop_i2f:
528 case ir_unop_u2f:
529 case ir_unop_f2i:
530 case ir_unop_f2u:
531 emit(MOV(this->result, op[0]));
532 break;
533
534 case ir_unop_b2i:
535 emit(AND(this->result, op[0], fs_reg(1)));
536 break;
537 case ir_unop_b2f:
538 temp = fs_reg(this, glsl_type::int_type);
539 emit(AND(temp, op[0], fs_reg(1)));
540 emit(MOV(this->result, temp));
541 break;
542
543 case ir_unop_f2b:
544 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
545 break;
546 case ir_unop_i2b:
547 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
548 break;
549
550 case ir_unop_trunc:
551 emit(RNDZ(this->result, op[0]));
552 break;
553 case ir_unop_ceil:
554 op[0].negate = !op[0].negate;
555 emit(RNDD(this->result, op[0]));
556 this->result.negate = true;
557 break;
558 case ir_unop_floor:
559 emit(RNDD(this->result, op[0]));
560 break;
561 case ir_unop_fract:
562 emit(FRC(this->result, op[0]));
563 break;
564 case ir_unop_round_even:
565 emit(RNDE(this->result, op[0]));
566 break;
567
568 case ir_binop_min:
569 case ir_binop_max:
570 resolve_ud_negate(&op[0]);
571 resolve_ud_negate(&op[1]);
572 emit_minmax(ir->operation == ir_binop_min ?
573 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
574 this->result, op[0], op[1]);
575 break;
576 case ir_unop_pack_snorm_2x16:
577 case ir_unop_pack_snorm_4x8:
578 case ir_unop_pack_unorm_2x16:
579 case ir_unop_pack_unorm_4x8:
580 case ir_unop_unpack_snorm_2x16:
581 case ir_unop_unpack_snorm_4x8:
582 case ir_unop_unpack_unorm_2x16:
583 case ir_unop_unpack_unorm_4x8:
584 case ir_unop_unpack_half_2x16:
585 case ir_unop_pack_half_2x16:
586 assert(!"not reached: should be handled by lower_packing_builtins");
587 break;
588 case ir_unop_unpack_half_2x16_split_x:
589 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
590 break;
591 case ir_unop_unpack_half_2x16_split_y:
592 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
593 break;
594 case ir_binop_pow:
595 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
596 break;
597
598 case ir_unop_bitfield_reverse:
599 emit(BFREV(this->result, op[0]));
600 break;
601 case ir_unop_bit_count:
602 emit(CBIT(this->result, op[0]));
603 break;
604 case ir_unop_find_msb:
605 temp = fs_reg(this, glsl_type::uint_type);
606 emit(FBH(temp, op[0]));
607
608 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
609 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
610 * subtract the result from 31 to convert the MSB count into an LSB count.
611 */
612
613 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
614 emit(MOV(this->result, temp));
615 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
616
617 temp.negate = true;
618 inst = emit(ADD(this->result, temp, fs_reg(31)));
619 inst->predicate = BRW_PREDICATE_NORMAL;
620 break;
621 case ir_unop_find_lsb:
622 emit(FBL(this->result, op[0]));
623 break;
624 case ir_triop_bitfield_extract:
625 /* Note that the instruction's argument order is reversed from GLSL
626 * and the IR.
627 */
628 emit(BFE(this->result, op[2], op[1], op[0]));
629 break;
630 case ir_binop_bfm:
631 emit(BFI1(this->result, op[0], op[1]));
632 break;
633 case ir_triop_bfi:
634 emit(BFI2(this->result, op[0], op[1], op[2]));
635 break;
636 case ir_quadop_bitfield_insert:
637 assert(!"not reached: should be handled by "
638 "lower_instructions::bitfield_insert_to_bfm_bfi");
639 break;
640
641 case ir_unop_bit_not:
642 emit(NOT(this->result, op[0]));
643 break;
644 case ir_binop_bit_and:
645 emit(AND(this->result, op[0], op[1]));
646 break;
647 case ir_binop_bit_xor:
648 emit(XOR(this->result, op[0], op[1]));
649 break;
650 case ir_binop_bit_or:
651 emit(OR(this->result, op[0], op[1]));
652 break;
653
654 case ir_binop_lshift:
655 emit(SHL(this->result, op[0], op[1]));
656 break;
657
658 case ir_binop_rshift:
659 if (ir->type->base_type == GLSL_TYPE_INT)
660 emit(ASR(this->result, op[0], op[1]));
661 else
662 emit(SHR(this->result, op[0], op[1]));
663 break;
664 case ir_binop_pack_half_2x16_split:
665 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
666 break;
667 case ir_binop_ubo_load: {
668 /* This IR node takes a constant uniform block and a constant or
669 * variable byte offset within the block and loads a vector from that.
670 */
671 ir_constant *uniform_block = ir->operands[0]->as_constant();
672 ir_constant *const_offset = ir->operands[1]->as_constant();
673 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
674 if (const_offset) {
675 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
676 packed_consts.type = result.type;
677
678 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
679 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
680 packed_consts, surf_index, const_offset_reg));
681
682 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
683 for (int i = 0; i < ir->type->vector_elements; i++) {
684 /* UBO bools are any nonzero value. We consider bools to be
685 * values with the low bit set to 1. Convert them using CMP.
686 */
687 if (ir->type->base_type == GLSL_TYPE_BOOL) {
688 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
689 } else {
690 emit(MOV(result, packed_consts));
691 }
692
693 packed_consts.smear++;
694 result.reg_offset++;
695
696 /* The std140 packing rules don't allow vectors to cross 16-byte
697 * boundaries, and a reg is 32 bytes.
698 */
699 assert(packed_consts.smear < 8);
700 }
701 } else {
702 /* Turn the byte offset into a dword offset. */
703 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
704 emit(SHR(base_offset, op[1], fs_reg(2)));
705
706 for (int i = 0; i < ir->type->vector_elements; i++) {
707 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
708 base_offset, i));
709
710 if (ir->type->base_type == GLSL_TYPE_BOOL)
711 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
712
713 result.reg_offset++;
714 }
715 }
716
717 result.reg_offset = 0;
718 break;
719 }
720
721 case ir_triop_fma:
722 /* Note that the instruction's argument order is reversed from GLSL
723 * and the IR.
724 */
725 emit(MAD(this->result, op[2], op[1], op[0]));
726 break;
727
728 case ir_triop_lrp:
729 emit_lrp(this->result, op[0], op[1], op[2]);
730 break;
731 }
732 }
733
734 void
735 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
736 const glsl_type *type, bool predicated)
737 {
738 switch (type->base_type) {
739 case GLSL_TYPE_FLOAT:
740 case GLSL_TYPE_UINT:
741 case GLSL_TYPE_INT:
742 case GLSL_TYPE_BOOL:
743 for (unsigned int i = 0; i < type->components(); i++) {
744 l.type = brw_type_for_base_type(type);
745 r.type = brw_type_for_base_type(type);
746
747 if (predicated || !l.equals(r)) {
748 fs_inst *inst = emit(MOV(l, r));
749 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
750 }
751
752 l.reg_offset++;
753 r.reg_offset++;
754 }
755 break;
756 case GLSL_TYPE_ARRAY:
757 for (unsigned int i = 0; i < type->length; i++) {
758 emit_assignment_writes(l, r, type->fields.array, predicated);
759 }
760 break;
761
762 case GLSL_TYPE_STRUCT:
763 for (unsigned int i = 0; i < type->length; i++) {
764 emit_assignment_writes(l, r, type->fields.structure[i].type,
765 predicated);
766 }
767 break;
768
769 case GLSL_TYPE_SAMPLER:
770 break;
771
772 case GLSL_TYPE_VOID:
773 case GLSL_TYPE_ERROR:
774 case GLSL_TYPE_INTERFACE:
775 assert(!"not reached");
776 break;
777 }
778 }
779
780 /* If the RHS processing resulted in an instruction generating a
781 * temporary value, and it would be easy to rewrite the instruction to
782 * generate its result right into the LHS instead, do so. This ends
783 * up reliably removing instructions where it can be tricky to do so
784 * later without real UD chain information.
785 */
786 bool
787 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
788 fs_reg dst,
789 fs_reg src,
790 fs_inst *pre_rhs_inst,
791 fs_inst *last_rhs_inst)
792 {
793 /* Only attempt if we're doing a direct assignment. */
794 if (ir->condition ||
795 !(ir->lhs->type->is_scalar() ||
796 (ir->lhs->type->is_vector() &&
797 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
798 return false;
799
800 /* Make sure the last instruction generated our source reg. */
801 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
802 last_rhs_inst,
803 src);
804 if (!modify)
805 return false;
806
807 /* If last_rhs_inst wrote a different number of components than our LHS,
808 * we can't safely rewrite it.
809 */
810 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
811 return false;
812
813 /* Success! Rewrite the instruction. */
814 modify->dst = dst;
815
816 return true;
817 }
818
819 void
820 fs_visitor::visit(ir_assignment *ir)
821 {
822 fs_reg l, r;
823 fs_inst *inst;
824
825 /* FINISHME: arrays on the lhs */
826 ir->lhs->accept(this);
827 l = this->result;
828
829 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
830
831 ir->rhs->accept(this);
832 r = this->result;
833
834 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
835
836 assert(l.file != BAD_FILE);
837 assert(r.file != BAD_FILE);
838
839 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
840 return;
841
842 if (ir->condition) {
843 emit_bool_to_cond_code(ir->condition);
844 }
845
846 if (ir->lhs->type->is_scalar() ||
847 ir->lhs->type->is_vector()) {
848 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
849 if (ir->write_mask & (1 << i)) {
850 inst = emit(MOV(l, r));
851 if (ir->condition)
852 inst->predicate = BRW_PREDICATE_NORMAL;
853 r.reg_offset++;
854 }
855 l.reg_offset++;
856 }
857 } else {
858 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
859 }
860 }
861
862 fs_inst *
863 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
864 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
865 {
866 int mlen;
867 int base_mrf = 1;
868 bool simd16 = false;
869 fs_reg orig_dst;
870
871 /* g0 header. */
872 mlen = 1;
873
874 if (ir->shadow_comparitor) {
875 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
876 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
877 coordinate.reg_offset++;
878 }
879 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
880 mlen += 3;
881
882 if (ir->op == ir_tex) {
883 /* There's no plain shadow compare message, so we use shadow
884 * compare with a bias of 0.0.
885 */
886 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
887 mlen++;
888 } else if (ir->op == ir_txb || ir->op == ir_txl) {
889 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
890 mlen++;
891 } else {
892 assert(!"Should not get here.");
893 }
894
895 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
896 mlen++;
897 } else if (ir->op == ir_tex) {
898 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
899 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
900 coordinate.reg_offset++;
901 }
902 /* zero the others. */
903 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
904 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
905 }
906 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
907 mlen += 3;
908 } else if (ir->op == ir_txd) {
909 fs_reg &dPdx = lod;
910
911 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
912 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
913 coordinate.reg_offset++;
914 }
915 /* the slots for u and v are always present, but r is optional */
916 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
917
918 /* P = u, v, r
919 * dPdx = dudx, dvdx, drdx
920 * dPdy = dudy, dvdy, drdy
921 *
922 * 1-arg: Does not exist.
923 *
924 * 2-arg: dudx dvdx dudy dvdy
925 * dPdx.x dPdx.y dPdy.x dPdy.y
926 * m4 m5 m6 m7
927 *
928 * 3-arg: dudx dvdx drdx dudy dvdy drdy
929 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
930 * m5 m6 m7 m8 m9 m10
931 */
932 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
933 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
934 dPdx.reg_offset++;
935 }
936 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
937
938 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
939 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
940 dPdy.reg_offset++;
941 }
942 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
943 } else if (ir->op == ir_txs) {
944 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
945 simd16 = true;
946 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
947 mlen += 2;
948 } else {
949 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
950 * instructions. We'll need to do SIMD16 here.
951 */
952 simd16 = true;
953 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
954
955 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
956 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
957 coordinate));
958 coordinate.reg_offset++;
959 }
960
961 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
962 * be necessary for TXF (ld), but seems wise to do for all messages.
963 */
964 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
965 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
966 }
967
968 /* lod/bias appears after u/v/r. */
969 mlen += 6;
970
971 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
972 mlen++;
973
974 /* The unused upper half. */
975 mlen++;
976 }
977
978 if (simd16) {
979 /* Now, since we're doing simd16, the return is 2 interleaved
980 * vec4s where the odd-indexed ones are junk. We'll need to move
981 * this weirdness around to the expected layout.
982 */
983 orig_dst = dst;
984 dst = fs_reg(GRF, virtual_grf_alloc(8),
985 (brw->is_g4x ?
986 brw_type_for_base_type(ir->type) :
987 BRW_REGISTER_TYPE_F));
988 }
989
990 fs_inst *inst = NULL;
991 switch (ir->op) {
992 case ir_tex:
993 inst = emit(SHADER_OPCODE_TEX, dst);
994 break;
995 case ir_txb:
996 inst = emit(FS_OPCODE_TXB, dst);
997 break;
998 case ir_txl:
999 inst = emit(SHADER_OPCODE_TXL, dst);
1000 break;
1001 case ir_txd:
1002 inst = emit(SHADER_OPCODE_TXD, dst);
1003 break;
1004 case ir_txs:
1005 inst = emit(SHADER_OPCODE_TXS, dst);
1006 break;
1007 case ir_txf:
1008 inst = emit(SHADER_OPCODE_TXF, dst);
1009 break;
1010 default:
1011 fail("unrecognized texture opcode");
1012 }
1013 inst->base_mrf = base_mrf;
1014 inst->mlen = mlen;
1015 inst->header_present = true;
1016 inst->regs_written = simd16 ? 8 : 4;
1017
1018 if (simd16) {
1019 for (int i = 0; i < 4; i++) {
1020 emit(MOV(orig_dst, dst));
1021 orig_dst.reg_offset++;
1022 dst.reg_offset += 2;
1023 }
1024 }
1025
1026 return inst;
1027 }
1028
1029 /* gen5's sampler has slots for u, v, r, array index, then optional
1030 * parameters like shadow comparitor or LOD bias. If optional
1031 * parameters aren't present, those base slots are optional and don't
1032 * need to be included in the message.
1033 *
1034 * We don't fill in the unnecessary slots regardless, which may look
1035 * surprising in the disassembly.
1036 */
1037 fs_inst *
1038 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1039 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1040 fs_reg sample_index)
1041 {
1042 int mlen = 0;
1043 int base_mrf = 2;
1044 int reg_width = dispatch_width / 8;
1045 bool header_present = false;
1046 const int vector_elements =
1047 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1048
1049 if (ir->offset != NULL && ir->op == ir_txf) {
1050 /* It appears that the ld instruction used for txf does its
1051 * address bounds check before adding in the offset. To work
1052 * around this, just add the integer offset to the integer texel
1053 * coordinate, and don't put the offset in the header.
1054 */
1055 ir_constant *offset = ir->offset->as_constant();
1056 for (int i = 0; i < vector_elements; i++) {
1057 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1058 coordinate,
1059 offset->value.i[i]));
1060 coordinate.reg_offset++;
1061 }
1062 } else {
1063 if (ir->offset) {
1064 /* The offsets set up by the ir_texture visitor are in the
1065 * m1 header, so we can't go headerless.
1066 */
1067 header_present = true;
1068 mlen++;
1069 base_mrf--;
1070 }
1071
1072 for (int i = 0; i < vector_elements; i++) {
1073 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1074 coordinate));
1075 coordinate.reg_offset++;
1076 }
1077 }
1078 mlen += vector_elements * reg_width;
1079
1080 if (ir->shadow_comparitor) {
1081 mlen = MAX2(mlen, header_present + 4 * reg_width);
1082
1083 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1084 mlen += reg_width;
1085 }
1086
1087 fs_inst *inst = NULL;
1088 switch (ir->op) {
1089 case ir_tex:
1090 inst = emit(SHADER_OPCODE_TEX, dst);
1091 break;
1092 case ir_txb:
1093 mlen = MAX2(mlen, header_present + 4 * reg_width);
1094 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1095 mlen += reg_width;
1096
1097 inst = emit(FS_OPCODE_TXB, dst);
1098 break;
1099 case ir_txl:
1100 mlen = MAX2(mlen, header_present + 4 * reg_width);
1101 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1102 mlen += reg_width;
1103
1104 inst = emit(SHADER_OPCODE_TXL, dst);
1105 break;
1106 case ir_txd: {
1107 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1108
1109 /**
1110 * P = u, v, r
1111 * dPdx = dudx, dvdx, drdx
1112 * dPdy = dudy, dvdy, drdy
1113 *
1114 * Load up these values:
1115 * - dudx dudy dvdx dvdy drdx drdy
1116 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1117 */
1118 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1119 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1120 lod.reg_offset++;
1121 mlen += reg_width;
1122
1123 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1124 lod2.reg_offset++;
1125 mlen += reg_width;
1126 }
1127
1128 inst = emit(SHADER_OPCODE_TXD, dst);
1129 break;
1130 }
1131 case ir_txs:
1132 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1133 mlen += reg_width;
1134 inst = emit(SHADER_OPCODE_TXS, dst);
1135 break;
1136 case ir_txf:
1137 mlen = header_present + 4 * reg_width;
1138 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1139 inst = emit(SHADER_OPCODE_TXF, dst);
1140 break;
1141 case ir_txf_ms:
1142 mlen = header_present + 4 * reg_width;
1143
1144 /* lod */
1145 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1146 /* sample index */
1147 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1148 mlen += reg_width;
1149 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1150 break;
1151 case ir_lod:
1152 inst = emit(SHADER_OPCODE_LOD, dst);
1153 break;
1154 }
1155 inst->base_mrf = base_mrf;
1156 inst->mlen = mlen;
1157 inst->header_present = header_present;
1158 inst->regs_written = 4;
1159
1160 if (mlen > 11) {
1161 fail("Message length >11 disallowed by hardware\n");
1162 }
1163
1164 return inst;
1165 }
1166
1167 fs_inst *
1168 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1169 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1170 fs_reg sample_index)
1171 {
1172 int mlen = 0;
1173 int base_mrf = 2;
1174 int reg_width = dispatch_width / 8;
1175 bool header_present = false;
1176 int offsets[3];
1177
1178 if (ir->offset && ir->op != ir_txf) {
1179 /* The offsets set up by the ir_texture visitor are in the
1180 * m1 header, so we can't go headerless.
1181 */
1182 header_present = true;
1183 mlen++;
1184 base_mrf--;
1185 }
1186
1187 if (ir->shadow_comparitor) {
1188 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1189 mlen += reg_width;
1190 }
1191
1192 /* Set up the LOD info */
1193 switch (ir->op) {
1194 case ir_tex:
1195 case ir_lod:
1196 break;
1197 case ir_txb:
1198 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1199 mlen += reg_width;
1200 break;
1201 case ir_txl:
1202 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1203 mlen += reg_width;
1204 break;
1205 case ir_txd: {
1206 if (dispatch_width == 16)
1207 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1208
1209 /* Load dPdx and the coordinate together:
1210 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1211 */
1212 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1213 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1214 coordinate.reg_offset++;
1215 mlen += reg_width;
1216
1217 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1218 * only derivatives for (u, v, r).
1219 */
1220 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1221 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1222 lod.reg_offset++;
1223 mlen += reg_width;
1224
1225 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1226 lod2.reg_offset++;
1227 mlen += reg_width;
1228 }
1229 }
1230 break;
1231 }
1232 case ir_txs:
1233 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1234 mlen += reg_width;
1235 break;
1236 case ir_txf:
1237 /* It appears that the ld instruction used for txf does its
1238 * address bounds check before adding in the offset. To work
1239 * around this, just add the integer offset to the integer texel
1240 * coordinate, and don't put the offset in the header.
1241 */
1242 if (ir->offset) {
1243 ir_constant *offset = ir->offset->as_constant();
1244 offsets[0] = offset->value.i[0];
1245 offsets[1] = offset->value.i[1];
1246 offsets[2] = offset->value.i[2];
1247 } else {
1248 memset(offsets, 0, sizeof(offsets));
1249 }
1250
1251 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1252 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1253 coordinate, offsets[0]));
1254 coordinate.reg_offset++;
1255 mlen += reg_width;
1256
1257 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1258 mlen += reg_width;
1259
1260 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1261 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1262 coordinate, offsets[i]));
1263 coordinate.reg_offset++;
1264 mlen += reg_width;
1265 }
1266 break;
1267 case ir_txf_ms:
1268 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1269 mlen += reg_width;
1270
1271 /* constant zero MCS; we arrange to never actually have a compressed
1272 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1273 * if we ever support texturing from compressed multisample surfaces
1274 */
1275 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1276 mlen += reg_width;
1277
1278 /* there is no offsetting for this message; just copy in the integer
1279 * texture coordinates
1280 */
1281 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1282 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1283 coordinate));
1284 coordinate.reg_offset++;
1285 mlen += reg_width;
1286 }
1287 break;
1288 }
1289
1290 /* Set up the coordinate (except for cases where it was done above) */
1291 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
1292 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1293 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1294 coordinate.reg_offset++;
1295 mlen += reg_width;
1296 }
1297 }
1298
1299 /* Generate the SEND */
1300 fs_inst *inst = NULL;
1301 switch (ir->op) {
1302 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1303 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1304 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1305 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1306 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1307 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1308 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1309 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1310 }
1311 inst->base_mrf = base_mrf;
1312 inst->mlen = mlen;
1313 inst->header_present = header_present;
1314 inst->regs_written = 4;
1315
1316 if (mlen > 11) {
1317 fail("Message length >11 disallowed by hardware\n");
1318 }
1319
1320 return inst;
1321 }
1322
1323 fs_reg
1324 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1325 bool is_rect, int sampler, int texunit)
1326 {
1327 fs_inst *inst = NULL;
1328 bool needs_gl_clamp = true;
1329 fs_reg scale_x, scale_y;
1330
1331 /* The 965 requires the EU to do the normalization of GL rectangle
1332 * texture coordinates. We use the program parameter state
1333 * tracking to get the scaling factor.
1334 */
1335 if (is_rect &&
1336 (brw->gen < 6 ||
1337 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1338 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1339 struct gl_program_parameter_list *params = fp->Base.Parameters;
1340 int tokens[STATE_LENGTH] = {
1341 STATE_INTERNAL,
1342 STATE_TEXRECT_SCALE,
1343 texunit,
1344 0,
1345 0
1346 };
1347
1348 if (dispatch_width == 16) {
1349 fail("rectangle scale uniform setup not supported on 16-wide\n");
1350 return coordinate;
1351 }
1352
1353 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1354 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1355
1356 GLuint index = _mesa_add_state_reference(params,
1357 (gl_state_index *)tokens);
1358 c->prog_data.param[c->prog_data.nr_params++] =
1359 &fp->Base.Parameters->ParameterValues[index][0].f;
1360 c->prog_data.param[c->prog_data.nr_params++] =
1361 &fp->Base.Parameters->ParameterValues[index][1].f;
1362 }
1363
1364 /* The 965 requires the EU to do the normalization of GL rectangle
1365 * texture coordinates. We use the program parameter state
1366 * tracking to get the scaling factor.
1367 */
1368 if (brw->gen < 6 && is_rect) {
1369 fs_reg dst = fs_reg(this, ir->coordinate->type);
1370 fs_reg src = coordinate;
1371 coordinate = dst;
1372
1373 emit(MUL(dst, src, scale_x));
1374 dst.reg_offset++;
1375 src.reg_offset++;
1376 emit(MUL(dst, src, scale_y));
1377 } else if (is_rect) {
1378 /* On gen6+, the sampler handles the rectangle coordinates
1379 * natively, without needing rescaling. But that means we have
1380 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1381 * not [0, 1] like the default case below.
1382 */
1383 needs_gl_clamp = false;
1384
1385 for (int i = 0; i < 2; i++) {
1386 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1387 fs_reg chan = coordinate;
1388 chan.reg_offset += i;
1389
1390 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1391 inst->conditional_mod = BRW_CONDITIONAL_G;
1392
1393 /* Our parameter comes in as 1.0/width or 1.0/height,
1394 * because that's what people normally want for doing
1395 * texture rectangle handling. We need width or height
1396 * for clamping, but we don't care enough to make a new
1397 * parameter type, so just invert back.
1398 */
1399 fs_reg limit = fs_reg(this, glsl_type::float_type);
1400 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1401 emit(SHADER_OPCODE_RCP, limit, limit);
1402
1403 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1404 inst->conditional_mod = BRW_CONDITIONAL_L;
1405 }
1406 }
1407 }
1408
1409 if (ir->coordinate && needs_gl_clamp) {
1410 for (unsigned int i = 0;
1411 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1412 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1413 fs_reg chan = coordinate;
1414 chan.reg_offset += i;
1415
1416 fs_inst *inst = emit(MOV(chan, chan));
1417 inst->saturate = true;
1418 }
1419 }
1420 }
1421 return coordinate;
1422 }
1423
1424 void
1425 fs_visitor::visit(ir_texture *ir)
1426 {
1427 fs_inst *inst = NULL;
1428
1429 int sampler =
1430 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1431 /* FINISHME: We're failing to recompile our programs when the sampler is
1432 * updated. This only matters for the texture rectangle scale parameters
1433 * (pre-gen6, or gen6+ with GL_CLAMP).
1434 */
1435 int texunit = fp->Base.SamplerUnits[sampler];
1436
1437 /* Should be lowered by do_lower_texture_projection */
1438 assert(!ir->projector);
1439
1440 /* Generate code to compute all the subexpression trees. This has to be
1441 * done before loading any values into MRFs for the sampler message since
1442 * generating these values may involve SEND messages that need the MRFs.
1443 */
1444 fs_reg coordinate;
1445 if (ir->coordinate) {
1446 ir->coordinate->accept(this);
1447
1448 coordinate = rescale_texcoord(ir, this->result,
1449 ir->sampler->type->sampler_dimensionality ==
1450 GLSL_SAMPLER_DIM_RECT,
1451 sampler, texunit);
1452 }
1453
1454 fs_reg shadow_comparitor;
1455 if (ir->shadow_comparitor) {
1456 ir->shadow_comparitor->accept(this);
1457 shadow_comparitor = this->result;
1458 }
1459
1460 fs_reg lod, lod2, sample_index;
1461 switch (ir->op) {
1462 case ir_tex:
1463 case ir_lod:
1464 break;
1465 case ir_txb:
1466 ir->lod_info.bias->accept(this);
1467 lod = this->result;
1468 break;
1469 case ir_txd:
1470 ir->lod_info.grad.dPdx->accept(this);
1471 lod = this->result;
1472
1473 ir->lod_info.grad.dPdy->accept(this);
1474 lod2 = this->result;
1475 break;
1476 case ir_txf:
1477 case ir_txl:
1478 case ir_txs:
1479 ir->lod_info.lod->accept(this);
1480 lod = this->result;
1481 break;
1482 case ir_txf_ms:
1483 ir->lod_info.sample_index->accept(this);
1484 sample_index = this->result;
1485 break;
1486 };
1487
1488 /* Writemasking doesn't eliminate channels on SIMD8 texture
1489 * samples, so don't worry about them.
1490 */
1491 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1492
1493 if (brw->gen >= 7) {
1494 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1495 lod, lod2, sample_index);
1496 } else if (brw->gen >= 5) {
1497 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1498 lod, lod2, sample_index);
1499 } else {
1500 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1501 lod, lod2);
1502 }
1503
1504 /* The header is set up by generate_tex() when necessary. */
1505 inst->src[0] = reg_undef;
1506
1507 if (ir->offset != NULL && ir->op != ir_txf)
1508 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1509
1510 inst->sampler = sampler;
1511
1512 if (ir->shadow_comparitor)
1513 inst->shadow_compare = true;
1514
1515 /* fixup #layers for cube map arrays */
1516 if (ir->op == ir_txs) {
1517 glsl_type const *type = ir->sampler->type;
1518 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1519 type->sampler_array) {
1520 fs_reg depth = dst;
1521 depth.reg_offset = 2;
1522 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1523 }
1524 }
1525
1526 swizzle_result(ir, dst, sampler);
1527 }
1528
1529 /**
1530 * Swizzle the result of a texture result. This is necessary for
1531 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1532 */
1533 void
1534 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1535 {
1536 this->result = orig_val;
1537
1538 if (ir->op == ir_txs || ir->op == ir_lod)
1539 return;
1540
1541 if (ir->type == glsl_type::float_type) {
1542 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1543 assert(ir->sampler->type->sampler_shadow);
1544 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1545 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1546
1547 for (int i = 0; i < 4; i++) {
1548 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1549 fs_reg l = swizzled_result;
1550 l.reg_offset += i;
1551
1552 if (swiz == SWIZZLE_ZERO) {
1553 emit(MOV(l, fs_reg(0.0f)));
1554 } else if (swiz == SWIZZLE_ONE) {
1555 emit(MOV(l, fs_reg(1.0f)));
1556 } else {
1557 fs_reg r = orig_val;
1558 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1559 emit(MOV(l, r));
1560 }
1561 }
1562 this->result = swizzled_result;
1563 }
1564 }
1565
1566 void
1567 fs_visitor::visit(ir_swizzle *ir)
1568 {
1569 ir->val->accept(this);
1570 fs_reg val = this->result;
1571
1572 if (ir->type->vector_elements == 1) {
1573 this->result.reg_offset += ir->mask.x;
1574 return;
1575 }
1576
1577 fs_reg result = fs_reg(this, ir->type);
1578 this->result = result;
1579
1580 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1581 fs_reg channel = val;
1582 int swiz = 0;
1583
1584 switch (i) {
1585 case 0:
1586 swiz = ir->mask.x;
1587 break;
1588 case 1:
1589 swiz = ir->mask.y;
1590 break;
1591 case 2:
1592 swiz = ir->mask.z;
1593 break;
1594 case 3:
1595 swiz = ir->mask.w;
1596 break;
1597 }
1598
1599 channel.reg_offset += swiz;
1600 emit(MOV(result, channel));
1601 result.reg_offset++;
1602 }
1603 }
1604
1605 void
1606 fs_visitor::visit(ir_discard *ir)
1607 {
1608 assert(ir->condition == NULL); /* FINISHME */
1609
1610 /* We track our discarded pixels in f0.1. By predicating on it, we can
1611 * update just the flag bits that aren't yet discarded. By emitting a
1612 * CMP of g0 != g0, all our currently executing channels will get turned
1613 * off.
1614 */
1615 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1616 BRW_REGISTER_TYPE_UW));
1617 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1618 BRW_CONDITIONAL_NZ));
1619 cmp->predicate = BRW_PREDICATE_NORMAL;
1620 cmp->flag_subreg = 1;
1621
1622 if (brw->gen >= 6) {
1623 /* For performance, after a discard, jump to the end of the shader.
1624 * However, many people will do foliage by discarding based on a
1625 * texture's alpha mask, and then continue on to texture with the
1626 * remaining pixels. To avoid trashing the derivatives for those
1627 * texture samples, we'll only jump if all of the pixels in the subspan
1628 * have been discarded.
1629 */
1630 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1631 discard_jump->flag_subreg = 1;
1632 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1633 discard_jump->predicate_inverse = true;
1634 }
1635 }
1636
1637 void
1638 fs_visitor::visit(ir_constant *ir)
1639 {
1640 /* Set this->result to reg at the bottom of the function because some code
1641 * paths will cause this visitor to be applied to other fields. This will
1642 * cause the value stored in this->result to be modified.
1643 *
1644 * Make reg constant so that it doesn't get accidentally modified along the
1645 * way. Yes, I actually had this problem. :(
1646 */
1647 const fs_reg reg(this, ir->type);
1648 fs_reg dst_reg = reg;
1649
1650 if (ir->type->is_array()) {
1651 const unsigned size = type_size(ir->type->fields.array);
1652
1653 for (unsigned i = 0; i < ir->type->length; i++) {
1654 ir->array_elements[i]->accept(this);
1655 fs_reg src_reg = this->result;
1656
1657 dst_reg.type = src_reg.type;
1658 for (unsigned j = 0; j < size; j++) {
1659 emit(MOV(dst_reg, src_reg));
1660 src_reg.reg_offset++;
1661 dst_reg.reg_offset++;
1662 }
1663 }
1664 } else if (ir->type->is_record()) {
1665 foreach_list(node, &ir->components) {
1666 ir_constant *const field = (ir_constant *) node;
1667 const unsigned size = type_size(field->type);
1668
1669 field->accept(this);
1670 fs_reg src_reg = this->result;
1671
1672 dst_reg.type = src_reg.type;
1673 for (unsigned j = 0; j < size; j++) {
1674 emit(MOV(dst_reg, src_reg));
1675 src_reg.reg_offset++;
1676 dst_reg.reg_offset++;
1677 }
1678 }
1679 } else {
1680 const unsigned size = type_size(ir->type);
1681
1682 for (unsigned i = 0; i < size; i++) {
1683 switch (ir->type->base_type) {
1684 case GLSL_TYPE_FLOAT:
1685 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1686 break;
1687 case GLSL_TYPE_UINT:
1688 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1689 break;
1690 case GLSL_TYPE_INT:
1691 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1692 break;
1693 case GLSL_TYPE_BOOL:
1694 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1695 break;
1696 default:
1697 assert(!"Non-float/uint/int/bool constant");
1698 }
1699 dst_reg.reg_offset++;
1700 }
1701 }
1702
1703 this->result = reg;
1704 }
1705
1706 void
1707 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1708 {
1709 ir_expression *expr = ir->as_expression();
1710
1711 if (expr) {
1712 fs_reg op[2];
1713 fs_inst *inst;
1714
1715 assert(expr->get_num_operands() <= 2);
1716 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1717 assert(expr->operands[i]->type->is_scalar());
1718
1719 expr->operands[i]->accept(this);
1720 op[i] = this->result;
1721
1722 resolve_ud_negate(&op[i]);
1723 }
1724
1725 switch (expr->operation) {
1726 case ir_unop_logic_not:
1727 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1728 inst->conditional_mod = BRW_CONDITIONAL_Z;
1729 break;
1730
1731 case ir_binop_logic_xor:
1732 case ir_binop_logic_or:
1733 case ir_binop_logic_and:
1734 goto out;
1735
1736 case ir_unop_f2b:
1737 if (brw->gen >= 6) {
1738 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1739 } else {
1740 inst = emit(MOV(reg_null_f, op[0]));
1741 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1742 }
1743 break;
1744
1745 case ir_unop_i2b:
1746 if (brw->gen >= 6) {
1747 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1748 } else {
1749 inst = emit(MOV(reg_null_d, op[0]));
1750 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1751 }
1752 break;
1753
1754 case ir_binop_greater:
1755 case ir_binop_gequal:
1756 case ir_binop_less:
1757 case ir_binop_lequal:
1758 case ir_binop_equal:
1759 case ir_binop_all_equal:
1760 case ir_binop_nequal:
1761 case ir_binop_any_nequal:
1762 resolve_bool_comparison(expr->operands[0], &op[0]);
1763 resolve_bool_comparison(expr->operands[1], &op[1]);
1764
1765 emit(CMP(reg_null_d, op[0], op[1],
1766 brw_conditional_for_comparison(expr->operation)));
1767 break;
1768
1769 default:
1770 assert(!"not reached");
1771 fail("bad cond code\n");
1772 break;
1773 }
1774 return;
1775 }
1776
1777 out:
1778 ir->accept(this);
1779
1780 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1781 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1782 }
1783
1784 /**
1785 * Emit a gen6 IF statement with the comparison folded into the IF
1786 * instruction.
1787 */
1788 void
1789 fs_visitor::emit_if_gen6(ir_if *ir)
1790 {
1791 ir_expression *expr = ir->condition->as_expression();
1792
1793 if (expr) {
1794 fs_reg op[2];
1795 fs_inst *inst;
1796 fs_reg temp;
1797
1798 assert(expr->get_num_operands() <= 2);
1799 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1800 assert(expr->operands[i]->type->is_scalar());
1801
1802 expr->operands[i]->accept(this);
1803 op[i] = this->result;
1804 }
1805
1806 switch (expr->operation) {
1807 case ir_unop_logic_not:
1808 case ir_binop_logic_xor:
1809 case ir_binop_logic_or:
1810 case ir_binop_logic_and:
1811 /* For operations on bool arguments, only the low bit of the bool is
1812 * valid, and the others are undefined. Fall back to the condition
1813 * code path.
1814 */
1815 break;
1816
1817 case ir_unop_f2b:
1818 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1819 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1820 return;
1821
1822 case ir_unop_i2b:
1823 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1824 return;
1825
1826 case ir_binop_greater:
1827 case ir_binop_gequal:
1828 case ir_binop_less:
1829 case ir_binop_lequal:
1830 case ir_binop_equal:
1831 case ir_binop_all_equal:
1832 case ir_binop_nequal:
1833 case ir_binop_any_nequal:
1834 resolve_bool_comparison(expr->operands[0], &op[0]);
1835 resolve_bool_comparison(expr->operands[1], &op[1]);
1836
1837 emit(IF(op[0], op[1],
1838 brw_conditional_for_comparison(expr->operation)));
1839 return;
1840 default:
1841 assert(!"not reached");
1842 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1843 fail("bad condition\n");
1844 return;
1845 }
1846 }
1847
1848 emit_bool_to_cond_code(ir->condition);
1849 fs_inst *inst = emit(BRW_OPCODE_IF);
1850 inst->predicate = BRW_PREDICATE_NORMAL;
1851 }
1852
1853 /**
1854 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1855 *
1856 * Many GLSL shaders contain the following pattern:
1857 *
1858 * x = condition ? foo : bar
1859 *
1860 * The compiler emits an ir_if tree for this, since each subexpression might be
1861 * a complex tree that could have side-effects or short-circuit logic.
1862 *
1863 * However, the common case is to simply select one of two constants or
1864 * variable values---which is exactly what SEL is for. In this case, the
1865 * assembly looks like:
1866 *
1867 * (+f0) IF
1868 * MOV dst src0
1869 * ELSE
1870 * MOV dst src1
1871 * ENDIF
1872 *
1873 * which can be easily translated into:
1874 *
1875 * (+f0) SEL dst src0 src1
1876 *
1877 * If src0 is an immediate value, we promote it to a temporary GRF.
1878 */
1879 void
1880 fs_visitor::try_replace_with_sel()
1881 {
1882 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1883 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1884
1885 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1886 int opcodes[] = {
1887 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1888 };
1889
1890 fs_inst *match = (fs_inst *) endif_inst->prev;
1891 for (int i = 0; i < 4; i++) {
1892 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1893 return;
1894 match = (fs_inst *) match->prev;
1895 }
1896
1897 /* The opcodes match; it looks like the right sequence of instructions. */
1898 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1899 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1900 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1901
1902 /* Check that the MOVs are the right form. */
1903 if (then_mov->dst.equals(else_mov->dst) &&
1904 !then_mov->is_partial_write() &&
1905 !else_mov->is_partial_write()) {
1906
1907 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1908 while (!if_inst->next->is_tail_sentinel())
1909 if_inst->next->remove();
1910 if_inst->remove();
1911
1912 /* Only the last source register can be a constant, so if the MOV in
1913 * the "then" clause uses a constant, we need to put it in a temporary.
1914 */
1915 fs_reg src0(then_mov->src[0]);
1916 if (src0.file == IMM) {
1917 src0 = fs_reg(this, glsl_type::float_type);
1918 src0.type = then_mov->src[0].type;
1919 emit(MOV(src0, then_mov->src[0]));
1920 }
1921
1922 fs_inst *sel;
1923 if (if_inst->conditional_mod) {
1924 /* Sandybridge-specific IF with embedded comparison */
1925 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
1926 if_inst->conditional_mod));
1927 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1928 sel->predicate = BRW_PREDICATE_NORMAL;
1929 } else {
1930 /* Separate CMP and IF instructions */
1931 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1932 sel->predicate = if_inst->predicate;
1933 sel->predicate_inverse = if_inst->predicate_inverse;
1934 }
1935 }
1936 }
1937
1938 void
1939 fs_visitor::visit(ir_if *ir)
1940 {
1941 if (brw->gen < 6 && dispatch_width == 16) {
1942 fail("Can't support (non-uniform) control flow on 16-wide\n");
1943 }
1944
1945 /* Don't point the annotation at the if statement, because then it plus
1946 * the then and else blocks get printed.
1947 */
1948 this->base_ir = ir->condition;
1949
1950 if (brw->gen == 6) {
1951 emit_if_gen6(ir);
1952 } else {
1953 emit_bool_to_cond_code(ir->condition);
1954
1955 emit(IF(BRW_PREDICATE_NORMAL));
1956 }
1957
1958 foreach_list(node, &ir->then_instructions) {
1959 ir_instruction *ir = (ir_instruction *)node;
1960 this->base_ir = ir;
1961
1962 ir->accept(this);
1963 }
1964
1965 if (!ir->else_instructions.is_empty()) {
1966 emit(BRW_OPCODE_ELSE);
1967
1968 foreach_list(node, &ir->else_instructions) {
1969 ir_instruction *ir = (ir_instruction *)node;
1970 this->base_ir = ir;
1971
1972 ir->accept(this);
1973 }
1974 }
1975
1976 emit(BRW_OPCODE_ENDIF);
1977
1978 try_replace_with_sel();
1979 }
1980
1981 void
1982 fs_visitor::visit(ir_loop *ir)
1983 {
1984 fs_reg counter = reg_undef;
1985
1986 if (brw->gen < 6 && dispatch_width == 16) {
1987 fail("Can't support (non-uniform) control flow on 16-wide\n");
1988 }
1989
1990 if (ir->counter) {
1991 this->base_ir = ir->counter;
1992 ir->counter->accept(this);
1993 counter = *(variable_storage(ir->counter));
1994
1995 if (ir->from) {
1996 this->base_ir = ir->from;
1997 ir->from->accept(this);
1998
1999 emit(MOV(counter, this->result));
2000 }
2001 }
2002
2003 this->base_ir = NULL;
2004 emit(BRW_OPCODE_DO);
2005
2006 if (ir->to) {
2007 this->base_ir = ir->to;
2008 ir->to->accept(this);
2009
2010 emit(CMP(reg_null_d, counter, this->result,
2011 brw_conditional_for_comparison(ir->cmp)));
2012
2013 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2014 inst->predicate = BRW_PREDICATE_NORMAL;
2015 }
2016
2017 foreach_list(node, &ir->body_instructions) {
2018 ir_instruction *ir = (ir_instruction *)node;
2019
2020 this->base_ir = ir;
2021 ir->accept(this);
2022 }
2023
2024 if (ir->increment) {
2025 this->base_ir = ir->increment;
2026 ir->increment->accept(this);
2027 emit(ADD(counter, counter, this->result));
2028 }
2029
2030 this->base_ir = NULL;
2031 emit(BRW_OPCODE_WHILE);
2032 }
2033
2034 void
2035 fs_visitor::visit(ir_loop_jump *ir)
2036 {
2037 switch (ir->mode) {
2038 case ir_loop_jump::jump_break:
2039 emit(BRW_OPCODE_BREAK);
2040 break;
2041 case ir_loop_jump::jump_continue:
2042 emit(BRW_OPCODE_CONTINUE);
2043 break;
2044 }
2045 }
2046
2047 void
2048 fs_visitor::visit(ir_call *ir)
2049 {
2050 assert(!"FINISHME");
2051 }
2052
2053 void
2054 fs_visitor::visit(ir_return *ir)
2055 {
2056 assert(!"FINISHME");
2057 }
2058
2059 void
2060 fs_visitor::visit(ir_function *ir)
2061 {
2062 /* Ignore function bodies other than main() -- we shouldn't see calls to
2063 * them since they should all be inlined before we get to ir_to_mesa.
2064 */
2065 if (strcmp(ir->name, "main") == 0) {
2066 const ir_function_signature *sig;
2067 exec_list empty;
2068
2069 sig = ir->matching_signature(&empty);
2070
2071 assert(sig);
2072
2073 foreach_list(node, &sig->body) {
2074 ir_instruction *ir = (ir_instruction *)node;
2075 this->base_ir = ir;
2076
2077 ir->accept(this);
2078 }
2079 }
2080 }
2081
2082 void
2083 fs_visitor::visit(ir_function_signature *ir)
2084 {
2085 assert(!"not reached");
2086 (void)ir;
2087 }
2088
2089 void
2090 fs_visitor::visit(ir_emit_vertex *)
2091 {
2092 assert(!"not reached");
2093 }
2094
2095 void
2096 fs_visitor::visit(ir_end_primitive *)
2097 {
2098 assert(!"not reached");
2099 }
2100
2101 fs_inst *
2102 fs_visitor::emit(fs_inst inst)
2103 {
2104 fs_inst *list_inst = new(mem_ctx) fs_inst;
2105 *list_inst = inst;
2106 emit(list_inst);
2107 return list_inst;
2108 }
2109
2110 fs_inst *
2111 fs_visitor::emit(fs_inst *inst)
2112 {
2113 if (force_uncompressed_stack > 0)
2114 inst->force_uncompressed = true;
2115 else if (force_sechalf_stack > 0)
2116 inst->force_sechalf = true;
2117
2118 inst->annotation = this->current_annotation;
2119 inst->ir = this->base_ir;
2120
2121 this->instructions.push_tail(inst);
2122
2123 return inst;
2124 }
2125
2126 void
2127 fs_visitor::emit(exec_list list)
2128 {
2129 foreach_list_safe(node, &list) {
2130 fs_inst *inst = (fs_inst *)node;
2131 inst->remove();
2132 emit(inst);
2133 }
2134 }
2135
2136 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2137 void
2138 fs_visitor::emit_dummy_fs()
2139 {
2140 int reg_width = dispatch_width / 8;
2141
2142 /* Everyone's favorite color. */
2143 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2144 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2145 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2146 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2147
2148 fs_inst *write;
2149 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2150 write->base_mrf = 2;
2151 write->mlen = 4 * reg_width;
2152 write->eot = true;
2153 }
2154
2155 /* The register location here is relative to the start of the URB
2156 * data. It will get adjusted to be a real location before
2157 * generate_code() time.
2158 */
2159 struct brw_reg
2160 fs_visitor::interp_reg(int location, int channel)
2161 {
2162 int regnr = urb_setup[location] * 2 + channel / 2;
2163 int stride = (channel & 1) * 4;
2164
2165 assert(urb_setup[location] != -1);
2166
2167 return brw_vec1_grf(regnr, stride);
2168 }
2169
2170 /** Emits the interpolation for the varying inputs. */
2171 void
2172 fs_visitor::emit_interpolation_setup_gen4()
2173 {
2174 this->current_annotation = "compute pixel centers";
2175 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2176 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2177 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2178 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2179
2180 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2181 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2182
2183 this->current_annotation = "compute pixel deltas from v0";
2184 if (brw->has_pln) {
2185 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2186 fs_reg(this, glsl_type::vec2_type);
2187 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2188 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2189 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2190 } else {
2191 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2192 fs_reg(this, glsl_type::float_type);
2193 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2194 fs_reg(this, glsl_type::float_type);
2195 }
2196 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2197 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2198 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2199 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2200
2201 this->current_annotation = "compute pos.w and 1/pos.w";
2202 /* Compute wpos.w. It's always in our setup, since it's needed to
2203 * interpolate the other attributes.
2204 */
2205 this->wpos_w = fs_reg(this, glsl_type::float_type);
2206 emit(FS_OPCODE_LINTERP, wpos_w,
2207 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2208 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2209 interp_reg(VARYING_SLOT_POS, 3));
2210 /* Compute the pixel 1/W value from wpos.w. */
2211 this->pixel_w = fs_reg(this, glsl_type::float_type);
2212 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2213 this->current_annotation = NULL;
2214 }
2215
2216 /** Emits the interpolation for the varying inputs. */
2217 void
2218 fs_visitor::emit_interpolation_setup_gen6()
2219 {
2220 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2221
2222 /* If the pixel centers end up used, the setup is the same as for gen4. */
2223 this->current_annotation = "compute pixel centers";
2224 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2225 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2226 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2227 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2228 emit(ADD(int_pixel_x,
2229 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2230 fs_reg(brw_imm_v(0x10101010))));
2231 emit(ADD(int_pixel_y,
2232 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2233 fs_reg(brw_imm_v(0x11001100))));
2234
2235 /* As of gen6, we can no longer mix float and int sources. We have
2236 * to turn the integer pixel centers into floats for their actual
2237 * use.
2238 */
2239 this->pixel_x = fs_reg(this, glsl_type::float_type);
2240 this->pixel_y = fs_reg(this, glsl_type::float_type);
2241 emit(MOV(this->pixel_x, int_pixel_x));
2242 emit(MOV(this->pixel_y, int_pixel_y));
2243
2244 this->current_annotation = "compute pos.w";
2245 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2246 this->wpos_w = fs_reg(this, glsl_type::float_type);
2247 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2248
2249 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2250 uint8_t reg = c->barycentric_coord_reg[i];
2251 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2252 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2253 }
2254
2255 this->current_annotation = NULL;
2256 }
2257
2258 void
2259 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2260 {
2261 int reg_width = dispatch_width / 8;
2262 fs_inst *inst;
2263 fs_reg color = outputs[target];
2264 fs_reg mrf;
2265
2266 /* If there's no color data to be written, skip it. */
2267 if (color.file == BAD_FILE)
2268 return;
2269
2270 color.reg_offset += index;
2271
2272 if (dispatch_width == 8 || brw->gen >= 6) {
2273 /* SIMD8 write looks like:
2274 * m + 0: r0
2275 * m + 1: r1
2276 * m + 2: g0
2277 * m + 3: g1
2278 *
2279 * gen6 SIMD16 DP write looks like:
2280 * m + 0: r0
2281 * m + 1: r1
2282 * m + 2: g0
2283 * m + 3: g1
2284 * m + 4: b0
2285 * m + 5: b1
2286 * m + 6: a0
2287 * m + 7: a1
2288 */
2289 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2290 color.type),
2291 color));
2292 inst->saturate = c->key.clamp_fragment_color;
2293 } else {
2294 /* pre-gen6 SIMD16 single source DP write looks like:
2295 * m + 0: r0
2296 * m + 1: g0
2297 * m + 2: b0
2298 * m + 3: a0
2299 * m + 4: r1
2300 * m + 5: g1
2301 * m + 6: b1
2302 * m + 7: a1
2303 */
2304 if (brw->has_compr4) {
2305 /* By setting the high bit of the MRF register number, we
2306 * indicate that we want COMPR4 mode - instead of doing the
2307 * usual destination + 1 for the second half we get
2308 * destination + 4.
2309 */
2310 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2311 color.type),
2312 color));
2313 inst->saturate = c->key.clamp_fragment_color;
2314 } else {
2315 push_force_uncompressed();
2316 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2317 color));
2318 inst->saturate = c->key.clamp_fragment_color;
2319 pop_force_uncompressed();
2320
2321 push_force_sechalf();
2322 color.sechalf = true;
2323 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2324 color));
2325 inst->saturate = c->key.clamp_fragment_color;
2326 pop_force_sechalf();
2327 color.sechalf = false;
2328 }
2329 }
2330 }
2331
2332 void
2333 fs_visitor::emit_fb_writes()
2334 {
2335 this->current_annotation = "FB write header";
2336 bool header_present = true;
2337 /* We can potentially have a message length of up to 15, so we have to set
2338 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2339 */
2340 int base_mrf = 1;
2341 int nr = base_mrf;
2342 int reg_width = dispatch_width / 8;
2343 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2344 bool src0_alpha_to_render_target = false;
2345
2346 if (dispatch_width == 16 && do_dual_src) {
2347 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2348 do_dual_src = false;
2349 }
2350
2351 /* From the Sandy Bridge PRM, volume 4, page 198:
2352 *
2353 * "Dispatched Pixel Enables. One bit per pixel indicating
2354 * which pixels were originally enabled when the thread was
2355 * dispatched. This field is only required for the end-of-
2356 * thread message and on all dual-source messages."
2357 */
2358 if (brw->gen >= 6 &&
2359 !this->fp->UsesKill &&
2360 !do_dual_src &&
2361 c->key.nr_color_regions == 1) {
2362 header_present = false;
2363 }
2364
2365 if (header_present) {
2366 src0_alpha_to_render_target = brw->gen >= 6 &&
2367 !do_dual_src &&
2368 c->key.replicate_alpha;
2369 /* m2, m3 header */
2370 nr += 2;
2371 }
2372
2373 if (c->aa_dest_stencil_reg) {
2374 push_force_uncompressed();
2375 emit(MOV(fs_reg(MRF, nr++),
2376 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2377 pop_force_uncompressed();
2378 }
2379
2380 /* Reserve space for color. It'll be filled in per MRT below. */
2381 int color_mrf = nr;
2382 nr += 4 * reg_width;
2383 if (do_dual_src)
2384 nr += 4;
2385 if (src0_alpha_to_render_target)
2386 nr += reg_width;
2387
2388 if (c->source_depth_to_render_target) {
2389 if (brw->gen == 6 && dispatch_width == 16) {
2390 /* For outputting oDepth on gen6, SIMD8 writes have to be
2391 * used. This would require 8-wide moves of each half to
2392 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2393 * Just bail on doing so for now.
2394 */
2395 fail("Missing support for simd16 depth writes on gen6\n");
2396 }
2397
2398 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2399 /* Hand over gl_FragDepth. */
2400 assert(this->frag_depth.file != BAD_FILE);
2401 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2402 } else {
2403 /* Pass through the payload depth. */
2404 emit(MOV(fs_reg(MRF, nr),
2405 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2406 }
2407 nr += reg_width;
2408 }
2409
2410 if (c->dest_depth_reg) {
2411 emit(MOV(fs_reg(MRF, nr),
2412 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2413 nr += reg_width;
2414 }
2415
2416 if (do_dual_src) {
2417 fs_reg src0 = this->outputs[0];
2418 fs_reg src1 = this->dual_src_output;
2419
2420 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2421 "FB write src0");
2422 for (int i = 0; i < 4; i++) {
2423 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2424 src0.reg_offset++;
2425 inst->saturate = c->key.clamp_fragment_color;
2426 }
2427
2428 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2429 "FB write src1");
2430 for (int i = 0; i < 4; i++) {
2431 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2432 src1));
2433 src1.reg_offset++;
2434 inst->saturate = c->key.clamp_fragment_color;
2435 }
2436
2437 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2438 emit_shader_time_end();
2439
2440 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2441 inst->target = 0;
2442 inst->base_mrf = base_mrf;
2443 inst->mlen = nr - base_mrf;
2444 inst->eot = true;
2445 inst->header_present = header_present;
2446
2447 c->prog_data.dual_src_blend = true;
2448 this->current_annotation = NULL;
2449 return;
2450 }
2451
2452 for (int target = 0; target < c->key.nr_color_regions; target++) {
2453 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2454 "FB write target %d",
2455 target);
2456 /* If src0_alpha_to_render_target is true, include source zero alpha
2457 * data in RenderTargetWrite message for targets > 0.
2458 */
2459 int write_color_mrf = color_mrf;
2460 if (src0_alpha_to_render_target && target != 0) {
2461 fs_inst *inst;
2462 fs_reg color = outputs[0];
2463 color.reg_offset += 3;
2464
2465 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2466 color));
2467 inst->saturate = c->key.clamp_fragment_color;
2468 write_color_mrf = color_mrf + reg_width;
2469 }
2470
2471 for (unsigned i = 0; i < this->output_components[target]; i++)
2472 emit_color_write(target, i, write_color_mrf);
2473
2474 bool eot = false;
2475 if (target == c->key.nr_color_regions - 1) {
2476 eot = true;
2477
2478 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2479 emit_shader_time_end();
2480 }
2481
2482 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2483 inst->target = target;
2484 inst->base_mrf = base_mrf;
2485 if (src0_alpha_to_render_target && target == 0)
2486 inst->mlen = nr - base_mrf - reg_width;
2487 else
2488 inst->mlen = nr - base_mrf;
2489 inst->eot = eot;
2490 inst->header_present = header_present;
2491 }
2492
2493 if (c->key.nr_color_regions == 0) {
2494 /* Even if there's no color buffers enabled, we still need to send
2495 * alpha out the pipeline to our null renderbuffer to support
2496 * alpha-testing, alpha-to-coverage, and so on.
2497 */
2498 emit_color_write(0, 3, color_mrf);
2499
2500 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2501 emit_shader_time_end();
2502
2503 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2504 inst->base_mrf = base_mrf;
2505 inst->mlen = nr - base_mrf;
2506 inst->eot = true;
2507 inst->header_present = header_present;
2508 }
2509
2510 this->current_annotation = NULL;
2511 }
2512
2513 void
2514 fs_visitor::resolve_ud_negate(fs_reg *reg)
2515 {
2516 if (reg->type != BRW_REGISTER_TYPE_UD ||
2517 !reg->negate)
2518 return;
2519
2520 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2521 emit(MOV(temp, *reg));
2522 *reg = temp;
2523 }
2524
2525 void
2526 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2527 {
2528 if (rvalue->type != glsl_type::bool_type)
2529 return;
2530
2531 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2532 emit(AND(temp, *reg, fs_reg(1)));
2533 *reg = temp;
2534 }
2535
2536 fs_visitor::fs_visitor(struct brw_context *brw,
2537 struct brw_wm_compile *c,
2538 struct gl_shader_program *shader_prog,
2539 struct gl_fragment_program *fp,
2540 unsigned dispatch_width)
2541 : dispatch_width(dispatch_width)
2542 {
2543 this->c = c;
2544 this->brw = brw;
2545 this->fp = fp;
2546 this->shader_prog = shader_prog;
2547 this->ctx = &brw->ctx;
2548 this->mem_ctx = ralloc_context(NULL);
2549 if (shader_prog)
2550 shader = (struct brw_shader *)
2551 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2552 else
2553 shader = NULL;
2554 this->failed = false;
2555 this->variable_ht = hash_table_ctor(0,
2556 hash_table_pointer_hash,
2557 hash_table_pointer_compare);
2558
2559 memset(this->outputs, 0, sizeof(this->outputs));
2560 memset(this->output_components, 0, sizeof(this->output_components));
2561 this->first_non_payload_grf = 0;
2562 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2563
2564 this->current_annotation = NULL;
2565 this->base_ir = NULL;
2566
2567 this->virtual_grf_sizes = NULL;
2568 this->virtual_grf_count = 0;
2569 this->virtual_grf_array_size = 0;
2570 this->virtual_grf_start = NULL;
2571 this->virtual_grf_end = NULL;
2572 this->live_intervals_valid = false;
2573
2574 this->params_remap = NULL;
2575 this->nr_params_remap = 0;
2576
2577 this->force_uncompressed_stack = 0;
2578 this->force_sechalf_stack = 0;
2579
2580 memset(&this->param_size, 0, sizeof(this->param_size));
2581 }
2582
2583 fs_visitor::~fs_visitor()
2584 {
2585 ralloc_free(this->mem_ctx);
2586 hash_table_dtor(this->variable_ht);
2587 }