2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "util/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation();
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 assert(stage
== MESA_SHADER_FRAGMENT
);
81 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
82 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
83 this->outputs
[i
] = *reg
;
84 this->output_components
[i
] = 4;
86 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
87 this->frag_depth
= *reg
;
88 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
89 this->sample_mask
= *reg
;
91 /* gl_FragData or a user-defined FS output */
92 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
93 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
96 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
97 : ir
->type
->vector_elements
;
99 /* General color output. */
100 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
101 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
102 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
103 this->output_components
[output
] = vector_elements
;
106 } else if (ir
->data
.mode
== ir_var_uniform
) {
107 int param_index
= uniforms
;
109 /* Thanks to the lower_ubo_reference pass, we will see only
110 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
111 * variables, so no need for them to be in variable_ht.
113 * Some uniforms, such as samplers and atomic counters, have no actual
114 * storage, so we should ignore them.
116 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
119 if (dispatch_width
== 16) {
120 if (!variable_storage(ir
)) {
121 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
126 param_size
[param_index
] = type_size(ir
->type
);
127 if (!strncmp(ir
->name
, "gl_", 3)) {
128 setup_builtin_uniform_values(ir
);
130 setup_uniform_values(ir
);
133 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
134 reg
->type
= brw_type_for_base_type(ir
->type
);
136 } else if (ir
->data
.mode
== ir_var_system_value
) {
137 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
138 reg
= emit_samplepos_setup();
139 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
140 reg
= emit_sampleid_setup(ir
);
141 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
142 assert(brw
->gen
>= 7);
144 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
145 BRW_REGISTER_TYPE_D
));
150 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
152 hash_table_insert(this->variable_ht
, reg
, ir
);
156 fs_visitor::visit(ir_dereference_variable
*ir
)
158 fs_reg
*reg
= variable_storage(ir
->var
);
161 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
162 this->result
= fs_reg(reg_null_d
);
169 fs_visitor::visit(ir_dereference_record
*ir
)
171 const glsl_type
*struct_type
= ir
->record
->type
;
173 ir
->record
->accept(this);
175 unsigned int off
= 0;
176 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
177 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
179 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
181 this->result
= offset(this->result
, off
);
182 this->result
.type
= brw_type_for_base_type(ir
->type
);
186 fs_visitor::visit(ir_dereference_array
*ir
)
188 ir_constant
*constant_index
;
190 int element_size
= type_size(ir
->type
);
192 constant_index
= ir
->array_index
->as_constant();
194 ir
->array
->accept(this);
196 src
.type
= brw_type_for_base_type(ir
->type
);
198 if (constant_index
) {
199 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
200 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
202 /* Variable index array dereference. We attach the variable index
203 * component to the reg as a pointer to a register containing the
204 * offset. Currently only uniform arrays are supported in this patch,
205 * and that reladdr pointer is resolved by
206 * move_uniform_array_access_to_pull_constants(). All other array types
207 * are lowered by lower_variable_index_to_cond_assign().
209 ir
->array_index
->accept(this);
212 index_reg
= fs_reg(this, glsl_type::int_type
);
213 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
216 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
219 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
220 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
226 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
230 !x
.is_valid_3src() ||
231 !y
.is_valid_3src() ||
232 !a
.is_valid_3src()) {
233 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
234 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
235 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
236 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
238 emit(MUL(y_times_a
, y
, a
));
240 fs_reg negative_a
= a
;
241 negative_a
.negate
= !a
.negate
;
242 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
243 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
245 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
247 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
248 * we need to reorder the operands.
250 emit(LRP(dst
, a
, y
, x
));
255 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
256 const fs_reg
&src0
, const fs_reg
&src1
)
261 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
262 inst
->conditional_mod
= conditionalmod
;
264 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
266 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
267 inst
->predicate
= BRW_PREDICATE_NORMAL
;
272 fs_visitor::try_emit_saturate(ir_expression
*ir
)
274 if (ir
->operation
!= ir_unop_saturate
)
277 ir_rvalue
*sat_val
= ir
->operands
[0];
279 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
281 sat_val
->accept(this);
282 fs_reg src
= this->result
;
284 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
286 /* If the last instruction from our accept() generated our
287 * src, just set the saturate flag instead of emmitting a separate mov.
289 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
290 if (modify
&& modify
->regs_written
== 1 && modify
->can_do_saturate()) {
291 modify
->saturate
= true;
300 fs_visitor::try_emit_mad(ir_expression
*ir
)
302 /* 3-src instructions were introduced in gen6. */
306 /* MAD can only handle floating-point data. */
307 if (ir
->type
!= glsl_type::float_type
)
310 ir_rvalue
*nonmul
= ir
->operands
[1];
311 ir_expression
*mul
= ir
->operands
[0]->as_expression();
313 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
314 nonmul
= ir
->operands
[0];
315 mul
= ir
->operands
[1]->as_expression();
317 if (!mul
|| mul
->operation
!= ir_binop_mul
)
321 if (nonmul
->as_constant() ||
322 mul
->operands
[0]->as_constant() ||
323 mul
->operands
[1]->as_constant())
326 nonmul
->accept(this);
327 fs_reg src0
= this->result
;
329 mul
->operands
[0]->accept(this);
330 fs_reg src1
= this->result
;
332 mul
->operands
[1]->accept(this);
333 fs_reg src2
= this->result
;
335 this->result
= fs_reg(this, ir
->type
);
336 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
342 pack_pixel_offset(float x
)
344 /* Clamp upper end of the range to +7/16. See explanation in non-constant
345 * offset case below. */
346 int n
= MIN2((int)(x
* 16), 7);
351 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
353 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
354 * 8 channels at a time, same as the barycentric coords presented in
355 * the FS payload. this requires a bit of extra work to support.
357 no16("interpolate_at_* not yet supported in SIMD16 mode.");
359 assert(stage
== MESA_SHADER_FRAGMENT
);
360 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
362 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
363 ir_swizzle
* swiz
= NULL
;
365 /* the api does not allow a swizzle here, but the varying packing code
366 * may have pushed one into here.
368 swiz
= ir
->operands
[0]->as_swizzle();
370 deref
= swiz
->val
->as_dereference();
373 ir_variable
* var
= deref
->variable_referenced();
376 /* 1. collect interpolation factors */
378 fs_reg dst_x
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
379 fs_reg dst_y
= offset(dst_x
, 1);
381 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
382 * even when there is no payload. in the per-slot offset case, we'll replace this with
383 * the proper source data. */
384 fs_reg src
= fs_reg(this, glsl_type::float_type
);
385 int mlen
= 1; /* one reg unless overriden */
386 int reg_width
= dispatch_width
/ 8;
389 switch (ir
->operation
) {
390 case ir_unop_interpolate_at_centroid
:
391 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
394 case ir_binop_interpolate_at_sample
: {
395 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
396 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
398 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
399 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
403 case ir_binop_interpolate_at_offset
: {
404 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
406 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
407 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
408 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
411 /* pack the operands: hw wants offsets as 4 bit signed ints */
412 ir
->operands
[1]->accept(this);
413 src
= fs_reg(this, glsl_type::ivec2_type
);
415 for (int i
= 0; i
< 2; i
++) {
416 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
417 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
418 emit(MOV(src2
, temp
)); /* float to int */
420 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
421 * that we support a maximum offset of +0.5, which isn't representable
422 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
423 * which is the opposite of what the shader author wanted.
425 * This is legal due to ARB_gpu_shader5's quantization rules:
427 * "Not all values of <offset> may be supported; x and y offsets may
428 * be rounded to fixed-point values with the number of fraction bits
429 * given by the implementation-dependent constant
430 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
433 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
434 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
436 src2
= offset(src2
, 1);
437 this->result
= offset(this->result
, 1);
440 mlen
= 2 * reg_width
;
441 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
448 unreachable("not reached");
452 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
453 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
454 INTERP_QUALIFIER_NOPERSPECTIVE
;
456 /* 2. emit linterp */
458 fs_reg
res(this, ir
->type
);
461 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
462 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
463 emit(FS_OPCODE_LINTERP
, res
,
465 fs_reg(interp_reg(var
->data
.location
, ch
)));
466 res
= offset(res
, 1);
471 fs_visitor::visit(ir_expression
*ir
)
473 unsigned int operand
;
477 assert(ir
->get_num_operands() <= 3);
479 if (try_emit_saturate(ir
))
482 /* Deal with the real oddball stuff first */
483 switch (ir
->operation
) {
485 if (try_emit_mad(ir
))
489 case ir_unop_interpolate_at_centroid
:
490 case ir_binop_interpolate_at_offset
:
491 case ir_binop_interpolate_at_sample
:
492 emit_interpolate_expression(ir
);
499 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
500 ir
->operands
[operand
]->accept(this);
501 if (this->result
.file
== BAD_FILE
) {
502 fail("Failed to get tree for expression operand:\n");
503 ir
->operands
[operand
]->fprint(stderr
);
504 fprintf(stderr
, "\n");
506 assert(this->result
.is_valid_3src());
507 op
[operand
] = this->result
;
509 /* Matrix expression operands should have been broken down to vector
510 * operations already.
512 assert(!ir
->operands
[operand
]->type
->is_matrix());
513 /* And then those vector operands should have been broken down to scalar.
515 assert(!ir
->operands
[operand
]->type
->is_vector());
518 /* Storage for our result. If our result goes into an assignment, it will
519 * just get copy-propagated out, so no worries.
521 this->result
= fs_reg(this, ir
->type
);
523 switch (ir
->operation
) {
524 case ir_unop_logic_not
:
525 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
526 emit(NOT(this->result
, op
[0]));
528 emit(XOR(this->result
, op
[0], fs_reg(1)));
532 op
[0].negate
= !op
[0].negate
;
533 emit(MOV(this->result
, op
[0]));
537 op
[0].negate
= false;
538 emit(MOV(this->result
, op
[0]));
541 if (ir
->type
->is_float()) {
542 /* AND(val, 0x80000000) gives the sign bit.
544 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
547 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
549 op
[0].type
= BRW_REGISTER_TYPE_UD
;
550 this->result
.type
= BRW_REGISTER_TYPE_UD
;
551 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
553 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
554 inst
->predicate
= BRW_PREDICATE_NORMAL
;
556 this->result
.type
= BRW_REGISTER_TYPE_F
;
558 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
559 * -> non-negative val generates 0x00000000.
560 * Predicated OR sets 1 if val is positive.
562 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
564 emit(ASR(this->result
, op
[0], fs_reg(31)));
566 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
567 inst
->predicate
= BRW_PREDICATE_NORMAL
;
571 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
575 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
578 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
582 unreachable("not reached: should be handled by ir_explog_to_explog2");
584 case ir_unop_sin_reduced
:
585 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
588 case ir_unop_cos_reduced
:
589 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
593 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
595 case ir_unop_dFdx_coarse
:
596 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
598 case ir_unop_dFdx_fine
:
599 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
602 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
604 case ir_unop_dFdy_coarse
:
605 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
607 case ir_unop_dFdy_fine
:
608 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
612 emit(ADD(this->result
, op
[0], op
[1]));
615 unreachable("not reached: should be handled by ir_sub_to_add_neg");
618 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
619 /* For integer multiplication, the MUL uses the low 16 bits
620 * of one of the operands (src0 on gen6, src1 on gen7). The
621 * MACH accumulates in the contribution of the upper 16 bits
624 if (ir
->operands
[0]->is_uint16_constant()) {
626 emit(MUL(this->result
, op
[0], op
[1]));
628 emit(MUL(this->result
, op
[1], op
[0]));
629 } else if (ir
->operands
[1]->is_uint16_constant()) {
631 emit(MUL(this->result
, op
[1], op
[0]));
633 emit(MUL(this->result
, op
[0], op
[1]));
636 no16("SIMD16 explicit accumulator operands unsupported\n");
638 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
640 emit(MUL(acc
, op
[0], op
[1]));
641 emit(MACH(reg_null_d
, op
[0], op
[1]));
642 emit(MOV(this->result
, fs_reg(acc
)));
645 emit(MUL(this->result
, op
[0], op
[1]));
648 case ir_binop_imul_high
: {
650 no16("SIMD16 explicit accumulator operands unsupported\n");
652 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
654 emit(MUL(acc
, op
[0], op
[1]));
655 emit(MACH(this->result
, op
[0], op
[1]));
659 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
660 assert(ir
->type
->is_integer());
661 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
663 case ir_binop_carry
: {
665 no16("SIMD16 explicit accumulator operands unsupported\n");
667 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
669 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
670 emit(MOV(this->result
, fs_reg(acc
)));
673 case ir_binop_borrow
: {
675 no16("SIMD16 explicit accumulator operands unsupported\n");
677 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
679 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
680 emit(MOV(this->result
, fs_reg(acc
)));
684 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
685 assert(ir
->type
->is_integer());
686 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
690 case ir_binop_greater
:
691 case ir_binop_lequal
:
692 case ir_binop_gequal
:
694 case ir_binop_all_equal
:
695 case ir_binop_nequal
:
696 case ir_binop_any_nequal
:
697 if (ctx
->Const
.UniformBooleanTrue
== 1) {
698 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
699 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
702 emit(CMP(this->result
, op
[0], op
[1],
703 brw_conditional_for_comparison(ir
->operation
)));
706 case ir_binop_logic_xor
:
707 emit(XOR(this->result
, op
[0], op
[1]));
710 case ir_binop_logic_or
:
711 emit(OR(this->result
, op
[0], op
[1]));
714 case ir_binop_logic_and
:
715 emit(AND(this->result
, op
[0], op
[1]));
720 unreachable("not reached: should be handled by brw_fs_channel_expressions");
723 unreachable("not reached: should be handled by lower_noise");
725 case ir_quadop_vector
:
726 unreachable("not reached: should be handled by lower_quadop_vector");
728 case ir_binop_vector_extract
:
729 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
731 case ir_triop_vector_insert
:
732 unreachable("not reached: should be handled by lower_vector_insert()");
735 unreachable("not reached: should be handled by ldexp_to_arith()");
738 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
742 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
745 case ir_unop_bitcast_i2f
:
746 case ir_unop_bitcast_u2f
:
747 op
[0].type
= BRW_REGISTER_TYPE_F
;
748 this->result
= op
[0];
751 case ir_unop_bitcast_f2u
:
752 op
[0].type
= BRW_REGISTER_TYPE_UD
;
753 this->result
= op
[0];
756 case ir_unop_bitcast_f2i
:
757 op
[0].type
= BRW_REGISTER_TYPE_D
;
758 this->result
= op
[0];
764 emit(MOV(this->result
, op
[0]));
768 emit(AND(this->result
, op
[0], fs_reg(1)));
771 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
772 op
[0].type
= BRW_REGISTER_TYPE_UD
;
773 this->result
.type
= BRW_REGISTER_TYPE_UD
;
774 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
775 this->result
.type
= BRW_REGISTER_TYPE_F
;
777 temp
= fs_reg(this, glsl_type::int_type
);
778 emit(AND(temp
, op
[0], fs_reg(1)));
779 emit(MOV(this->result
, temp
));
784 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
787 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
791 emit(RNDZ(this->result
, op
[0]));
794 op
[0].negate
= !op
[0].negate
;
795 emit(RNDD(this->result
, op
[0]));
796 this->result
.negate
= true;
799 emit(RNDD(this->result
, op
[0]));
802 emit(FRC(this->result
, op
[0]));
804 case ir_unop_round_even
:
805 emit(RNDE(this->result
, op
[0]));
810 resolve_ud_negate(&op
[0]);
811 resolve_ud_negate(&op
[1]);
812 emit_minmax(ir
->operation
== ir_binop_min
?
813 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
814 this->result
, op
[0], op
[1]);
816 case ir_unop_pack_snorm_2x16
:
817 case ir_unop_pack_snorm_4x8
:
818 case ir_unop_pack_unorm_2x16
:
819 case ir_unop_pack_unorm_4x8
:
820 case ir_unop_unpack_snorm_2x16
:
821 case ir_unop_unpack_snorm_4x8
:
822 case ir_unop_unpack_unorm_2x16
:
823 case ir_unop_unpack_unorm_4x8
:
824 case ir_unop_unpack_half_2x16
:
825 case ir_unop_pack_half_2x16
:
826 unreachable("not reached: should be handled by lower_packing_builtins");
827 case ir_unop_unpack_half_2x16_split_x
:
828 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
830 case ir_unop_unpack_half_2x16_split_y
:
831 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
834 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
837 case ir_unop_bitfield_reverse
:
838 emit(BFREV(this->result
, op
[0]));
840 case ir_unop_bit_count
:
841 emit(CBIT(this->result
, op
[0]));
843 case ir_unop_find_msb
:
844 temp
= fs_reg(this, glsl_type::uint_type
);
845 emit(FBH(temp
, op
[0]));
847 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
848 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
849 * subtract the result from 31 to convert the MSB count into an LSB count.
852 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
853 emit(MOV(this->result
, temp
));
854 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
857 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
858 inst
->predicate
= BRW_PREDICATE_NORMAL
;
860 case ir_unop_find_lsb
:
861 emit(FBL(this->result
, op
[0]));
863 case ir_unop_saturate
:
864 inst
= emit(MOV(this->result
, op
[0]));
865 inst
->saturate
= true;
867 case ir_triop_bitfield_extract
:
868 /* Note that the instruction's argument order is reversed from GLSL
871 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
874 emit(BFI1(this->result
, op
[0], op
[1]));
877 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
879 case ir_quadop_bitfield_insert
:
880 unreachable("not reached: should be handled by "
881 "lower_instructions::bitfield_insert_to_bfm_bfi");
883 case ir_unop_bit_not
:
884 emit(NOT(this->result
, op
[0]));
886 case ir_binop_bit_and
:
887 emit(AND(this->result
, op
[0], op
[1]));
889 case ir_binop_bit_xor
:
890 emit(XOR(this->result
, op
[0], op
[1]));
892 case ir_binop_bit_or
:
893 emit(OR(this->result
, op
[0], op
[1]));
896 case ir_binop_lshift
:
897 emit(SHL(this->result
, op
[0], op
[1]));
900 case ir_binop_rshift
:
901 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
902 emit(ASR(this->result
, op
[0], op
[1]));
904 emit(SHR(this->result
, op
[0], op
[1]));
906 case ir_binop_pack_half_2x16_split
:
907 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
909 case ir_binop_ubo_load
: {
910 /* This IR node takes a constant uniform block and a constant or
911 * variable byte offset within the block and loads a vector from that.
913 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
914 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
917 if (const_uniform_block
) {
918 /* The block index is a constant, so just emit the binding table entry
921 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
922 const_uniform_block
->value
.u
[0]);
924 /* The block index is not a constant. Evaluate the index expression
925 * per-channel and add the base UBO index; the generator will select
926 * a value from any live channel.
928 surf_index
= fs_reg(this, glsl_type::uint_type
);
929 emit(ADD(surf_index
, op
[0],
930 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
931 ->force_writemask_all
= true;
933 /* Assume this may touch any UBO. It would be nice to provide
934 * a tighter bound, but the array information is already lowered away.
936 brw_mark_surface_used(prog_data
,
937 stage_prog_data
->binding_table
.ubo_start
+
938 shader_prog
->NumUniformBlocks
- 1);
942 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
943 packed_consts
.type
= result
.type
;
945 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
946 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
947 packed_consts
, surf_index
, const_offset_reg
));
949 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
950 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
952 /* The std140 packing rules don't allow vectors to cross 16-byte
953 * boundaries, and a reg is 32 bytes.
955 assert(packed_consts
.subreg_offset
< 32);
957 /* UBO bools are any nonzero value. We consider bools to be
958 * values with the low bit set to 1. Convert them using CMP.
960 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
961 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
963 emit(MOV(result
, packed_consts
));
966 result
= offset(result
, 1);
969 /* Turn the byte offset into a dword offset. */
970 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
971 emit(SHR(base_offset
, op
[1], fs_reg(2)));
973 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
974 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
977 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
978 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
980 result
= offset(result
, 1);
984 result
.reg_offset
= 0;
989 /* Note that the instruction's argument order is reversed from GLSL
992 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
996 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1000 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1001 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
1002 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1005 case ir_unop_interpolate_at_centroid
:
1006 case ir_binop_interpolate_at_offset
:
1007 case ir_binop_interpolate_at_sample
:
1008 unreachable("already handled above");
1014 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1015 const glsl_type
*type
, bool predicated
)
1017 switch (type
->base_type
) {
1018 case GLSL_TYPE_FLOAT
:
1019 case GLSL_TYPE_UINT
:
1021 case GLSL_TYPE_BOOL
:
1022 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1023 l
.type
= brw_type_for_base_type(type
);
1024 r
.type
= brw_type_for_base_type(type
);
1026 if (predicated
|| !l
.equals(r
)) {
1027 fs_inst
*inst
= emit(MOV(l
, r
));
1028 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1035 case GLSL_TYPE_ARRAY
:
1036 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1037 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1041 case GLSL_TYPE_STRUCT
:
1042 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1043 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1048 case GLSL_TYPE_SAMPLER
:
1049 case GLSL_TYPE_IMAGE
:
1050 case GLSL_TYPE_ATOMIC_UINT
:
1053 case GLSL_TYPE_VOID
:
1054 case GLSL_TYPE_ERROR
:
1055 case GLSL_TYPE_INTERFACE
:
1056 unreachable("not reached");
1060 /* If the RHS processing resulted in an instruction generating a
1061 * temporary value, and it would be easy to rewrite the instruction to
1062 * generate its result right into the LHS instead, do so. This ends
1063 * up reliably removing instructions where it can be tricky to do so
1064 * later without real UD chain information.
1067 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1070 fs_inst
*pre_rhs_inst
,
1071 fs_inst
*last_rhs_inst
)
1073 /* Only attempt if we're doing a direct assignment. */
1074 if (ir
->condition
||
1075 !(ir
->lhs
->type
->is_scalar() ||
1076 (ir
->lhs
->type
->is_vector() &&
1077 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1080 /* Make sure the last instruction generated our source reg. */
1081 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1087 /* If last_rhs_inst wrote a different number of components than our LHS,
1088 * we can't safely rewrite it.
1090 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
1093 /* Success! Rewrite the instruction. */
1100 fs_visitor::visit(ir_assignment
*ir
)
1105 /* FINISHME: arrays on the lhs */
1106 ir
->lhs
->accept(this);
1109 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1111 ir
->rhs
->accept(this);
1114 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1116 assert(l
.file
!= BAD_FILE
);
1117 assert(r
.file
!= BAD_FILE
);
1119 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1122 if (ir
->condition
) {
1123 emit_bool_to_cond_code(ir
->condition
);
1126 if (ir
->lhs
->type
->is_scalar() ||
1127 ir
->lhs
->type
->is_vector()) {
1128 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1129 if (ir
->write_mask
& (1 << i
)) {
1130 inst
= emit(MOV(l
, r
));
1132 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1138 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1143 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1144 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
,
1149 bool simd16
= false;
1155 if (shadow_c
.file
!= BAD_FILE
) {
1156 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1157 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1158 coordinate
= offset(coordinate
, 1);
1161 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1162 * the unused slots must be zeroed.
1164 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1165 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1169 if (ir
->op
== ir_tex
) {
1170 /* There's no plain shadow compare message, so we use shadow
1171 * compare with a bias of 0.0.
1173 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1175 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
1176 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1179 unreachable("Should not get here.");
1182 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1184 } else if (ir
->op
== ir_tex
) {
1185 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1186 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1187 coordinate
= offset(coordinate
, 1);
1189 /* zero the others. */
1190 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
1191 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1193 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1195 } else if (ir
->op
== ir_txd
) {
1198 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1199 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1200 coordinate
= offset(coordinate
, 1);
1202 /* the slots for u and v are always present, but r is optional */
1203 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
1206 * dPdx = dudx, dvdx, drdx
1207 * dPdy = dudy, dvdy, drdy
1209 * 1-arg: Does not exist.
1211 * 2-arg: dudx dvdx dudy dvdy
1212 * dPdx.x dPdx.y dPdy.x dPdy.y
1215 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1216 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1217 * m5 m6 m7 m8 m9 m10
1219 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1220 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1221 dPdx
= offset(dPdx
, 1);
1223 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1225 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1226 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1227 dPdy
= offset(dPdy
, 1);
1229 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1230 } else if (ir
->op
== ir_txs
) {
1231 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1233 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1236 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1237 * instructions. We'll need to do SIMD16 here.
1240 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1242 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1243 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1245 coordinate
= offset(coordinate
, 1);
1248 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1249 * be necessary for TXF (ld), but seems wise to do for all messages.
1251 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1252 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1255 /* lod/bias appears after u/v/r. */
1258 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1261 /* The unused upper half. */
1266 /* Now, since we're doing simd16, the return is 2 interleaved
1267 * vec4s where the odd-indexed ones are junk. We'll need to move
1268 * this weirdness around to the expected layout.
1271 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1273 brw_type_for_base_type(ir
->type
) :
1274 BRW_REGISTER_TYPE_F
));
1280 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1281 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1282 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1283 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1284 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1285 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1287 unreachable("not reached");
1290 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1291 inst
->base_mrf
= base_mrf
;
1293 inst
->header_present
= true;
1294 inst
->regs_written
= simd16
? 8 : 4;
1297 for (int i
= 0; i
< 4; i
++) {
1298 emit(MOV(orig_dst
, dst
));
1299 orig_dst
= offset(orig_dst
, 1);
1300 dst
= offset(dst
, 2);
1307 /* gen5's sampler has slots for u, v, r, array index, then optional
1308 * parameters like shadow comparitor or LOD bias. If optional
1309 * parameters aren't present, those base slots are optional and don't
1310 * need to be included in the message.
1312 * We don't fill in the unnecessary slots regardless, which may look
1313 * surprising in the disassembly.
1316 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1317 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1318 fs_reg sample_index
, uint32_t sampler
)
1322 int reg_width
= dispatch_width
/ 8;
1323 bool header_present
= false;
1324 const int vector_elements
=
1325 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1328 /* The offsets set up by the ir_texture visitor are in the
1329 * m1 header, so we can't go headerless.
1331 header_present
= true;
1336 for (int i
= 0; i
< vector_elements
; i
++) {
1337 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1339 coordinate
= offset(coordinate
, 1);
1341 mlen
+= vector_elements
* reg_width
;
1343 if (shadow_c
.file
!= BAD_FILE
) {
1344 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1346 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1353 opcode
= SHADER_OPCODE_TEX
;
1356 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1357 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1360 opcode
= FS_OPCODE_TXB
;
1363 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1364 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1367 opcode
= SHADER_OPCODE_TXL
;
1370 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1374 * dPdx = dudx, dvdx, drdx
1375 * dPdy = dudy, dvdy, drdy
1377 * Load up these values:
1378 * - dudx dudy dvdx dvdy drdx drdy
1379 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1381 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1382 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1383 lod
= offset(lod
, 1);
1386 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1387 lod2
= offset(lod2
, 1);
1391 opcode
= SHADER_OPCODE_TXD
;
1395 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1398 opcode
= SHADER_OPCODE_TXS
;
1400 case ir_query_levels
:
1401 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1404 opcode
= SHADER_OPCODE_TXS
;
1407 mlen
= header_present
+ 4 * reg_width
;
1408 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1410 opcode
= SHADER_OPCODE_TXF
;
1413 mlen
= header_present
+ 4 * reg_width
;
1416 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1418 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1421 opcode
= SHADER_OPCODE_TXF_CMS
;
1424 opcode
= SHADER_OPCODE_LOD
;
1427 opcode
= SHADER_OPCODE_TG4
;
1430 unreachable("not reached");
1433 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1434 inst
->base_mrf
= base_mrf
;
1436 inst
->header_present
= header_present
;
1437 inst
->regs_written
= 4;
1439 if (mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1440 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1441 " disallowed by hardware\n");
1448 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1450 if (brw
->gen
< 8 && !brw
->is_haswell
)
1453 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1457 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1458 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1459 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
)
1461 int reg_width
= dispatch_width
/ 8;
1462 bool header_present
= false;
1464 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1465 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1466 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1470 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
) ||
1471 is_high_sampler(brw
, sampler
)) {
1472 /* For general texture offsets (no txf workaround), we need a header to
1473 * put them in. Note that for SIMD16 we're making space for two actual
1474 * hardware registers here, so the emit will have to fix up for this.
1476 * * ir4_tg4 needs to place its channel select in the header,
1477 * for interaction with ARB_texture_swizzle
1479 * The sampler index is only 4-bits, so for larger sampler numbers we
1480 * need to offset the Sampler State Pointer in the header.
1482 header_present
= true;
1483 sources
[length
] = reg_undef
;
1487 if (shadow_c
.file
!= BAD_FILE
) {
1488 emit(MOV(sources
[length
], shadow_c
));
1492 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
1493 bool coordinate_done
= false;
1495 /* Set up the LOD info */
1501 emit(MOV(sources
[length
], lod
));
1505 emit(MOV(sources
[length
], lod
));
1509 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1511 /* Load dPdx and the coordinate together:
1512 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1514 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1515 emit(MOV(sources
[length
], coordinate
));
1516 coordinate
= offset(coordinate
, 1);
1519 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1520 * only derivatives for (u, v, r).
1522 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1523 emit(MOV(sources
[length
], lod
));
1524 lod
= offset(lod
, 1);
1527 emit(MOV(sources
[length
], lod2
));
1528 lod2
= offset(lod2
, 1);
1533 coordinate_done
= true;
1537 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1540 case ir_query_levels
:
1541 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1545 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1546 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1547 coordinate
= offset(coordinate
, 1);
1550 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1553 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1554 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1555 coordinate
= offset(coordinate
, 1);
1559 coordinate_done
= true;
1562 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1565 /* data from the multisample control surface */
1566 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1569 /* there is no offsetting for this message; just copy in the integer
1570 * texture coordinates
1572 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1573 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1574 coordinate
= offset(coordinate
, 1);
1578 coordinate_done
= true;
1581 if (has_nonconstant_offset
) {
1582 if (shadow_c
.file
!= BAD_FILE
)
1583 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1585 /* More crazy intermixing */
1586 ir
->offset
->accept(this);
1587 fs_reg offset_value
= this->result
;
1589 for (int i
= 0; i
< 2; i
++) { /* u, v */
1590 emit(MOV(sources
[length
], coordinate
));
1591 coordinate
= offset(coordinate
, 1);
1595 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1596 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1597 offset_value
= offset(offset_value
, 1);
1601 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1602 emit(MOV(sources
[length
], coordinate
));
1603 coordinate
= offset(coordinate
, 1);
1607 coordinate_done
= true;
1612 /* Set up the coordinate (except for cases where it was done above) */
1613 if (ir
->coordinate
&& !coordinate_done
) {
1614 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1615 emit(MOV(sources
[length
], coordinate
));
1616 coordinate
= offset(coordinate
, 1);
1621 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1622 BRW_REGISTER_TYPE_F
);
1623 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1625 /* Generate the SEND */
1628 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1629 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1630 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1631 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1632 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1633 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1634 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1635 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1636 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1638 if (has_nonconstant_offset
)
1639 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1641 opcode
= SHADER_OPCODE_TG4
;
1644 unreachable("not reached");
1646 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1647 inst
->base_mrf
= -1;
1649 inst
->mlen
= length
* reg_width
- header_present
;
1651 inst
->mlen
= length
* reg_width
;
1652 inst
->header_present
= header_present
;
1653 inst
->regs_written
= 4;
1655 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1656 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1657 " disallowed by hardware\n");
1664 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1665 bool is_rect
, uint32_t sampler
, int texunit
)
1667 fs_inst
*inst
= NULL
;
1668 bool needs_gl_clamp
= true;
1669 fs_reg scale_x
, scale_y
;
1670 const struct brw_sampler_prog_key_data
*tex
=
1671 (stage
== MESA_SHADER_FRAGMENT
) ?
1672 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1675 /* The 965 requires the EU to do the normalization of GL rectangle
1676 * texture coordinates. We use the program parameter state
1677 * tracking to get the scaling factor.
1681 (brw
->gen
>= 6 && (tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
1682 tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
1683 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1684 int tokens
[STATE_LENGTH
] = {
1686 STATE_TEXRECT_SCALE
,
1692 no16("rectangle scale uniform setup not supported on SIMD16\n");
1693 if (dispatch_width
== 16) {
1697 GLuint index
= _mesa_add_state_reference(params
,
1698 (gl_state_index
*)tokens
);
1699 /* Try to find existing copies of the texrect scale uniforms. */
1700 for (unsigned i
= 0; i
< uniforms
; i
++) {
1701 if (stage_prog_data
->param
[i
] ==
1702 &prog
->Parameters
->ParameterValues
[index
][0]) {
1703 scale_x
= fs_reg(UNIFORM
, i
);
1704 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1709 /* If we didn't already set them up, do so now. */
1710 if (scale_x
.file
== BAD_FILE
) {
1711 scale_x
= fs_reg(UNIFORM
, uniforms
);
1712 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1714 stage_prog_data
->param
[uniforms
++] =
1715 &prog
->Parameters
->ParameterValues
[index
][0];
1716 stage_prog_data
->param
[uniforms
++] =
1717 &prog
->Parameters
->ParameterValues
[index
][1];
1721 /* The 965 requires the EU to do the normalization of GL rectangle
1722 * texture coordinates. We use the program parameter state
1723 * tracking to get the scaling factor.
1725 if (brw
->gen
< 6 && is_rect
) {
1726 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1727 fs_reg src
= coordinate
;
1730 emit(MUL(dst
, src
, scale_x
));
1731 dst
= offset(dst
, 1);
1732 src
= offset(src
, 1);
1733 emit(MUL(dst
, src
, scale_y
));
1734 } else if (is_rect
) {
1735 /* On gen6+, the sampler handles the rectangle coordinates
1736 * natively, without needing rescaling. But that means we have
1737 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1738 * not [0, 1] like the default case below.
1740 needs_gl_clamp
= false;
1742 for (int i
= 0; i
< 2; i
++) {
1743 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1744 fs_reg chan
= coordinate
;
1745 chan
= offset(chan
, i
);
1747 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1748 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1750 /* Our parameter comes in as 1.0/width or 1.0/height,
1751 * because that's what people normally want for doing
1752 * texture rectangle handling. We need width or height
1753 * for clamping, but we don't care enough to make a new
1754 * parameter type, so just invert back.
1756 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1757 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1758 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1760 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1761 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1766 if (ir
->coordinate
&& needs_gl_clamp
) {
1767 for (unsigned int i
= 0;
1768 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1769 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1770 fs_reg chan
= coordinate
;
1771 chan
= offset(chan
, i
);
1773 fs_inst
*inst
= emit(MOV(chan
, chan
));
1774 inst
->saturate
= true;
1781 /* Sample from the MCS surface attached to this multisample texture. */
1783 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, fs_reg sampler
)
1785 int reg_width
= dispatch_width
/ 8;
1786 int length
= ir
->coordinate
->type
->vector_elements
;
1787 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1788 BRW_REGISTER_TYPE_F
);
1789 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1790 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, length
);
1792 /* parameters are: u, v, r; missing parameters are treated as zero */
1793 for (int i
= 0; i
< length
; i
++) {
1794 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1795 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1796 coordinate
= offset(coordinate
, 1);
1799 emit(LOAD_PAYLOAD(payload
, sources
, length
));
1801 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
1802 inst
->base_mrf
= -1;
1803 inst
->mlen
= length
* reg_width
;
1804 inst
->header_present
= false;
1805 inst
->regs_written
= 4; /* we only care about one reg of response,
1806 * but the sampler always writes 4/8
1813 fs_visitor::visit(ir_texture
*ir
)
1815 const struct brw_sampler_prog_key_data
*tex
=
1816 (stage
== MESA_SHADER_FRAGMENT
) ?
1817 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1819 fs_inst
*inst
= NULL
;
1822 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1824 ir_rvalue
*nonconst_sampler_index
=
1825 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
1827 /* Handle non-constant sampler array indexing */
1829 if (nonconst_sampler_index
) {
1830 /* The highest sampler which may be used by this operation is
1831 * the last element of the array. Mark it here, because the generator
1832 * doesn't have enough information to determine the bound.
1834 uint32_t array_size
= ir
->sampler
->as_dereference_array()
1835 ->array
->type
->array_size();
1837 uint32_t max_used
= sampler
+ array_size
- 1;
1838 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
1839 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1841 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1844 brw_mark_surface_used(prog_data
, max_used
);
1846 /* Emit code to evaluate the actual indexing expression */
1847 nonconst_sampler_index
->accept(this);
1848 fs_reg
temp(this, glsl_type::uint_type
);
1849 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
1850 ->force_writemask_all
= true;
1853 /* Single sampler, or constant array index; the indexing expression
1854 * is just an immediate.
1856 sampler_reg
= fs_reg(sampler
);
1859 /* FINISHME: We're failing to recompile our programs when the sampler is
1860 * updated. This only matters for the texture rectangle scale parameters
1861 * (pre-gen6, or gen6+ with GL_CLAMP).
1863 int texunit
= prog
->SamplerUnits
[sampler
];
1865 if (ir
->op
== ir_tg4
) {
1866 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1867 * emitting anything other than setting up the constant result.
1869 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1870 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], chan
->value
.i
[0]);
1871 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1873 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1876 for (int i
=0; i
<4; i
++) {
1877 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1878 res
= offset(res
, 1);
1884 /* Should be lowered by do_lower_texture_projection */
1885 assert(!ir
->projector
);
1887 /* Should be lowered */
1888 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1890 /* Generate code to compute all the subexpression trees. This has to be
1891 * done before loading any values into MRFs for the sampler message since
1892 * generating these values may involve SEND messages that need the MRFs.
1895 if (ir
->coordinate
) {
1896 ir
->coordinate
->accept(this);
1898 coordinate
= rescale_texcoord(ir
, this->result
,
1899 ir
->sampler
->type
->sampler_dimensionality
==
1900 GLSL_SAMPLER_DIM_RECT
,
1904 fs_reg shadow_comparitor
;
1905 if (ir
->shadow_comparitor
) {
1906 ir
->shadow_comparitor
->accept(this);
1907 shadow_comparitor
= this->result
;
1910 fs_reg lod
, lod2
, sample_index
, mcs
;
1915 case ir_query_levels
:
1918 ir
->lod_info
.bias
->accept(this);
1922 ir
->lod_info
.grad
.dPdx
->accept(this);
1925 ir
->lod_info
.grad
.dPdy
->accept(this);
1926 lod2
= this->result
;
1931 ir
->lod_info
.lod
->accept(this);
1935 ir
->lod_info
.sample_index
->accept(this);
1936 sample_index
= this->result
;
1938 if (brw
->gen
>= 7 && tex
->compressed_multisample_layout_mask
& (1<<sampler
))
1939 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
1944 unreachable("Unrecognized texture opcode");
1947 /* Writemasking doesn't eliminate channels on SIMD8 texture
1948 * samples, so don't worry about them.
1950 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1952 if (brw
->gen
>= 7) {
1953 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1954 lod
, lod2
, sample_index
, mcs
, sampler_reg
);
1955 } else if (brw
->gen
>= 5) {
1956 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1957 lod
, lod2
, sample_index
, sampler
);
1959 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1960 lod
, lod2
, sampler
);
1963 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1964 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
1966 if (ir
->op
== ir_tg4
)
1967 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1969 if (ir
->shadow_comparitor
)
1970 inst
->shadow_compare
= true;
1972 /* fixup #layers for cube map arrays */
1973 if (ir
->op
== ir_txs
) {
1974 glsl_type
const *type
= ir
->sampler
->type
;
1975 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1976 type
->sampler_array
) {
1977 fs_reg depth
= offset(dst
, 2);
1978 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
1979 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
1981 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
1982 for (int i
= 0; i
< inst
->regs_written
; i
++) {
1984 fixed_payload
[i
] = fixed_depth
;
1986 fixed_payload
[i
] = offset(dst
, i
);
1989 emit(LOAD_PAYLOAD(dst
, fixed_payload
, inst
->regs_written
));
1993 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
1994 emit_gen6_gather_wa(tex
->gen6_gather_wa
[sampler
], dst
);
1997 swizzle_result(ir
, dst
, sampler
);
2001 * Apply workarounds for Gen6 gather with UINT/SINT
2004 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2009 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2011 for (int i
= 0; i
< 4; i
++) {
2012 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2013 /* Convert from UNORM to UINT */
2014 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2015 emit(MOV(dst
, dst_f
));
2018 /* Reinterpret the UINT value as a signed INT value by
2019 * shifting the sign bit into place, then shifting back
2022 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2023 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2026 dst
= offset(dst
, 1);
2031 * Set up the gather channel based on the swizzle, for gather4.
2034 fs_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2036 const struct brw_sampler_prog_key_data
*tex
=
2037 (stage
== MESA_SHADER_FRAGMENT
) ?
2038 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2040 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2041 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], chan
->value
.i
[0]);
2043 case SWIZZLE_X
: return 0;
2045 /* gather4 sampler is broken for green channel on RG32F --
2046 * we must ask for blue instead.
2048 if (tex
->gather_channel_quirk_mask
& (1<<sampler
))
2051 case SWIZZLE_Z
: return 2;
2052 case SWIZZLE_W
: return 3;
2054 unreachable("Not reached"); /* zero, one swizzles handled already */
2059 * Swizzle the result of a texture result. This is necessary for
2060 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2063 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, uint32_t sampler
)
2065 if (ir
->op
== ir_query_levels
) {
2066 /* # levels is in .w */
2067 this->result
= offset(orig_val
, 3);
2071 this->result
= orig_val
;
2073 /* txs,lod don't actually sample the texture, so swizzling the result
2076 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
2079 const struct brw_sampler_prog_key_data
*tex
=
2080 (stage
== MESA_SHADER_FRAGMENT
) ?
2081 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2084 if (ir
->type
== glsl_type::float_type
) {
2085 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2086 assert(ir
->sampler
->type
->sampler_shadow
);
2087 } else if (tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2088 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
2090 for (int i
= 0; i
< 4; i
++) {
2091 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], i
);
2092 fs_reg l
= swizzled_result
;
2095 if (swiz
== SWIZZLE_ZERO
) {
2096 emit(MOV(l
, fs_reg(0.0f
)));
2097 } else if (swiz
== SWIZZLE_ONE
) {
2098 emit(MOV(l
, fs_reg(1.0f
)));
2100 emit(MOV(l
, offset(orig_val
,
2101 GET_SWZ(tex
->swizzles
[sampler
], i
))));
2104 this->result
= swizzled_result
;
2109 fs_visitor::visit(ir_swizzle
*ir
)
2111 ir
->val
->accept(this);
2112 fs_reg val
= this->result
;
2114 if (ir
->type
->vector_elements
== 1) {
2115 this->result
= offset(this->result
, ir
->mask
.x
);
2119 fs_reg result
= fs_reg(this, ir
->type
);
2120 this->result
= result
;
2122 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2123 fs_reg channel
= val
;
2141 emit(MOV(result
, offset(channel
, swiz
)));
2142 result
= offset(result
, 1);
2147 fs_visitor::visit(ir_discard
*ir
)
2149 assert(ir
->condition
== NULL
); /* FINISHME */
2151 /* We track our discarded pixels in f0.1. By predicating on it, we can
2152 * update just the flag bits that aren't yet discarded. By emitting a
2153 * CMP of g0 != g0, all our currently executing channels will get turned
2156 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2157 BRW_REGISTER_TYPE_UW
));
2158 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2159 BRW_CONDITIONAL_NZ
));
2160 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2161 cmp
->flag_subreg
= 1;
2163 if (brw
->gen
>= 6) {
2164 /* For performance, after a discard, jump to the end of the shader.
2165 * Only jump if all relevant channels have been discarded.
2167 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2168 discard_jump
->flag_subreg
= 1;
2170 discard_jump
->predicate
= (dispatch_width
== 8)
2171 ? BRW_PREDICATE_ALIGN1_ANY8H
2172 : BRW_PREDICATE_ALIGN1_ANY16H
;
2173 discard_jump
->predicate_inverse
= true;
2178 fs_visitor::visit(ir_constant
*ir
)
2180 /* Set this->result to reg at the bottom of the function because some code
2181 * paths will cause this visitor to be applied to other fields. This will
2182 * cause the value stored in this->result to be modified.
2184 * Make reg constant so that it doesn't get accidentally modified along the
2185 * way. Yes, I actually had this problem. :(
2187 const fs_reg
reg(this, ir
->type
);
2188 fs_reg dst_reg
= reg
;
2190 if (ir
->type
->is_array()) {
2191 const unsigned size
= type_size(ir
->type
->fields
.array
);
2193 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2194 ir
->array_elements
[i
]->accept(this);
2195 fs_reg src_reg
= this->result
;
2197 dst_reg
.type
= src_reg
.type
;
2198 for (unsigned j
= 0; j
< size
; j
++) {
2199 emit(MOV(dst_reg
, src_reg
));
2200 src_reg
= offset(src_reg
, 1);
2201 dst_reg
= offset(dst_reg
, 1);
2204 } else if (ir
->type
->is_record()) {
2205 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2206 const unsigned size
= type_size(field
->type
);
2208 field
->accept(this);
2209 fs_reg src_reg
= this->result
;
2211 dst_reg
.type
= src_reg
.type
;
2212 for (unsigned j
= 0; j
< size
; j
++) {
2213 emit(MOV(dst_reg
, src_reg
));
2214 src_reg
= offset(src_reg
, 1);
2215 dst_reg
= offset(dst_reg
, 1);
2219 const unsigned size
= type_size(ir
->type
);
2221 for (unsigned i
= 0; i
< size
; i
++) {
2222 switch (ir
->type
->base_type
) {
2223 case GLSL_TYPE_FLOAT
:
2224 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2226 case GLSL_TYPE_UINT
:
2227 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2230 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2232 case GLSL_TYPE_BOOL
:
2234 fs_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2238 unreachable("Non-float/uint/int/bool constant");
2240 dst_reg
= offset(dst_reg
, 1);
2248 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2250 ir_expression
*expr
= ir
->as_expression();
2252 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2255 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2256 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2263 assert(expr
->get_num_operands() <= 3);
2264 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2265 assert(expr
->operands
[i
]->type
->is_scalar());
2267 expr
->operands
[i
]->accept(this);
2268 op
[i
] = this->result
;
2270 resolve_ud_negate(&op
[i
]);
2273 switch (expr
->operation
) {
2274 case ir_unop_logic_not
:
2275 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2276 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2279 case ir_binop_logic_xor
:
2280 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2281 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2282 emit(XOR(dst
, op
[0], op
[1]));
2283 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2284 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2286 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2287 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2291 case ir_binop_logic_or
:
2292 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2293 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2294 emit(OR(dst
, op
[0], op
[1]));
2295 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2296 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2298 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2299 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2303 case ir_binop_logic_and
:
2304 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2305 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2306 emit(AND(dst
, op
[0], op
[1]));
2307 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2308 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2310 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2311 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2316 if (brw
->gen
>= 6) {
2317 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2319 inst
= emit(MOV(reg_null_f
, op
[0]));
2320 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2325 if (brw
->gen
>= 6) {
2326 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2328 inst
= emit(MOV(reg_null_d
, op
[0]));
2329 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2333 case ir_binop_greater
:
2334 case ir_binop_gequal
:
2336 case ir_binop_lequal
:
2337 case ir_binop_equal
:
2338 case ir_binop_all_equal
:
2339 case ir_binop_nequal
:
2340 case ir_binop_any_nequal
:
2341 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2342 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2343 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2346 emit(CMP(reg_null_d
, op
[0], op
[1],
2347 brw_conditional_for_comparison(expr
->operation
)));
2350 case ir_triop_csel
: {
2351 /* Expand the boolean condition into the flag register. */
2352 inst
= emit(MOV(reg_null_d
, op
[0]));
2353 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2355 /* Select which boolean to return. */
2356 fs_reg
temp(this, expr
->operands
[1]->type
);
2357 inst
= emit(SEL(temp
, op
[1], op
[2]));
2358 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2360 /* Expand the result to a condition code. */
2361 inst
= emit(MOV(reg_null_d
, temp
));
2362 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2367 unreachable("not reached");
2372 * Emit a gen6 IF statement with the comparison folded into the IF
2376 fs_visitor::emit_if_gen6(ir_if
*ir
)
2378 ir_expression
*expr
= ir
->condition
->as_expression();
2380 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2385 assert(expr
->get_num_operands() <= 3);
2386 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2387 assert(expr
->operands
[i
]->type
->is_scalar());
2389 expr
->operands
[i
]->accept(this);
2390 op
[i
] = this->result
;
2393 switch (expr
->operation
) {
2394 case ir_unop_logic_not
:
2395 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2398 case ir_binop_logic_xor
:
2399 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2402 case ir_binop_logic_or
:
2403 temp
= fs_reg(this, glsl_type::bool_type
);
2404 emit(OR(temp
, op
[0], op
[1]));
2405 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2408 case ir_binop_logic_and
:
2409 temp
= fs_reg(this, glsl_type::bool_type
);
2410 emit(AND(temp
, op
[0], op
[1]));
2411 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2415 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2416 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2420 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2423 case ir_binop_greater
:
2424 case ir_binop_gequal
:
2426 case ir_binop_lequal
:
2427 case ir_binop_equal
:
2428 case ir_binop_all_equal
:
2429 case ir_binop_nequal
:
2430 case ir_binop_any_nequal
:
2431 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2432 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2433 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2436 emit(IF(op
[0], op
[1],
2437 brw_conditional_for_comparison(expr
->operation
)));
2440 case ir_triop_csel
: {
2441 /* Expand the boolean condition into the flag register. */
2442 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2443 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2445 /* Select which boolean to use as the result. */
2446 fs_reg
temp(this, expr
->operands
[1]->type
);
2447 inst
= emit(SEL(temp
, op
[1], op
[2]));
2448 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2450 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2455 unreachable("not reached");
2459 ir
->condition
->accept(this);
2460 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2464 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2466 * Many GLSL shaders contain the following pattern:
2468 * x = condition ? foo : bar
2470 * The compiler emits an ir_if tree for this, since each subexpression might be
2471 * a complex tree that could have side-effects or short-circuit logic.
2473 * However, the common case is to simply select one of two constants or
2474 * variable values---which is exactly what SEL is for. In this case, the
2475 * assembly looks like:
2483 * which can be easily translated into:
2485 * (+f0) SEL dst src0 src1
2487 * If src0 is an immediate value, we promote it to a temporary GRF.
2490 fs_visitor::try_replace_with_sel()
2492 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2493 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2495 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2497 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2500 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2501 for (int i
= 0; i
< 4; i
++) {
2502 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2504 match
= (fs_inst
*) match
->prev
;
2507 /* The opcodes match; it looks like the right sequence of instructions. */
2508 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2509 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2510 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2512 /* Check that the MOVs are the right form. */
2513 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2514 !then_mov
->is_partial_write() &&
2515 !else_mov
->is_partial_write()) {
2517 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2518 while (!if_inst
->next
->is_tail_sentinel())
2519 if_inst
->next
->exec_node::remove();
2520 if_inst
->exec_node::remove();
2522 /* Only the last source register can be a constant, so if the MOV in
2523 * the "then" clause uses a constant, we need to put it in a temporary.
2525 fs_reg
src0(then_mov
->src
[0]);
2526 if (src0
.file
== IMM
) {
2527 src0
= fs_reg(this, glsl_type::float_type
);
2528 src0
.type
= then_mov
->src
[0].type
;
2529 emit(MOV(src0
, then_mov
->src
[0]));
2533 if (if_inst
->conditional_mod
) {
2534 /* Sandybridge-specific IF with embedded comparison */
2535 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2536 if_inst
->conditional_mod
));
2537 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2538 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2540 /* Separate CMP and IF instructions */
2541 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2542 sel
->predicate
= if_inst
->predicate
;
2543 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2549 fs_visitor::visit(ir_if
*ir
)
2552 no16("Can't support (non-uniform) control flow on SIMD16\n");
2555 /* Don't point the annotation at the if statement, because then it plus
2556 * the then and else blocks get printed.
2558 this->base_ir
= ir
->condition
;
2560 if (brw
->gen
== 6) {
2563 emit_bool_to_cond_code(ir
->condition
);
2565 emit(IF(BRW_PREDICATE_NORMAL
));
2568 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2569 this->base_ir
= ir_
;
2573 if (!ir
->else_instructions
.is_empty()) {
2574 emit(BRW_OPCODE_ELSE
);
2576 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2577 this->base_ir
= ir_
;
2582 emit(BRW_OPCODE_ENDIF
);
2584 try_replace_with_sel();
2588 fs_visitor::visit(ir_loop
*ir
)
2591 no16("Can't support (non-uniform) control flow on SIMD16\n");
2594 this->base_ir
= NULL
;
2595 emit(BRW_OPCODE_DO
);
2597 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2598 this->base_ir
= ir_
;
2602 this->base_ir
= NULL
;
2603 emit(BRW_OPCODE_WHILE
);
2607 fs_visitor::visit(ir_loop_jump
*ir
)
2610 case ir_loop_jump::jump_break
:
2611 emit(BRW_OPCODE_BREAK
);
2613 case ir_loop_jump::jump_continue
:
2614 emit(BRW_OPCODE_CONTINUE
);
2620 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2622 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2623 ir
->actual_parameters
.get_head());
2624 ir_variable
*location
= deref
->variable_referenced();
2625 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2626 location
->data
.binding
);
2628 /* Calculate the surface offset */
2629 fs_reg
offset(this, glsl_type::uint_type
);
2630 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2633 deref_array
->array_index
->accept(this);
2635 fs_reg
tmp(this, glsl_type::uint_type
);
2636 emit(MUL(tmp
, this->result
, ATOMIC_COUNTER_SIZE
));
2637 emit(ADD(offset
, tmp
, location
->data
.atomic
.offset
));
2639 offset
= location
->data
.atomic
.offset
;
2642 /* Emit the appropriate machine instruction */
2643 const char *callee
= ir
->callee
->function_name();
2644 ir
->return_deref
->accept(this);
2645 fs_reg dst
= this->result
;
2647 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2648 emit_untyped_surface_read(surf_index
, dst
, offset
);
2650 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2651 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2652 fs_reg(), fs_reg());
2654 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2655 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2656 fs_reg(), fs_reg());
2661 fs_visitor::visit(ir_call
*ir
)
2663 const char *callee
= ir
->callee
->function_name();
2665 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2666 !strcmp("__intrinsic_atomic_increment", callee
) ||
2667 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2668 visit_atomic_counter_intrinsic(ir
);
2670 unreachable("Unsupported intrinsic.");
2675 fs_visitor::visit(ir_return
*)
2677 unreachable("FINISHME");
2681 fs_visitor::visit(ir_function
*ir
)
2683 /* Ignore function bodies other than main() -- we shouldn't see calls to
2684 * them since they should all be inlined before we get to ir_to_mesa.
2686 if (strcmp(ir
->name
, "main") == 0) {
2687 const ir_function_signature
*sig
;
2690 sig
= ir
->matching_signature(NULL
, &empty
, false);
2694 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2695 this->base_ir
= ir_
;
2702 fs_visitor::visit(ir_function_signature
*)
2704 unreachable("not reached");
2708 fs_visitor::visit(ir_emit_vertex
*)
2710 unreachable("not reached");
2714 fs_visitor::visit(ir_end_primitive
*)
2716 unreachable("not reached");
2720 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2721 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2725 (stage
== MESA_SHADER_FRAGMENT
) &&
2726 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2727 const unsigned operand_len
= dispatch_width
/ 8;
2731 /* Initialize the sample mask in the message header. */
2732 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2733 ->force_writemask_all
= true;
2736 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2737 ->force_writemask_all
= true;
2739 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2740 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2741 ->force_writemask_all
= true;
2746 /* Set the atomic operation offset. */
2747 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2748 mlen
+= operand_len
;
2750 /* Set the atomic operation arguments. */
2751 if (src0
.file
!= BAD_FILE
) {
2752 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src0
));
2753 mlen
+= operand_len
;
2756 if (src1
.file
!= BAD_FILE
) {
2757 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src1
));
2758 mlen
+= operand_len
;
2761 /* Emit the instruction. */
2762 inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, atomic_op
, surf_index
);
2765 inst
->header_present
= true;
2769 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2773 (stage
== MESA_SHADER_FRAGMENT
) &&
2774 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2775 const unsigned operand_len
= dispatch_width
/ 8;
2779 /* Initialize the sample mask in the message header. */
2780 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2781 ->force_writemask_all
= true;
2784 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2785 ->force_writemask_all
= true;
2787 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2788 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2789 ->force_writemask_all
= true;
2794 /* Set the surface read offset. */
2795 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2796 mlen
+= operand_len
;
2798 /* Emit the instruction. */
2799 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, surf_index
);
2802 inst
->header_present
= true;
2806 fs_visitor::emit(fs_inst
*inst
)
2808 if (force_uncompressed_stack
> 0)
2809 inst
->force_uncompressed
= true;
2811 inst
->annotation
= this->current_annotation
;
2812 inst
->ir
= this->base_ir
;
2814 this->instructions
.push_tail(inst
);
2820 fs_visitor::emit(exec_list list
)
2822 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2823 inst
->exec_node::remove();
2828 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2830 fs_visitor::emit_dummy_fs()
2832 int reg_width
= dispatch_width
/ 8;
2834 /* Everyone's favorite color. */
2835 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2836 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2837 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2838 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2841 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2842 write
->base_mrf
= 2;
2843 write
->mlen
= 4 * reg_width
;
2847 /* The register location here is relative to the start of the URB
2848 * data. It will get adjusted to be a real location before
2849 * generate_code() time.
2852 fs_visitor::interp_reg(int location
, int channel
)
2854 assert(stage
== MESA_SHADER_FRAGMENT
);
2855 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
2856 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
2857 int stride
= (channel
& 1) * 4;
2859 assert(prog_data
->urb_setup
[location
] != -1);
2861 return brw_vec1_grf(regnr
, stride
);
2864 /** Emits the interpolation for the varying inputs. */
2866 fs_visitor::emit_interpolation_setup_gen4()
2868 this->current_annotation
= "compute pixel centers";
2869 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2870 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2871 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2872 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2874 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2875 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2877 this->current_annotation
= "compute pixel deltas from v0";
2879 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2880 fs_reg(this, glsl_type::vec2_type
);
2881 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2882 offset(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
], 1);
2884 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2885 fs_reg(this, glsl_type::float_type
);
2886 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2887 fs_reg(this, glsl_type::float_type
);
2889 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2890 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2891 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2892 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2894 this->current_annotation
= "compute pos.w and 1/pos.w";
2895 /* Compute wpos.w. It's always in our setup, since it's needed to
2896 * interpolate the other attributes.
2898 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2899 emit(FS_OPCODE_LINTERP
, wpos_w
,
2900 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2901 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2902 interp_reg(VARYING_SLOT_POS
, 3));
2903 /* Compute the pixel 1/W value from wpos.w. */
2904 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2905 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2906 this->current_annotation
= NULL
;
2909 /** Emits the interpolation for the varying inputs. */
2911 fs_visitor::emit_interpolation_setup_gen6()
2913 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2915 /* If the pixel centers end up used, the setup is the same as for gen4. */
2916 this->current_annotation
= "compute pixel centers";
2917 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2918 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2919 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2920 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2921 emit(ADD(int_pixel_x
,
2922 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2923 fs_reg(brw_imm_v(0x10101010))));
2924 emit(ADD(int_pixel_y
,
2925 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2926 fs_reg(brw_imm_v(0x11001100))));
2928 /* As of gen6, we can no longer mix float and int sources. We have
2929 * to turn the integer pixel centers into floats for their actual
2932 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2933 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2934 emit(MOV(this->pixel_x
, int_pixel_x
));
2935 emit(MOV(this->pixel_y
, int_pixel_y
));
2937 this->current_annotation
= "compute pos.w";
2938 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
2939 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2940 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2942 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2943 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
2944 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2945 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2948 this->current_annotation
= NULL
;
2952 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2954 assert(stage
== MESA_SHADER_FRAGMENT
);
2955 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2956 int reg_width
= dispatch_width
/ 8;
2958 fs_reg color
= outputs
[target
];
2961 /* If there's no color data to be written, skip it. */
2962 if (color
.file
== BAD_FILE
)
2965 color
= offset(color
, index
);
2967 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2968 /* SIMD8 write looks like:
2974 * gen6 SIMD16 DP write looks like:
2984 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2987 inst
->saturate
= key
->clamp_fragment_color
;
2989 /* pre-gen6 SIMD16 single source DP write looks like:
2999 if (brw
->has_compr4
) {
3000 /* By setting the high bit of the MRF register number, we
3001 * indicate that we want COMPR4 mode - instead of doing the
3002 * usual destination + 1 for the second half we get
3005 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
3008 inst
->saturate
= key
->clamp_fragment_color
;
3010 push_force_uncompressed();
3011 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
3013 inst
->saturate
= key
->clamp_fragment_color
;
3014 pop_force_uncompressed();
3016 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
3018 inst
->force_sechalf
= true;
3019 inst
->saturate
= key
->clamp_fragment_color
;
3024 static enum brw_conditional_mod
3025 cond_for_alpha_func(GLenum func
)
3029 return BRW_CONDITIONAL_G
;
3031 return BRW_CONDITIONAL_GE
;
3033 return BRW_CONDITIONAL_L
;
3035 return BRW_CONDITIONAL_LE
;
3037 return BRW_CONDITIONAL_EQ
;
3039 return BRW_CONDITIONAL_NEQ
;
3041 unreachable("Not reached");
3046 * Alpha test support for when we compile it into the shader instead
3047 * of using the normal fixed-function alpha test.
3050 fs_visitor::emit_alpha_test()
3052 assert(stage
== MESA_SHADER_FRAGMENT
);
3053 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3054 this->current_annotation
= "Alpha test";
3057 if (key
->alpha_test_func
== GL_ALWAYS
)
3060 if (key
->alpha_test_func
== GL_NEVER
) {
3062 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3063 BRW_REGISTER_TYPE_UW
));
3064 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3065 BRW_CONDITIONAL_NEQ
));
3068 fs_reg color
= offset(outputs
[0], 3);
3070 /* f0.1 &= func(color, ref) */
3071 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3072 cond_for_alpha_func(key
->alpha_test_func
)));
3074 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3075 cmp
->flag_subreg
= 1;
3079 fs_visitor::emit_fb_writes()
3081 assert(stage
== MESA_SHADER_FRAGMENT
);
3082 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3083 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3085 this->current_annotation
= "FB write header";
3086 bool header_present
= true;
3087 /* We can potentially have a message length of up to 15, so we have to set
3088 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3092 int reg_width
= dispatch_width
/ 8;
3093 bool src0_alpha_to_render_target
= false;
3096 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
3097 if (dispatch_width
== 16)
3098 do_dual_src
= false;
3101 /* From the Sandy Bridge PRM, volume 4, page 198:
3103 * "Dispatched Pixel Enables. One bit per pixel indicating
3104 * which pixels were originally enabled when the thread was
3105 * dispatched. This field is only required for the end-of-
3106 * thread message and on all dual-source messages."
3108 if (brw
->gen
>= 6 &&
3109 (brw
->is_haswell
|| brw
->gen
>= 8 || !prog_data
->uses_kill
) &&
3111 key
->nr_color_regions
== 1) {
3112 header_present
= false;
3115 if (header_present
) {
3116 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
3118 key
->replicate_alpha
;
3123 if (payload
.aa_dest_stencil_reg
) {
3124 push_force_uncompressed();
3125 emit(MOV(fs_reg(MRF
, nr
++),
3126 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3127 pop_force_uncompressed();
3130 prog_data
->uses_omask
=
3131 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3132 if (prog_data
->uses_omask
) {
3133 this->current_annotation
= "FB write oMask";
3134 assert(this->sample_mask
.file
!= BAD_FILE
);
3135 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
3136 emit(FS_OPCODE_SET_OMASK
, fs_reg(MRF
, nr
, BRW_REGISTER_TYPE_UW
), this->sample_mask
);
3140 /* Reserve space for color. It'll be filled in per MRT below. */
3142 nr
+= 4 * reg_width
;
3145 if (src0_alpha_to_render_target
)
3148 if (source_depth_to_render_target
) {
3149 if (brw
->gen
== 6) {
3150 /* For outputting oDepth on gen6, SIMD8 writes have to be
3151 * used. This would require SIMD8 moves of each half to
3152 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3153 * Just bail on doing so for now.
3155 no16("Missing support for simd16 depth writes on gen6\n");
3158 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3159 /* Hand over gl_FragDepth. */
3160 assert(this->frag_depth
.file
!= BAD_FILE
);
3161 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
3163 /* Pass through the payload depth. */
3164 emit(MOV(fs_reg(MRF
, nr
),
3165 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3170 if (payload
.dest_depth_reg
) {
3171 emit(MOV(fs_reg(MRF
, nr
),
3172 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3177 fs_reg src0
= this->outputs
[0];
3178 fs_reg src1
= this->dual_src_output
;
3180 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3182 for (int i
= 0; i
< 4; i
++) {
3183 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
3184 src0
= offset(src0
, 1);
3185 inst
->saturate
= key
->clamp_fragment_color
;
3188 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3190 for (int i
= 0; i
< 4; i
++) {
3191 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
3193 src1
= offset(src1
, 1);
3194 inst
->saturate
= key
->clamp_fragment_color
;
3197 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3198 emit_shader_time_end();
3200 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3202 inst
->base_mrf
= base_mrf
;
3203 inst
->mlen
= nr
- base_mrf
;
3205 inst
->header_present
= header_present
;
3206 if ((brw
->gen
>= 8 || brw
->is_haswell
) && prog_data
->uses_kill
) {
3207 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3208 inst
->flag_subreg
= 1;
3211 prog_data
->dual_src_blend
= true;
3212 this->current_annotation
= NULL
;
3216 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3217 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3218 "FB write target %d",
3220 /* If src0_alpha_to_render_target is true, include source zero alpha
3221 * data in RenderTargetWrite message for targets > 0.
3223 int write_color_mrf
= color_mrf
;
3224 if (src0_alpha_to_render_target
&& target
!= 0) {
3226 fs_reg color
= offset(outputs
[0], 3);
3228 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
3230 inst
->saturate
= key
->clamp_fragment_color
;
3231 write_color_mrf
= color_mrf
+ reg_width
;
3234 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
3235 emit_color_write(target
, i
, write_color_mrf
);
3238 if (target
== key
->nr_color_regions
- 1) {
3241 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3242 emit_shader_time_end();
3245 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3246 inst
->target
= target
;
3247 inst
->base_mrf
= base_mrf
;
3248 if (src0_alpha_to_render_target
&& target
== 0)
3249 inst
->mlen
= nr
- base_mrf
- reg_width
;
3251 inst
->mlen
= nr
- base_mrf
;
3253 inst
->header_present
= header_present
;
3254 if ((brw
->gen
>= 8 || brw
->is_haswell
) && prog_data
->uses_kill
) {
3255 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3256 inst
->flag_subreg
= 1;
3260 if (key
->nr_color_regions
== 0) {
3261 /* Even if there's no color buffers enabled, we still need to send
3262 * alpha out the pipeline to our null renderbuffer to support
3263 * alpha-testing, alpha-to-coverage, and so on.
3265 emit_color_write(0, 3, color_mrf
);
3267 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3268 emit_shader_time_end();
3270 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3271 inst
->base_mrf
= base_mrf
;
3272 inst
->mlen
= nr
- base_mrf
;
3274 inst
->header_present
= header_present
;
3275 if ((brw
->gen
>= 8 || brw
->is_haswell
) && prog_data
->uses_kill
) {
3276 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3277 inst
->flag_subreg
= 1;
3281 this->current_annotation
= NULL
;
3285 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3287 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3291 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
3292 emit(MOV(temp
, *reg
));
3297 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3299 assert(ctx
->Const
.UniformBooleanTrue
== 1);
3301 if (rvalue
->type
!= glsl_type::bool_type
)
3304 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
3305 emit(AND(temp
, *reg
, fs_reg(1)));
3309 fs_visitor::fs_visitor(struct brw_context
*brw
,
3311 const struct brw_wm_prog_key
*key
,
3312 struct brw_wm_prog_data
*prog_data
,
3313 struct gl_shader_program
*shader_prog
,
3314 struct gl_fragment_program
*fp
,
3315 unsigned dispatch_width
)
3316 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3317 MESA_SHADER_FRAGMENT
),
3318 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
3319 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
3320 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
3321 key(key
), prog_data(&prog_data
->base
),
3322 dispatch_width(dispatch_width
)
3324 this->mem_ctx
= mem_ctx
;
3331 this->failed
= false;
3332 this->simd16_unsupported
= false;
3333 this->no16_msg
= NULL
;
3334 this->variable_ht
= hash_table_ctor(0,
3335 hash_table_pointer_hash
,
3336 hash_table_pointer_compare
);
3338 memset(&this->payload
, 0, sizeof(this->payload
));
3339 memset(this->outputs
, 0, sizeof(this->outputs
));
3340 memset(this->output_components
, 0, sizeof(this->output_components
));
3341 this->source_depth_to_render_target
= false;
3342 this->runtime_check_aads_emit
= false;
3343 this->first_non_payload_grf
= 0;
3344 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3346 this->current_annotation
= NULL
;
3347 this->base_ir
= NULL
;
3349 this->virtual_grf_sizes
= NULL
;
3350 this->virtual_grf_count
= 0;
3351 this->virtual_grf_array_size
= 0;
3352 this->virtual_grf_start
= NULL
;
3353 this->virtual_grf_end
= NULL
;
3354 this->live_intervals
= NULL
;
3355 this->regs_live_at_ip
= NULL
;
3358 this->last_scratch
= 0;
3359 this->pull_constant_loc
= NULL
;
3360 this->push_constant_loc
= NULL
;
3362 this->force_uncompressed_stack
= 0;
3364 this->spilled_any_registers
= false;
3365 this->do_dual_src
= false;
3367 if (dispatch_width
== 8)
3368 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3371 fs_visitor::~fs_visitor()
3373 hash_table_dtor(this->variable_ht
);