2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_optimization.h"
51 #include "../glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
62 this->frag_color
= ir
;
63 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
65 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
66 this->frag_depth
= ir
;
69 if (ir
->mode
== ir_var_in
) {
70 if (!strcmp(ir
->name
, "gl_FragCoord")) {
71 reg
= emit_fragcoord_interpolation(ir
);
72 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
73 reg
= emit_frontfacing_interpolation(ir
);
75 reg
= emit_general_interpolation(ir
);
78 hash_table_insert(this->variable_ht
, reg
, ir
);
82 if (ir
->mode
== ir_var_uniform
) {
83 int param_index
= c
->prog_data
.nr_params
;
85 if (c
->dispatch_width
== 16) {
86 if (!variable_storage(ir
)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
92 if (!strncmp(ir
->name
, "gl_", 3)) {
93 setup_builtin_uniform_values(ir
);
95 setup_uniform_values(ir
->location
, ir
->type
);
98 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
99 reg
->type
= brw_type_for_base_type(ir
->type
);
103 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
105 hash_table_insert(this->variable_ht
, reg
, ir
);
109 fs_visitor::visit(ir_dereference_variable
*ir
)
111 fs_reg
*reg
= variable_storage(ir
->var
);
116 fs_visitor::visit(ir_dereference_record
*ir
)
118 const glsl_type
*struct_type
= ir
->record
->type
;
120 ir
->record
->accept(this);
122 unsigned int offset
= 0;
123 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
124 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
126 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
128 this->result
.reg_offset
+= offset
;
129 this->result
.type
= brw_type_for_base_type(ir
->type
);
133 fs_visitor::visit(ir_dereference_array
*ir
)
138 ir
->array
->accept(this);
139 index
= ir
->array_index
->as_constant();
141 element_size
= type_size(ir
->type
);
142 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 assert(this->result
.file
== UNIFORM
||
146 (this->result
.file
== GRF
&&
147 this->result
.reg
!= 0));
148 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
150 assert(!"FINISHME: non-constant array element");
154 /* Instruction selection: Produce a MOV.sat instead of
155 * MIN(MAX(val, 0), 1) when possible.
158 fs_visitor::try_emit_saturate(ir_expression
*ir
)
160 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
165 this->result
= reg_undef
;
166 sat_val
->accept(this);
167 fs_reg src
= this->result
;
169 this->result
= fs_reg(this, ir
->type
);
170 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
171 inst
->saturate
= true;
177 fs_visitor::visit(ir_expression
*ir
)
179 unsigned int operand
;
183 assert(ir
->get_num_operands() <= 2);
185 if (try_emit_saturate(ir
))
188 /* This is where our caller would like us to put the result, if possible. */
189 fs_reg saved_result_storage
= this->result
;
191 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
192 this->result
= reg_undef
;
193 ir
->operands
[operand
]->accept(this);
194 if (this->result
.file
== BAD_FILE
) {
196 fail("Failed to get tree for expression operand:\n");
197 ir
->operands
[operand
]->accept(&v
);
199 op
[operand
] = this->result
;
201 /* Matrix expression operands should have been broken down to vector
202 * operations already.
204 assert(!ir
->operands
[operand
]->type
->is_matrix());
205 /* And then those vector operands should have been broken down to scalar.
207 assert(!ir
->operands
[operand
]->type
->is_vector());
210 /* Inherit storage from our parent if possible, and otherwise we
213 if (saved_result_storage
.file
== BAD_FILE
) {
214 this->result
= fs_reg(this, ir
->type
);
216 this->result
= saved_result_storage
;
219 switch (ir
->operation
) {
220 case ir_unop_logic_not
:
221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
222 * ones complement of the whole register, not just bit 0.
224 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
227 op
[0].negate
= !op
[0].negate
;
228 this->result
= op
[0];
232 op
[0].negate
= false;
233 this->result
= op
[0];
236 temp
= fs_reg(this, ir
->type
);
238 /* Unalias the destination. (imagine a = sign(a)) */
239 this->result
= fs_reg(this, ir
->type
);
241 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
243 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
244 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
245 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
246 inst
->predicated
= true;
248 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
249 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
250 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
251 inst
->predicated
= true;
255 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
259 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
262 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
266 assert(!"not reached: should be handled by ir_explog_to_explog2");
269 case ir_unop_sin_reduced
:
270 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
273 case ir_unop_cos_reduced
:
274 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
278 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
281 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
285 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
288 assert(!"not reached: should be handled by ir_sub_to_add_neg");
292 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
295 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
302 case ir_binop_greater
:
303 case ir_binop_lequal
:
304 case ir_binop_gequal
:
306 case ir_binop_all_equal
:
307 case ir_binop_nequal
:
308 case ir_binop_any_nequal
:
310 /* original gen4 does implicit conversion before comparison. */
312 temp
.type
= op
[0].type
;
314 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
315 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
316 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
319 case ir_binop_logic_xor
:
320 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
323 case ir_binop_logic_or
:
324 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
327 case ir_binop_logic_and
:
328 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
333 assert(!"not reached: should be handled by brw_fs_channel_expressions");
337 assert(!"not reached: should be handled by lower_noise");
340 case ir_quadop_vector
:
341 assert(!"not reached: should be handled by lower_quadop_vector");
345 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
349 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
353 op
[0].type
= BRW_REGISTER_TYPE_UD
;
354 this->result
= op
[0];
357 op
[0].type
= BRW_REGISTER_TYPE_D
;
358 this->result
= op
[0];
364 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
369 /* original gen4 does implicit conversion before comparison. */
371 temp
.type
= op
[0].type
;
373 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
375 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
379 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
382 op
[0].negate
= !op
[0].negate
;
383 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
384 this->result
.negate
= true;
387 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
390 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
392 case ir_unop_round_even
:
393 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
397 if (intel
->gen
>= 6) {
398 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
399 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
401 /* Unalias the destination */
402 this->result
= fs_reg(this, ir
->type
);
404 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
405 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
407 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
408 inst
->predicated
= true;
412 if (intel
->gen
>= 6) {
413 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
414 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
416 /* Unalias the destination */
417 this->result
= fs_reg(this, ir
->type
);
419 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
420 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
422 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
423 inst
->predicated
= true;
428 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
431 case ir_unop_bit_not
:
432 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
434 case ir_binop_bit_and
:
435 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
437 case ir_binop_bit_xor
:
438 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
440 case ir_binop_bit_or
:
441 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
445 case ir_binop_lshift
:
446 case ir_binop_rshift
:
447 assert(!"GLSL 1.30 features unsupported");
453 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
454 const glsl_type
*type
, bool predicated
)
456 switch (type
->base_type
) {
457 case GLSL_TYPE_FLOAT
:
461 for (unsigned int i
= 0; i
< type
->components(); i
++) {
462 l
.type
= brw_type_for_base_type(type
);
463 r
.type
= brw_type_for_base_type(type
);
465 if (predicated
|| !l
.equals(&r
)) {
466 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
467 inst
->predicated
= predicated
;
474 case GLSL_TYPE_ARRAY
:
475 for (unsigned int i
= 0; i
< type
->length
; i
++) {
476 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
480 case GLSL_TYPE_STRUCT
:
481 for (unsigned int i
= 0; i
< type
->length
; i
++) {
482 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
487 case GLSL_TYPE_SAMPLER
:
491 assert(!"not reached");
497 fs_visitor::visit(ir_assignment
*ir
)
502 /* FINISHME: arrays on the lhs */
503 this->result
= reg_undef
;
504 ir
->lhs
->accept(this);
507 /* If we're doing a direct assignment, an RHS expression could
508 * drop its result right into our destination. Otherwise, tell it
512 !(ir
->lhs
->type
->is_scalar() ||
513 (ir
->lhs
->type
->is_vector() &&
514 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1))) {
515 this->result
= reg_undef
;
518 ir
->rhs
->accept(this);
521 assert(l
.file
!= BAD_FILE
);
522 assert(r
.file
!= BAD_FILE
);
525 emit_bool_to_cond_code(ir
->condition
);
528 if (ir
->lhs
->type
->is_scalar() ||
529 ir
->lhs
->type
->is_vector()) {
530 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
531 if (ir
->write_mask
& (1 << i
)) {
533 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
534 inst
->predicated
= true;
535 } else if (!l
.equals(&r
)) {
536 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
544 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
549 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
560 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
561 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
562 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
563 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
564 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
565 inst
->saturate
= true;
567 coordinate
.reg_offset
++;
569 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
572 if (ir
->op
== ir_tex
) {
573 /* There's no plain shadow compare message, so we use shadow
574 * compare with a bias of 0.0.
576 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
578 } else if (ir
->op
== ir_txb
) {
579 this->result
= reg_undef
;
580 ir
->lod_info
.bias
->accept(this);
581 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
584 assert(ir
->op
== ir_txl
);
585 this->result
= reg_undef
;
586 ir
->lod_info
.lod
->accept(this);
587 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
591 this->result
= reg_undef
;
592 ir
->shadow_comparitor
->accept(this);
593 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
595 } else if (ir
->op
== ir_tex
) {
596 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
597 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
599 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
600 inst
->saturate
= true;
601 coordinate
.reg_offset
++;
603 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
605 } else if (ir
->op
== ir_txd
) {
606 ir
->lod_info
.grad
.dPdx
->accept(this);
607 fs_reg dPdx
= this->result
;
609 ir
->lod_info
.grad
.dPdy
->accept(this);
610 fs_reg dPdy
= this->result
;
612 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
613 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
614 coordinate
.reg_offset
++;
616 /* the slots for u and v are always present, but r is optional */
617 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
620 * dPdx = dudx, dvdx, drdx
621 * dPdy = dudy, dvdy, drdy
623 * 2-arg: dudx dvdx dudy dvdy
624 * dPdx.x dPdx.y dPdy.x dPdy.y
627 * 3-arg: dudx dvdx drdx dudy dvdy drdy
628 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
631 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
632 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
637 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
638 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
643 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
644 * instructions. We'll need to do SIMD16 here.
646 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
648 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
649 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
650 base_mrf
+ mlen
+ i
* 2),
652 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
653 inst
->saturate
= true;
654 coordinate
.reg_offset
++;
657 /* lod/bias appears after u/v/r. */
660 if (ir
->op
== ir_txb
) {
661 this->result
= reg_undef
;
662 ir
->lod_info
.bias
->accept(this);
663 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
666 this->result
= reg_undef
;
667 ir
->lod_info
.lod
->accept(this);
668 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
672 /* The unused upper half. */
675 /* Now, since we're doing simd16, the return is 2 interleaved
676 * vec4s where the odd-indexed ones are junk. We'll need to move
677 * this weirdness around to the expected layout.
681 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
683 dst
.type
= BRW_REGISTER_TYPE_F
;
686 fs_inst
*inst
= NULL
;
689 inst
= emit(FS_OPCODE_TEX
, dst
);
692 inst
= emit(FS_OPCODE_TXB
, dst
);
695 inst
= emit(FS_OPCODE_TXL
, dst
);
698 inst
= emit(FS_OPCODE_TXD
, dst
);
701 assert(!"GLSL 1.30 features unsupported");
704 inst
->base_mrf
= base_mrf
;
706 inst
->header_present
= true;
709 for (int i
= 0; i
< 4; i
++) {
710 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
711 orig_dst
.reg_offset
++;
719 /* gen5's sampler has slots for u, v, r, array index, then optional
720 * parameters like shadow comparitor or LOD bias. If optional
721 * parameters aren't present, those base slots are optional and don't
722 * need to be included in the message.
724 * We don't fill in the unnecessary slots regardless, which may look
725 * surprising in the disassembly.
728 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
733 int reg_width
= c
->dispatch_width
/ 8;
734 bool header_present
= false;
737 /* The offsets set up by the ir_texture visitor are in the
738 * m1 header, so we can't go headerless.
740 header_present
= true;
745 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
746 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
747 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
),
749 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
750 inst
->saturate
= true;
751 coordinate
.reg_offset
++;
753 mlen
+= ir
->coordinate
->type
->vector_elements
* reg_width
;
755 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
756 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
758 this->result
= reg_undef
;
759 ir
->shadow_comparitor
->accept(this);
760 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
764 fs_inst
*inst
= NULL
;
767 inst
= emit(FS_OPCODE_TEX
, dst
);
770 this->result
= reg_undef
;
771 ir
->lod_info
.bias
->accept(this);
772 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
773 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
776 inst
= emit(FS_OPCODE_TXB
, dst
);
780 this->result
= reg_undef
;
781 ir
->lod_info
.lod
->accept(this);
782 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
783 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
786 inst
= emit(FS_OPCODE_TXL
, dst
);
789 ir
->lod_info
.grad
.dPdx
->accept(this);
790 fs_reg dPdx
= this->result
;
792 ir
->lod_info
.grad
.dPdy
->accept(this);
793 fs_reg dPdy
= this->result
;
795 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
799 * dPdx = dudx, dvdx, drdx
800 * dPdy = dudy, dvdy, drdy
802 * Load up these values:
803 * - dudx dudy dvdx dvdy drdx drdy
804 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
806 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
807 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
811 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
816 inst
= emit(FS_OPCODE_TXD
, dst
);
820 assert(!"GLSL 1.30 features unsupported");
823 inst
->base_mrf
= base_mrf
;
825 inst
->header_present
= header_present
;
828 fail("Message length >11 disallowed by hardware\n");
835 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
840 int reg_width
= c
->dispatch_width
/ 8;
841 bool header_present
= false;
844 /* The offsets set up by the ir_texture visitor are in the
845 * m1 header, so we can't go headerless.
847 header_present
= true;
852 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
853 ir
->shadow_comparitor
->accept(this);
854 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
858 /* Set up the LOD info */
863 ir
->lod_info
.bias
->accept(this);
864 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
868 ir
->lod_info
.lod
->accept(this);
869 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
873 if (c
->dispatch_width
== 16)
874 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
876 ir
->lod_info
.grad
.dPdx
->accept(this);
877 fs_reg dPdx
= this->result
;
879 ir
->lod_info
.grad
.dPdy
->accept(this);
880 fs_reg dPdy
= this->result
;
882 /* Load dPdx and the coordinate together:
883 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
885 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
886 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
888 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
889 inst
->saturate
= true;
890 coordinate
.reg_offset
++;
893 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
897 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
904 assert(!"GLSL 1.30 features unsupported");
908 /* Set up the coordinate (except for TXD where it was done earlier) */
909 if (ir
->op
!= ir_txd
) {
910 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
911 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
913 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
914 inst
->saturate
= true;
915 coordinate
.reg_offset
++;
920 /* Generate the SEND */
921 fs_inst
*inst
= NULL
;
923 case ir_tex
: inst
= emit(FS_OPCODE_TEX
, dst
); break;
924 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
925 case ir_txl
: inst
= emit(FS_OPCODE_TXL
, dst
); break;
926 case ir_txd
: inst
= emit(FS_OPCODE_TXD
, dst
); break;
927 case ir_txf
: assert(!"TXF unsupported.");
929 inst
->base_mrf
= base_mrf
;
931 inst
->header_present
= header_present
;
934 fail("Message length >11 disallowed by hardware\n");
941 fs_visitor::visit(ir_texture
*ir
)
943 fs_inst
*inst
= NULL
;
945 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
946 sampler
= fp
->Base
.SamplerUnits
[sampler
];
948 /* Our hardware doesn't have a sample_d_c message, so shadow compares
949 * for textureGrad/TXD need to be emulated with instructions.
951 bool hw_compare_supported
= ir
->op
!= ir_txd
;
952 if (ir
->shadow_comparitor
&& !hw_compare_supported
) {
953 assert(c
->key
.compare_funcs
[sampler
] != GL_NONE
);
954 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
955 if (c
->key
.compare_funcs
[sampler
] == GL_ALWAYS
)
956 return swizzle_result(ir
, fs_reg(1.0f
), sampler
);
957 else if (c
->key
.compare_funcs
[sampler
] == GL_NEVER
)
958 return swizzle_result(ir
, fs_reg(0.0f
), sampler
);
961 this->result
= reg_undef
;
962 ir
->coordinate
->accept(this);
963 fs_reg coordinate
= this->result
;
965 if (ir
->offset
!= NULL
) {
966 ir_constant
*offset
= ir
->offset
->as_constant();
967 assert(offset
!= NULL
);
969 signed char offsets
[3];
970 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
971 offsets
[i
] = (signed char) offset
->value
.i
[i
];
973 /* Combine all three offsets into a single unsigned dword:
975 * bits 11:8 - U Offset (X component)
976 * bits 7:4 - V Offset (Y component)
977 * bits 3:0 - R Offset (Z component)
979 unsigned offset_bits
= 0;
980 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
981 const unsigned shift
= 4 * (2 - i
);
982 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
985 /* Explicitly set up the message header by copying g0 to msg reg m1. */
986 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
987 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
989 /* Then set the offset bits in DWord 2 of the message header. */
991 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
992 BRW_REGISTER_TYPE_UD
)),
993 fs_reg(brw_imm_uw(offset_bits
)));
996 /* Should be lowered by do_lower_texture_projection */
997 assert(!ir
->projector
);
999 /* The 965 requires the EU to do the normalization of GL rectangle
1000 * texture coordinates. We use the program parameter state
1001 * tracking to get the scaling factor.
1003 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1004 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1005 int tokens
[STATE_LENGTH
] = {
1007 STATE_TEXRECT_SCALE
,
1013 if (c
->dispatch_width
== 16) {
1014 fail("rectangle scale uniform setup not supported on 16-wide\n");
1015 this->result
= fs_reg(this, ir
->type
);
1019 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1021 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1024 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1025 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1026 GLuint index
= _mesa_add_state_reference(params
,
1027 (gl_state_index
*)tokens
);
1029 this->param_index
[c
->prog_data
.nr_params
] = index
;
1030 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1031 c
->prog_data
.nr_params
++;
1032 this->param_index
[c
->prog_data
.nr_params
] = index
;
1033 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1034 c
->prog_data
.nr_params
++;
1036 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1037 fs_reg src
= coordinate
;
1040 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1043 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1046 /* Writemasking doesn't eliminate channels on SIMD8 texture
1047 * samples, so don't worry about them.
1049 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1051 if (intel
->gen
>= 7) {
1052 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1053 } else if (intel
->gen
>= 5) {
1054 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1056 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1059 /* If there's an offset, we already set up m1. To avoid the implied move,
1060 * use the null register. Otherwise, we want an implied move from g0.
1062 if (ir
->offset
!= NULL
|| !inst
->header_present
)
1063 inst
->src
[0] = reg_undef
;
1065 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1067 inst
->sampler
= sampler
;
1069 if (ir
->shadow_comparitor
) {
1070 if (hw_compare_supported
) {
1071 inst
->shadow_compare
= true;
1073 ir
->shadow_comparitor
->accept(this);
1074 fs_reg ref
= this->result
;
1077 dst
= fs_reg(this, glsl_type::vec4_type
);
1079 /* FINISHME: This needs to be done pre-filtering. */
1081 uint32_t conditional
= 0;
1082 switch (c
->key
.compare_funcs
[sampler
]) {
1083 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1084 case GL_LESS
: conditional
= BRW_CONDITIONAL_L
; break;
1085 case GL_GREATER
: conditional
= BRW_CONDITIONAL_G
; break;
1086 case GL_LEQUAL
: conditional
= BRW_CONDITIONAL_LE
; break;
1087 case GL_GEQUAL
: conditional
= BRW_CONDITIONAL_GE
; break;
1088 case GL_EQUAL
: conditional
= BRW_CONDITIONAL_EQ
; break;
1089 case GL_NOTEQUAL
: conditional
= BRW_CONDITIONAL_NEQ
; break;
1090 default: assert(!"Should not get here: bad shadow compare function");
1093 /* Use conditional moves to load 0 or 1 as the result */
1094 this->current_annotation
= "manual shadow comparison";
1095 for (int i
= 0; i
< 4; i
++) {
1096 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(0.0f
));
1098 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, ref
, value
);
1099 inst
->conditional_mod
= conditional
;
1101 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(1.0f
));
1102 inst
->predicated
= true;
1111 swizzle_result(ir
, dst
, sampler
);
1115 * Swizzle the result of a texture result. This is necessary for
1116 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1119 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1121 this->result
= orig_val
;
1123 if (ir
->type
== glsl_type::float_type
) {
1124 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1125 assert(ir
->sampler
->type
->sampler_shadow
);
1126 } else if (c
->key
.tex_swizzles
[sampler
] != SWIZZLE_NOOP
) {
1127 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1129 for (int i
= 0; i
< 4; i
++) {
1130 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1131 fs_reg l
= swizzled_result
;
1134 if (swiz
== SWIZZLE_ZERO
) {
1135 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1136 } else if (swiz
== SWIZZLE_ONE
) {
1137 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1139 fs_reg r
= orig_val
;
1140 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1141 emit(BRW_OPCODE_MOV
, l
, r
);
1144 this->result
= swizzled_result
;
1149 fs_visitor::visit(ir_swizzle
*ir
)
1151 this->result
= reg_undef
;
1152 ir
->val
->accept(this);
1153 fs_reg val
= this->result
;
1155 if (ir
->type
->vector_elements
== 1) {
1156 this->result
.reg_offset
+= ir
->mask
.x
;
1160 fs_reg result
= fs_reg(this, ir
->type
);
1161 this->result
= result
;
1163 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1164 fs_reg channel
= val
;
1182 channel
.reg_offset
+= swiz
;
1183 emit(BRW_OPCODE_MOV
, result
, channel
);
1184 result
.reg_offset
++;
1189 fs_visitor::visit(ir_discard
*ir
)
1191 assert(ir
->condition
== NULL
); /* FINISHME */
1193 emit(FS_OPCODE_DISCARD
);
1194 kill_emitted
= true;
1198 fs_visitor::visit(ir_constant
*ir
)
1200 /* Set this->result to reg at the bottom of the function because some code
1201 * paths will cause this visitor to be applied to other fields. This will
1202 * cause the value stored in this->result to be modified.
1204 * Make reg constant so that it doesn't get accidentally modified along the
1205 * way. Yes, I actually had this problem. :(
1207 const fs_reg
reg(this, ir
->type
);
1208 fs_reg dst_reg
= reg
;
1210 if (ir
->type
->is_array()) {
1211 const unsigned size
= type_size(ir
->type
->fields
.array
);
1213 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1214 this->result
= reg_undef
;
1215 ir
->array_elements
[i
]->accept(this);
1216 fs_reg src_reg
= this->result
;
1218 dst_reg
.type
= src_reg
.type
;
1219 for (unsigned j
= 0; j
< size
; j
++) {
1220 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1221 src_reg
.reg_offset
++;
1222 dst_reg
.reg_offset
++;
1225 } else if (ir
->type
->is_record()) {
1226 foreach_list(node
, &ir
->components
) {
1227 ir_instruction
*const field
= (ir_instruction
*) node
;
1228 const unsigned size
= type_size(field
->type
);
1230 this->result
= reg_undef
;
1231 field
->accept(this);
1232 fs_reg src_reg
= this->result
;
1234 dst_reg
.type
= src_reg
.type
;
1235 for (unsigned j
= 0; j
< size
; j
++) {
1236 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1237 src_reg
.reg_offset
++;
1238 dst_reg
.reg_offset
++;
1242 const unsigned size
= type_size(ir
->type
);
1244 for (unsigned i
= 0; i
< size
; i
++) {
1245 switch (ir
->type
->base_type
) {
1246 case GLSL_TYPE_FLOAT
:
1247 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1249 case GLSL_TYPE_UINT
:
1250 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1253 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1255 case GLSL_TYPE_BOOL
:
1256 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1259 assert(!"Non-float/uint/int/bool constant");
1261 dst_reg
.reg_offset
++;
1269 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1271 ir_expression
*expr
= ir
->as_expression();
1277 assert(expr
->get_num_operands() <= 2);
1278 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1279 assert(expr
->operands
[i
]->type
->is_scalar());
1281 this->result
= reg_undef
;
1282 expr
->operands
[i
]->accept(this);
1283 op
[i
] = this->result
;
1286 switch (expr
->operation
) {
1287 case ir_unop_logic_not
:
1288 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1289 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1292 case ir_binop_logic_xor
:
1293 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1294 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1297 case ir_binop_logic_or
:
1298 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1299 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1302 case ir_binop_logic_and
:
1303 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1304 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1308 if (intel
->gen
>= 6) {
1309 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1311 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1313 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1317 if (intel
->gen
>= 6) {
1318 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1320 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1322 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1325 case ir_binop_greater
:
1326 case ir_binop_gequal
:
1328 case ir_binop_lequal
:
1329 case ir_binop_equal
:
1330 case ir_binop_all_equal
:
1331 case ir_binop_nequal
:
1332 case ir_binop_any_nequal
:
1333 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1334 inst
->conditional_mod
=
1335 brw_conditional_for_comparison(expr
->operation
);
1339 assert(!"not reached");
1340 fail("bad cond code\n");
1346 this->result
= reg_undef
;
1349 if (intel
->gen
>= 6) {
1350 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1351 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1353 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1354 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1359 * Emit a gen6 IF statement with the comparison folded into the IF
1363 fs_visitor::emit_if_gen6(ir_if
*ir
)
1365 ir_expression
*expr
= ir
->condition
->as_expression();
1372 assert(expr
->get_num_operands() <= 2);
1373 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1374 assert(expr
->operands
[i
]->type
->is_scalar());
1376 this->result
= reg_undef
;
1377 expr
->operands
[i
]->accept(this);
1378 op
[i
] = this->result
;
1381 switch (expr
->operation
) {
1382 case ir_unop_logic_not
:
1383 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1384 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1387 case ir_binop_logic_xor
:
1388 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1389 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1392 case ir_binop_logic_or
:
1393 temp
= fs_reg(this, glsl_type::bool_type
);
1394 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1395 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1396 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1399 case ir_binop_logic_and
:
1400 temp
= fs_reg(this, glsl_type::bool_type
);
1401 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1402 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1403 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1407 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1408 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1412 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1413 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1416 case ir_binop_greater
:
1417 case ir_binop_gequal
:
1419 case ir_binop_lequal
:
1420 case ir_binop_equal
:
1421 case ir_binop_all_equal
:
1422 case ir_binop_nequal
:
1423 case ir_binop_any_nequal
:
1424 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1425 inst
->conditional_mod
=
1426 brw_conditional_for_comparison(expr
->operation
);
1429 assert(!"not reached");
1430 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1431 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1432 fail("bad condition\n");
1438 this->result
= reg_undef
;
1439 ir
->condition
->accept(this);
1441 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1442 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1446 fs_visitor::visit(ir_if
*ir
)
1450 if (intel
->gen
!= 6 && c
->dispatch_width
== 16) {
1451 fail("Can't support (non-uniform) control flow on 16-wide\n");
1454 /* Don't point the annotation at the if statement, because then it plus
1455 * the then and else blocks get printed.
1457 this->base_ir
= ir
->condition
;
1459 if (intel
->gen
== 6) {
1462 emit_bool_to_cond_code(ir
->condition
);
1464 inst
= emit(BRW_OPCODE_IF
);
1465 inst
->predicated
= true;
1468 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1469 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1471 this->result
= reg_undef
;
1475 if (!ir
->else_instructions
.is_empty()) {
1476 emit(BRW_OPCODE_ELSE
);
1478 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1479 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1481 this->result
= reg_undef
;
1486 emit(BRW_OPCODE_ENDIF
);
1490 fs_visitor::visit(ir_loop
*ir
)
1492 fs_reg counter
= reg_undef
;
1494 if (c
->dispatch_width
== 16) {
1495 fail("Can't support (non-uniform) control flow on 16-wide\n");
1499 this->base_ir
= ir
->counter
;
1500 ir
->counter
->accept(this);
1501 counter
= *(variable_storage(ir
->counter
));
1504 this->result
= counter
;
1506 this->base_ir
= ir
->from
;
1507 this->result
= counter
;
1508 ir
->from
->accept(this);
1510 if (!this->result
.equals(&counter
))
1511 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1515 emit(BRW_OPCODE_DO
);
1518 this->base_ir
= ir
->to
;
1519 this->result
= reg_undef
;
1520 ir
->to
->accept(this);
1522 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1523 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1525 inst
= emit(BRW_OPCODE_BREAK
);
1526 inst
->predicated
= true;
1529 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1530 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1533 this->result
= reg_undef
;
1537 if (ir
->increment
) {
1538 this->base_ir
= ir
->increment
;
1539 this->result
= reg_undef
;
1540 ir
->increment
->accept(this);
1541 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1544 emit(BRW_OPCODE_WHILE
);
1548 fs_visitor::visit(ir_loop_jump
*ir
)
1551 case ir_loop_jump::jump_break
:
1552 emit(BRW_OPCODE_BREAK
);
1554 case ir_loop_jump::jump_continue
:
1555 emit(BRW_OPCODE_CONTINUE
);
1561 fs_visitor::visit(ir_call
*ir
)
1563 assert(!"FINISHME");
1567 fs_visitor::visit(ir_return
*ir
)
1569 assert(!"FINISHME");
1573 fs_visitor::visit(ir_function
*ir
)
1575 /* Ignore function bodies other than main() -- we shouldn't see calls to
1576 * them since they should all be inlined before we get to ir_to_mesa.
1578 if (strcmp(ir
->name
, "main") == 0) {
1579 const ir_function_signature
*sig
;
1582 sig
= ir
->matching_signature(&empty
);
1586 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1587 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1589 this->result
= reg_undef
;
1596 fs_visitor::visit(ir_function_signature
*ir
)
1598 assert(!"not reached");
1603 fs_visitor::emit(fs_inst inst
)
1605 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1608 if (force_uncompressed_stack
> 0)
1609 list_inst
->force_uncompressed
= true;
1610 else if (force_sechalf_stack
> 0)
1611 list_inst
->force_sechalf
= true;
1613 list_inst
->annotation
= this->current_annotation
;
1614 list_inst
->ir
= this->base_ir
;
1616 this->instructions
.push_tail(list_inst
);
1621 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1623 fs_visitor::emit_dummy_fs()
1625 /* Everyone's favorite color. */
1626 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1627 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1628 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1629 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1632 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1633 write
->base_mrf
= 2;
1636 /* The register location here is relative to the start of the URB
1637 * data. It will get adjusted to be a real location before
1638 * generate_code() time.
1641 fs_visitor::interp_reg(int location
, int channel
)
1643 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1644 int stride
= (channel
& 1) * 4;
1646 assert(urb_setup
[location
] != -1);
1648 return brw_vec1_grf(regnr
, stride
);
1651 /** Emits the interpolation for the varying inputs. */
1653 fs_visitor::emit_interpolation_setup_gen4()
1655 this->current_annotation
= "compute pixel centers";
1656 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1657 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1658 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1659 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1661 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1662 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1664 this->current_annotation
= "compute pixel deltas from v0";
1666 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1667 this->delta_y
= this->delta_x
;
1668 this->delta_y
.reg_offset
++;
1670 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1671 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1673 emit(BRW_OPCODE_ADD
, this->delta_x
,
1674 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1675 emit(BRW_OPCODE_ADD
, this->delta_y
,
1676 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1678 this->current_annotation
= "compute pos.w and 1/pos.w";
1679 /* Compute wpos.w. It's always in our setup, since it's needed to
1680 * interpolate the other attributes.
1682 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1683 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1684 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1685 /* Compute the pixel 1/W value from wpos.w. */
1686 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1687 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1688 this->current_annotation
= NULL
;
1691 /** Emits the interpolation for the varying inputs. */
1693 fs_visitor::emit_interpolation_setup_gen6()
1695 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1697 /* If the pixel centers end up used, the setup is the same as for gen4. */
1698 this->current_annotation
= "compute pixel centers";
1699 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1700 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1701 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1702 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1703 emit(BRW_OPCODE_ADD
,
1705 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1706 fs_reg(brw_imm_v(0x10101010)));
1707 emit(BRW_OPCODE_ADD
,
1709 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1710 fs_reg(brw_imm_v(0x11001100)));
1712 /* As of gen6, we can no longer mix float and int sources. We have
1713 * to turn the integer pixel centers into floats for their actual
1716 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1717 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1718 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1719 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1721 this->current_annotation
= "compute pos.w";
1722 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1723 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1724 emit_math(FS_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1726 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1727 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1729 this->current_annotation
= NULL
;
1733 fs_visitor::emit_color_write(int index
, int first_color_mrf
, fs_reg color
)
1735 int reg_width
= c
->dispatch_width
/ 8;
1737 if (c
->dispatch_width
== 8 || intel
->gen
== 6) {
1738 /* SIMD8 write looks like:
1744 * gen6 SIMD16 DP write looks like:
1754 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
* reg_width
),
1757 /* pre-gen6 SIMD16 single source DP write looks like:
1767 if (brw
->has_compr4
) {
1768 /* By setting the high bit of the MRF register number, we
1769 * indicate that we want COMPR4 mode - instead of doing the
1770 * usual destination + 1 for the second half we get
1773 emit(BRW_OPCODE_MOV
,
1774 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
), color
);
1776 push_force_uncompressed();
1777 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
), color
);
1778 pop_force_uncompressed();
1780 push_force_sechalf();
1781 color
.sechalf
= true;
1782 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4), color
);
1783 pop_force_sechalf();
1784 color
.sechalf
= false;
1790 fs_visitor::emit_fb_writes()
1792 this->current_annotation
= "FB write header";
1793 GLboolean header_present
= GL_TRUE
;
1796 int reg_width
= c
->dispatch_width
/ 8;
1798 if (intel
->gen
>= 6 &&
1799 !this->kill_emitted
&&
1800 c
->key
.nr_color_regions
== 1) {
1801 header_present
= false;
1804 if (header_present
) {
1809 if (c
->aa_dest_stencil_reg
) {
1810 push_force_uncompressed();
1811 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1812 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1813 pop_force_uncompressed();
1816 /* Reserve space for color. It'll be filled in per MRT below. */
1818 nr
+= 4 * reg_width
;
1820 if (c
->source_depth_to_render_target
) {
1821 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1822 /* For outputting oDepth on gen6, SIMD8 writes have to be
1823 * used. This would require 8-wide moves of each half to
1824 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1825 * Just bail on doing so for now.
1827 fail("Missing support for simd16 depth writes on gen6\n");
1830 if (c
->computes_depth
) {
1831 /* Hand over gl_FragDepth. */
1832 assert(this->frag_depth
);
1833 fs_reg depth
= *(variable_storage(this->frag_depth
));
1835 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1837 /* Pass through the payload depth. */
1838 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1839 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1844 if (c
->dest_depth_reg
) {
1845 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1846 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1850 fs_reg color
= reg_undef
;
1851 if (this->frag_color
)
1852 color
= *(variable_storage(this->frag_color
));
1853 else if (this->frag_data
) {
1854 color
= *(variable_storage(this->frag_data
));
1855 color
.type
= BRW_REGISTER_TYPE_F
;
1858 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1859 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1860 "FB write target %d",
1862 if (this->frag_color
|| this->frag_data
) {
1863 for (int i
= 0; i
< 4; i
++) {
1864 emit_color_write(i
, color_mrf
, color
);
1869 if (this->frag_color
)
1870 color
.reg_offset
-= 4;
1872 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1873 inst
->target
= target
;
1874 inst
->base_mrf
= base_mrf
;
1875 inst
->mlen
= nr
- base_mrf
;
1876 if (target
== c
->key
.nr_color_regions
- 1)
1878 inst
->header_present
= header_present
;
1881 if (c
->key
.nr_color_regions
== 0) {
1882 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
1883 /* If the alpha test is enabled but there's no color buffer,
1884 * we still need to send alpha out the pipeline to our null
1887 color
.reg_offset
+= 3;
1888 emit_color_write(3, color_mrf
, color
);
1891 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1892 inst
->base_mrf
= base_mrf
;
1893 inst
->mlen
= nr
- base_mrf
;
1895 inst
->header_present
= header_present
;
1898 this->current_annotation
= NULL
;