2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "glsl/nir/glsl_types.h"
36 fs_visitor::emit_vs_system_value(int location
)
38 fs_reg
*reg
= new(this->mem_ctx
)
39 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
41 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
44 case SYSTEM_VALUE_BASE_VERTEX
:
46 vs_prog_data
->uses_basevertex
= true;
48 case SYSTEM_VALUE_BASE_INSTANCE
:
50 vs_prog_data
->uses_baseinstance
= true;
52 case SYSTEM_VALUE_VERTEX_ID
:
53 unreachable("should have been lowered");
54 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
56 vs_prog_data
->uses_vertexid
= true;
58 case SYSTEM_VALUE_INSTANCE_ID
:
60 vs_prog_data
->uses_instanceid
= true;
63 unreachable("not reached");
69 /* Sample from the MCS surface attached to this multisample texture. */
71 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
72 const fs_reg
&sampler
)
74 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
75 const fs_reg srcs
[] = {
76 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
77 sampler
, fs_reg(), brw_imm_ud(components
), brw_imm_d(0)
79 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
82 /* We only care about one or two regs of response, but the sampler always
85 inst
->regs_written
= 4 * dispatch_width
/ 8;
91 fs_visitor::emit_texture(ir_texture_opcode op
,
92 const glsl_type
*dest_type
,
93 fs_reg coordinate
, int coord_components
,
95 fs_reg lod
, fs_reg lod2
, int grad_components
,
104 fs_inst
*inst
= NULL
;
106 if (op
== ir_query_levels
) {
107 /* textureQueryLevels() is implemented in terms of TXS so we need to
108 * pass a valid LOD argument.
110 assert(lod
.file
== BAD_FILE
);
111 lod
= brw_imm_ud(0u);
114 if (op
== ir_samples_identical
) {
115 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
117 /* If mcs is an immediate value, it means there is no MCS. In that case
120 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
121 bld
.MOV(dst
, brw_imm_ud(0u));
122 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
123 fs_reg tmp
= vgrf(glsl_type::uint_type
);
124 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
125 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
127 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
134 /* Writemasking doesn't eliminate channels on SIMD8 texture
135 * samples, so don't worry about them.
137 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
138 const fs_reg srcs
[] = {
139 coordinate
, shadow_c
, lod
, lod2
,
140 sample_index
, mcs
, sampler_reg
, offset_value
,
141 brw_imm_d(coord_components
), brw_imm_d(grad_components
)
147 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
150 opcode
= FS_OPCODE_TXB_LOGICAL
;
153 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
156 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
159 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
162 if ((key_tex
->msaa_16
& (1 << sampler
)))
163 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
165 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
168 case ir_query_levels
:
169 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
172 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
175 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
176 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
179 unreachable("Invalid texture opcode.");
182 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
183 inst
->regs_written
= 4 * dispatch_width
/ 8;
185 if (shadow_c
.file
!= BAD_FILE
)
186 inst
->shadow_compare
= true;
188 if (offset_value
.file
== IMM
)
189 inst
->offset
= offset_value
.ud
;
192 if (gather_component
== 1 &&
193 key_tex
->gather_channel_quirk_mask
& (1 << sampler
)) {
194 /* gather4 sampler is broken for green channel on RG32F --
195 * we must ask for blue instead.
197 inst
->offset
|= 2 << 16;
199 inst
->offset
|= gather_component
<< 16;
202 if (devinfo
->gen
== 6)
203 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
206 /* fixup #layers for cube map arrays */
207 if (op
== ir_txs
&& is_cube_array
) {
208 fs_reg depth
= offset(dst
, bld
, 2);
209 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
210 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
212 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
213 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
214 for (int i
= 0; i
< components
; i
++) {
216 fixed_payload
[i
] = fixed_depth
;
218 fixed_payload
[i
] = offset(dst
, bld
, i
);
221 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
224 if (op
== ir_query_levels
) {
225 /* # levels is in .w */
226 dst
= offset(dst
, bld
, 3);
233 * Apply workarounds for Gen6 gather with UINT/SINT
236 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
241 int width
= (wa
& WA_8BIT
) ? 8 : 16;
243 for (int i
= 0; i
< 4; i
++) {
244 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
245 /* Convert from UNORM to UINT */
246 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
250 /* Reinterpret the UINT value as a signed INT value by
251 * shifting the sign bit into place, then shifting back
254 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
255 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
258 dst
= offset(dst
, bld
, 1);
262 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
264 fs_visitor::emit_dummy_fs()
266 int reg_width
= dispatch_width
/ 8;
268 /* Everyone's favorite color. */
269 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
270 for (int i
= 0; i
< 4; i
++) {
271 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
272 brw_imm_f(color
[i
]));
276 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
278 if (devinfo
->gen
>= 6) {
280 write
->mlen
= 4 * reg_width
;
282 write
->header_size
= 2;
284 write
->mlen
= 2 + 4 * reg_width
;
287 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
288 * varying to avoid GPU hangs, so set that.
290 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
291 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
292 memset(wm_prog_data
->urb_setup
, -1,
293 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
295 /* We don't have any uniforms. */
296 stage_prog_data
->nr_params
= 0;
297 stage_prog_data
->nr_pull_params
= 0;
298 stage_prog_data
->curb_read_length
= 0;
299 stage_prog_data
->dispatch_grf_start_reg
= 2;
300 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
301 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
306 /* The register location here is relative to the start of the URB
307 * data. It will get adjusted to be a real location before
308 * generate_code() time.
311 fs_visitor::interp_reg(int location
, int channel
)
313 assert(stage
== MESA_SHADER_FRAGMENT
);
314 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
315 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
316 int stride
= (channel
& 1) * 4;
318 assert(prog_data
->urb_setup
[location
] != -1);
320 return brw_vec1_grf(regnr
, stride
);
323 /** Emits the interpolation for the varying inputs. */
325 fs_visitor::emit_interpolation_setup_gen4()
327 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
329 fs_builder abld
= bld
.annotate("compute pixel centers");
330 this->pixel_x
= vgrf(glsl_type::uint_type
);
331 this->pixel_y
= vgrf(glsl_type::uint_type
);
332 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
333 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
334 abld
.ADD(this->pixel_x
,
335 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
336 fs_reg(brw_imm_v(0x10101010)));
337 abld
.ADD(this->pixel_y
,
338 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
339 fs_reg(brw_imm_v(0x11001100)));
341 abld
= bld
.annotate("compute pixel deltas from v0");
343 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
344 vgrf(glsl_type::vec2_type
);
345 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
346 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
347 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
349 if (devinfo
->has_pln
&& dispatch_width
== 16) {
350 for (unsigned i
= 0; i
< 2; i
++) {
351 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
352 half(this->pixel_x
, i
), xstart
);
353 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
354 half(this->pixel_y
, i
), ystart
);
357 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
358 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
361 abld
= bld
.annotate("compute pos.w and 1/pos.w");
362 /* Compute wpos.w. It's always in our setup, since it's needed to
363 * interpolate the other attributes.
365 this->wpos_w
= vgrf(glsl_type::float_type
);
366 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
367 interp_reg(VARYING_SLOT_POS
, 3));
368 /* Compute the pixel 1/W value from wpos.w. */
369 this->pixel_w
= vgrf(glsl_type::float_type
);
370 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
373 /** Emits the interpolation for the varying inputs. */
375 fs_visitor::emit_interpolation_setup_gen6()
377 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
379 fs_builder abld
= bld
.annotate("compute pixel centers");
380 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
381 /* The "Register Region Restrictions" page says for BDW (and newer,
384 * "When destination spans two registers, the source may be one or
385 * two registers. The destination elements must be evenly split
386 * between the two registers."
388 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
389 * compute our pixel centers.
391 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
392 BRW_REGISTER_TYPE_UW
);
394 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
395 dbld
.ADD(int_pixel_xy
,
396 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
397 fs_reg(brw_imm_v(0x11001010)));
399 this->pixel_x
= vgrf(glsl_type::float_type
);
400 this->pixel_y
= vgrf(glsl_type::float_type
);
401 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
402 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
404 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
406 * "When destination spans two registers, the source MUST span two
409 * Since the GRF source of the ADD will only read a single register, we
410 * must do two separate ADDs in SIMD16.
412 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
413 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
414 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
415 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
416 abld
.ADD(int_pixel_x
,
417 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
418 fs_reg(brw_imm_v(0x10101010)));
419 abld
.ADD(int_pixel_y
,
420 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
421 fs_reg(brw_imm_v(0x11001100)));
423 /* As of gen6, we can no longer mix float and int sources. We have
424 * to turn the integer pixel centers into floats for their actual
427 this->pixel_x
= vgrf(glsl_type::float_type
);
428 this->pixel_y
= vgrf(glsl_type::float_type
);
429 abld
.MOV(this->pixel_x
, int_pixel_x
);
430 abld
.MOV(this->pixel_y
, int_pixel_y
);
433 abld
= bld
.annotate("compute pos.w");
434 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
435 this->wpos_w
= vgrf(glsl_type::float_type
);
436 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
438 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
439 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
440 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
444 static enum brw_conditional_mod
445 cond_for_alpha_func(GLenum func
)
449 return BRW_CONDITIONAL_G
;
451 return BRW_CONDITIONAL_GE
;
453 return BRW_CONDITIONAL_L
;
455 return BRW_CONDITIONAL_LE
;
457 return BRW_CONDITIONAL_EQ
;
459 return BRW_CONDITIONAL_NEQ
;
461 unreachable("Not reached");
466 * Alpha test support for when we compile it into the shader instead
467 * of using the normal fixed-function alpha test.
470 fs_visitor::emit_alpha_test()
472 assert(stage
== MESA_SHADER_FRAGMENT
);
473 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
474 const fs_builder abld
= bld
.annotate("Alpha test");
477 if (key
->alpha_test_func
== GL_ALWAYS
)
480 if (key
->alpha_test_func
== GL_NEVER
) {
482 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
483 BRW_REGISTER_TYPE_UW
));
484 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
485 BRW_CONDITIONAL_NEQ
);
488 fs_reg color
= offset(outputs
[0], bld
, 3);
490 /* f0.1 &= func(color, ref) */
491 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
492 cond_for_alpha_func(key
->alpha_test_func
));
494 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
495 cmp
->flag_subreg
= 1;
499 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
500 fs_reg color0
, fs_reg color1
,
501 fs_reg src0_alpha
, unsigned components
)
503 assert(stage
== MESA_SHADER_FRAGMENT
);
504 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
506 /* Hand over gl_FragDepth or the payload depth. */
507 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
508 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
510 fs_reg src_depth
, src_stencil
;
512 if (source_depth_to_render_target
) {
513 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
514 src_depth
= frag_depth
;
516 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
519 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
520 src_stencil
= frag_stencil
;
522 const fs_reg sources
[] = {
523 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
524 sample_mask
, brw_imm_ud(components
)
526 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
527 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
528 sources
, ARRAY_SIZE(sources
));
530 if (prog_data
->uses_kill
) {
531 write
->predicate
= BRW_PREDICATE_NORMAL
;
532 write
->flag_subreg
= 1;
539 fs_visitor::emit_fb_writes()
541 assert(stage
== MESA_SHADER_FRAGMENT
);
542 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
543 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
545 fs_inst
*inst
= NULL
;
547 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
548 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
549 * would require SIMD8 moves of each half to message regs, e.g. by using
550 * the SIMD lowering pass. Unfortunately this is more difficult than it
551 * sounds because the SIMD8 single-source message lacks channel selects
552 * for the second and third subspans.
554 no16("Missing support for simd16 depth writes on gen6\n");
557 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
558 /* From the 'Render Target Write message' section of the docs:
559 * "Output Stencil is not supported with SIMD16 Render Target Write
562 * FINISHME: split 16 into 2 8s
564 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
568 const fs_builder abld
= bld
.annotate("FB dual-source write");
570 inst
= emit_single_fb_write(abld
, this->outputs
[0],
571 this->dual_src_output
, reg_undef
, 4);
574 prog_data
->dual_src_blend
= true;
576 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
577 /* Skip over outputs that weren't written. */
578 if (this->outputs
[target
].file
== BAD_FILE
)
581 const fs_builder abld
= bld
.annotate(
582 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
585 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
586 src0_alpha
= offset(outputs
[0], bld
, 3);
588 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
590 this->output_components
[target
]);
591 inst
->target
= target
;
596 /* Even if there's no color buffers enabled, we still need to send
597 * alpha out the pipeline to our null renderbuffer to support
598 * alpha-testing, alpha-to-coverage, and so on.
600 /* FINISHME: Factor out this frequently recurring pattern into a
603 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
604 reg_undef
, offset(this->outputs
[0], bld
, 3) };
605 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
606 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
608 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
616 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
618 const struct brw_vs_prog_key
*key
=
619 (const struct brw_vs_prog_key
*) this->key
;
621 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
622 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
623 for (int j
= 0; j
< 4; ++j
) {
624 stage_prog_data
->param
[uniforms
+ j
] =
625 (gl_constant_value
*) &clip_planes
[i
][j
];
632 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
634 * This does nothing if the shader uses gl_ClipDistance or user clipping is
635 * disabled altogether.
637 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
639 struct brw_vue_prog_data
*vue_prog_data
=
640 (struct brw_vue_prog_data
*) prog_data
;
641 const struct brw_vs_prog_key
*key
=
642 (const struct brw_vs_prog_key
*) this->key
;
644 /* Bail unless some sort of legacy clipping is enabled */
645 if (key
->nr_userclip_plane_consts
== 0)
648 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
650 * "If a linked set of shaders forming the vertex stage contains no
651 * static write to gl_ClipVertex or gl_ClipDistance, but the
652 * application has requested clipping against user clip planes through
653 * the API, then the coordinate written to gl_Position is used for
654 * comparison against the user clip planes."
656 * This function is only called if the shader didn't write to
657 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
658 * if the user wrote to it; otherwise we use gl_Position.
661 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
662 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
663 clip_vertex
= VARYING_SLOT_POS
;
665 /* If the clip vertex isn't written, skip this. Typically this means
666 * the GS will set up clipping. */
667 if (outputs
[clip_vertex
].file
== BAD_FILE
)
670 setup_uniform_clipplane_values(clip_planes
);
672 const fs_builder abld
= bld
.annotate("user clip distances");
674 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
675 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
676 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
677 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
679 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
680 fs_reg u
= userplane
[i
];
681 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
682 output
.reg_offset
= i
& 3;
684 abld
.MUL(output
, outputs
[clip_vertex
], u
);
685 for (int j
= 1; j
< 4; j
++) {
686 u
.nr
= userplane
[i
].nr
+ j
;
687 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
693 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
695 int slot
, urb_offset
, length
;
696 int starting_urb_offset
= 0;
697 const struct brw_vue_prog_data
*vue_prog_data
=
698 (const struct brw_vue_prog_data
*) this->prog_data
;
699 const struct brw_vs_prog_key
*vs_key
=
700 (const struct brw_vs_prog_key
*) this->key
;
701 const GLbitfield64 psiz_mask
=
702 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
703 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
708 if (stage
== MESA_SHADER_TESS_EVAL
)
709 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
711 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
713 /* If we don't have any valid slots to write, just do a minimal urb write
714 * send to terminate the shader. This includes 1 slot of undefined data,
715 * because it's invalid to write 0 data:
717 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
718 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
719 * Write Data Payload:
721 * "The write data payload can be between 1 and 8 message phases long."
723 if (vue_map
->slots_valid
== 0) {
724 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
725 bld
.exec_all().MOV(payload
, urb_handle
);
727 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
734 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
736 fs_reg per_slot_offsets
;
738 if (stage
== MESA_SHADER_GEOMETRY
) {
739 const struct brw_gs_prog_data
*gs_prog_data
=
740 (const struct brw_gs_prog_data
*) this->prog_data
;
742 /* We need to increment the Global Offset to skip over the control data
743 * header and the extra "Vertex Count" field (1 HWord) at the beginning
744 * of the VUE. We're counting in OWords, so the units are doubled.
746 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
747 if (gs_prog_data
->static_vertex_count
== -1)
748 starting_urb_offset
+= 2;
750 /* We also need to use per-slot offsets. The per-slot offset is the
751 * Vertex Count. SIMD8 mode processes 8 different primitives at a
752 * time; each may output a different number of vertices.
754 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
757 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
758 const int output_vertex_size_owords
=
759 gs_prog_data
->output_vertex_size_hwords
* 2;
761 if (gs_vertex_count
.file
== IMM
) {
762 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
765 per_slot_offsets
= vgrf(glsl_type::int_type
);
766 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
767 brw_imm_ud(output_vertex_size_owords
));
772 urb_offset
= starting_urb_offset
;
774 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
775 int varying
= vue_map
->slot_to_varying
[slot
];
777 case VARYING_SLOT_PSIZ
: {
778 /* The point size varying slot is the vue header and is always in the
779 * vue map. But often none of the special varyings that live there
780 * are written and in that case we can skip writing to the vue
781 * header, provided the corresponding state properly clamps the
782 * values further down the pipeline. */
783 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
789 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
790 bld
.MOV(zero
, brw_imm_ud(0u));
792 sources
[length
++] = zero
;
793 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
794 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
796 sources
[length
++] = zero
;
798 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
799 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
801 sources
[length
++] = zero
;
803 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
804 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
806 sources
[length
++] = zero
;
809 case BRW_VARYING_SLOT_NDC
:
810 case VARYING_SLOT_EDGE
:
811 unreachable("unexpected scalar vs output");
815 /* gl_Position is always in the vue map, but isn't always written by
816 * the shader. Other varyings (clip distances) get added to the vue
817 * map but don't always get written. In those cases, the
818 * corresponding this->output[] slot will be invalid we and can skip
819 * the urb write for the varying. If we've already queued up a vue
820 * slot for writing we flush a mlen 5 urb write, otherwise we just
821 * advance the urb_offset.
823 if (varying
== BRW_VARYING_SLOT_PAD
||
824 this->outputs
[varying
].file
== BAD_FILE
) {
832 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
833 (varying
== VARYING_SLOT_COL0
||
834 varying
== VARYING_SLOT_COL1
||
835 varying
== VARYING_SLOT_BFC0
||
836 varying
== VARYING_SLOT_BFC1
)) {
837 /* We need to clamp these guys, so do a saturating MOV into a
838 * temp register and use that for the payload.
840 for (int i
= 0; i
< 4; i
++) {
841 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
842 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
843 set_saturate(true, bld
.MOV(reg
, src
));
844 sources
[length
++] = reg
;
847 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
848 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
849 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
850 sources
[length
++] = brw_imm_d(0);
855 const fs_builder abld
= bld
.annotate("URB write");
857 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
858 * the last slot or if we need to flush (see BAD_FILE varying case
859 * above), emit a URB write send now to flush out the data.
861 int last
= slot
== vue_map
->num_slots
- 1;
862 if (length
== 8 || last
)
865 fs_reg
*payload_sources
=
866 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
867 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
868 BRW_REGISTER_TYPE_F
);
869 payload_sources
[0] = urb_handle
;
871 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
872 payload_sources
[1] = per_slot_offsets
;
874 memcpy(&payload_sources
[header_size
], sources
,
875 length
* sizeof sources
[0]);
877 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
880 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
881 inst
->eot
= last
&& stage
!= MESA_SHADER_GEOMETRY
;
882 inst
->mlen
= length
+ header_size
;
883 inst
->offset
= urb_offset
;
884 urb_offset
= starting_urb_offset
+ slot
+ 1;
892 fs_visitor::emit_cs_terminate()
894 assert(devinfo
->gen
>= 7);
896 /* We are getting the thread ID from the compute shader header */
897 assert(stage
== MESA_SHADER_COMPUTE
);
899 /* We can't directly send from g0, since sends with EOT have to use
900 * g112-127. So, copy it to a virtual register, The register allocator will
901 * make sure it uses the appropriate register range.
903 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
904 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
905 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
907 /* Send a message to the thread spawner to terminate the thread. */
908 fs_inst
*inst
= bld
.exec_all()
909 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
914 fs_visitor::emit_barrier()
916 assert(devinfo
->gen
>= 7);
918 /* We are getting the barrier ID from the compute shader header */
919 assert(stage
== MESA_SHADER_COMPUTE
);
921 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
923 const fs_builder pbld
= bld
.exec_all().group(8, 0);
925 /* Clear the message payload */
926 pbld
.MOV(payload
, brw_imm_ud(0u));
928 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
929 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
930 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(0x0f000000u
));
932 /* Emit a gateway "barrier" message using the payload we set up, followed
933 * by a wait instruction.
935 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
938 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
941 struct brw_stage_prog_data
*prog_data
,
942 struct gl_program
*prog
,
943 const nir_shader
*shader
,
944 unsigned dispatch_width
,
945 int shader_time_index
,
946 const struct brw_vue_map
*input_vue_map
)
947 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
948 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
949 input_vue_map(input_vue_map
),
950 dispatch_width(dispatch_width
),
951 shader_time_index(shader_time_index
),
952 bld(fs_builder(this, dispatch_width
).at_end())
957 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
959 struct brw_gs_compile
*c
,
960 struct brw_gs_prog_data
*prog_data
,
961 const nir_shader
*shader
,
962 int shader_time_index
)
963 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
964 &prog_data
->base
.base
),
965 key(&c
->key
), gs_compile(c
),
966 prog_data(&prog_data
->base
.base
), prog(NULL
),
968 shader_time_index(shader_time_index
),
969 bld(fs_builder(this, dispatch_width
).at_end())
979 case MESA_SHADER_FRAGMENT
:
980 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
982 case MESA_SHADER_VERTEX
:
983 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
985 case MESA_SHADER_TESS_EVAL
:
986 key_tex
= &((const brw_tes_prog_key
*) key
)->tex
;
988 case MESA_SHADER_GEOMETRY
:
989 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
991 case MESA_SHADER_COMPUTE
:
992 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
995 unreachable("unhandled shader stage");
998 this->prog_data
= this->stage_prog_data
;
1000 this->failed
= false;
1001 this->simd16_unsupported
= false;
1002 this->no16_msg
= NULL
;
1004 this->nir_locals
= NULL
;
1005 this->nir_ssa_values
= NULL
;
1007 memset(&this->payload
, 0, sizeof(this->payload
));
1008 memset(this->output_components
, 0, sizeof(this->output_components
));
1009 this->source_depth_to_render_target
= false;
1010 this->runtime_check_aads_emit
= false;
1011 this->first_non_payload_grf
= 0;
1012 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1014 this->virtual_grf_start
= NULL
;
1015 this->virtual_grf_end
= NULL
;
1016 this->live_intervals
= NULL
;
1017 this->regs_live_at_ip
= NULL
;
1020 this->last_scratch
= 0;
1021 this->pull_constant_loc
= NULL
;
1022 this->push_constant_loc
= NULL
;
1024 this->promoted_constants
= 0,
1026 this->spilled_any_registers
= false;
1027 this->do_dual_src
= false;
1029 if (dispatch_width
== 8)
1030 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1033 fs_visitor::~fs_visitor()