2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_optimization.h"
51 #include "../glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
62 this->frag_color
= ir
;
63 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
65 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
66 this->frag_depth
= ir
;
69 if (ir
->mode
== ir_var_in
) {
70 if (!strcmp(ir
->name
, "gl_FragCoord")) {
71 reg
= emit_fragcoord_interpolation(ir
);
72 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
73 reg
= emit_frontfacing_interpolation(ir
);
75 reg
= emit_general_interpolation(ir
);
78 hash_table_insert(this->variable_ht
, reg
, ir
);
82 if (ir
->mode
== ir_var_uniform
) {
83 int param_index
= c
->prog_data
.nr_params
;
85 if (c
->dispatch_width
== 16) {
86 if (!variable_storage(ir
)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
92 if (!strncmp(ir
->name
, "gl_", 3)) {
93 setup_builtin_uniform_values(ir
);
95 setup_uniform_values(ir
->location
, ir
->type
);
98 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
99 reg
->type
= brw_type_for_base_type(ir
->type
);
103 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
105 hash_table_insert(this->variable_ht
, reg
, ir
);
109 fs_visitor::visit(ir_dereference_variable
*ir
)
111 fs_reg
*reg
= variable_storage(ir
->var
);
116 fs_visitor::visit(ir_dereference_record
*ir
)
118 const glsl_type
*struct_type
= ir
->record
->type
;
120 ir
->record
->accept(this);
122 unsigned int offset
= 0;
123 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
124 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
126 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
128 this->result
.reg_offset
+= offset
;
129 this->result
.type
= brw_type_for_base_type(ir
->type
);
133 fs_visitor::visit(ir_dereference_array
*ir
)
138 ir
->array
->accept(this);
139 index
= ir
->array_index
->as_constant();
141 element_size
= type_size(ir
->type
);
142 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 assert(this->result
.file
== UNIFORM
|| this->result
.file
== GRF
);
146 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
148 assert(!"FINISHME: non-constant array element");
152 /* Instruction selection: Produce a MOV.sat instead of
153 * MIN(MAX(val, 0), 1) when possible.
156 fs_visitor::try_emit_saturate(ir_expression
*ir
)
158 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
163 sat_val
->accept(this);
164 fs_reg src
= this->result
;
166 this->result
= fs_reg(this, ir
->type
);
167 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
168 inst
->saturate
= true;
174 fs_visitor::visit(ir_expression
*ir
)
176 unsigned int operand
;
180 assert(ir
->get_num_operands() <= 2);
182 if (try_emit_saturate(ir
))
185 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
186 ir
->operands
[operand
]->accept(this);
187 if (this->result
.file
== BAD_FILE
) {
189 fail("Failed to get tree for expression operand:\n");
190 ir
->operands
[operand
]->accept(&v
);
192 op
[operand
] = this->result
;
194 /* Matrix expression operands should have been broken down to vector
195 * operations already.
197 assert(!ir
->operands
[operand
]->type
->is_matrix());
198 /* And then those vector operands should have been broken down to scalar.
200 assert(!ir
->operands
[operand
]->type
->is_vector());
203 /* Storage for our result. If our result goes into an assignment, it will
204 * just get copy-propagated out, so no worries.
206 this->result
= fs_reg(this, ir
->type
);
208 switch (ir
->operation
) {
209 case ir_unop_logic_not
:
210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
211 * ones complement of the whole register, not just bit 0.
213 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
216 op
[0].negate
= !op
[0].negate
;
217 this->result
= op
[0];
221 op
[0].negate
= false;
222 this->result
= op
[0];
225 temp
= fs_reg(this, ir
->type
);
227 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
229 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
230 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
231 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
232 inst
->predicated
= true;
234 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
235 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
236 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
237 inst
->predicated
= true;
241 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
245 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
248 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
252 assert(!"not reached: should be handled by ir_explog_to_explog2");
255 case ir_unop_sin_reduced
:
256 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
259 case ir_unop_cos_reduced
:
260 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
264 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
267 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
271 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
274 assert(!"not reached: should be handled by ir_sub_to_add_neg");
278 if (ir
->type
->is_integer()) {
279 /* For integer multiplication, the MUL uses the low 16 bits
280 * of one of the operands (src0 on gen6, src1 on gen7). The
281 * MACH accumulates in the contribution of the upper 16 bits
284 * FINISHME: Emit just the MUL if we know an operand is small
287 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
289 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
290 emit(BRW_OPCODE_MACH
, reg_null_d
, op
[0], op
[1]);
291 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(acc
));
293 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
297 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
300 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
304 case ir_binop_greater
:
305 case ir_binop_lequal
:
306 case ir_binop_gequal
:
308 case ir_binop_all_equal
:
309 case ir_binop_nequal
:
310 case ir_binop_any_nequal
:
312 /* original gen4 does implicit conversion before comparison. */
314 temp
.type
= op
[0].type
;
316 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
317 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
318 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
321 case ir_binop_logic_xor
:
322 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
325 case ir_binop_logic_or
:
326 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
329 case ir_binop_logic_and
:
330 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
335 assert(!"not reached: should be handled by brw_fs_channel_expressions");
339 assert(!"not reached: should be handled by lower_noise");
342 case ir_quadop_vector
:
343 assert(!"not reached: should be handled by lower_quadop_vector");
347 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
351 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
355 op
[0].type
= BRW_REGISTER_TYPE_UD
;
356 this->result
= op
[0];
359 op
[0].type
= BRW_REGISTER_TYPE_D
;
360 this->result
= op
[0];
366 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
371 /* original gen4 does implicit conversion before comparison. */
373 temp
.type
= op
[0].type
;
375 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
376 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
377 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
381 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
384 op
[0].negate
= !op
[0].negate
;
385 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
386 this->result
.negate
= true;
389 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
392 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
394 case ir_unop_round_even
:
395 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
399 if (intel
->gen
>= 6) {
400 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
401 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
403 /* Unalias the destination */
404 this->result
= fs_reg(this, ir
->type
);
406 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
407 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
409 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
410 inst
->predicated
= true;
414 if (intel
->gen
>= 6) {
415 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
416 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
418 /* Unalias the destination */
419 this->result
= fs_reg(this, ir
->type
);
421 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
422 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
424 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
425 inst
->predicated
= true;
430 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
433 case ir_unop_bit_not
:
434 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
436 case ir_binop_bit_and
:
437 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
439 case ir_binop_bit_xor
:
440 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
442 case ir_binop_bit_or
:
443 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
447 case ir_binop_lshift
:
448 case ir_binop_rshift
:
449 assert(!"GLSL 1.30 features unsupported");
455 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
456 const glsl_type
*type
, bool predicated
)
458 switch (type
->base_type
) {
459 case GLSL_TYPE_FLOAT
:
463 for (unsigned int i
= 0; i
< type
->components(); i
++) {
464 l
.type
= brw_type_for_base_type(type
);
465 r
.type
= brw_type_for_base_type(type
);
467 if (predicated
|| !l
.equals(&r
)) {
468 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
469 inst
->predicated
= predicated
;
476 case GLSL_TYPE_ARRAY
:
477 for (unsigned int i
= 0; i
< type
->length
; i
++) {
478 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
482 case GLSL_TYPE_STRUCT
:
483 for (unsigned int i
= 0; i
< type
->length
; i
++) {
484 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
489 case GLSL_TYPE_SAMPLER
:
493 assert(!"not reached");
499 fs_visitor::visit(ir_assignment
*ir
)
504 /* FINISHME: arrays on the lhs */
505 ir
->lhs
->accept(this);
508 ir
->rhs
->accept(this);
511 assert(l
.file
!= BAD_FILE
);
512 assert(r
.file
!= BAD_FILE
);
515 emit_bool_to_cond_code(ir
->condition
);
518 if (ir
->lhs
->type
->is_scalar() ||
519 ir
->lhs
->type
->is_vector()) {
520 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
521 if (ir
->write_mask
& (1 << i
)) {
522 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
524 inst
->predicated
= true;
530 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
535 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
546 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
547 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
548 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
549 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
550 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
551 inst
->saturate
= true;
553 coordinate
.reg_offset
++;
555 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
558 if (ir
->op
== ir_tex
) {
559 /* There's no plain shadow compare message, so we use shadow
560 * compare with a bias of 0.0.
562 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
564 } else if (ir
->op
== ir_txb
) {
565 ir
->lod_info
.bias
->accept(this);
566 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
569 assert(ir
->op
== ir_txl
);
570 ir
->lod_info
.lod
->accept(this);
571 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
575 ir
->shadow_comparitor
->accept(this);
576 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
578 } else if (ir
->op
== ir_tex
) {
579 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
580 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
582 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
583 inst
->saturate
= true;
584 coordinate
.reg_offset
++;
586 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
588 } else if (ir
->op
== ir_txd
) {
589 ir
->lod_info
.grad
.dPdx
->accept(this);
590 fs_reg dPdx
= this->result
;
592 ir
->lod_info
.grad
.dPdy
->accept(this);
593 fs_reg dPdy
= this->result
;
595 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
596 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
597 coordinate
.reg_offset
++;
599 /* the slots for u and v are always present, but r is optional */
600 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
603 * dPdx = dudx, dvdx, drdx
604 * dPdy = dudy, dvdy, drdy
606 * 1-arg: Does not exist.
608 * 2-arg: dudx dvdx dudy dvdy
609 * dPdx.x dPdx.y dPdy.x dPdy.y
612 * 3-arg: dudx dvdx drdx dudy dvdy drdy
613 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
616 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
617 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
620 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
622 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
623 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
626 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
627 } else if (ir
->op
== ir_txs
) {
628 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
630 ir
->lod_info
.lod
->accept(this);
631 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
634 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
635 * instructions. We'll need to do SIMD16 here.
638 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
640 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
641 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
642 base_mrf
+ mlen
+ i
* 2),
644 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
645 inst
->saturate
= true;
646 coordinate
.reg_offset
++;
649 /* lod/bias appears after u/v/r. */
652 if (ir
->op
== ir_txb
) {
653 ir
->lod_info
.bias
->accept(this);
654 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
657 ir
->lod_info
.lod
->accept(this);
658 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
662 /* The unused upper half. */
667 /* Now, since we're doing simd16, the return is 2 interleaved
668 * vec4s where the odd-indexed ones are junk. We'll need to move
669 * this weirdness around to the expected layout.
672 const glsl_type
*vec_type
=
673 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
674 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
675 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
676 : BRW_REGISTER_TYPE_F
;
679 fs_inst
*inst
= NULL
;
682 inst
= emit(FS_OPCODE_TEX
, dst
);
685 inst
= emit(FS_OPCODE_TXB
, dst
);
688 inst
= emit(FS_OPCODE_TXL
, dst
);
691 inst
= emit(FS_OPCODE_TXD
, dst
);
694 inst
= emit(FS_OPCODE_TXS
, dst
);
697 assert(!"GLSL 1.30 features unsupported");
700 inst
->base_mrf
= base_mrf
;
702 inst
->header_present
= true;
705 for (int i
= 0; i
< 4; i
++) {
706 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
707 orig_dst
.reg_offset
++;
715 /* gen5's sampler has slots for u, v, r, array index, then optional
716 * parameters like shadow comparitor or LOD bias. If optional
717 * parameters aren't present, those base slots are optional and don't
718 * need to be included in the message.
720 * We don't fill in the unnecessary slots regardless, which may look
721 * surprising in the disassembly.
724 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
729 int reg_width
= c
->dispatch_width
/ 8;
730 bool header_present
= false;
731 const int vector_elements
=
732 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
735 /* The offsets set up by the ir_texture visitor are in the
736 * m1 header, so we can't go headerless.
738 header_present
= true;
743 for (int i
= 0; i
< vector_elements
; i
++) {
744 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
745 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
),
747 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
748 inst
->saturate
= true;
749 coordinate
.reg_offset
++;
751 mlen
+= vector_elements
* reg_width
;
753 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
754 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
756 ir
->shadow_comparitor
->accept(this);
757 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
761 fs_inst
*inst
= NULL
;
764 inst
= emit(FS_OPCODE_TEX
, dst
);
767 ir
->lod_info
.bias
->accept(this);
768 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
769 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
772 inst
= emit(FS_OPCODE_TXB
, dst
);
776 ir
->lod_info
.lod
->accept(this);
777 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
778 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
781 inst
= emit(FS_OPCODE_TXL
, dst
);
784 ir
->lod_info
.grad
.dPdx
->accept(this);
785 fs_reg dPdx
= this->result
;
787 ir
->lod_info
.grad
.dPdy
->accept(this);
788 fs_reg dPdy
= this->result
;
790 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
794 * dPdx = dudx, dvdx, drdx
795 * dPdy = dudy, dvdy, drdy
797 * Load up these values:
798 * - dudx dudy dvdx dvdy drdx drdy
799 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
801 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
802 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
806 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
811 inst
= emit(FS_OPCODE_TXD
, dst
);
815 ir
->lod_info
.lod
->accept(this);
816 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
818 inst
= emit(FS_OPCODE_TXS
, dst
);
821 assert(!"GLSL 1.30 features unsupported");
824 inst
->base_mrf
= base_mrf
;
826 inst
->header_present
= header_present
;
829 fail("Message length >11 disallowed by hardware\n");
836 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
841 int reg_width
= c
->dispatch_width
/ 8;
842 bool header_present
= false;
845 /* The offsets set up by the ir_texture visitor are in the
846 * m1 header, so we can't go headerless.
848 header_present
= true;
853 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
854 ir
->shadow_comparitor
->accept(this);
855 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
859 /* Set up the LOD info */
864 ir
->lod_info
.bias
->accept(this);
865 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
869 ir
->lod_info
.lod
->accept(this);
870 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
874 if (c
->dispatch_width
== 16)
875 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
877 ir
->lod_info
.grad
.dPdx
->accept(this);
878 fs_reg dPdx
= this->result
;
880 ir
->lod_info
.grad
.dPdy
->accept(this);
881 fs_reg dPdy
= this->result
;
883 /* Load dPdx and the coordinate together:
884 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
886 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
887 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
889 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
890 inst
->saturate
= true;
891 coordinate
.reg_offset
++;
894 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
898 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
905 ir
->lod_info
.lod
->accept(this);
906 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
910 assert(!"GLSL 1.30 features unsupported");
914 /* Set up the coordinate (except for TXD where it was done earlier) */
915 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
) {
916 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
917 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
919 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
920 inst
->saturate
= true;
921 coordinate
.reg_offset
++;
926 /* Generate the SEND */
927 fs_inst
*inst
= NULL
;
929 case ir_tex
: inst
= emit(FS_OPCODE_TEX
, dst
); break;
930 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
931 case ir_txl
: inst
= emit(FS_OPCODE_TXL
, dst
); break;
932 case ir_txd
: inst
= emit(FS_OPCODE_TXD
, dst
); break;
933 case ir_txf
: assert(!"TXF unsupported."); break;
934 case ir_txs
: inst
= emit(FS_OPCODE_TXS
, dst
); break;
936 inst
->base_mrf
= base_mrf
;
938 inst
->header_present
= header_present
;
941 fail("Message length >11 disallowed by hardware\n");
948 fs_visitor::visit(ir_texture
*ir
)
950 fs_inst
*inst
= NULL
;
952 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
953 sampler
= fp
->Base
.SamplerUnits
[sampler
];
955 /* Our hardware doesn't have a sample_d_c message, so shadow compares
956 * for textureGrad/TXD need to be emulated with instructions.
958 bool hw_compare_supported
= ir
->op
!= ir_txd
;
959 if (ir
->shadow_comparitor
&& !hw_compare_supported
) {
960 assert(c
->key
.compare_funcs
[sampler
] != GL_NONE
);
961 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
962 if (c
->key
.compare_funcs
[sampler
] == GL_ALWAYS
)
963 return swizzle_result(ir
, fs_reg(1.0f
), sampler
);
964 else if (c
->key
.compare_funcs
[sampler
] == GL_NEVER
)
965 return swizzle_result(ir
, fs_reg(0.0f
), sampler
);
969 ir
->coordinate
->accept(this);
970 fs_reg coordinate
= this->result
;
972 if (ir
->offset
!= NULL
) {
973 ir_constant
*offset
= ir
->offset
->as_constant();
974 assert(offset
!= NULL
);
976 signed char offsets
[3];
977 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
978 offsets
[i
] = (signed char) offset
->value
.i
[i
];
980 /* Combine all three offsets into a single unsigned dword:
982 * bits 11:8 - U Offset (X component)
983 * bits 7:4 - V Offset (Y component)
984 * bits 3:0 - R Offset (Z component)
986 unsigned offset_bits
= 0;
987 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
988 const unsigned shift
= 4 * (2 - i
);
989 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
992 /* Explicitly set up the message header by copying g0 to msg reg m1. */
993 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
994 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
996 /* Then set the offset bits in DWord 2 of the message header. */
998 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
999 BRW_REGISTER_TYPE_UD
)),
1000 fs_reg(brw_imm_uw(offset_bits
)));
1003 /* Should be lowered by do_lower_texture_projection */
1004 assert(!ir
->projector
);
1006 /* The 965 requires the EU to do the normalization of GL rectangle
1007 * texture coordinates. We use the program parameter state
1008 * tracking to get the scaling factor.
1010 if (intel
->gen
< 6 &&
1011 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1012 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1013 int tokens
[STATE_LENGTH
] = {
1015 STATE_TEXRECT_SCALE
,
1021 if (c
->dispatch_width
== 16) {
1022 fail("rectangle scale uniform setup not supported on 16-wide\n");
1023 this->result
= fs_reg(this, ir
->type
);
1027 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1029 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1032 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1033 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1034 GLuint index
= _mesa_add_state_reference(params
,
1035 (gl_state_index
*)tokens
);
1037 this->param_index
[c
->prog_data
.nr_params
] = index
;
1038 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1039 c
->prog_data
.nr_params
++;
1040 this->param_index
[c
->prog_data
.nr_params
] = index
;
1041 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1042 c
->prog_data
.nr_params
++;
1044 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1045 fs_reg src
= coordinate
;
1048 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1051 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1054 /* Writemasking doesn't eliminate channels on SIMD8 texture
1055 * samples, so don't worry about them.
1057 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1059 if (intel
->gen
>= 7) {
1060 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1061 } else if (intel
->gen
>= 5) {
1062 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1064 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1067 /* If there's an offset, we already set up m1. To avoid the implied move,
1068 * use the null register. Otherwise, we want an implied move from g0.
1070 if (ir
->offset
!= NULL
|| !inst
->header_present
)
1071 inst
->src
[0] = reg_undef
;
1073 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1075 inst
->sampler
= sampler
;
1077 if (ir
->shadow_comparitor
) {
1078 if (hw_compare_supported
) {
1079 inst
->shadow_compare
= true;
1081 ir
->shadow_comparitor
->accept(this);
1082 fs_reg ref
= this->result
;
1085 dst
= fs_reg(this, glsl_type::vec4_type
);
1087 /* FINISHME: This needs to be done pre-filtering. */
1089 uint32_t conditional
= 0;
1090 switch (c
->key
.compare_funcs
[sampler
]) {
1091 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1092 case GL_LESS
: conditional
= BRW_CONDITIONAL_L
; break;
1093 case GL_GREATER
: conditional
= BRW_CONDITIONAL_G
; break;
1094 case GL_LEQUAL
: conditional
= BRW_CONDITIONAL_LE
; break;
1095 case GL_GEQUAL
: conditional
= BRW_CONDITIONAL_GE
; break;
1096 case GL_EQUAL
: conditional
= BRW_CONDITIONAL_EQ
; break;
1097 case GL_NOTEQUAL
: conditional
= BRW_CONDITIONAL_NEQ
; break;
1098 default: assert(!"Should not get here: bad shadow compare function");
1101 /* Use conditional moves to load 0 or 1 as the result */
1102 this->current_annotation
= "manual shadow comparison";
1103 for (int i
= 0; i
< 4; i
++) {
1104 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(0.0f
));
1106 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, ref
, value
);
1107 inst
->conditional_mod
= conditional
;
1109 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(1.0f
));
1110 inst
->predicated
= true;
1119 swizzle_result(ir
, dst
, sampler
);
1123 * Swizzle the result of a texture result. This is necessary for
1124 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1127 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1129 this->result
= orig_val
;
1131 if (ir
->type
== glsl_type::float_type
) {
1132 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1133 assert(ir
->sampler
->type
->sampler_shadow
);
1134 } else if (c
->key
.tex_swizzles
[sampler
] != SWIZZLE_NOOP
) {
1135 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1137 for (int i
= 0; i
< 4; i
++) {
1138 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1139 fs_reg l
= swizzled_result
;
1142 if (swiz
== SWIZZLE_ZERO
) {
1143 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1144 } else if (swiz
== SWIZZLE_ONE
) {
1145 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1147 fs_reg r
= orig_val
;
1148 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1149 emit(BRW_OPCODE_MOV
, l
, r
);
1152 this->result
= swizzled_result
;
1157 fs_visitor::visit(ir_swizzle
*ir
)
1159 ir
->val
->accept(this);
1160 fs_reg val
= this->result
;
1162 if (ir
->type
->vector_elements
== 1) {
1163 this->result
.reg_offset
+= ir
->mask
.x
;
1167 fs_reg result
= fs_reg(this, ir
->type
);
1168 this->result
= result
;
1170 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1171 fs_reg channel
= val
;
1189 channel
.reg_offset
+= swiz
;
1190 emit(BRW_OPCODE_MOV
, result
, channel
);
1191 result
.reg_offset
++;
1196 fs_visitor::visit(ir_discard
*ir
)
1198 assert(ir
->condition
== NULL
); /* FINISHME */
1200 emit(FS_OPCODE_DISCARD
);
1201 kill_emitted
= true;
1205 fs_visitor::visit(ir_constant
*ir
)
1207 /* Set this->result to reg at the bottom of the function because some code
1208 * paths will cause this visitor to be applied to other fields. This will
1209 * cause the value stored in this->result to be modified.
1211 * Make reg constant so that it doesn't get accidentally modified along the
1212 * way. Yes, I actually had this problem. :(
1214 const fs_reg
reg(this, ir
->type
);
1215 fs_reg dst_reg
= reg
;
1217 if (ir
->type
->is_array()) {
1218 const unsigned size
= type_size(ir
->type
->fields
.array
);
1220 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1221 ir
->array_elements
[i
]->accept(this);
1222 fs_reg src_reg
= this->result
;
1224 dst_reg
.type
= src_reg
.type
;
1225 for (unsigned j
= 0; j
< size
; j
++) {
1226 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1227 src_reg
.reg_offset
++;
1228 dst_reg
.reg_offset
++;
1231 } else if (ir
->type
->is_record()) {
1232 foreach_list(node
, &ir
->components
) {
1233 ir_instruction
*const field
= (ir_instruction
*) node
;
1234 const unsigned size
= type_size(field
->type
);
1236 field
->accept(this);
1237 fs_reg src_reg
= this->result
;
1239 dst_reg
.type
= src_reg
.type
;
1240 for (unsigned j
= 0; j
< size
; j
++) {
1241 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1242 src_reg
.reg_offset
++;
1243 dst_reg
.reg_offset
++;
1247 const unsigned size
= type_size(ir
->type
);
1249 for (unsigned i
= 0; i
< size
; i
++) {
1250 switch (ir
->type
->base_type
) {
1251 case GLSL_TYPE_FLOAT
:
1252 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1254 case GLSL_TYPE_UINT
:
1255 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1258 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1260 case GLSL_TYPE_BOOL
:
1261 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1264 assert(!"Non-float/uint/int/bool constant");
1266 dst_reg
.reg_offset
++;
1274 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1276 ir_expression
*expr
= ir
->as_expression();
1282 assert(expr
->get_num_operands() <= 2);
1283 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1284 assert(expr
->operands
[i
]->type
->is_scalar());
1286 expr
->operands
[i
]->accept(this);
1287 op
[i
] = this->result
;
1290 switch (expr
->operation
) {
1291 case ir_unop_logic_not
:
1292 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1293 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1296 case ir_binop_logic_xor
:
1297 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1298 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1301 case ir_binop_logic_or
:
1302 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1303 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1306 case ir_binop_logic_and
:
1307 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1308 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1312 if (intel
->gen
>= 6) {
1313 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1315 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1317 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1321 if (intel
->gen
>= 6) {
1322 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1324 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1326 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1329 case ir_binop_greater
:
1330 case ir_binop_gequal
:
1332 case ir_binop_lequal
:
1333 case ir_binop_equal
:
1334 case ir_binop_all_equal
:
1335 case ir_binop_nequal
:
1336 case ir_binop_any_nequal
:
1337 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1338 inst
->conditional_mod
=
1339 brw_conditional_for_comparison(expr
->operation
);
1343 assert(!"not reached");
1344 fail("bad cond code\n");
1352 if (intel
->gen
>= 6) {
1353 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1354 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1356 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1357 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1362 * Emit a gen6 IF statement with the comparison folded into the IF
1366 fs_visitor::emit_if_gen6(ir_if
*ir
)
1368 ir_expression
*expr
= ir
->condition
->as_expression();
1375 assert(expr
->get_num_operands() <= 2);
1376 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1377 assert(expr
->operands
[i
]->type
->is_scalar());
1379 expr
->operands
[i
]->accept(this);
1380 op
[i
] = this->result
;
1383 switch (expr
->operation
) {
1384 case ir_unop_logic_not
:
1385 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1386 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1389 case ir_binop_logic_xor
:
1390 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1391 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1394 case ir_binop_logic_or
:
1395 temp
= fs_reg(this, glsl_type::bool_type
);
1396 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1397 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1398 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1401 case ir_binop_logic_and
:
1402 temp
= fs_reg(this, glsl_type::bool_type
);
1403 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1404 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1409 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1410 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1414 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1418 case ir_binop_greater
:
1419 case ir_binop_gequal
:
1421 case ir_binop_lequal
:
1422 case ir_binop_equal
:
1423 case ir_binop_all_equal
:
1424 case ir_binop_nequal
:
1425 case ir_binop_any_nequal
:
1426 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1427 inst
->conditional_mod
=
1428 brw_conditional_for_comparison(expr
->operation
);
1431 assert(!"not reached");
1432 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1433 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1434 fail("bad condition\n");
1440 ir
->condition
->accept(this);
1442 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1443 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1447 fs_visitor::visit(ir_if
*ir
)
1451 if (intel
->gen
!= 6 && c
->dispatch_width
== 16) {
1452 fail("Can't support (non-uniform) control flow on 16-wide\n");
1455 /* Don't point the annotation at the if statement, because then it plus
1456 * the then and else blocks get printed.
1458 this->base_ir
= ir
->condition
;
1460 if (intel
->gen
== 6) {
1463 emit_bool_to_cond_code(ir
->condition
);
1465 inst
= emit(BRW_OPCODE_IF
);
1466 inst
->predicated
= true;
1469 foreach_list(node
, &ir
->then_instructions
) {
1470 ir_instruction
*ir
= (ir_instruction
*)node
;
1476 if (!ir
->else_instructions
.is_empty()) {
1477 emit(BRW_OPCODE_ELSE
);
1479 foreach_list(node
, &ir
->else_instructions
) {
1480 ir_instruction
*ir
= (ir_instruction
*)node
;
1487 emit(BRW_OPCODE_ENDIF
);
1491 fs_visitor::visit(ir_loop
*ir
)
1493 fs_reg counter
= reg_undef
;
1495 if (c
->dispatch_width
== 16) {
1496 fail("Can't support (non-uniform) control flow on 16-wide\n");
1500 this->base_ir
= ir
->counter
;
1501 ir
->counter
->accept(this);
1502 counter
= *(variable_storage(ir
->counter
));
1505 this->base_ir
= ir
->from
;
1506 ir
->from
->accept(this);
1508 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1512 emit(BRW_OPCODE_DO
);
1515 this->base_ir
= ir
->to
;
1516 ir
->to
->accept(this);
1518 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1519 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1521 inst
= emit(BRW_OPCODE_BREAK
);
1522 inst
->predicated
= true;
1525 foreach_list(node
, &ir
->body_instructions
) {
1526 ir_instruction
*ir
= (ir_instruction
*)node
;
1532 if (ir
->increment
) {
1533 this->base_ir
= ir
->increment
;
1534 ir
->increment
->accept(this);
1535 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1538 emit(BRW_OPCODE_WHILE
);
1542 fs_visitor::visit(ir_loop_jump
*ir
)
1545 case ir_loop_jump::jump_break
:
1546 emit(BRW_OPCODE_BREAK
);
1548 case ir_loop_jump::jump_continue
:
1549 emit(BRW_OPCODE_CONTINUE
);
1555 fs_visitor::visit(ir_call
*ir
)
1557 assert(!"FINISHME");
1561 fs_visitor::visit(ir_return
*ir
)
1563 assert(!"FINISHME");
1567 fs_visitor::visit(ir_function
*ir
)
1569 /* Ignore function bodies other than main() -- we shouldn't see calls to
1570 * them since they should all be inlined before we get to ir_to_mesa.
1572 if (strcmp(ir
->name
, "main") == 0) {
1573 const ir_function_signature
*sig
;
1576 sig
= ir
->matching_signature(&empty
);
1580 foreach_list(node
, &sig
->body
) {
1581 ir_instruction
*ir
= (ir_instruction
*)node
;
1590 fs_visitor::visit(ir_function_signature
*ir
)
1592 assert(!"not reached");
1597 fs_visitor::emit(fs_inst inst
)
1599 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1602 if (force_uncompressed_stack
> 0)
1603 list_inst
->force_uncompressed
= true;
1604 else if (force_sechalf_stack
> 0)
1605 list_inst
->force_sechalf
= true;
1607 list_inst
->annotation
= this->current_annotation
;
1608 list_inst
->ir
= this->base_ir
;
1610 this->instructions
.push_tail(list_inst
);
1615 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1617 fs_visitor::emit_dummy_fs()
1619 /* Everyone's favorite color. */
1620 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1621 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1622 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1623 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1626 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1627 write
->base_mrf
= 2;
1630 /* The register location here is relative to the start of the URB
1631 * data. It will get adjusted to be a real location before
1632 * generate_code() time.
1635 fs_visitor::interp_reg(int location
, int channel
)
1637 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1638 int stride
= (channel
& 1) * 4;
1640 assert(urb_setup
[location
] != -1);
1642 return brw_vec1_grf(regnr
, stride
);
1645 /** Emits the interpolation for the varying inputs. */
1647 fs_visitor::emit_interpolation_setup_gen4()
1649 this->current_annotation
= "compute pixel centers";
1650 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1651 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1652 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1653 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1655 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1656 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1658 this->current_annotation
= "compute pixel deltas from v0";
1660 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1661 this->delta_y
= this->delta_x
;
1662 this->delta_y
.reg_offset
++;
1664 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1665 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1667 emit(BRW_OPCODE_ADD
, this->delta_x
,
1668 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1669 emit(BRW_OPCODE_ADD
, this->delta_y
,
1670 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1672 this->current_annotation
= "compute pos.w and 1/pos.w";
1673 /* Compute wpos.w. It's always in our setup, since it's needed to
1674 * interpolate the other attributes.
1676 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1677 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1678 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1679 /* Compute the pixel 1/W value from wpos.w. */
1680 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1681 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1682 this->current_annotation
= NULL
;
1685 /** Emits the interpolation for the varying inputs. */
1687 fs_visitor::emit_interpolation_setup_gen6()
1689 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1691 /* If the pixel centers end up used, the setup is the same as for gen4. */
1692 this->current_annotation
= "compute pixel centers";
1693 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1694 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1695 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1696 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1697 emit(BRW_OPCODE_ADD
,
1699 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1700 fs_reg(brw_imm_v(0x10101010)));
1701 emit(BRW_OPCODE_ADD
,
1703 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1704 fs_reg(brw_imm_v(0x11001100)));
1706 /* As of gen6, we can no longer mix float and int sources. We have
1707 * to turn the integer pixel centers into floats for their actual
1710 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1711 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1712 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1713 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1715 this->current_annotation
= "compute pos.w";
1716 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1717 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1718 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1720 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1721 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1723 this->current_annotation
= NULL
;
1727 fs_visitor::emit_color_write(int index
, int first_color_mrf
, fs_reg color
)
1729 int reg_width
= c
->dispatch_width
/ 8;
1732 if (c
->dispatch_width
== 8 || intel
->gen
== 6) {
1733 /* SIMD8 write looks like:
1739 * gen6 SIMD16 DP write looks like:
1749 inst
= emit(BRW_OPCODE_MOV
,
1750 fs_reg(MRF
, first_color_mrf
+ index
* reg_width
),
1752 inst
->saturate
= c
->key
.clamp_fragment_color
;
1754 /* pre-gen6 SIMD16 single source DP write looks like:
1764 if (brw
->has_compr4
) {
1765 /* By setting the high bit of the MRF register number, we
1766 * indicate that we want COMPR4 mode - instead of doing the
1767 * usual destination + 1 for the second half we get
1770 inst
= emit(BRW_OPCODE_MOV
,
1771 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
),
1773 inst
->saturate
= c
->key
.clamp_fragment_color
;
1775 push_force_uncompressed();
1776 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
),
1778 inst
->saturate
= c
->key
.clamp_fragment_color
;
1779 pop_force_uncompressed();
1781 push_force_sechalf();
1782 color
.sechalf
= true;
1783 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4),
1785 inst
->saturate
= c
->key
.clamp_fragment_color
;
1786 pop_force_sechalf();
1787 color
.sechalf
= false;
1793 fs_visitor::emit_fb_writes()
1795 this->current_annotation
= "FB write header";
1796 GLboolean header_present
= GL_TRUE
;
1799 int reg_width
= c
->dispatch_width
/ 8;
1801 if (intel
->gen
>= 6 &&
1802 !this->kill_emitted
&&
1803 c
->key
.nr_color_regions
== 1) {
1804 header_present
= false;
1807 if (header_present
) {
1812 if (c
->aa_dest_stencil_reg
) {
1813 push_force_uncompressed();
1814 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1815 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1816 pop_force_uncompressed();
1819 /* Reserve space for color. It'll be filled in per MRT below. */
1821 nr
+= 4 * reg_width
;
1823 if (c
->source_depth_to_render_target
) {
1824 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1825 /* For outputting oDepth on gen6, SIMD8 writes have to be
1826 * used. This would require 8-wide moves of each half to
1827 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1828 * Just bail on doing so for now.
1830 fail("Missing support for simd16 depth writes on gen6\n");
1833 if (c
->computes_depth
) {
1834 /* Hand over gl_FragDepth. */
1835 assert(this->frag_depth
);
1836 fs_reg depth
= *(variable_storage(this->frag_depth
));
1838 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1840 /* Pass through the payload depth. */
1841 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1842 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1847 if (c
->dest_depth_reg
) {
1848 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1849 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1853 fs_reg color
= reg_undef
;
1854 if (this->frag_color
)
1855 color
= *(variable_storage(this->frag_color
));
1856 else if (this->frag_data
) {
1857 color
= *(variable_storage(this->frag_data
));
1858 color
.type
= BRW_REGISTER_TYPE_F
;
1861 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1862 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1863 "FB write target %d",
1865 if (this->frag_color
|| this->frag_data
) {
1866 for (int i
= 0; i
< 4; i
++) {
1867 emit_color_write(i
, color_mrf
, color
);
1872 if (this->frag_color
)
1873 color
.reg_offset
-= 4;
1875 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1876 inst
->target
= target
;
1877 inst
->base_mrf
= base_mrf
;
1878 inst
->mlen
= nr
- base_mrf
;
1879 if (target
== c
->key
.nr_color_regions
- 1)
1881 inst
->header_present
= header_present
;
1884 if (c
->key
.nr_color_regions
== 0) {
1885 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
1886 /* If the alpha test is enabled but there's no color buffer,
1887 * we still need to send alpha out the pipeline to our null
1890 color
.reg_offset
+= 3;
1891 emit_color_write(3, color_mrf
, color
);
1894 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1895 inst
->base_mrf
= base_mrf
;
1896 inst
->mlen
= nr
- base_mrf
;
1898 inst
->header_present
= header_present
;
1901 this->current_annotation
= NULL
;