2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation();
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
86 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
87 this->sample_mask
= *reg
;
89 /* gl_FragData or a user-defined FS output */
90 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
91 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
94 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
95 : ir
->type
->vector_elements
;
97 /* General color output. */
98 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
99 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
100 this->outputs
[output
] = *reg
;
101 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
102 this->output_components
[output
] = vector_elements
;
105 } else if (ir
->data
.mode
== ir_var_uniform
) {
106 int param_index
= uniforms
;
108 /* Thanks to the lower_ubo_reference pass, we will see only
109 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
110 * variables, so no need for them to be in variable_ht.
112 * Atomic counters take no uniform storage, no need to do
115 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
118 if (dispatch_width
== 16) {
119 if (!variable_storage(ir
)) {
120 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
125 param_size
[param_index
] = type_size(ir
->type
);
126 if (!strncmp(ir
->name
, "gl_", 3)) {
127 setup_builtin_uniform_values(ir
);
129 setup_uniform_values(ir
);
132 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
133 reg
->type
= brw_type_for_base_type(ir
->type
);
135 } else if (ir
->data
.mode
== ir_var_system_value
) {
136 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
137 reg
= emit_samplepos_setup();
138 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
139 reg
= emit_sampleid_setup(ir
);
140 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
141 assert(brw
->gen
>= 7);
143 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
144 BRW_REGISTER_TYPE_D
));
149 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
151 hash_table_insert(this->variable_ht
, reg
, ir
);
155 fs_visitor::visit(ir_dereference_variable
*ir
)
157 fs_reg
*reg
= variable_storage(ir
->var
);
160 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
161 this->result
= fs_reg(reg_null_d
);
168 fs_visitor::visit(ir_dereference_record
*ir
)
170 const glsl_type
*struct_type
= ir
->record
->type
;
172 ir
->record
->accept(this);
174 unsigned int offset
= 0;
175 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
176 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
178 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
180 this->result
.reg_offset
+= offset
;
181 this->result
.type
= brw_type_for_base_type(ir
->type
);
185 fs_visitor::visit(ir_dereference_array
*ir
)
187 ir_constant
*constant_index
;
189 int element_size
= type_size(ir
->type
);
191 constant_index
= ir
->array_index
->as_constant();
193 ir
->array
->accept(this);
195 src
.type
= brw_type_for_base_type(ir
->type
);
197 if (constant_index
) {
198 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
199 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
201 /* Variable index array dereference. We attach the variable index
202 * component to the reg as a pointer to a register containing the
203 * offset. Currently only uniform arrays are supported in this patch,
204 * and that reladdr pointer is resolved by
205 * move_uniform_array_access_to_pull_constants(). All other array types
206 * are lowered by lower_variable_index_to_cond_assign().
208 ir
->array_index
->accept(this);
211 index_reg
= fs_reg(this, glsl_type::int_type
);
212 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
215 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
218 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
219 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
225 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
229 !x
.is_valid_3src() ||
230 !y
.is_valid_3src() ||
231 !a
.is_valid_3src()) {
232 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
233 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
234 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
235 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
237 emit(MUL(y_times_a
, y
, a
));
239 fs_reg negative_a
= a
;
240 negative_a
.negate
= !a
.negate
;
241 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
242 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
244 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
246 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
247 * we need to reorder the operands.
249 emit(LRP(dst
, a
, y
, x
));
254 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
255 const fs_reg
&src0
, const fs_reg
&src1
)
260 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
261 inst
->conditional_mod
= conditionalmod
;
263 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
265 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
266 inst
->predicate
= BRW_PREDICATE_NORMAL
;
271 fs_visitor::try_emit_saturate(ir_expression
*ir
)
273 if (ir
->operation
!= ir_unop_saturate
)
276 ir_rvalue
*sat_val
= ir
->operands
[0];
278 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
280 sat_val
->accept(this);
281 fs_reg src
= this->result
;
283 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
285 /* If the last instruction from our accept() generated our
286 * src, just set the saturate flag instead of emmitting a separate mov.
288 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
289 if (modify
&& modify
->regs_written
== 1 && modify
->can_do_saturate()) {
290 modify
->saturate
= true;
299 fs_visitor::try_emit_mad(ir_expression
*ir
)
301 /* 3-src instructions were introduced in gen6. */
305 /* MAD can only handle floating-point data. */
306 if (ir
->type
!= glsl_type::float_type
)
309 ir_rvalue
*nonmul
= ir
->operands
[1];
310 ir_expression
*mul
= ir
->operands
[0]->as_expression();
312 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
313 nonmul
= ir
->operands
[0];
314 mul
= ir
->operands
[1]->as_expression();
316 if (!mul
|| mul
->operation
!= ir_binop_mul
)
320 if (nonmul
->as_constant() ||
321 mul
->operands
[0]->as_constant() ||
322 mul
->operands
[1]->as_constant())
325 nonmul
->accept(this);
326 fs_reg src0
= this->result
;
328 mul
->operands
[0]->accept(this);
329 fs_reg src1
= this->result
;
331 mul
->operands
[1]->accept(this);
332 fs_reg src2
= this->result
;
334 this->result
= fs_reg(this, ir
->type
);
335 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
341 pack_pixel_offset(float x
)
343 /* Clamp upper end of the range to +7/16. See explanation in non-constant
344 * offset case below. */
345 int n
= MIN2((int)(x
* 16), 7);
350 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
352 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
353 * 8 channels at a time, same as the barycentric coords presented in
354 * the FS payload. this requires a bit of extra work to support.
356 no16("interpolate_at_* not yet supported in SIMD16 mode.");
358 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
359 ir_swizzle
* swiz
= NULL
;
361 /* the api does not allow a swizzle here, but the varying packing code
362 * may have pushed one into here.
364 swiz
= ir
->operands
[0]->as_swizzle();
366 deref
= swiz
->val
->as_dereference();
369 ir_variable
* var
= deref
->variable_referenced();
372 /* 1. collect interpolation factors */
374 fs_reg dst_x
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
375 fs_reg dst_y
= dst_x
;
378 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
379 * even when there is no payload. in the per-slot offset case, we'll replace this with
380 * the proper source data. */
381 fs_reg src
= fs_reg(this, glsl_type::float_type
);
382 int mlen
= 1; /* one reg unless overriden */
383 int reg_width
= dispatch_width
/ 8;
386 switch (ir
->operation
) {
387 case ir_unop_interpolate_at_centroid
:
388 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
391 case ir_binop_interpolate_at_sample
: {
392 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
393 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
395 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
396 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
400 case ir_binop_interpolate_at_offset
: {
401 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
403 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
404 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
405 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
408 /* pack the operands: hw wants offsets as 4 bit signed ints */
409 ir
->operands
[1]->accept(this);
410 src
= fs_reg(this, glsl_type::ivec2_type
);
412 for (int i
= 0; i
< 2; i
++) {
413 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
414 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
415 emit(MOV(src2
, temp
)); /* float to int */
417 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
418 * that we support a maximum offset of +0.5, which isn't representable
419 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
420 * which is the opposite of what the shader author wanted.
422 * This is legal due to ARB_gpu_shader5's quantization rules:
424 * "Not all values of <offset> may be supported; x and y offsets may
425 * be rounded to fixed-point values with the number of fraction bits
426 * given by the implementation-dependent constant
427 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
430 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
431 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
434 this->result
.reg_offset
++;
437 mlen
= 2 * reg_width
;
438 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
445 unreachable("not reached");
449 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
450 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
451 INTERP_QUALIFIER_NOPERSPECTIVE
;
453 /* 2. emit linterp */
455 fs_reg
res(this, ir
->type
);
458 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
459 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
460 emit(FS_OPCODE_LINTERP
, res
,
462 fs_reg(interp_reg(var
->data
.location
, ch
)));
468 fs_visitor::visit(ir_expression
*ir
)
470 unsigned int operand
;
474 assert(ir
->get_num_operands() <= 3);
476 if (try_emit_saturate(ir
))
479 /* Deal with the real oddball stuff first */
480 switch (ir
->operation
) {
482 if (try_emit_mad(ir
))
486 case ir_unop_interpolate_at_centroid
:
487 case ir_binop_interpolate_at_offset
:
488 case ir_binop_interpolate_at_sample
:
489 emit_interpolate_expression(ir
);
496 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
497 ir
->operands
[operand
]->accept(this);
498 if (this->result
.file
== BAD_FILE
) {
499 fail("Failed to get tree for expression operand:\n");
500 ir
->operands
[operand
]->fprint(stderr
);
501 fprintf(stderr
, "\n");
503 assert(this->result
.is_valid_3src());
504 op
[operand
] = this->result
;
506 /* Matrix expression operands should have been broken down to vector
507 * operations already.
509 assert(!ir
->operands
[operand
]->type
->is_matrix());
510 /* And then those vector operands should have been broken down to scalar.
512 assert(!ir
->operands
[operand
]->type
->is_vector());
515 /* Storage for our result. If our result goes into an assignment, it will
516 * just get copy-propagated out, so no worries.
518 this->result
= fs_reg(this, ir
->type
);
520 switch (ir
->operation
) {
521 case ir_unop_logic_not
:
522 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
523 emit(NOT(this->result
, op
[0]));
525 emit(XOR(this->result
, op
[0], fs_reg(1)));
529 op
[0].negate
= !op
[0].negate
;
530 emit(MOV(this->result
, op
[0]));
534 op
[0].negate
= false;
535 emit(MOV(this->result
, op
[0]));
538 if (ir
->type
->is_float()) {
539 /* AND(val, 0x80000000) gives the sign bit.
541 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
544 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
546 op
[0].type
= BRW_REGISTER_TYPE_UD
;
547 this->result
.type
= BRW_REGISTER_TYPE_UD
;
548 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
550 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
551 inst
->predicate
= BRW_PREDICATE_NORMAL
;
553 this->result
.type
= BRW_REGISTER_TYPE_F
;
555 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
556 * -> non-negative val generates 0x00000000.
557 * Predicated OR sets 1 if val is positive.
559 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
561 emit(ASR(this->result
, op
[0], fs_reg(31)));
563 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
564 inst
->predicate
= BRW_PREDICATE_NORMAL
;
568 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
572 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
575 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
579 unreachable("not reached: should be handled by ir_explog_to_explog2");
581 case ir_unop_sin_reduced
:
582 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
585 case ir_unop_cos_reduced
:
586 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
590 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
592 case ir_unop_dFdx_coarse
:
593 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
595 case ir_unop_dFdx_fine
:
596 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
599 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
601 case ir_unop_dFdy_coarse
:
602 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
604 case ir_unop_dFdy_fine
:
605 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
609 emit(ADD(this->result
, op
[0], op
[1]));
612 unreachable("not reached: should be handled by ir_sub_to_add_neg");
615 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
616 /* For integer multiplication, the MUL uses the low 16 bits
617 * of one of the operands (src0 on gen6, src1 on gen7). The
618 * MACH accumulates in the contribution of the upper 16 bits
621 if (ir
->operands
[0]->is_uint16_constant()) {
623 emit(MUL(this->result
, op
[0], op
[1]));
625 emit(MUL(this->result
, op
[1], op
[0]));
626 } else if (ir
->operands
[1]->is_uint16_constant()) {
628 emit(MUL(this->result
, op
[1], op
[0]));
630 emit(MUL(this->result
, op
[0], op
[1]));
633 no16("SIMD16 explicit accumulator operands unsupported\n");
635 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
637 emit(MUL(acc
, op
[0], op
[1]));
638 emit(MACH(reg_null_d
, op
[0], op
[1]));
639 emit(MOV(this->result
, fs_reg(acc
)));
642 emit(MUL(this->result
, op
[0], op
[1]));
645 case ir_binop_imul_high
: {
647 no16("SIMD16 explicit accumulator operands unsupported\n");
649 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
651 emit(MUL(acc
, op
[0], op
[1]));
652 emit(MACH(this->result
, op
[0], op
[1]));
656 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
657 assert(ir
->type
->is_integer());
658 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
660 case ir_binop_carry
: {
662 no16("SIMD16 explicit accumulator operands unsupported\n");
664 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
666 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
667 emit(MOV(this->result
, fs_reg(acc
)));
670 case ir_binop_borrow
: {
672 no16("SIMD16 explicit accumulator operands unsupported\n");
674 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
676 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
677 emit(MOV(this->result
, fs_reg(acc
)));
681 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
682 assert(ir
->type
->is_integer());
683 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
687 case ir_binop_greater
:
688 case ir_binop_lequal
:
689 case ir_binop_gequal
:
691 case ir_binop_all_equal
:
692 case ir_binop_nequal
:
693 case ir_binop_any_nequal
:
694 if (ctx
->Const
.UniformBooleanTrue
== 1) {
695 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
696 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
699 emit(CMP(this->result
, op
[0], op
[1],
700 brw_conditional_for_comparison(ir
->operation
)));
703 case ir_binop_logic_xor
:
704 emit(XOR(this->result
, op
[0], op
[1]));
707 case ir_binop_logic_or
:
708 emit(OR(this->result
, op
[0], op
[1]));
711 case ir_binop_logic_and
:
712 emit(AND(this->result
, op
[0], op
[1]));
717 unreachable("not reached: should be handled by brw_fs_channel_expressions");
720 unreachable("not reached: should be handled by lower_noise");
722 case ir_quadop_vector
:
723 unreachable("not reached: should be handled by lower_quadop_vector");
725 case ir_binop_vector_extract
:
726 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
728 case ir_triop_vector_insert
:
729 unreachable("not reached: should be handled by lower_vector_insert()");
732 unreachable("not reached: should be handled by ldexp_to_arith()");
735 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
739 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
742 case ir_unop_bitcast_i2f
:
743 case ir_unop_bitcast_u2f
:
744 op
[0].type
= BRW_REGISTER_TYPE_F
;
745 this->result
= op
[0];
748 case ir_unop_bitcast_f2u
:
749 op
[0].type
= BRW_REGISTER_TYPE_UD
;
750 this->result
= op
[0];
753 case ir_unop_bitcast_f2i
:
754 op
[0].type
= BRW_REGISTER_TYPE_D
;
755 this->result
= op
[0];
761 emit(MOV(this->result
, op
[0]));
765 emit(AND(this->result
, op
[0], fs_reg(1)));
768 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
769 op
[0].type
= BRW_REGISTER_TYPE_UD
;
770 this->result
.type
= BRW_REGISTER_TYPE_UD
;
771 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
772 this->result
.type
= BRW_REGISTER_TYPE_F
;
774 temp
= fs_reg(this, glsl_type::int_type
);
775 emit(AND(temp
, op
[0], fs_reg(1)));
776 emit(MOV(this->result
, temp
));
781 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
784 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
788 emit(RNDZ(this->result
, op
[0]));
791 op
[0].negate
= !op
[0].negate
;
792 emit(RNDD(this->result
, op
[0]));
793 this->result
.negate
= true;
796 emit(RNDD(this->result
, op
[0]));
799 emit(FRC(this->result
, op
[0]));
801 case ir_unop_round_even
:
802 emit(RNDE(this->result
, op
[0]));
807 resolve_ud_negate(&op
[0]);
808 resolve_ud_negate(&op
[1]);
809 emit_minmax(ir
->operation
== ir_binop_min
?
810 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
811 this->result
, op
[0], op
[1]);
813 case ir_unop_pack_snorm_2x16
:
814 case ir_unop_pack_snorm_4x8
:
815 case ir_unop_pack_unorm_2x16
:
816 case ir_unop_pack_unorm_4x8
:
817 case ir_unop_unpack_snorm_2x16
:
818 case ir_unop_unpack_snorm_4x8
:
819 case ir_unop_unpack_unorm_2x16
:
820 case ir_unop_unpack_unorm_4x8
:
821 case ir_unop_unpack_half_2x16
:
822 case ir_unop_pack_half_2x16
:
823 unreachable("not reached: should be handled by lower_packing_builtins");
824 case ir_unop_unpack_half_2x16_split_x
:
825 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
827 case ir_unop_unpack_half_2x16_split_y
:
828 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
831 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
834 case ir_unop_bitfield_reverse
:
835 emit(BFREV(this->result
, op
[0]));
837 case ir_unop_bit_count
:
838 emit(CBIT(this->result
, op
[0]));
840 case ir_unop_find_msb
:
841 temp
= fs_reg(this, glsl_type::uint_type
);
842 emit(FBH(temp
, op
[0]));
844 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
845 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
846 * subtract the result from 31 to convert the MSB count into an LSB count.
849 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
850 emit(MOV(this->result
, temp
));
851 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
854 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
855 inst
->predicate
= BRW_PREDICATE_NORMAL
;
857 case ir_unop_find_lsb
:
858 emit(FBL(this->result
, op
[0]));
860 case ir_unop_saturate
:
861 inst
= emit(MOV(this->result
, op
[0]));
862 inst
->saturate
= true;
864 case ir_triop_bitfield_extract
:
865 /* Note that the instruction's argument order is reversed from GLSL
868 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
871 emit(BFI1(this->result
, op
[0], op
[1]));
874 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
876 case ir_quadop_bitfield_insert
:
877 unreachable("not reached: should be handled by "
878 "lower_instructions::bitfield_insert_to_bfm_bfi");
880 case ir_unop_bit_not
:
881 emit(NOT(this->result
, op
[0]));
883 case ir_binop_bit_and
:
884 emit(AND(this->result
, op
[0], op
[1]));
886 case ir_binop_bit_xor
:
887 emit(XOR(this->result
, op
[0], op
[1]));
889 case ir_binop_bit_or
:
890 emit(OR(this->result
, op
[0], op
[1]));
893 case ir_binop_lshift
:
894 emit(SHL(this->result
, op
[0], op
[1]));
897 case ir_binop_rshift
:
898 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
899 emit(ASR(this->result
, op
[0], op
[1]));
901 emit(SHR(this->result
, op
[0], op
[1]));
903 case ir_binop_pack_half_2x16_split
:
904 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
906 case ir_binop_ubo_load
: {
907 /* This IR node takes a constant uniform block and a constant or
908 * variable byte offset within the block and loads a vector from that.
910 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
911 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
914 if (const_uniform_block
) {
915 /* The block index is a constant, so just emit the binding table entry
918 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
919 const_uniform_block
->value
.u
[0]);
921 /* The block index is not a constant. Evaluate the index expression
922 * per-channel and add the base UBO index; the generator will select
923 * a value from any live channel.
925 surf_index
= fs_reg(this, glsl_type::uint_type
);
926 emit(ADD(surf_index
, op
[0],
927 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
928 ->force_writemask_all
= true;
930 /* Assume this may touch any UBO. It would be nice to provide
931 * a tighter bound, but the array information is already lowered away.
933 brw_mark_surface_used(&prog_data
->base
,
934 stage_prog_data
->binding_table
.ubo_start
+
935 shader_prog
->NumUniformBlocks
- 1);
939 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
940 packed_consts
.type
= result
.type
;
942 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
943 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
944 packed_consts
, surf_index
, const_offset_reg
));
946 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
947 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
949 /* The std140 packing rules don't allow vectors to cross 16-byte
950 * boundaries, and a reg is 32 bytes.
952 assert(packed_consts
.subreg_offset
< 32);
954 /* UBO bools are any nonzero value. We consider bools to be
955 * values with the low bit set to 1. Convert them using CMP.
957 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
958 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
960 emit(MOV(result
, packed_consts
));
966 /* Turn the byte offset into a dword offset. */
967 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
968 emit(SHR(base_offset
, op
[1], fs_reg(2)));
970 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
971 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
974 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
975 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
981 result
.reg_offset
= 0;
986 /* Note that the instruction's argument order is reversed from GLSL
989 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
993 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
997 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
998 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
999 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1002 case ir_unop_interpolate_at_centroid
:
1003 case ir_binop_interpolate_at_offset
:
1004 case ir_binop_interpolate_at_sample
:
1005 unreachable("already handled above");
1011 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1012 const glsl_type
*type
, bool predicated
)
1014 switch (type
->base_type
) {
1015 case GLSL_TYPE_FLOAT
:
1016 case GLSL_TYPE_UINT
:
1018 case GLSL_TYPE_BOOL
:
1019 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1020 l
.type
= brw_type_for_base_type(type
);
1021 r
.type
= brw_type_for_base_type(type
);
1023 if (predicated
|| !l
.equals(r
)) {
1024 fs_inst
*inst
= emit(MOV(l
, r
));
1025 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1032 case GLSL_TYPE_ARRAY
:
1033 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1034 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1038 case GLSL_TYPE_STRUCT
:
1039 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1040 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1045 case GLSL_TYPE_SAMPLER
:
1046 case GLSL_TYPE_IMAGE
:
1047 case GLSL_TYPE_ATOMIC_UINT
:
1050 case GLSL_TYPE_VOID
:
1051 case GLSL_TYPE_ERROR
:
1052 case GLSL_TYPE_INTERFACE
:
1053 unreachable("not reached");
1057 /* If the RHS processing resulted in an instruction generating a
1058 * temporary value, and it would be easy to rewrite the instruction to
1059 * generate its result right into the LHS instead, do so. This ends
1060 * up reliably removing instructions where it can be tricky to do so
1061 * later without real UD chain information.
1064 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1067 fs_inst
*pre_rhs_inst
,
1068 fs_inst
*last_rhs_inst
)
1070 /* Only attempt if we're doing a direct assignment. */
1071 if (ir
->condition
||
1072 !(ir
->lhs
->type
->is_scalar() ||
1073 (ir
->lhs
->type
->is_vector() &&
1074 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1077 /* Make sure the last instruction generated our source reg. */
1078 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1084 /* If last_rhs_inst wrote a different number of components than our LHS,
1085 * we can't safely rewrite it.
1087 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
1090 /* Success! Rewrite the instruction. */
1097 fs_visitor::visit(ir_assignment
*ir
)
1102 /* FINISHME: arrays on the lhs */
1103 ir
->lhs
->accept(this);
1106 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1108 ir
->rhs
->accept(this);
1111 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1113 assert(l
.file
!= BAD_FILE
);
1114 assert(r
.file
!= BAD_FILE
);
1116 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1119 if (ir
->condition
) {
1120 emit_bool_to_cond_code(ir
->condition
);
1123 if (ir
->lhs
->type
->is_scalar() ||
1124 ir
->lhs
->type
->is_vector()) {
1125 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1126 if (ir
->write_mask
& (1 << i
)) {
1127 inst
= emit(MOV(l
, r
));
1129 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1135 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1140 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1141 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
,
1146 bool simd16
= false;
1152 if (shadow_c
.file
!= BAD_FILE
) {
1153 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1154 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1155 coordinate
.reg_offset
++;
1158 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1159 * the unused slots must be zeroed.
1161 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1162 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1166 if (ir
->op
== ir_tex
) {
1167 /* There's no plain shadow compare message, so we use shadow
1168 * compare with a bias of 0.0.
1170 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1172 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
1173 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1176 unreachable("Should not get here.");
1179 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1181 } else if (ir
->op
== ir_tex
) {
1182 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1183 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1184 coordinate
.reg_offset
++;
1186 /* zero the others. */
1187 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
1188 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1190 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1192 } else if (ir
->op
== ir_txd
) {
1195 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1196 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1197 coordinate
.reg_offset
++;
1199 /* the slots for u and v are always present, but r is optional */
1200 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
1203 * dPdx = dudx, dvdx, drdx
1204 * dPdy = dudy, dvdy, drdy
1206 * 1-arg: Does not exist.
1208 * 2-arg: dudx dvdx dudy dvdy
1209 * dPdx.x dPdx.y dPdy.x dPdy.y
1212 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1213 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1214 * m5 m6 m7 m8 m9 m10
1216 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1217 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1220 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1222 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1223 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1226 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1227 } else if (ir
->op
== ir_txs
) {
1228 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1230 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1233 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1234 * instructions. We'll need to do SIMD16 here.
1237 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1239 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1240 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1242 coordinate
.reg_offset
++;
1245 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1246 * be necessary for TXF (ld), but seems wise to do for all messages.
1248 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1249 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1252 /* lod/bias appears after u/v/r. */
1255 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1258 /* The unused upper half. */
1263 /* Now, since we're doing simd16, the return is 2 interleaved
1264 * vec4s where the odd-indexed ones are junk. We'll need to move
1265 * this weirdness around to the expected layout.
1268 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1270 brw_type_for_base_type(ir
->type
) :
1271 BRW_REGISTER_TYPE_F
));
1277 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1278 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1279 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1280 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1281 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1282 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1284 unreachable("not reached");
1287 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1288 inst
->base_mrf
= base_mrf
;
1290 inst
->header_present
= true;
1291 inst
->regs_written
= simd16
? 8 : 4;
1294 for (int i
= 0; i
< 4; i
++) {
1295 emit(MOV(orig_dst
, dst
));
1296 orig_dst
.reg_offset
++;
1297 dst
.reg_offset
+= 2;
1304 /* gen5's sampler has slots for u, v, r, array index, then optional
1305 * parameters like shadow comparitor or LOD bias. If optional
1306 * parameters aren't present, those base slots are optional and don't
1307 * need to be included in the message.
1309 * We don't fill in the unnecessary slots regardless, which may look
1310 * surprising in the disassembly.
1313 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1314 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1315 fs_reg sample_index
, uint32_t sampler
)
1319 int reg_width
= dispatch_width
/ 8;
1320 bool header_present
= false;
1321 const int vector_elements
=
1322 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1325 /* The offsets set up by the ir_texture visitor are in the
1326 * m1 header, so we can't go headerless.
1328 header_present
= true;
1333 for (int i
= 0; i
< vector_elements
; i
++) {
1334 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1336 coordinate
.reg_offset
++;
1338 mlen
+= vector_elements
* reg_width
;
1340 if (shadow_c
.file
!= BAD_FILE
) {
1341 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1343 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1350 opcode
= SHADER_OPCODE_TEX
;
1353 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1354 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1357 opcode
= FS_OPCODE_TXB
;
1360 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1361 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1364 opcode
= SHADER_OPCODE_TXL
;
1367 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1371 * dPdx = dudx, dvdx, drdx
1372 * dPdy = dudy, dvdy, drdy
1374 * Load up these values:
1375 * - dudx dudy dvdx dvdy drdx drdy
1376 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1378 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1379 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1383 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1388 opcode
= SHADER_OPCODE_TXD
;
1392 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1395 opcode
= SHADER_OPCODE_TXS
;
1397 case ir_query_levels
:
1398 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1401 opcode
= SHADER_OPCODE_TXS
;
1404 mlen
= header_present
+ 4 * reg_width
;
1405 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1407 opcode
= SHADER_OPCODE_TXF
;
1410 mlen
= header_present
+ 4 * reg_width
;
1413 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1415 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1418 opcode
= SHADER_OPCODE_TXF_CMS
;
1421 opcode
= SHADER_OPCODE_LOD
;
1424 opcode
= SHADER_OPCODE_TG4
;
1427 unreachable("not reached");
1430 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1431 inst
->base_mrf
= base_mrf
;
1433 inst
->header_present
= header_present
;
1434 inst
->regs_written
= 4;
1436 if (mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1437 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1438 " disallowed by hardware\n");
1445 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1447 if (brw
->gen
< 8 && !brw
->is_haswell
)
1450 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1454 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1455 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1456 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
)
1458 int reg_width
= dispatch_width
/ 8;
1459 bool header_present
= false;
1461 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1462 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1463 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1467 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
) ||
1468 is_high_sampler(brw
, sampler
)) {
1469 /* For general texture offsets (no txf workaround), we need a header to
1470 * put them in. Note that for SIMD16 we're making space for two actual
1471 * hardware registers here, so the emit will have to fix up for this.
1473 * * ir4_tg4 needs to place its channel select in the header,
1474 * for interaction with ARB_texture_swizzle
1476 * The sampler index is only 4-bits, so for larger sampler numbers we
1477 * need to offset the Sampler State Pointer in the header.
1479 header_present
= true;
1480 sources
[length
] = reg_undef
;
1484 if (shadow_c
.file
!= BAD_FILE
) {
1485 emit(MOV(sources
[length
], shadow_c
));
1489 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
1490 bool coordinate_done
= false;
1492 /* Set up the LOD info */
1498 emit(MOV(sources
[length
], lod
));
1502 emit(MOV(sources
[length
], lod
));
1506 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1508 /* Load dPdx and the coordinate together:
1509 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1511 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1512 emit(MOV(sources
[length
], coordinate
));
1513 coordinate
.reg_offset
++;
1516 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1517 * only derivatives for (u, v, r).
1519 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1520 emit(MOV(sources
[length
], lod
));
1524 emit(MOV(sources
[length
], lod2
));
1530 coordinate_done
= true;
1534 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1537 case ir_query_levels
:
1538 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1542 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1543 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1544 coordinate
.reg_offset
++;
1547 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1550 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1551 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1552 coordinate
.reg_offset
++;
1556 coordinate_done
= true;
1559 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1562 /* data from the multisample control surface */
1563 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1566 /* there is no offsetting for this message; just copy in the integer
1567 * texture coordinates
1569 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1570 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1571 coordinate
.reg_offset
++;
1575 coordinate_done
= true;
1578 if (has_nonconstant_offset
) {
1579 if (shadow_c
.file
!= BAD_FILE
)
1580 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1582 /* More crazy intermixing */
1583 ir
->offset
->accept(this);
1584 fs_reg offset_value
= this->result
;
1586 for (int i
= 0; i
< 2; i
++) { /* u, v */
1587 emit(MOV(sources
[length
], coordinate
));
1588 coordinate
.reg_offset
++;
1592 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1593 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1594 offset_value
.reg_offset
++;
1598 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1599 emit(MOV(sources
[length
], coordinate
));
1600 coordinate
.reg_offset
++;
1604 coordinate_done
= true;
1609 /* Set up the coordinate (except for cases where it was done above) */
1610 if (ir
->coordinate
&& !coordinate_done
) {
1611 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1612 emit(MOV(sources
[length
], coordinate
));
1613 coordinate
.reg_offset
++;
1618 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1619 BRW_REGISTER_TYPE_F
);
1620 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1622 /* Generate the SEND */
1625 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1626 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1627 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1628 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1629 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1630 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1631 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1632 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1633 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1635 if (has_nonconstant_offset
)
1636 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1638 opcode
= SHADER_OPCODE_TG4
;
1641 unreachable("not reached");
1643 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1644 inst
->base_mrf
= -1;
1646 inst
->mlen
= length
* reg_width
- header_present
;
1648 inst
->mlen
= length
* reg_width
;
1649 inst
->header_present
= header_present
;
1650 inst
->regs_written
= 4;
1652 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1653 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1654 " disallowed by hardware\n");
1661 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1662 bool is_rect
, uint32_t sampler
, int texunit
)
1664 fs_inst
*inst
= NULL
;
1665 bool needs_gl_clamp
= true;
1666 fs_reg scale_x
, scale_y
;
1668 /* The 965 requires the EU to do the normalization of GL rectangle
1669 * texture coordinates. We use the program parameter state
1670 * tracking to get the scaling factor.
1674 (brw
->gen
>= 6 && (key
->tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1675 key
->tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1676 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1677 int tokens
[STATE_LENGTH
] = {
1679 STATE_TEXRECT_SCALE
,
1685 no16("rectangle scale uniform setup not supported on SIMD16\n");
1686 if (dispatch_width
== 16) {
1690 GLuint index
= _mesa_add_state_reference(params
,
1691 (gl_state_index
*)tokens
);
1692 /* Try to find existing copies of the texrect scale uniforms. */
1693 for (unsigned i
= 0; i
< uniforms
; i
++) {
1694 if (stage_prog_data
->param
[i
] ==
1695 &prog
->Parameters
->ParameterValues
[index
][0]) {
1696 scale_x
= fs_reg(UNIFORM
, i
);
1697 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1702 /* If we didn't already set them up, do so now. */
1703 if (scale_x
.file
== BAD_FILE
) {
1704 scale_x
= fs_reg(UNIFORM
, uniforms
);
1705 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1707 stage_prog_data
->param
[uniforms
++] =
1708 &prog
->Parameters
->ParameterValues
[index
][0];
1709 stage_prog_data
->param
[uniforms
++] =
1710 &prog
->Parameters
->ParameterValues
[index
][1];
1714 /* The 965 requires the EU to do the normalization of GL rectangle
1715 * texture coordinates. We use the program parameter state
1716 * tracking to get the scaling factor.
1718 if (brw
->gen
< 6 && is_rect
) {
1719 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1720 fs_reg src
= coordinate
;
1723 emit(MUL(dst
, src
, scale_x
));
1726 emit(MUL(dst
, src
, scale_y
));
1727 } else if (is_rect
) {
1728 /* On gen6+, the sampler handles the rectangle coordinates
1729 * natively, without needing rescaling. But that means we have
1730 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1731 * not [0, 1] like the default case below.
1733 needs_gl_clamp
= false;
1735 for (int i
= 0; i
< 2; i
++) {
1736 if (key
->tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1737 fs_reg chan
= coordinate
;
1738 chan
.reg_offset
+= i
;
1740 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1741 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1743 /* Our parameter comes in as 1.0/width or 1.0/height,
1744 * because that's what people normally want for doing
1745 * texture rectangle handling. We need width or height
1746 * for clamping, but we don't care enough to make a new
1747 * parameter type, so just invert back.
1749 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1750 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1751 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1753 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1754 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1759 if (ir
->coordinate
&& needs_gl_clamp
) {
1760 for (unsigned int i
= 0;
1761 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1762 if (key
->tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1763 fs_reg chan
= coordinate
;
1764 chan
.reg_offset
+= i
;
1766 fs_inst
*inst
= emit(MOV(chan
, chan
));
1767 inst
->saturate
= true;
1774 /* Sample from the MCS surface attached to this multisample texture. */
1776 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, fs_reg sampler
)
1778 int reg_width
= dispatch_width
/ 8;
1779 int length
= ir
->coordinate
->type
->vector_elements
;
1780 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(length
),
1781 BRW_REGISTER_TYPE_F
);
1782 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1783 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, length
);
1785 /* parameters are: u, v, r; missing parameters are treated as zero */
1786 for (int i
= 0; i
< length
; i
++) {
1787 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1788 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1789 coordinate
.reg_offset
++;
1792 emit(LOAD_PAYLOAD(payload
, sources
, length
));
1794 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
1795 inst
->base_mrf
= -1;
1796 inst
->mlen
= length
* reg_width
;
1797 inst
->header_present
= false;
1798 inst
->regs_written
= 4; /* we only care about one reg of response,
1799 * but the sampler always writes 4/8
1806 fs_visitor::visit(ir_texture
*ir
)
1808 fs_inst
*inst
= NULL
;
1811 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1813 ir_rvalue
*nonconst_sampler_index
=
1814 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
1816 /* Handle non-constant sampler array indexing */
1818 if (nonconst_sampler_index
) {
1819 /* The highest sampler which may be used by this operation is
1820 * the last element of the array. Mark it here, because the generator
1821 * doesn't have enough information to determine the bound.
1823 uint32_t array_size
= ir
->sampler
->as_dereference_array()
1824 ->array
->type
->array_size();
1826 uint32_t max_used
= sampler
+ array_size
- 1;
1827 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
1828 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1830 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1833 brw_mark_surface_used(&prog_data
->base
, max_used
);
1835 /* Emit code to evaluate the actual indexing expression */
1836 nonconst_sampler_index
->accept(this);
1837 fs_reg
temp(this, glsl_type::uint_type
);
1838 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
1839 ->force_writemask_all
= true;
1842 /* Single sampler, or constant array index; the indexing expression
1843 * is just an immediate.
1845 sampler_reg
= fs_reg(sampler
);
1848 /* FINISHME: We're failing to recompile our programs when the sampler is
1849 * updated. This only matters for the texture rectangle scale parameters
1850 * (pre-gen6, or gen6+ with GL_CLAMP).
1852 int texunit
= prog
->SamplerUnits
[sampler
];
1854 if (ir
->op
== ir_tg4
) {
1855 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1856 * emitting anything other than setting up the constant result.
1858 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1859 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1860 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1862 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1865 for (int i
=0; i
<4; i
++) {
1866 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1873 /* Should be lowered by do_lower_texture_projection */
1874 assert(!ir
->projector
);
1876 /* Should be lowered */
1877 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1879 /* Generate code to compute all the subexpression trees. This has to be
1880 * done before loading any values into MRFs for the sampler message since
1881 * generating these values may involve SEND messages that need the MRFs.
1884 if (ir
->coordinate
) {
1885 ir
->coordinate
->accept(this);
1887 coordinate
= rescale_texcoord(ir
, this->result
,
1888 ir
->sampler
->type
->sampler_dimensionality
==
1889 GLSL_SAMPLER_DIM_RECT
,
1893 fs_reg shadow_comparitor
;
1894 if (ir
->shadow_comparitor
) {
1895 ir
->shadow_comparitor
->accept(this);
1896 shadow_comparitor
= this->result
;
1899 fs_reg lod
, lod2
, sample_index
, mcs
;
1904 case ir_query_levels
:
1907 ir
->lod_info
.bias
->accept(this);
1911 ir
->lod_info
.grad
.dPdx
->accept(this);
1914 ir
->lod_info
.grad
.dPdy
->accept(this);
1915 lod2
= this->result
;
1920 ir
->lod_info
.lod
->accept(this);
1924 ir
->lod_info
.sample_index
->accept(this);
1925 sample_index
= this->result
;
1927 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1928 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
1933 unreachable("Unrecognized texture opcode");
1936 /* Writemasking doesn't eliminate channels on SIMD8 texture
1937 * samples, so don't worry about them.
1939 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1941 if (brw
->gen
>= 7) {
1942 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1943 lod
, lod2
, sample_index
, mcs
, sampler_reg
);
1944 } else if (brw
->gen
>= 5) {
1945 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1946 lod
, lod2
, sample_index
, sampler
);
1948 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1949 lod
, lod2
, sampler
);
1952 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1953 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
1955 if (ir
->op
== ir_tg4
)
1956 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1958 if (ir
->shadow_comparitor
)
1959 inst
->shadow_compare
= true;
1961 /* fixup #layers for cube map arrays */
1962 if (ir
->op
== ir_txs
) {
1963 glsl_type
const *type
= ir
->sampler
->type
;
1964 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1965 type
->sampler_array
) {
1967 depth
.reg_offset
= 2;
1968 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
1969 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
1971 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
1973 for (int i
= 0; i
< inst
->regs_written
; i
++) {
1975 fixed_payload
[i
] = fixed_depth
;
1978 fixed_payload
[i
] = d
;
1981 emit(LOAD_PAYLOAD(dst
, fixed_payload
, inst
->regs_written
));
1985 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
1986 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], dst
);
1989 swizzle_result(ir
, dst
, sampler
);
1993 * Apply workarounds for Gen6 gather with UINT/SINT
1996 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2001 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2003 for (int i
= 0; i
< 4; i
++) {
2004 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2005 /* Convert from UNORM to UINT */
2006 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2007 emit(MOV(dst
, dst_f
));
2010 /* Reinterpret the UINT value as a signed INT value by
2011 * shifting the sign bit into place, then shifting back
2014 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2015 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2023 * Set up the gather channel based on the swizzle, for gather4.
2026 fs_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2028 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2029 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2031 case SWIZZLE_X
: return 0;
2033 /* gather4 sampler is broken for green channel on RG32F --
2034 * we must ask for blue instead.
2036 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2039 case SWIZZLE_Z
: return 2;
2040 case SWIZZLE_W
: return 3;
2042 unreachable("Not reached"); /* zero, one swizzles handled already */
2047 * Swizzle the result of a texture result. This is necessary for
2048 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2051 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, uint32_t sampler
)
2053 if (ir
->op
== ir_query_levels
) {
2054 /* # levels is in .w */
2055 orig_val
.reg_offset
+= 3;
2056 this->result
= orig_val
;
2060 this->result
= orig_val
;
2062 /* txs,lod don't actually sample the texture, so swizzling the result
2065 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
2068 if (ir
->type
== glsl_type::float_type
) {
2069 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2070 assert(ir
->sampler
->type
->sampler_shadow
);
2071 } else if (key
->tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
2072 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
2074 for (int i
= 0; i
< 4; i
++) {
2075 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], i
);
2076 fs_reg l
= swizzled_result
;
2079 if (swiz
== SWIZZLE_ZERO
) {
2080 emit(MOV(l
, fs_reg(0.0f
)));
2081 } else if (swiz
== SWIZZLE_ONE
) {
2082 emit(MOV(l
, fs_reg(1.0f
)));
2084 fs_reg r
= orig_val
;
2085 r
.reg_offset
+= GET_SWZ(key
->tex
.swizzles
[sampler
], i
);
2089 this->result
= swizzled_result
;
2094 fs_visitor::visit(ir_swizzle
*ir
)
2096 ir
->val
->accept(this);
2097 fs_reg val
= this->result
;
2099 if (ir
->type
->vector_elements
== 1) {
2100 this->result
.reg_offset
+= ir
->mask
.x
;
2104 fs_reg result
= fs_reg(this, ir
->type
);
2105 this->result
= result
;
2107 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2108 fs_reg channel
= val
;
2126 channel
.reg_offset
+= swiz
;
2127 emit(MOV(result
, channel
));
2128 result
.reg_offset
++;
2133 fs_visitor::visit(ir_discard
*ir
)
2135 assert(ir
->condition
== NULL
); /* FINISHME */
2137 /* We track our discarded pixels in f0.1. By predicating on it, we can
2138 * update just the flag bits that aren't yet discarded. By emitting a
2139 * CMP of g0 != g0, all our currently executing channels will get turned
2142 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2143 BRW_REGISTER_TYPE_UW
));
2144 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2145 BRW_CONDITIONAL_NZ
));
2146 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2147 cmp
->flag_subreg
= 1;
2149 if (brw
->gen
>= 6) {
2150 /* For performance, after a discard, jump to the end of the shader.
2151 * Only jump if all relevant channels have been discarded.
2153 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2154 discard_jump
->flag_subreg
= 1;
2156 discard_jump
->predicate
= (dispatch_width
== 8)
2157 ? BRW_PREDICATE_ALIGN1_ANY8H
2158 : BRW_PREDICATE_ALIGN1_ANY16H
;
2159 discard_jump
->predicate_inverse
= true;
2164 fs_visitor::visit(ir_constant
*ir
)
2166 /* Set this->result to reg at the bottom of the function because some code
2167 * paths will cause this visitor to be applied to other fields. This will
2168 * cause the value stored in this->result to be modified.
2170 * Make reg constant so that it doesn't get accidentally modified along the
2171 * way. Yes, I actually had this problem. :(
2173 const fs_reg
reg(this, ir
->type
);
2174 fs_reg dst_reg
= reg
;
2176 if (ir
->type
->is_array()) {
2177 const unsigned size
= type_size(ir
->type
->fields
.array
);
2179 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2180 ir
->array_elements
[i
]->accept(this);
2181 fs_reg src_reg
= this->result
;
2183 dst_reg
.type
= src_reg
.type
;
2184 for (unsigned j
= 0; j
< size
; j
++) {
2185 emit(MOV(dst_reg
, src_reg
));
2186 src_reg
.reg_offset
++;
2187 dst_reg
.reg_offset
++;
2190 } else if (ir
->type
->is_record()) {
2191 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2192 const unsigned size
= type_size(field
->type
);
2194 field
->accept(this);
2195 fs_reg src_reg
= this->result
;
2197 dst_reg
.type
= src_reg
.type
;
2198 for (unsigned j
= 0; j
< size
; j
++) {
2199 emit(MOV(dst_reg
, src_reg
));
2200 src_reg
.reg_offset
++;
2201 dst_reg
.reg_offset
++;
2205 const unsigned size
= type_size(ir
->type
);
2207 for (unsigned i
= 0; i
< size
; i
++) {
2208 switch (ir
->type
->base_type
) {
2209 case GLSL_TYPE_FLOAT
:
2210 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2212 case GLSL_TYPE_UINT
:
2213 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2216 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2218 case GLSL_TYPE_BOOL
:
2220 fs_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2224 unreachable("Non-float/uint/int/bool constant");
2226 dst_reg
.reg_offset
++;
2234 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2236 ir_expression
*expr
= ir
->as_expression();
2241 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2242 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2249 assert(expr
->get_num_operands() <= 3);
2250 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2251 assert(expr
->operands
[i
]->type
->is_scalar());
2253 expr
->operands
[i
]->accept(this);
2254 op
[i
] = this->result
;
2256 resolve_ud_negate(&op
[i
]);
2259 switch (expr
->operation
) {
2260 case ir_unop_logic_not
:
2261 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2262 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2265 case ir_binop_logic_xor
:
2266 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2267 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2268 emit(XOR(dst
, op
[0], op
[1]));
2269 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2270 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2272 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2273 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2277 case ir_binop_logic_or
:
2278 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2279 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2280 emit(OR(dst
, op
[0], op
[1]));
2281 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2282 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2284 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2285 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2289 case ir_binop_logic_and
:
2290 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2291 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2292 emit(AND(dst
, op
[0], op
[1]));
2293 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2294 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2296 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2297 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2302 if (brw
->gen
>= 6) {
2303 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2305 inst
= emit(MOV(reg_null_f
, op
[0]));
2306 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2311 if (brw
->gen
>= 6) {
2312 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2314 inst
= emit(MOV(reg_null_d
, op
[0]));
2315 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2319 case ir_binop_greater
:
2320 case ir_binop_gequal
:
2322 case ir_binop_lequal
:
2323 case ir_binop_equal
:
2324 case ir_binop_all_equal
:
2325 case ir_binop_nequal
:
2326 case ir_binop_any_nequal
:
2327 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2328 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2329 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2332 emit(CMP(reg_null_d
, op
[0], op
[1],
2333 brw_conditional_for_comparison(expr
->operation
)));
2336 case ir_triop_csel
: {
2337 /* Expand the boolean condition into the flag register. */
2338 inst
= emit(MOV(reg_null_d
, op
[0]));
2339 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2341 /* Select which boolean to return. */
2342 fs_reg
temp(this, expr
->operands
[1]->type
);
2343 inst
= emit(SEL(temp
, op
[1], op
[2]));
2344 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2346 /* Expand the result to a condition code. */
2347 inst
= emit(MOV(reg_null_d
, temp
));
2348 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2353 unreachable("not reached");
2358 * Emit a gen6 IF statement with the comparison folded into the IF
2362 fs_visitor::emit_if_gen6(ir_if
*ir
)
2364 ir_expression
*expr
= ir
->condition
->as_expression();
2371 assert(expr
->get_num_operands() <= 2);
2372 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2373 assert(expr
->operands
[i
]->type
->is_scalar());
2375 expr
->operands
[i
]->accept(this);
2376 op
[i
] = this->result
;
2379 switch (expr
->operation
) {
2380 case ir_unop_logic_not
:
2381 case ir_binop_logic_xor
:
2382 case ir_binop_logic_or
:
2383 case ir_binop_logic_and
:
2384 /* For operations on bool arguments, only the low bit of the bool is
2385 * valid, and the others are undefined. Fall back to the condition
2391 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2392 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2396 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2399 case ir_binop_greater
:
2400 case ir_binop_gequal
:
2402 case ir_binop_lequal
:
2403 case ir_binop_equal
:
2404 case ir_binop_all_equal
:
2405 case ir_binop_nequal
:
2406 case ir_binop_any_nequal
:
2407 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2408 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2409 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2412 emit(IF(op
[0], op
[1],
2413 brw_conditional_for_comparison(expr
->operation
)));
2416 unreachable("not reached");
2420 emit_bool_to_cond_code(ir
->condition
);
2421 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
2422 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2426 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2428 * Many GLSL shaders contain the following pattern:
2430 * x = condition ? foo : bar
2432 * The compiler emits an ir_if tree for this, since each subexpression might be
2433 * a complex tree that could have side-effects or short-circuit logic.
2435 * However, the common case is to simply select one of two constants or
2436 * variable values---which is exactly what SEL is for. In this case, the
2437 * assembly looks like:
2445 * which can be easily translated into:
2447 * (+f0) SEL dst src0 src1
2449 * If src0 is an immediate value, we promote it to a temporary GRF.
2452 fs_visitor::try_replace_with_sel()
2454 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2455 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2457 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2459 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2462 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2463 for (int i
= 0; i
< 4; i
++) {
2464 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2466 match
= (fs_inst
*) match
->prev
;
2469 /* The opcodes match; it looks like the right sequence of instructions. */
2470 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2471 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2472 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2474 /* Check that the MOVs are the right form. */
2475 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2476 !then_mov
->is_partial_write() &&
2477 !else_mov
->is_partial_write()) {
2479 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2480 while (!if_inst
->next
->is_tail_sentinel())
2481 if_inst
->next
->remove();
2484 /* Only the last source register can be a constant, so if the MOV in
2485 * the "then" clause uses a constant, we need to put it in a temporary.
2487 fs_reg
src0(then_mov
->src
[0]);
2488 if (src0
.file
== IMM
) {
2489 src0
= fs_reg(this, glsl_type::float_type
);
2490 src0
.type
= then_mov
->src
[0].type
;
2491 emit(MOV(src0
, then_mov
->src
[0]));
2495 if (if_inst
->conditional_mod
) {
2496 /* Sandybridge-specific IF with embedded comparison */
2497 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2498 if_inst
->conditional_mod
));
2499 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2500 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2502 /* Separate CMP and IF instructions */
2503 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2504 sel
->predicate
= if_inst
->predicate
;
2505 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2511 fs_visitor::visit(ir_if
*ir
)
2514 no16("Can't support (non-uniform) control flow on SIMD16\n");
2517 /* Don't point the annotation at the if statement, because then it plus
2518 * the then and else blocks get printed.
2520 this->base_ir
= ir
->condition
;
2522 if (brw
->gen
== 6) {
2525 emit_bool_to_cond_code(ir
->condition
);
2527 emit(IF(BRW_PREDICATE_NORMAL
));
2530 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2531 this->base_ir
= ir_
;
2535 if (!ir
->else_instructions
.is_empty()) {
2536 emit(BRW_OPCODE_ELSE
);
2538 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2539 this->base_ir
= ir_
;
2544 emit(BRW_OPCODE_ENDIF
);
2546 try_replace_with_sel();
2550 fs_visitor::visit(ir_loop
*ir
)
2553 no16("Can't support (non-uniform) control flow on SIMD16\n");
2556 this->base_ir
= NULL
;
2557 emit(BRW_OPCODE_DO
);
2559 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2560 this->base_ir
= ir_
;
2564 this->base_ir
= NULL
;
2565 emit(BRW_OPCODE_WHILE
);
2569 fs_visitor::visit(ir_loop_jump
*ir
)
2572 case ir_loop_jump::jump_break
:
2573 emit(BRW_OPCODE_BREAK
);
2575 case ir_loop_jump::jump_continue
:
2576 emit(BRW_OPCODE_CONTINUE
);
2582 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2584 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2585 ir
->actual_parameters
.get_head());
2586 ir_variable
*location
= deref
->variable_referenced();
2587 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2588 location
->data
.binding
);
2590 /* Calculate the surface offset */
2591 fs_reg
offset(this, glsl_type::uint_type
);
2592 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2595 deref_array
->array_index
->accept(this);
2597 fs_reg
tmp(this, glsl_type::uint_type
);
2598 emit(MUL(tmp
, this->result
, ATOMIC_COUNTER_SIZE
));
2599 emit(ADD(offset
, tmp
, location
->data
.atomic
.offset
));
2601 offset
= location
->data
.atomic
.offset
;
2604 /* Emit the appropriate machine instruction */
2605 const char *callee
= ir
->callee
->function_name();
2606 ir
->return_deref
->accept(this);
2607 fs_reg dst
= this->result
;
2609 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2610 emit_untyped_surface_read(surf_index
, dst
, offset
);
2612 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2613 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2614 fs_reg(), fs_reg());
2616 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2617 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2618 fs_reg(), fs_reg());
2623 fs_visitor::visit(ir_call
*ir
)
2625 const char *callee
= ir
->callee
->function_name();
2627 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2628 !strcmp("__intrinsic_atomic_increment", callee
) ||
2629 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2630 visit_atomic_counter_intrinsic(ir
);
2632 unreachable("Unsupported intrinsic.");
2637 fs_visitor::visit(ir_return
*)
2639 unreachable("FINISHME");
2643 fs_visitor::visit(ir_function
*ir
)
2645 /* Ignore function bodies other than main() -- we shouldn't see calls to
2646 * them since they should all be inlined before we get to ir_to_mesa.
2648 if (strcmp(ir
->name
, "main") == 0) {
2649 const ir_function_signature
*sig
;
2652 sig
= ir
->matching_signature(NULL
, &empty
, false);
2656 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2657 this->base_ir
= ir_
;
2664 fs_visitor::visit(ir_function_signature
*)
2666 unreachable("not reached");
2670 fs_visitor::visit(ir_emit_vertex
*)
2672 unreachable("not reached");
2676 fs_visitor::visit(ir_end_primitive
*)
2678 unreachable("not reached");
2682 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2683 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2686 const unsigned operand_len
= dispatch_width
/ 8;
2689 /* Initialize the sample mask in the message header. */
2690 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2691 ->force_writemask_all
= true;
2694 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2695 ->force_writemask_all
= true;
2697 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2698 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2699 ->force_writemask_all
= true;
2704 /* Set the atomic operation offset. */
2705 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2706 mlen
+= operand_len
;
2708 /* Set the atomic operation arguments. */
2709 if (src0
.file
!= BAD_FILE
) {
2710 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src0
));
2711 mlen
+= operand_len
;
2714 if (src1
.file
!= BAD_FILE
) {
2715 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), src1
));
2716 mlen
+= operand_len
;
2719 /* Emit the instruction. */
2720 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2721 atomic_op
, surf_index
);
2724 inst
->header_present
= true;
2729 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2732 const unsigned operand_len
= dispatch_width
/ 8;
2735 /* Initialize the sample mask in the message header. */
2736 emit(MOV(brw_uvec_mrf(8, mlen
, 0), fs_reg(0u)))
2737 ->force_writemask_all
= true;
2740 emit(MOV(brw_uvec_mrf(1, mlen
, 7), brw_flag_reg(0, 1)))
2741 ->force_writemask_all
= true;
2743 emit(MOV(brw_uvec_mrf(1, mlen
, 7),
2744 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2745 ->force_writemask_all
= true;
2750 /* Set the surface read offset. */
2751 emit(MOV(brw_uvec_mrf(dispatch_width
, mlen
, 0), offset
));
2752 mlen
+= operand_len
;
2754 /* Emit the instruction. */
2755 fs_inst
*inst
= new(mem_ctx
)
2756 fs_inst(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, surf_index
);
2759 inst
->header_present
= true;
2764 fs_visitor::emit(fs_inst
*inst
)
2766 if (force_uncompressed_stack
> 0)
2767 inst
->force_uncompressed
= true;
2769 inst
->annotation
= this->current_annotation
;
2770 inst
->ir
= this->base_ir
;
2772 this->instructions
.push_tail(inst
);
2778 fs_visitor::emit(exec_list list
)
2780 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2786 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2788 fs_visitor::emit_dummy_fs()
2790 int reg_width
= dispatch_width
/ 8;
2792 /* Everyone's favorite color. */
2793 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2794 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2795 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2796 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2799 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2800 write
->base_mrf
= 2;
2801 write
->mlen
= 4 * reg_width
;
2805 /* The register location here is relative to the start of the URB
2806 * data. It will get adjusted to be a real location before
2807 * generate_code() time.
2810 fs_visitor::interp_reg(int location
, int channel
)
2812 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
2813 int stride
= (channel
& 1) * 4;
2815 assert(prog_data
->urb_setup
[location
] != -1);
2817 return brw_vec1_grf(regnr
, stride
);
2820 /** Emits the interpolation for the varying inputs. */
2822 fs_visitor::emit_interpolation_setup_gen4()
2824 this->current_annotation
= "compute pixel centers";
2825 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2826 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2827 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2828 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2830 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2831 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2833 this->current_annotation
= "compute pixel deltas from v0";
2835 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2836 fs_reg(this, glsl_type::vec2_type
);
2837 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2838 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2839 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2841 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2842 fs_reg(this, glsl_type::float_type
);
2843 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2844 fs_reg(this, glsl_type::float_type
);
2846 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2847 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2848 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2849 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2851 this->current_annotation
= "compute pos.w and 1/pos.w";
2852 /* Compute wpos.w. It's always in our setup, since it's needed to
2853 * interpolate the other attributes.
2855 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2856 emit(FS_OPCODE_LINTERP
, wpos_w
,
2857 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2858 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2859 interp_reg(VARYING_SLOT_POS
, 3));
2860 /* Compute the pixel 1/W value from wpos.w. */
2861 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2862 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2863 this->current_annotation
= NULL
;
2866 /** Emits the interpolation for the varying inputs. */
2868 fs_visitor::emit_interpolation_setup_gen6()
2870 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2872 /* If the pixel centers end up used, the setup is the same as for gen4. */
2873 this->current_annotation
= "compute pixel centers";
2874 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2875 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2876 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2877 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2878 emit(ADD(int_pixel_x
,
2879 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2880 fs_reg(brw_imm_v(0x10101010))));
2881 emit(ADD(int_pixel_y
,
2882 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2883 fs_reg(brw_imm_v(0x11001100))));
2885 /* As of gen6, we can no longer mix float and int sources. We have
2886 * to turn the integer pixel centers into floats for their actual
2889 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2890 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2891 emit(MOV(this->pixel_x
, int_pixel_x
));
2892 emit(MOV(this->pixel_y
, int_pixel_y
));
2894 this->current_annotation
= "compute pos.w";
2895 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
2896 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2897 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2899 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2900 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
2901 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2902 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2905 this->current_annotation
= NULL
;
2909 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2911 int reg_width
= dispatch_width
/ 8;
2913 fs_reg color
= outputs
[target
];
2916 /* If there's no color data to be written, skip it. */
2917 if (color
.file
== BAD_FILE
)
2920 color
.reg_offset
+= index
;
2922 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2923 /* SIMD8 write looks like:
2929 * gen6 SIMD16 DP write looks like:
2939 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2942 inst
->saturate
= key
->clamp_fragment_color
;
2944 /* pre-gen6 SIMD16 single source DP write looks like:
2954 if (brw
->has_compr4
) {
2955 /* By setting the high bit of the MRF register number, we
2956 * indicate that we want COMPR4 mode - instead of doing the
2957 * usual destination + 1 for the second half we get
2960 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2963 inst
->saturate
= key
->clamp_fragment_color
;
2965 push_force_uncompressed();
2966 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2968 inst
->saturate
= key
->clamp_fragment_color
;
2969 pop_force_uncompressed();
2971 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2973 inst
->force_sechalf
= true;
2974 inst
->saturate
= key
->clamp_fragment_color
;
2979 static enum brw_conditional_mod
2980 cond_for_alpha_func(GLenum func
)
2984 return BRW_CONDITIONAL_G
;
2986 return BRW_CONDITIONAL_GE
;
2988 return BRW_CONDITIONAL_L
;
2990 return BRW_CONDITIONAL_LE
;
2992 return BRW_CONDITIONAL_EQ
;
2994 return BRW_CONDITIONAL_NEQ
;
2996 unreachable("Not reached");
3001 * Alpha test support for when we compile it into the shader instead
3002 * of using the normal fixed-function alpha test.
3005 fs_visitor::emit_alpha_test()
3007 this->current_annotation
= "Alpha test";
3010 if (key
->alpha_test_func
== GL_ALWAYS
)
3013 if (key
->alpha_test_func
== GL_NEVER
) {
3015 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3016 BRW_REGISTER_TYPE_UW
));
3017 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3018 BRW_CONDITIONAL_NEQ
));
3021 fs_reg color
= outputs
[0];
3022 color
.reg_offset
+= 3;
3024 /* f0.1 &= func(color, ref) */
3025 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3026 cond_for_alpha_func(key
->alpha_test_func
)));
3028 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3029 cmp
->flag_subreg
= 1;
3033 fs_visitor::emit_fb_writes()
3035 this->current_annotation
= "FB write header";
3036 bool header_present
= true;
3037 /* We can potentially have a message length of up to 15, so we have to set
3038 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3042 int reg_width
= dispatch_width
/ 8;
3043 bool src0_alpha_to_render_target
= false;
3046 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
3047 if (dispatch_width
== 16)
3048 do_dual_src
= false;
3051 /* From the Sandy Bridge PRM, volume 4, page 198:
3053 * "Dispatched Pixel Enables. One bit per pixel indicating
3054 * which pixels were originally enabled when the thread was
3055 * dispatched. This field is only required for the end-of-
3056 * thread message and on all dual-source messages."
3058 if (brw
->gen
>= 6 &&
3059 (brw
->is_haswell
|| brw
->gen
>= 8 || !this->fp
->UsesKill
) &&
3061 key
->nr_color_regions
== 1) {
3062 header_present
= false;
3065 if (header_present
) {
3066 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
3068 key
->replicate_alpha
;
3073 if (payload
.aa_dest_stencil_reg
) {
3074 push_force_uncompressed();
3075 emit(MOV(fs_reg(MRF
, nr
++),
3076 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3077 pop_force_uncompressed();
3080 prog_data
->uses_omask
=
3081 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3082 if (prog_data
->uses_omask
) {
3083 this->current_annotation
= "FB write oMask";
3084 assert(this->sample_mask
.file
!= BAD_FILE
);
3085 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
3086 emit(FS_OPCODE_SET_OMASK
, fs_reg(MRF
, nr
, BRW_REGISTER_TYPE_UW
), this->sample_mask
);
3090 /* Reserve space for color. It'll be filled in per MRT below. */
3092 nr
+= 4 * reg_width
;
3095 if (src0_alpha_to_render_target
)
3098 if (source_depth_to_render_target
) {
3099 if (brw
->gen
== 6) {
3100 /* For outputting oDepth on gen6, SIMD8 writes have to be
3101 * used. This would require SIMD8 moves of each half to
3102 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3103 * Just bail on doing so for now.
3105 no16("Missing support for simd16 depth writes on gen6\n");
3108 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3109 /* Hand over gl_FragDepth. */
3110 assert(this->frag_depth
.file
!= BAD_FILE
);
3111 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
3113 /* Pass through the payload depth. */
3114 emit(MOV(fs_reg(MRF
, nr
),
3115 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3120 if (payload
.dest_depth_reg
) {
3121 emit(MOV(fs_reg(MRF
, nr
),
3122 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3127 fs_reg src0
= this->outputs
[0];
3128 fs_reg src1
= this->dual_src_output
;
3130 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3132 for (int i
= 0; i
< 4; i
++) {
3133 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
3135 inst
->saturate
= key
->clamp_fragment_color
;
3138 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3140 for (int i
= 0; i
< 4; i
++) {
3141 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
3144 inst
->saturate
= key
->clamp_fragment_color
;
3147 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3148 emit_shader_time_end();
3150 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3152 inst
->base_mrf
= base_mrf
;
3153 inst
->mlen
= nr
- base_mrf
;
3155 inst
->header_present
= header_present
;
3156 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
3157 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3158 inst
->flag_subreg
= 1;
3161 prog_data
->dual_src_blend
= true;
3162 this->current_annotation
= NULL
;
3166 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3167 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3168 "FB write target %d",
3170 /* If src0_alpha_to_render_target is true, include source zero alpha
3171 * data in RenderTargetWrite message for targets > 0.
3173 int write_color_mrf
= color_mrf
;
3174 if (src0_alpha_to_render_target
&& target
!= 0) {
3176 fs_reg color
= outputs
[0];
3177 color
.reg_offset
+= 3;
3179 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
3181 inst
->saturate
= key
->clamp_fragment_color
;
3182 write_color_mrf
= color_mrf
+ reg_width
;
3185 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
3186 emit_color_write(target
, i
, write_color_mrf
);
3189 if (target
== key
->nr_color_regions
- 1) {
3192 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3193 emit_shader_time_end();
3196 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3197 inst
->target
= target
;
3198 inst
->base_mrf
= base_mrf
;
3199 if (src0_alpha_to_render_target
&& target
== 0)
3200 inst
->mlen
= nr
- base_mrf
- reg_width
;
3202 inst
->mlen
= nr
- base_mrf
;
3204 inst
->header_present
= header_present
;
3205 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
3206 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3207 inst
->flag_subreg
= 1;
3211 if (key
->nr_color_regions
== 0) {
3212 /* Even if there's no color buffers enabled, we still need to send
3213 * alpha out the pipeline to our null renderbuffer to support
3214 * alpha-testing, alpha-to-coverage, and so on.
3216 emit_color_write(0, 3, color_mrf
);
3218 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3219 emit_shader_time_end();
3221 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
3222 inst
->base_mrf
= base_mrf
;
3223 inst
->mlen
= nr
- base_mrf
;
3225 inst
->header_present
= header_present
;
3226 if ((brw
->gen
>= 8 || brw
->is_haswell
) && fp
->UsesKill
) {
3227 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3228 inst
->flag_subreg
= 1;
3232 this->current_annotation
= NULL
;
3236 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3238 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3242 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
3243 emit(MOV(temp
, *reg
));
3248 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3250 assert(ctx
->Const
.UniformBooleanTrue
== 1);
3252 if (rvalue
->type
!= glsl_type::bool_type
)
3255 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
3256 emit(AND(temp
, *reg
, fs_reg(1)));
3260 fs_visitor::fs_visitor(struct brw_context
*brw
,
3262 const struct brw_wm_prog_key
*key
,
3263 struct brw_wm_prog_data
*prog_data
,
3264 struct gl_shader_program
*shader_prog
,
3265 struct gl_fragment_program
*fp
,
3266 unsigned dispatch_width
)
3267 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3268 MESA_SHADER_FRAGMENT
),
3269 key(key
), prog_data(prog_data
),
3270 dispatch_width(dispatch_width
)
3273 this->mem_ctx
= mem_ctx
;
3280 this->failed
= false;
3281 this->simd16_unsupported
= false;
3282 this->no16_msg
= NULL
;
3283 this->variable_ht
= hash_table_ctor(0,
3284 hash_table_pointer_hash
,
3285 hash_table_pointer_compare
);
3287 memset(&this->payload
, 0, sizeof(this->payload
));
3288 memset(this->outputs
, 0, sizeof(this->outputs
));
3289 memset(this->output_components
, 0, sizeof(this->output_components
));
3290 this->source_depth_to_render_target
= false;
3291 this->runtime_check_aads_emit
= false;
3292 this->first_non_payload_grf
= 0;
3293 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3295 this->current_annotation
= NULL
;
3296 this->base_ir
= NULL
;
3298 this->virtual_grf_sizes
= NULL
;
3299 this->virtual_grf_count
= 0;
3300 this->virtual_grf_array_size
= 0;
3301 this->virtual_grf_start
= NULL
;
3302 this->virtual_grf_end
= NULL
;
3303 this->live_intervals
= NULL
;
3304 this->regs_live_at_ip
= NULL
;
3307 this->last_scratch
= 0;
3308 this->pull_constant_loc
= NULL
;
3309 this->push_constant_loc
= NULL
;
3311 this->force_uncompressed_stack
= 0;
3313 this->spilled_any_registers
= false;
3314 this->do_dual_src
= false;
3316 if (dispatch_width
== 8)
3317 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3320 fs_visitor::~fs_visitor()
3322 hash_table_dtor(this->variable_ht
);