2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
82 bool is_rect
, uint32_t sampler
, int texunit
)
84 bool needs_gl_clamp
= true;
85 fs_reg scale_x
, scale_y
;
87 /* The 965 requires the EU to do the normalization of GL rectangle
88 * texture coordinates. We use the program parameter state
89 * tracking to get the scaling factor.
93 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
94 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
95 struct gl_program_parameter_list
*params
= prog
->Parameters
;
96 int tokens
[STATE_LENGTH
] = {
104 no16("rectangle scale uniform setup not supported on SIMD16\n");
105 if (dispatch_width
== 16) {
109 GLuint index
= _mesa_add_state_reference(params
,
110 (gl_state_index
*)tokens
);
111 /* Try to find existing copies of the texrect scale uniforms. */
112 for (unsigned i
= 0; i
< uniforms
; i
++) {
113 if (stage_prog_data
->param
[i
] ==
114 &prog
->Parameters
->ParameterValues
[index
][0]) {
115 scale_x
= fs_reg(UNIFORM
, i
);
116 scale_y
= fs_reg(UNIFORM
, i
+ 1);
121 /* If we didn't already set them up, do so now. */
122 if (scale_x
.file
== BAD_FILE
) {
123 scale_x
= fs_reg(UNIFORM
, uniforms
);
124 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
126 stage_prog_data
->param
[uniforms
++] =
127 &prog
->Parameters
->ParameterValues
[index
][0];
128 stage_prog_data
->param
[uniforms
++] =
129 &prog
->Parameters
->ParameterValues
[index
][1];
133 /* The 965 requires the EU to do the normalization of GL rectangle
134 * texture coordinates. We use the program parameter state
135 * tracking to get the scaling factor.
137 if (devinfo
->gen
< 6 && is_rect
) {
138 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
139 fs_reg src
= coordinate
;
142 bld
.MUL(dst
, src
, scale_x
);
143 dst
= offset(dst
, bld
, 1);
144 src
= offset(src
, bld
, 1);
145 bld
.MUL(dst
, src
, scale_y
);
146 } else if (is_rect
) {
147 /* On gen6+, the sampler handles the rectangle coordinates
148 * natively, without needing rescaling. But that means we have
149 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
150 * not [0, 1] like the default case below.
152 needs_gl_clamp
= false;
154 for (int i
= 0; i
< 2; i
++) {
155 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
156 fs_reg chan
= coordinate
;
157 chan
= offset(chan
, bld
, i
);
159 set_condmod(BRW_CONDITIONAL_GE
,
160 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
162 /* Our parameter comes in as 1.0/width or 1.0/height,
163 * because that's what people normally want for doing
164 * texture rectangle handling. We need width or height
165 * for clamping, but we don't care enough to make a new
166 * parameter type, so just invert back.
168 fs_reg limit
= vgrf(glsl_type::float_type
);
169 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
170 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
172 set_condmod(BRW_CONDITIONAL_L
,
173 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
178 if (coord_components
> 0 && needs_gl_clamp
) {
179 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
180 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
181 fs_reg chan
= coordinate
;
182 chan
= offset(chan
, bld
, i
);
183 set_saturate(true, bld
.MOV(chan
, chan
));
190 /* Sample from the MCS surface attached to this multisample texture. */
192 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
193 const fs_reg
&sampler
)
195 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
196 const fs_reg srcs
[] = {
197 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
198 sampler
, fs_reg(), fs_reg(components
), fs_reg(0)
200 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
203 /* We only care about one reg of response, but the sampler always writes
206 inst
->regs_written
= 4 * dispatch_width
/ 8;
212 fs_visitor::emit_texture(ir_texture_opcode op
,
213 const glsl_type
*dest_type
,
214 fs_reg coordinate
, int coord_components
,
216 fs_reg lod
, fs_reg lod2
, int grad_components
,
220 int gather_component
,
224 fs_reg sampler_reg
, int texunit
)
226 fs_inst
*inst
= NULL
;
229 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
230 * emitting anything other than setting up the constant result.
232 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
233 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
235 fs_reg res
= vgrf(glsl_type::vec4_type
);
238 for (int i
=0; i
<4; i
++) {
239 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
240 res
= offset(res
, bld
, 1);
246 if (op
== ir_query_levels
) {
247 /* textureQueryLevels() is implemented in terms of TXS so we need to
248 * pass a valid LOD argument.
250 assert(lod
.file
== BAD_FILE
);
254 if (coordinate
.file
!= BAD_FILE
) {
255 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
256 * samplers. This should only be a problem with GL_CLAMP on Gen7.
258 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
262 /* Writemasking doesn't eliminate channels on SIMD8 texture
263 * samples, so don't worry about them.
265 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
266 const fs_reg srcs
[] = {
267 coordinate
, shadow_c
, lod
, lod2
,
268 sample_index
, mcs
, sampler_reg
, offset_value
,
269 fs_reg(coord_components
), fs_reg(grad_components
)
275 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
278 opcode
= FS_OPCODE_TXB_LOGICAL
;
281 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
284 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
287 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
290 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
293 case ir_query_levels
:
294 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
297 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
300 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
301 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
304 unreachable("Invalid texture opcode.");
307 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
308 inst
->regs_written
= 4 * dispatch_width
/ 8;
310 if (shadow_c
.file
!= BAD_FILE
)
311 inst
->shadow_compare
= true;
313 if (offset_value
.file
== IMM
)
314 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
318 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
320 if (devinfo
->gen
== 6)
321 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
324 /* fixup #layers for cube map arrays */
325 if (op
== ir_txs
&& is_cube_array
) {
326 fs_reg depth
= offset(dst
, bld
, 2);
327 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
328 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
330 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
331 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
332 for (int i
= 0; i
< components
; i
++) {
334 fixed_payload
[i
] = fixed_depth
;
336 fixed_payload
[i
] = offset(dst
, bld
, i
);
339 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
342 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
346 * Apply workarounds for Gen6 gather with UINT/SINT
349 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
354 int width
= (wa
& WA_8BIT
) ? 8 : 16;
356 for (int i
= 0; i
< 4; i
++) {
357 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
358 /* Convert from UNORM to UINT */
359 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
363 /* Reinterpret the UINT value as a signed INT value by
364 * shifting the sign bit into place, then shifting back
367 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
368 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
371 dst
= offset(dst
, bld
, 1);
376 * Set up the gather channel based on the swizzle, for gather4.
379 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
381 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
383 case SWIZZLE_X
: return 0;
385 /* gather4 sampler is broken for green channel on RG32F --
386 * we must ask for blue instead.
388 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
391 case SWIZZLE_Z
: return 2;
392 case SWIZZLE_W
: return 3;
394 unreachable("Not reached"); /* zero, one swizzles handled already */
399 * Swizzle the result of a texture result. This is necessary for
400 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
403 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
404 fs_reg orig_val
, uint32_t sampler
)
406 if (op
== ir_query_levels
) {
407 /* # levels is in .w */
408 this->result
= offset(orig_val
, bld
, 3);
412 this->result
= orig_val
;
414 /* txs,lod don't actually sample the texture, so swizzling the result
417 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
420 if (dest_components
== 1) {
421 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
422 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
423 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
424 swizzled_result
.type
= orig_val
.type
;
426 for (int i
= 0; i
< 4; i
++) {
427 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
428 fs_reg l
= swizzled_result
;
429 l
= offset(l
, bld
, i
);
431 if (swiz
== SWIZZLE_ZERO
) {
432 bld
.MOV(l
, fs_reg(0.0f
));
433 } else if (swiz
== SWIZZLE_ONE
) {
434 bld
.MOV(l
, fs_reg(1.0f
));
436 bld
.MOV(l
, offset(orig_val
, bld
,
437 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
440 this->result
= swizzled_result
;
444 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
446 fs_visitor::emit_dummy_fs()
448 int reg_width
= dispatch_width
/ 8;
450 /* Everyone's favorite color. */
451 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
452 for (int i
= 0; i
< 4; i
++) {
453 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
458 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
460 if (devinfo
->gen
>= 6) {
462 write
->mlen
= 4 * reg_width
;
464 write
->header_size
= 2;
466 write
->mlen
= 2 + 4 * reg_width
;
469 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
470 * varying to avoid GPU hangs, so set that.
472 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
473 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
474 memset(wm_prog_data
->urb_setup
, -1,
475 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
477 /* We don't have any uniforms. */
478 stage_prog_data
->nr_params
= 0;
479 stage_prog_data
->nr_pull_params
= 0;
480 stage_prog_data
->curb_read_length
= 0;
481 stage_prog_data
->dispatch_grf_start_reg
= 2;
482 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
483 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
488 /* The register location here is relative to the start of the URB
489 * data. It will get adjusted to be a real location before
490 * generate_code() time.
493 fs_visitor::interp_reg(int location
, int channel
)
495 assert(stage
== MESA_SHADER_FRAGMENT
);
496 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
497 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
498 int stride
= (channel
& 1) * 4;
500 assert(prog_data
->urb_setup
[location
] != -1);
502 return brw_vec1_grf(regnr
, stride
);
505 /** Emits the interpolation for the varying inputs. */
507 fs_visitor::emit_interpolation_setup_gen4()
509 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
511 fs_builder abld
= bld
.annotate("compute pixel centers");
512 this->pixel_x
= vgrf(glsl_type::uint_type
);
513 this->pixel_y
= vgrf(glsl_type::uint_type
);
514 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
515 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
516 abld
.ADD(this->pixel_x
,
517 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
518 fs_reg(brw_imm_v(0x10101010)));
519 abld
.ADD(this->pixel_y
,
520 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
521 fs_reg(brw_imm_v(0x11001100)));
523 abld
= bld
.annotate("compute pixel deltas from v0");
525 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
526 vgrf(glsl_type::vec2_type
);
527 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
528 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
529 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
531 if (devinfo
->has_pln
&& dispatch_width
== 16) {
532 for (unsigned i
= 0; i
< 2; i
++) {
533 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
534 half(this->pixel_x
, i
), xstart
);
535 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
536 half(this->pixel_y
, i
), ystart
);
539 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
540 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
543 abld
= bld
.annotate("compute pos.w and 1/pos.w");
544 /* Compute wpos.w. It's always in our setup, since it's needed to
545 * interpolate the other attributes.
547 this->wpos_w
= vgrf(glsl_type::float_type
);
548 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
549 interp_reg(VARYING_SLOT_POS
, 3));
550 /* Compute the pixel 1/W value from wpos.w. */
551 this->pixel_w
= vgrf(glsl_type::float_type
);
552 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
555 /** Emits the interpolation for the varying inputs. */
557 fs_visitor::emit_interpolation_setup_gen6()
559 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
561 fs_builder abld
= bld
.annotate("compute pixel centers");
562 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
563 /* The "Register Region Restrictions" page says for BDW (and newer,
566 * "When destination spans two registers, the source may be one or
567 * two registers. The destination elements must be evenly split
568 * between the two registers."
570 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
571 * compute our pixel centers.
573 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
574 BRW_REGISTER_TYPE_UW
);
576 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
577 dbld
.ADD(int_pixel_xy
,
578 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
579 fs_reg(brw_imm_v(0x11001010)));
581 this->pixel_x
= vgrf(glsl_type::float_type
);
582 this->pixel_y
= vgrf(glsl_type::float_type
);
583 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
584 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
586 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
588 * "When destination spans two registers, the source MUST span two
591 * Since the GRF source of the ADD will only read a single register, we
592 * must do two separate ADDs in SIMD16.
594 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
595 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
596 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
597 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
598 abld
.ADD(int_pixel_x
,
599 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
600 fs_reg(brw_imm_v(0x10101010)));
601 abld
.ADD(int_pixel_y
,
602 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
603 fs_reg(brw_imm_v(0x11001100)));
605 /* As of gen6, we can no longer mix float and int sources. We have
606 * to turn the integer pixel centers into floats for their actual
609 this->pixel_x
= vgrf(glsl_type::float_type
);
610 this->pixel_y
= vgrf(glsl_type::float_type
);
611 abld
.MOV(this->pixel_x
, int_pixel_x
);
612 abld
.MOV(this->pixel_y
, int_pixel_y
);
615 abld
= bld
.annotate("compute pos.w");
616 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
617 this->wpos_w
= vgrf(glsl_type::float_type
);
618 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
620 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
621 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
622 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
626 static enum brw_conditional_mod
627 cond_for_alpha_func(GLenum func
)
631 return BRW_CONDITIONAL_G
;
633 return BRW_CONDITIONAL_GE
;
635 return BRW_CONDITIONAL_L
;
637 return BRW_CONDITIONAL_LE
;
639 return BRW_CONDITIONAL_EQ
;
641 return BRW_CONDITIONAL_NEQ
;
643 unreachable("Not reached");
648 * Alpha test support for when we compile it into the shader instead
649 * of using the normal fixed-function alpha test.
652 fs_visitor::emit_alpha_test()
654 assert(stage
== MESA_SHADER_FRAGMENT
);
655 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
656 const fs_builder abld
= bld
.annotate("Alpha test");
659 if (key
->alpha_test_func
== GL_ALWAYS
)
662 if (key
->alpha_test_func
== GL_NEVER
) {
664 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
665 BRW_REGISTER_TYPE_UW
));
666 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
667 BRW_CONDITIONAL_NEQ
);
670 fs_reg color
= offset(outputs
[0], bld
, 3);
672 /* f0.1 &= func(color, ref) */
673 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
674 cond_for_alpha_func(key
->alpha_test_func
));
676 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
677 cmp
->flag_subreg
= 1;
681 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
682 fs_reg color0
, fs_reg color1
,
683 fs_reg src0_alpha
, unsigned components
)
685 assert(stage
== MESA_SHADER_FRAGMENT
);
686 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
688 /* Hand over gl_FragDepth or the payload depth. */
689 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
690 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
694 if (source_depth_to_render_target
) {
695 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
696 src_depth
= frag_depth
;
698 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
701 const fs_reg sources
[] = {
702 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, sample_mask
,
705 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
706 sources
, ARRAY_SIZE(sources
));
708 if (prog_data
->uses_kill
) {
709 write
->predicate
= BRW_PREDICATE_NORMAL
;
710 write
->flag_subreg
= 1;
717 fs_visitor::emit_fb_writes()
719 assert(stage
== MESA_SHADER_FRAGMENT
);
720 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
721 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
723 fs_inst
*inst
= NULL
;
725 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
726 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
727 * would require SIMD8 moves of each half to message regs, e.g. by using
728 * the SIMD lowering pass. Unfortunately this is more difficult than it
729 * sounds because the SIMD8 single-source message lacks channel selects
730 * for the second and third subspans.
732 no16("Missing support for simd16 depth writes on gen6\n");
736 const fs_builder abld
= bld
.annotate("FB dual-source write");
738 inst
= emit_single_fb_write(abld
, this->outputs
[0],
739 this->dual_src_output
, reg_undef
, 4);
742 prog_data
->dual_src_blend
= true;
744 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
745 /* Skip over outputs that weren't written. */
746 if (this->outputs
[target
].file
== BAD_FILE
)
749 const fs_builder abld
= bld
.annotate(
750 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
753 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
754 src0_alpha
= offset(outputs
[0], bld
, 3);
756 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
758 this->output_components
[target
]);
759 inst
->target
= target
;
764 /* Even if there's no color buffers enabled, we still need to send
765 * alpha out the pipeline to our null renderbuffer to support
766 * alpha-testing, alpha-to-coverage, and so on.
768 /* FINISHME: Factor out this frequently recurring pattern into a
771 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
772 reg_undef
, offset(this->outputs
[0], bld
, 3) };
773 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
774 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
776 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
784 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
786 const struct brw_vue_prog_key
*key
=
787 (const struct brw_vue_prog_key
*) this->key
;
789 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
790 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
791 for (int j
= 0; j
< 4; ++j
) {
792 stage_prog_data
->param
[uniforms
+ j
] =
793 (gl_constant_value
*) &clip_planes
[i
][j
];
800 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
802 * This does nothing if the shader uses gl_ClipDistance or user clipping is
803 * disabled altogether.
805 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
807 struct brw_vue_prog_data
*vue_prog_data
=
808 (struct brw_vue_prog_data
*) prog_data
;
809 const struct brw_vue_prog_key
*key
=
810 (const struct brw_vue_prog_key
*) this->key
;
812 /* Bail unless some sort of legacy clipping is enabled */
813 if (key
->nr_userclip_plane_consts
== 0)
816 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
818 * "If a linked set of shaders forming the vertex stage contains no
819 * static write to gl_ClipVertex or gl_ClipDistance, but the
820 * application has requested clipping against user clip planes through
821 * the API, then the coordinate written to gl_Position is used for
822 * comparison against the user clip planes."
824 * This function is only called if the shader didn't write to
825 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
826 * if the user wrote to it; otherwise we use gl_Position.
829 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
830 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
831 clip_vertex
= VARYING_SLOT_POS
;
833 /* If the clip vertex isn't written, skip this. Typically this means
834 * the GS will set up clipping. */
835 if (outputs
[clip_vertex
].file
== BAD_FILE
)
838 setup_uniform_clipplane_values(clip_planes
);
840 const fs_builder abld
= bld
.annotate("user clip distances");
842 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
843 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
845 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
846 fs_reg u
= userplane
[i
];
847 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
848 output
.reg_offset
= i
& 3;
850 abld
.MUL(output
, outputs
[clip_vertex
], u
);
851 for (int j
= 1; j
< 4; j
++) {
852 u
.reg
= userplane
[i
].reg
+ j
;
853 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
859 fs_visitor::emit_urb_writes()
861 int slot
, urb_offset
, length
;
862 struct brw_vs_prog_data
*vs_prog_data
=
863 (struct brw_vs_prog_data
*) prog_data
;
864 const struct brw_vs_prog_key
*key
=
865 (const struct brw_vs_prog_key
*) this->key
;
866 const GLbitfield64 psiz_mask
=
867 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
868 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
872 /* If we don't have any valid slots to write, just do a minimal urb write
873 * send to terminate the shader. This includes 1 slot of undefined data,
874 * because it's invalid to write 0 data:
876 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
877 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
878 * Write Data Payload:
880 * "The write data payload can be between 1 and 8 message phases long."
882 if (vue_map
->slots_valid
== 0) {
883 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
884 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
885 BRW_REGISTER_TYPE_UD
)));
887 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
897 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
898 fs_reg reg
, src
, zero
;
900 int varying
= vue_map
->slot_to_varying
[slot
];
902 case VARYING_SLOT_PSIZ
:
904 /* The point size varying slot is the vue header and is always in the
905 * vue map. But often none of the special varyings that live there
906 * are written and in that case we can skip writing to the vue
907 * header, provided the corresponding state properly clamps the
908 * values further down the pipeline. */
909 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
915 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
916 bld
.MOV(zero
, fs_reg(0u));
918 sources
[length
++] = zero
;
919 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
920 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
922 sources
[length
++] = zero
;
924 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
925 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
927 sources
[length
++] = zero
;
929 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
930 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
932 sources
[length
++] = zero
;
935 case BRW_VARYING_SLOT_NDC
:
936 case VARYING_SLOT_EDGE
:
937 unreachable("unexpected scalar vs output");
940 case BRW_VARYING_SLOT_PAD
:
944 /* gl_Position is always in the vue map, but isn't always written by
945 * the shader. Other varyings (clip distances) get added to the vue
946 * map but don't always get written. In those cases, the
947 * corresponding this->output[] slot will be invalid we and can skip
948 * the urb write for the varying. If we've already queued up a vue
949 * slot for writing we flush a mlen 5 urb write, otherwise we just
950 * advance the urb_offset.
952 if (this->outputs
[varying
].file
== BAD_FILE
) {
960 if ((varying
== VARYING_SLOT_COL0
||
961 varying
== VARYING_SLOT_COL1
||
962 varying
== VARYING_SLOT_BFC0
||
963 varying
== VARYING_SLOT_BFC1
) &&
964 key
->clamp_vertex_color
) {
965 /* We need to clamp these guys, so do a saturating MOV into a
966 * temp register and use that for the payload.
968 for (int i
= 0; i
< 4; i
++) {
969 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
970 src
= offset(this->outputs
[varying
], bld
, i
);
971 set_saturate(true, bld
.MOV(reg
, src
));
972 sources
[length
++] = reg
;
975 for (int i
= 0; i
< 4; i
++)
976 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
981 const fs_builder abld
= bld
.annotate("URB write");
983 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
984 * the last slot or if we need to flush (see BAD_FILE varying case
985 * above), emit a URB write send now to flush out the data.
987 int last
= slot
== vue_map
->num_slots
- 1;
988 if (length
== 8 || last
)
991 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
992 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
993 BRW_REGISTER_TYPE_F
);
995 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
997 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
998 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1001 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1003 inst
->mlen
= length
+ 1;
1004 inst
->offset
= urb_offset
;
1005 urb_offset
= slot
+ 1;
1013 fs_visitor::emit_cs_terminate()
1015 assert(devinfo
->gen
>= 7);
1017 /* We are getting the thread ID from the compute shader header */
1018 assert(stage
== MESA_SHADER_COMPUTE
);
1020 /* We can't directly send from g0, since sends with EOT have to use
1021 * g112-127. So, copy it to a virtual register, The register allocator will
1022 * make sure it uses the appropriate register range.
1024 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1025 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1026 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
1028 /* Send a message to the thread spawner to terminate the thread. */
1029 fs_inst
*inst
= bld
.exec_all()
1030 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1035 fs_visitor::emit_barrier()
1037 assert(devinfo
->gen
>= 7);
1039 /* We are getting the barrier ID from the compute shader header */
1040 assert(stage
== MESA_SHADER_COMPUTE
);
1042 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1044 /* Clear the message payload */
1045 bld
.exec_all().MOV(payload
, fs_reg(0u));
1047 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1048 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1049 bld
.exec_all().AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1051 /* Emit a gateway "barrier" message using the payload we set up, followed
1052 * by a wait instruction.
1054 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1057 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1059 gl_shader_stage stage
,
1061 struct brw_stage_prog_data
*prog_data
,
1062 struct gl_shader_program
*shader_prog
,
1063 struct gl_program
*prog
,
1064 unsigned dispatch_width
,
1065 int shader_time_index
)
1066 : backend_shader(compiler
, log_data
, mem_ctx
,
1067 shader_prog
, prog
, prog_data
, stage
),
1068 key(key
), prog_data(prog_data
),
1069 dispatch_width(dispatch_width
),
1070 shader_time_index(shader_time_index
),
1071 promoted_constants(0),
1072 bld(fs_builder(this, dispatch_width
).at_end())
1075 case MESA_SHADER_FRAGMENT
:
1076 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1078 case MESA_SHADER_VERTEX
:
1079 case MESA_SHADER_GEOMETRY
:
1080 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
1082 case MESA_SHADER_COMPUTE
:
1083 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1086 unreachable("unhandled shader stage");
1089 this->failed
= false;
1090 this->simd16_unsupported
= false;
1091 this->no16_msg
= NULL
;
1093 this->nir_locals
= NULL
;
1094 this->nir_ssa_values
= NULL
;
1096 memset(&this->payload
, 0, sizeof(this->payload
));
1097 memset(this->outputs
, 0, sizeof(this->outputs
));
1098 memset(this->output_components
, 0, sizeof(this->output_components
));
1099 this->source_depth_to_render_target
= false;
1100 this->runtime_check_aads_emit
= false;
1101 this->first_non_payload_grf
= 0;
1102 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1104 this->virtual_grf_start
= NULL
;
1105 this->virtual_grf_end
= NULL
;
1106 this->live_intervals
= NULL
;
1107 this->regs_live_at_ip
= NULL
;
1110 this->last_scratch
= 0;
1111 this->pull_constant_loc
= NULL
;
1112 this->push_constant_loc
= NULL
;
1114 this->spilled_any_registers
= false;
1115 this->do_dual_src
= false;
1117 if (dispatch_width
== 8)
1118 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1121 fs_visitor::~fs_visitor()