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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "compiler/glsl_types.h"
36 fs_visitor::emit_vs_system_value(int location
)
38 fs_reg
*reg
= new(this->mem_ctx
)
39 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
41 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
44 case SYSTEM_VALUE_BASE_VERTEX
:
46 vs_prog_data
->uses_basevertex
= true;
48 case SYSTEM_VALUE_BASE_INSTANCE
:
50 vs_prog_data
->uses_baseinstance
= true;
52 case SYSTEM_VALUE_VERTEX_ID
:
53 unreachable("should have been lowered");
54 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
56 vs_prog_data
->uses_vertexid
= true;
58 case SYSTEM_VALUE_INSTANCE_ID
:
60 vs_prog_data
->uses_instanceid
= true;
62 case SYSTEM_VALUE_DRAW_ID
:
63 if (nir
->info
.system_values_read
&
64 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
65 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
66 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
67 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
)))
70 vs_prog_data
->uses_drawid
= true;
73 unreachable("not reached");
79 /* Sample from the MCS surface attached to this multisample texture. */
81 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
82 const fs_reg
&texture
)
84 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
86 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
87 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coordinate
;
88 srcs
[TEX_LOGICAL_SRC_SURFACE
] = texture
;
89 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = texture
;
90 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(components
);
91 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
93 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
96 /* We only care about one or two regs of response, but the sampler always
99 inst
->regs_written
= 4 * dispatch_width
/ 8;
105 fs_visitor::emit_texture(ir_texture_opcode op
,
106 const glsl_type
*dest_type
,
107 fs_reg coordinate
, int coord_components
,
109 fs_reg lod
, fs_reg lod2
, int grad_components
,
113 int gather_component
,
120 fs_inst
*inst
= NULL
;
122 if (op
== ir_query_levels
) {
123 /* textureQueryLevels() is implemented in terms of TXS so we need to
124 * pass a valid LOD argument.
126 assert(lod
.file
== BAD_FILE
);
127 lod
= brw_imm_ud(0u);
130 if (op
== ir_samples_identical
) {
131 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
133 /* If mcs is an immediate value, it means there is no MCS. In that case
136 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
137 bld
.MOV(dst
, brw_imm_ud(0u));
138 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
139 fs_reg tmp
= vgrf(glsl_type::uint_type
);
140 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
141 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
143 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
150 /* Writemasking doesn't eliminate channels on SIMD8 texture
151 * samples, so don't worry about them.
153 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
155 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
156 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coordinate
;
157 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = shadow_c
;
158 srcs
[TEX_LOGICAL_SRC_LOD
] = lod
;
159 srcs
[TEX_LOGICAL_SRC_LOD2
] = lod2
;
160 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample_index
;
161 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
162 srcs
[TEX_LOGICAL_SRC_SURFACE
] = surface_reg
;
163 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = sampler_reg
;
164 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = offset_value
;
165 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(coord_components
);
166 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(grad_components
);
171 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
174 opcode
= FS_OPCODE_TXB_LOGICAL
;
177 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
180 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
183 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
186 if ((key_tex
->msaa_16
& (1 << sampler
)))
187 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
189 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
192 case ir_query_levels
:
193 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
196 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
199 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
200 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
203 unreachable("Invalid texture opcode.");
206 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
207 inst
->regs_written
= 4 * dispatch_width
/ 8;
209 if (shadow_c
.file
!= BAD_FILE
)
210 inst
->shadow_compare
= true;
212 if (offset_value
.file
== IMM
)
213 inst
->offset
= offset_value
.ud
;
216 if (gather_component
== 1 &&
217 key_tex
->gather_channel_quirk_mask
& (1 << surface
)) {
218 /* gather4 sampler is broken for green channel on RG32F --
219 * we must ask for blue instead.
221 inst
->offset
|= 2 << 16;
223 inst
->offset
|= gather_component
<< 16;
226 if (devinfo
->gen
== 6)
227 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[surface
], dst
);
230 /* fixup #layers for cube map arrays */
231 if (op
== ir_txs
&& (devinfo
->gen
< 7 || is_cube_array
)) {
232 fs_reg depth
= offset(dst
, bld
, 2);
233 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
236 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
237 } else if (devinfo
->gen
< 7) {
238 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
239 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
242 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
243 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
244 for (int i
= 0; i
< components
; i
++) {
246 fixed_payload
[i
] = fixed_depth
;
248 fixed_payload
[i
] = offset(dst
, bld
, i
);
251 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
254 if (op
== ir_query_levels
) {
255 /* # levels is in .w */
256 dst
= offset(dst
, bld
, 3);
263 * Apply workarounds for Gen6 gather with UINT/SINT
266 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
271 int width
= (wa
& WA_8BIT
) ? 8 : 16;
273 for (int i
= 0; i
< 4; i
++) {
274 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
275 /* Convert from UNORM to UINT */
276 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
280 /* Reinterpret the UINT value as a signed INT value by
281 * shifting the sign bit into place, then shifting back
284 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
285 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
288 dst
= offset(dst
, bld
, 1);
292 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
294 fs_visitor::emit_dummy_fs()
296 int reg_width
= dispatch_width
/ 8;
298 /* Everyone's favorite color. */
299 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
300 for (int i
= 0; i
< 4; i
++) {
301 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
302 brw_imm_f(color
[i
]));
306 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
308 if (devinfo
->gen
>= 6) {
310 write
->mlen
= 4 * reg_width
;
312 write
->header_size
= 2;
314 write
->mlen
= 2 + 4 * reg_width
;
317 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
318 * varying to avoid GPU hangs, so set that.
320 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
321 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
322 memset(wm_prog_data
->urb_setup
, -1,
323 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
325 /* We don't have any uniforms. */
326 stage_prog_data
->nr_params
= 0;
327 stage_prog_data
->nr_pull_params
= 0;
328 stage_prog_data
->curb_read_length
= 0;
329 stage_prog_data
->dispatch_grf_start_reg
= 2;
330 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
331 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
336 /* The register location here is relative to the start of the URB
337 * data. It will get adjusted to be a real location before
338 * generate_code() time.
341 fs_visitor::interp_reg(int location
, int channel
)
343 assert(stage
== MESA_SHADER_FRAGMENT
);
344 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
345 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
346 int stride
= (channel
& 1) * 4;
348 assert(prog_data
->urb_setup
[location
] != -1);
350 return brw_vec1_grf(regnr
, stride
);
353 /** Emits the interpolation for the varying inputs. */
355 fs_visitor::emit_interpolation_setup_gen4()
357 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
359 fs_builder abld
= bld
.annotate("compute pixel centers");
360 this->pixel_x
= vgrf(glsl_type::uint_type
);
361 this->pixel_y
= vgrf(glsl_type::uint_type
);
362 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
363 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
364 abld
.ADD(this->pixel_x
,
365 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
366 fs_reg(brw_imm_v(0x10101010)));
367 abld
.ADD(this->pixel_y
,
368 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
369 fs_reg(brw_imm_v(0x11001100)));
371 abld
= bld
.annotate("compute pixel deltas from v0");
373 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
374 vgrf(glsl_type::vec2_type
);
375 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
376 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
377 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
379 if (devinfo
->has_pln
&& dispatch_width
== 16) {
380 for (unsigned i
= 0; i
< 2; i
++) {
381 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
382 half(this->pixel_x
, i
), xstart
);
383 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
384 half(this->pixel_y
, i
), ystart
);
387 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
388 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
391 abld
= bld
.annotate("compute pos.w and 1/pos.w");
392 /* Compute wpos.w. It's always in our setup, since it's needed to
393 * interpolate the other attributes.
395 this->wpos_w
= vgrf(glsl_type::float_type
);
396 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
397 interp_reg(VARYING_SLOT_POS
, 3));
398 /* Compute the pixel 1/W value from wpos.w. */
399 this->pixel_w
= vgrf(glsl_type::float_type
);
400 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
403 /** Emits the interpolation for the varying inputs. */
405 fs_visitor::emit_interpolation_setup_gen6()
407 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
409 fs_builder abld
= bld
.annotate("compute pixel centers");
410 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
411 /* The "Register Region Restrictions" page says for BDW (and newer,
414 * "When destination spans two registers, the source may be one or
415 * two registers. The destination elements must be evenly split
416 * between the two registers."
418 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
419 * compute our pixel centers.
421 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
422 BRW_REGISTER_TYPE_UW
);
424 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
425 dbld
.ADD(int_pixel_xy
,
426 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
427 fs_reg(brw_imm_v(0x11001010)));
429 this->pixel_x
= vgrf(glsl_type::float_type
);
430 this->pixel_y
= vgrf(glsl_type::float_type
);
431 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
432 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
434 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
436 * "When destination spans two registers, the source MUST span two
439 * Since the GRF source of the ADD will only read a single register, we
440 * must do two separate ADDs in SIMD16.
442 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
443 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
444 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
445 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
446 abld
.ADD(int_pixel_x
,
447 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
448 fs_reg(brw_imm_v(0x10101010)));
449 abld
.ADD(int_pixel_y
,
450 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
451 fs_reg(brw_imm_v(0x11001100)));
453 /* As of gen6, we can no longer mix float and int sources. We have
454 * to turn the integer pixel centers into floats for their actual
457 this->pixel_x
= vgrf(glsl_type::float_type
);
458 this->pixel_y
= vgrf(glsl_type::float_type
);
459 abld
.MOV(this->pixel_x
, int_pixel_x
);
460 abld
.MOV(this->pixel_y
, int_pixel_y
);
463 abld
= bld
.annotate("compute pos.w");
464 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
465 this->wpos_w
= vgrf(glsl_type::float_type
);
466 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
468 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
469 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
470 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
474 static enum brw_conditional_mod
475 cond_for_alpha_func(GLenum func
)
479 return BRW_CONDITIONAL_G
;
481 return BRW_CONDITIONAL_GE
;
483 return BRW_CONDITIONAL_L
;
485 return BRW_CONDITIONAL_LE
;
487 return BRW_CONDITIONAL_EQ
;
489 return BRW_CONDITIONAL_NEQ
;
491 unreachable("Not reached");
496 * Alpha test support for when we compile it into the shader instead
497 * of using the normal fixed-function alpha test.
500 fs_visitor::emit_alpha_test()
502 assert(stage
== MESA_SHADER_FRAGMENT
);
503 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
504 const fs_builder abld
= bld
.annotate("Alpha test");
507 if (key
->alpha_test_func
== GL_ALWAYS
)
510 if (key
->alpha_test_func
== GL_NEVER
) {
512 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
513 BRW_REGISTER_TYPE_UW
));
514 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
515 BRW_CONDITIONAL_NEQ
);
518 fs_reg color
= offset(outputs
[0], bld
, 3);
520 /* f0.1 &= func(color, ref) */
521 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
522 cond_for_alpha_func(key
->alpha_test_func
));
524 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
525 cmp
->flag_subreg
= 1;
529 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
530 fs_reg color0
, fs_reg color1
,
531 fs_reg src0_alpha
, unsigned components
)
533 assert(stage
== MESA_SHADER_FRAGMENT
);
534 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
536 /* Hand over gl_FragDepth or the payload depth. */
537 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
538 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
540 fs_reg src_depth
, src_stencil
;
542 if (source_depth_to_render_target
) {
543 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
544 src_depth
= frag_depth
;
546 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
549 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
550 src_stencil
= frag_stencil
;
552 const fs_reg sources
[] = {
553 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
554 sample_mask
, brw_imm_ud(components
)
556 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
557 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
558 sources
, ARRAY_SIZE(sources
));
560 if (prog_data
->uses_kill
) {
561 write
->predicate
= BRW_PREDICATE_NORMAL
;
562 write
->flag_subreg
= 1;
569 fs_visitor::emit_fb_writes()
571 assert(stage
== MESA_SHADER_FRAGMENT
);
572 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
573 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
575 fs_inst
*inst
= NULL
;
577 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
578 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
579 * would require SIMD8 moves of each half to message regs, e.g. by using
580 * the SIMD lowering pass. Unfortunately this is more difficult than it
581 * sounds because the SIMD8 single-source message lacks channel selects
582 * for the second and third subspans.
584 no16("Missing support for simd16 depth writes on gen6\n");
587 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
588 /* From the 'Render Target Write message' section of the docs:
589 * "Output Stencil is not supported with SIMD16 Render Target Write
592 * FINISHME: split 16 into 2 8s
594 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
598 const fs_builder abld
= bld
.annotate("FB dual-source write");
600 inst
= emit_single_fb_write(abld
, this->outputs
[0],
601 this->dual_src_output
, reg_undef
, 4);
604 prog_data
->dual_src_blend
= true;
606 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
607 /* Skip over outputs that weren't written. */
608 if (this->outputs
[target
].file
== BAD_FILE
)
611 const fs_builder abld
= bld
.annotate(
612 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
615 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
616 src0_alpha
= offset(outputs
[0], bld
, 3);
618 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
620 this->output_components
[target
]);
621 inst
->target
= target
;
626 /* Even if there's no color buffers enabled, we still need to send
627 * alpha out the pipeline to our null renderbuffer to support
628 * alpha-testing, alpha-to-coverage, and so on.
630 /* FINISHME: Factor out this frequently recurring pattern into a
633 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
634 reg_undef
, offset(this->outputs
[0], bld
, 3) };
635 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
636 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
638 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
646 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
648 const struct brw_vs_prog_key
*key
=
649 (const struct brw_vs_prog_key
*) this->key
;
651 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
652 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
653 for (int j
= 0; j
< 4; ++j
) {
654 stage_prog_data
->param
[uniforms
+ j
] =
655 (gl_constant_value
*) &clip_planes
[i
][j
];
662 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
664 * This does nothing if the shader uses gl_ClipDistance or user clipping is
665 * disabled altogether.
667 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
669 struct brw_vue_prog_data
*vue_prog_data
=
670 (struct brw_vue_prog_data
*) prog_data
;
671 const struct brw_vs_prog_key
*key
=
672 (const struct brw_vs_prog_key
*) this->key
;
674 /* Bail unless some sort of legacy clipping is enabled */
675 if (key
->nr_userclip_plane_consts
== 0)
678 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
680 * "If a linked set of shaders forming the vertex stage contains no
681 * static write to gl_ClipVertex or gl_ClipDistance, but the
682 * application has requested clipping against user clip planes through
683 * the API, then the coordinate written to gl_Position is used for
684 * comparison against the user clip planes."
686 * This function is only called if the shader didn't write to
687 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
688 * if the user wrote to it; otherwise we use gl_Position.
691 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
692 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
693 clip_vertex
= VARYING_SLOT_POS
;
695 /* If the clip vertex isn't written, skip this. Typically this means
696 * the GS will set up clipping. */
697 if (outputs
[clip_vertex
].file
== BAD_FILE
)
700 setup_uniform_clipplane_values(clip_planes
);
702 const fs_builder abld
= bld
.annotate("user clip distances");
704 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
705 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
706 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
707 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
709 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
710 fs_reg u
= userplane
[i
];
711 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
712 output
.reg_offset
= i
& 3;
714 abld
.MUL(output
, outputs
[clip_vertex
], u
);
715 for (int j
= 1; j
< 4; j
++) {
716 u
.nr
= userplane
[i
].nr
+ j
;
717 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
723 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
725 int slot
, urb_offset
, length
;
726 int starting_urb_offset
= 0;
727 const struct brw_vue_prog_data
*vue_prog_data
=
728 (const struct brw_vue_prog_data
*) this->prog_data
;
729 const struct brw_vs_prog_key
*vs_key
=
730 (const struct brw_vs_prog_key
*) this->key
;
731 const GLbitfield64 psiz_mask
=
732 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
733 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
738 if (stage
== MESA_SHADER_TESS_EVAL
)
739 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
741 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
743 /* If we don't have any valid slots to write, just do a minimal urb write
744 * send to terminate the shader. This includes 1 slot of undefined data,
745 * because it's invalid to write 0 data:
747 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
748 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
749 * Write Data Payload:
751 * "The write data payload can be between 1 and 8 message phases long."
753 if (vue_map
->slots_valid
== 0) {
754 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
755 bld
.exec_all().MOV(payload
, urb_handle
);
757 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
764 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
766 fs_reg per_slot_offsets
;
768 if (stage
== MESA_SHADER_GEOMETRY
) {
769 const struct brw_gs_prog_data
*gs_prog_data
=
770 (const struct brw_gs_prog_data
*) this->prog_data
;
772 /* We need to increment the Global Offset to skip over the control data
773 * header and the extra "Vertex Count" field (1 HWord) at the beginning
774 * of the VUE. We're counting in OWords, so the units are doubled.
776 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
777 if (gs_prog_data
->static_vertex_count
== -1)
778 starting_urb_offset
+= 2;
780 /* We also need to use per-slot offsets. The per-slot offset is the
781 * Vertex Count. SIMD8 mode processes 8 different primitives at a
782 * time; each may output a different number of vertices.
784 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
787 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
788 const int output_vertex_size_owords
=
789 gs_prog_data
->output_vertex_size_hwords
* 2;
791 if (gs_vertex_count
.file
== IMM
) {
792 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
795 per_slot_offsets
= vgrf(glsl_type::int_type
);
796 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
797 brw_imm_ud(output_vertex_size_owords
));
802 urb_offset
= starting_urb_offset
;
804 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
805 int varying
= vue_map
->slot_to_varying
[slot
];
807 case VARYING_SLOT_PSIZ
: {
808 /* The point size varying slot is the vue header and is always in the
809 * vue map. But often none of the special varyings that live there
810 * are written and in that case we can skip writing to the vue
811 * header, provided the corresponding state properly clamps the
812 * values further down the pipeline. */
813 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
819 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
820 bld
.MOV(zero
, brw_imm_ud(0u));
822 sources
[length
++] = zero
;
823 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
824 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
826 sources
[length
++] = zero
;
828 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
829 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
831 sources
[length
++] = zero
;
833 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
834 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
836 sources
[length
++] = zero
;
839 case BRW_VARYING_SLOT_NDC
:
840 case VARYING_SLOT_EDGE
:
841 unreachable("unexpected scalar vs output");
845 /* gl_Position is always in the vue map, but isn't always written by
846 * the shader. Other varyings (clip distances) get added to the vue
847 * map but don't always get written. In those cases, the
848 * corresponding this->output[] slot will be invalid we and can skip
849 * the urb write for the varying. If we've already queued up a vue
850 * slot for writing we flush a mlen 5 urb write, otherwise we just
851 * advance the urb_offset.
853 if (varying
== BRW_VARYING_SLOT_PAD
||
854 this->outputs
[varying
].file
== BAD_FILE
) {
862 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
863 (varying
== VARYING_SLOT_COL0
||
864 varying
== VARYING_SLOT_COL1
||
865 varying
== VARYING_SLOT_BFC0
||
866 varying
== VARYING_SLOT_BFC1
)) {
867 /* We need to clamp these guys, so do a saturating MOV into a
868 * temp register and use that for the payload.
870 for (int i
= 0; i
< 4; i
++) {
871 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
872 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
873 set_saturate(true, bld
.MOV(reg
, src
));
874 sources
[length
++] = reg
;
877 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
878 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
879 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
880 sources
[length
++] = brw_imm_d(0);
885 const fs_builder abld
= bld
.annotate("URB write");
887 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
888 * the last slot or if we need to flush (see BAD_FILE varying case
889 * above), emit a URB write send now to flush out the data.
891 int last
= slot
== vue_map
->num_slots
- 1;
892 if (length
== 8 || last
)
895 fs_reg
*payload_sources
=
896 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
897 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
898 BRW_REGISTER_TYPE_F
);
899 payload_sources
[0] = urb_handle
;
901 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
902 payload_sources
[1] = per_slot_offsets
;
904 memcpy(&payload_sources
[header_size
], sources
,
905 length
* sizeof sources
[0]);
907 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
910 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
911 inst
->eot
= last
&& stage
!= MESA_SHADER_GEOMETRY
;
912 inst
->mlen
= length
+ header_size
;
913 inst
->offset
= urb_offset
;
914 urb_offset
= starting_urb_offset
+ slot
+ 1;
922 fs_visitor::emit_cs_terminate()
924 assert(devinfo
->gen
>= 7);
926 /* We are getting the thread ID from the compute shader header */
927 assert(stage
== MESA_SHADER_COMPUTE
);
929 /* We can't directly send from g0, since sends with EOT have to use
930 * g112-127. So, copy it to a virtual register, The register allocator will
931 * make sure it uses the appropriate register range.
933 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
934 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
935 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
937 /* Send a message to the thread spawner to terminate the thread. */
938 fs_inst
*inst
= bld
.exec_all()
939 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
944 fs_visitor::emit_barrier()
946 assert(devinfo
->gen
>= 7);
947 const uint32_t barrier_id_mask
=
948 devinfo
->gen
>= 9 ? 0x8f000000u
: 0x0f000000u
;
950 /* We are getting the barrier ID from the compute shader header */
951 assert(stage
== MESA_SHADER_COMPUTE
);
953 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
955 const fs_builder pbld
= bld
.exec_all().group(8, 0);
957 /* Clear the message payload */
958 pbld
.MOV(payload
, brw_imm_ud(0u));
960 /* Copy the barrier id from r0.2 to the message payload reg.2 */
961 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
962 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(barrier_id_mask
));
964 /* Emit a gateway "barrier" message using the payload we set up, followed
965 * by a wait instruction.
967 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
970 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
973 struct brw_stage_prog_data
*prog_data
,
974 struct gl_program
*prog
,
975 const nir_shader
*shader
,
976 unsigned dispatch_width
,
977 int shader_time_index
,
978 const struct brw_vue_map
*input_vue_map
)
979 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
980 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
981 input_vue_map(input_vue_map
),
982 dispatch_width(dispatch_width
),
983 shader_time_index(shader_time_index
),
984 bld(fs_builder(this, dispatch_width
).at_end())
989 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
991 struct brw_gs_compile
*c
,
992 struct brw_gs_prog_data
*prog_data
,
993 const nir_shader
*shader
,
994 int shader_time_index
)
995 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
996 &prog_data
->base
.base
),
997 key(&c
->key
), gs_compile(c
),
998 prog_data(&prog_data
->base
.base
), prog(NULL
),
1000 shader_time_index(shader_time_index
),
1001 bld(fs_builder(this, dispatch_width
).at_end())
1011 case MESA_SHADER_FRAGMENT
:
1012 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1014 case MESA_SHADER_VERTEX
:
1015 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
1017 case MESA_SHADER_TESS_EVAL
:
1018 key_tex
= &((const brw_tes_prog_key
*) key
)->tex
;
1020 case MESA_SHADER_GEOMETRY
:
1021 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
1023 case MESA_SHADER_COMPUTE
:
1024 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1027 unreachable("unhandled shader stage");
1030 if (stage
== MESA_SHADER_COMPUTE
) {
1031 const brw_cs_prog_data
*cs_prog_data
=
1032 (const brw_cs_prog_data
*) prog_data
;
1033 unsigned size
= cs_prog_data
->local_size
[0] *
1034 cs_prog_data
->local_size
[1] *
1035 cs_prog_data
->local_size
[2];
1036 size
= DIV_ROUND_UP(size
, devinfo
->max_cs_threads
);
1037 min_dispatch_width
= size
> 16 ? 32 : (size
> 8 ? 16 : 8);
1039 min_dispatch_width
= 8;
1042 this->prog_data
= this->stage_prog_data
;
1044 this->failed
= false;
1045 this->simd16_unsupported
= false;
1046 this->no16_msg
= NULL
;
1048 this->nir_locals
= NULL
;
1049 this->nir_ssa_values
= NULL
;
1051 memset(&this->payload
, 0, sizeof(this->payload
));
1052 memset(this->output_components
, 0, sizeof(this->output_components
));
1053 this->source_depth_to_render_target
= false;
1054 this->runtime_check_aads_emit
= false;
1055 this->first_non_payload_grf
= 0;
1056 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1058 this->virtual_grf_start
= NULL
;
1059 this->virtual_grf_end
= NULL
;
1060 this->live_intervals
= NULL
;
1061 this->regs_live_at_ip
= NULL
;
1064 this->last_scratch
= 0;
1065 this->pull_constant_loc
= NULL
;
1066 this->push_constant_loc
= NULL
;
1068 this->promoted_constants
= 0,
1070 this->spilled_any_registers
= false;
1071 this->do_dual_src
= false;
1074 fs_visitor::~fs_visitor()