2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
82 fs_reg coordinate
, int coord_components
,
84 fs_reg lod
, fs_reg dPdy
, int grad_components
,
95 if (shadow_c
.file
!= BAD_FILE
) {
96 for (int i
= 0; i
< coord_components
; i
++) {
97 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
98 coordinate
= offset(coordinate
, 1);
101 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
102 * the unused slots must be zeroed.
104 for (int i
= coord_components
; i
< 3; i
++) {
105 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
110 /* There's no plain shadow compare message, so we use shadow
111 * compare with a bias of 0.0.
113 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
115 } else if (op
== ir_txb
|| op
== ir_txl
) {
116 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
);
119 unreachable("Should not get here.");
122 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
124 } else if (op
== ir_tex
) {
125 for (int i
= 0; i
< coord_components
; i
++) {
126 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
127 coordinate
= offset(coordinate
, 1);
129 /* zero the others. */
130 for (int i
= coord_components
; i
<3; i
++) {
131 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
133 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
135 } else if (op
== ir_txd
) {
138 for (int i
= 0; i
< coord_components
; i
++) {
139 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
140 coordinate
= offset(coordinate
, 1);
142 /* the slots for u and v are always present, but r is optional */
143 mlen
+= MAX2(coord_components
, 2);
146 * dPdx = dudx, dvdx, drdx
147 * dPdy = dudy, dvdy, drdy
149 * 1-arg: Does not exist.
151 * 2-arg: dudx dvdx dudy dvdy
152 * dPdx.x dPdx.y dPdy.x dPdy.y
155 * 3-arg: dudx dvdx drdx dudy dvdy drdy
156 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
159 for (int i
= 0; i
< grad_components
; i
++) {
160 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
161 dPdx
= offset(dPdx
, 1);
163 mlen
+= MAX2(grad_components
, 2);
165 for (int i
= 0; i
< grad_components
; i
++) {
166 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
167 dPdy
= offset(dPdy
, 1);
169 mlen
+= MAX2(grad_components
, 2);
170 } else if (op
== ir_txs
) {
171 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
173 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
176 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
177 * instructions. We'll need to do SIMD16 here.
180 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
182 for (int i
= 0; i
< coord_components
; i
++) {
183 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
185 coordinate
= offset(coordinate
, 1);
188 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
189 * be necessary for TXF (ld), but seems wise to do for all messages.
191 for (int i
= coord_components
; i
< 3; i
++) {
192 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
195 /* lod/bias appears after u/v/r. */
198 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
);
201 /* The unused upper half. */
206 /* Now, since we're doing simd16, the return is 2 interleaved
207 * vec4s where the odd-indexed ones are junk. We'll need to move
208 * this weirdness around to the expected layout.
211 dst
= fs_reg(GRF
, alloc
.allocate(8), orig_dst
.type
);
216 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
217 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
218 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
219 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
220 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
221 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
223 unreachable("not reached");
226 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
227 inst
->base_mrf
= base_mrf
;
229 inst
->header_size
= 1;
230 inst
->regs_written
= simd16
? 8 : 4;
233 for (int i
= 0; i
< 4; i
++) {
234 bld
.MOV(orig_dst
, dst
);
235 orig_dst
= offset(orig_dst
, 1);
236 dst
= offset(dst
, 2);
244 fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op
, fs_reg dst
,
245 fs_reg coordinate
, int vector_elements
,
246 fs_reg shadow_c
, fs_reg lod
,
249 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
250 bool has_lod
= op
== ir_txl
|| op
== ir_txb
|| op
== ir_txf
;
252 if (has_lod
&& shadow_c
.file
!= BAD_FILE
)
253 no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
256 no16("textureGrad unsupported in SIMD16.");
258 /* Copy the coordinates. */
259 for (int i
= 0; i
< vector_elements
; i
++) {
260 bld
.MOV(retype(offset(message
, i
), coordinate
.type
), coordinate
);
261 coordinate
= offset(coordinate
, 1);
264 fs_reg msg_end
= offset(message
, vector_elements
);
266 /* Messages other than sample and ld require all three components */
267 if (has_lod
|| shadow_c
.file
!= BAD_FILE
) {
268 for (int i
= vector_elements
; i
< 3; i
++) {
269 bld
.MOV(offset(message
, i
), fs_reg(0.0f
));
274 fs_reg msg_lod
= retype(offset(message
, 3), op
== ir_txf
?
275 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
276 bld
.MOV(msg_lod
, lod
);
277 msg_end
= offset(msg_lod
, 1);
280 if (shadow_c
.file
!= BAD_FILE
) {
281 fs_reg msg_ref
= offset(message
, 3 + has_lod
);
282 bld
.MOV(msg_ref
, shadow_c
);
283 msg_end
= offset(msg_ref
, 1);
288 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
289 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
290 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
291 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
292 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
293 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
294 default: unreachable("not reached");
297 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
298 inst
->base_mrf
= message
.reg
- 1;
299 inst
->mlen
= msg_end
.reg
- inst
->base_mrf
;
300 inst
->header_size
= 1;
301 inst
->regs_written
= 8;
306 /* gen5's sampler has slots for u, v, r, array index, then optional
307 * parameters like shadow comparitor or LOD bias. If optional
308 * parameters aren't present, those base slots are optional and don't
309 * need to be included in the message.
311 * We don't fill in the unnecessary slots regardless, which may look
312 * surprising in the disassembly.
315 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
316 fs_reg coordinate
, int vector_elements
,
318 fs_reg lod
, fs_reg lod2
, int grad_components
,
319 fs_reg sample_index
, uint32_t sampler
,
322 int reg_width
= dispatch_width
/ 8;
323 unsigned header_size
= 0;
325 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
326 fs_reg msg_coords
= message
;
329 /* The offsets set up by the ir_texture visitor are in the
330 * m1 header, so we can't go headerless.
336 for (int i
= 0; i
< vector_elements
; i
++) {
337 bld
.MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
);
338 coordinate
= offset(coordinate
, 1);
340 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
341 fs_reg msg_lod
= offset(msg_coords
, 4);
343 if (shadow_c
.file
!= BAD_FILE
) {
344 fs_reg msg_shadow
= msg_lod
;
345 bld
.MOV(msg_shadow
, shadow_c
);
346 msg_lod
= offset(msg_shadow
, 1);
353 opcode
= SHADER_OPCODE_TEX
;
356 bld
.MOV(msg_lod
, lod
);
357 msg_end
= offset(msg_lod
, 1);
359 opcode
= FS_OPCODE_TXB
;
362 bld
.MOV(msg_lod
, lod
);
363 msg_end
= offset(msg_lod
, 1);
365 opcode
= SHADER_OPCODE_TXL
;
370 * dPdx = dudx, dvdx, drdx
371 * dPdy = dudy, dvdy, drdy
373 * Load up these values:
374 * - dudx dudy dvdx dvdy drdx drdy
375 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
378 for (int i
= 0; i
< grad_components
; i
++) {
379 bld
.MOV(msg_end
, lod
);
380 lod
= offset(lod
, 1);
381 msg_end
= offset(msg_end
, 1);
383 bld
.MOV(msg_end
, lod2
);
384 lod2
= offset(lod2
, 1);
385 msg_end
= offset(msg_end
, 1);
388 opcode
= SHADER_OPCODE_TXD
;
392 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
393 bld
.MOV(msg_lod
, lod
);
394 msg_end
= offset(msg_lod
, 1);
396 opcode
= SHADER_OPCODE_TXS
;
398 case ir_query_levels
:
400 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
401 msg_end
= offset(msg_lod
, 1);
403 opcode
= SHADER_OPCODE_TXS
;
406 msg_lod
= offset(msg_coords
, 3);
407 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
408 msg_end
= offset(msg_lod
, 1);
410 opcode
= SHADER_OPCODE_TXF
;
413 msg_lod
= offset(msg_coords
, 3);
415 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
417 bld
.MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
418 msg_end
= offset(msg_lod
, 2);
420 opcode
= SHADER_OPCODE_TXF_CMS
;
423 opcode
= SHADER_OPCODE_LOD
;
426 opcode
= SHADER_OPCODE_TG4
;
429 unreachable("not reached");
432 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
433 inst
->base_mrf
= message
.reg
;
434 inst
->mlen
= msg_end
.reg
- message
.reg
;
435 inst
->header_size
= header_size
;
436 inst
->regs_written
= 4 * reg_width
;
438 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
439 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
440 " disallowed by hardware\n");
447 is_high_sampler(const struct brw_device_info
*devinfo
, fs_reg sampler
)
449 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
452 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
456 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
457 fs_reg coordinate
, int coord_components
,
459 fs_reg lod
, fs_reg lod2
, int grad_components
,
460 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
463 int reg_width
= dispatch_width
/ 8;
464 unsigned header_size
= 0;
466 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
467 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
468 sources
[i
] = vgrf(glsl_type::float_type
);
472 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
473 is_high_sampler(devinfo
, sampler
)) {
474 /* For general texture offsets (no txf workaround), we need a header to
475 * put them in. Note that for SIMD16 we're making space for two actual
476 * hardware registers here, so the emit will have to fix up for this.
478 * * ir4_tg4 needs to place its channel select in the header,
479 * for interaction with ARB_texture_swizzle
481 * The sampler index is only 4-bits, so for larger sampler numbers we
482 * need to offset the Sampler State Pointer in the header.
485 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
489 if (shadow_c
.file
!= BAD_FILE
) {
490 bld
.MOV(sources
[length
], shadow_c
);
494 bool has_nonconstant_offset
=
495 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
496 bool coordinate_done
= false;
498 /* The sampler can only meaningfully compute LOD for fragment shader
499 * messages. For all other stages, we change the opcode to ir_txl and
500 * hardcode the LOD to 0.
502 if (stage
!= MESA_SHADER_FRAGMENT
&& op
== ir_tex
) {
507 /* Set up the LOD info */
513 bld
.MOV(sources
[length
], lod
);
517 bld
.MOV(sources
[length
], lod
);
521 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
523 /* Load dPdx and the coordinate together:
524 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
526 for (int i
= 0; i
< coord_components
; i
++) {
527 bld
.MOV(sources
[length
], coordinate
);
528 coordinate
= offset(coordinate
, 1);
531 /* For cube map array, the coordinate is (u,v,r,ai) but there are
532 * only derivatives for (u, v, r).
534 if (i
< grad_components
) {
535 bld
.MOV(sources
[length
], lod
);
536 lod
= offset(lod
, 1);
539 bld
.MOV(sources
[length
], lod2
);
540 lod2
= offset(lod2
, 1);
545 coordinate_done
= true;
549 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
552 case ir_query_levels
:
553 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u));
557 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
558 * On Gen9 they are u, v, lod, r
561 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
562 coordinate
= offset(coordinate
, 1);
565 if (devinfo
->gen
>= 9) {
566 if (coord_components
>= 2) {
567 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
568 coordinate
= offset(coordinate
, 1);
573 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
576 for (int i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
577 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
578 coordinate
= offset(coordinate
, 1);
582 coordinate_done
= true;
585 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
588 /* data from the multisample control surface */
589 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
592 /* there is no offsetting for this message; just copy in the integer
593 * texture coordinates
595 for (int i
= 0; i
< coord_components
; i
++) {
596 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
597 coordinate
= offset(coordinate
, 1);
601 coordinate_done
= true;
604 if (has_nonconstant_offset
) {
605 if (shadow_c
.file
!= BAD_FILE
)
606 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
608 /* More crazy intermixing */
609 for (int i
= 0; i
< 2; i
++) { /* u, v */
610 bld
.MOV(sources
[length
], coordinate
);
611 coordinate
= offset(coordinate
, 1);
615 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
616 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
617 offset_value
= offset(offset_value
, 1);
621 if (coord_components
== 3) { /* r if present */
622 bld
.MOV(sources
[length
], coordinate
);
623 coordinate
= offset(coordinate
, 1);
627 coordinate_done
= true;
632 /* Set up the coordinate (except for cases where it was done above) */
633 if (!coordinate_done
) {
634 for (int i
= 0; i
< coord_components
; i
++) {
635 bld
.MOV(sources
[length
], coordinate
);
636 coordinate
= offset(coordinate
, 1);
643 mlen
= length
* reg_width
- header_size
;
645 mlen
= length
* reg_width
;
647 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
648 BRW_REGISTER_TYPE_F
, dispatch_width
);
649 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
651 /* Generate the SEND */
654 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
655 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
656 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
657 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
658 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
659 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
660 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
661 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
662 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
664 if (has_nonconstant_offset
)
665 opcode
= SHADER_OPCODE_TG4_OFFSET
;
667 opcode
= SHADER_OPCODE_TG4
;
670 unreachable("not reached");
672 fs_inst
*inst
= bld
.emit(opcode
, dst
, src_payload
, sampler
);
675 inst
->header_size
= header_size
;
676 inst
->regs_written
= 4 * reg_width
;
678 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
679 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
680 " disallowed by hardware\n");
687 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
688 bool is_rect
, uint32_t sampler
, int texunit
)
690 bool needs_gl_clamp
= true;
691 fs_reg scale_x
, scale_y
;
693 /* The 965 requires the EU to do the normalization of GL rectangle
694 * texture coordinates. We use the program parameter state
695 * tracking to get the scaling factor.
699 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
700 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
701 struct gl_program_parameter_list
*params
= prog
->Parameters
;
702 int tokens
[STATE_LENGTH
] = {
710 no16("rectangle scale uniform setup not supported on SIMD16\n");
711 if (dispatch_width
== 16) {
715 GLuint index
= _mesa_add_state_reference(params
,
716 (gl_state_index
*)tokens
);
717 /* Try to find existing copies of the texrect scale uniforms. */
718 for (unsigned i
= 0; i
< uniforms
; i
++) {
719 if (stage_prog_data
->param
[i
] ==
720 &prog
->Parameters
->ParameterValues
[index
][0]) {
721 scale_x
= fs_reg(UNIFORM
, i
);
722 scale_y
= fs_reg(UNIFORM
, i
+ 1);
727 /* If we didn't already set them up, do so now. */
728 if (scale_x
.file
== BAD_FILE
) {
729 scale_x
= fs_reg(UNIFORM
, uniforms
);
730 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
732 stage_prog_data
->param
[uniforms
++] =
733 &prog
->Parameters
->ParameterValues
[index
][0];
734 stage_prog_data
->param
[uniforms
++] =
735 &prog
->Parameters
->ParameterValues
[index
][1];
739 /* The 965 requires the EU to do the normalization of GL rectangle
740 * texture coordinates. We use the program parameter state
741 * tracking to get the scaling factor.
743 if (devinfo
->gen
< 6 && is_rect
) {
744 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
745 fs_reg src
= coordinate
;
748 bld
.MUL(dst
, src
, scale_x
);
749 dst
= offset(dst
, 1);
750 src
= offset(src
, 1);
751 bld
.MUL(dst
, src
, scale_y
);
752 } else if (is_rect
) {
753 /* On gen6+, the sampler handles the rectangle coordinates
754 * natively, without needing rescaling. But that means we have
755 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
756 * not [0, 1] like the default case below.
758 needs_gl_clamp
= false;
760 for (int i
= 0; i
< 2; i
++) {
761 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
762 fs_reg chan
= coordinate
;
763 chan
= offset(chan
, i
);
765 set_condmod(BRW_CONDITIONAL_GE
,
766 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
768 /* Our parameter comes in as 1.0/width or 1.0/height,
769 * because that's what people normally want for doing
770 * texture rectangle handling. We need width or height
771 * for clamping, but we don't care enough to make a new
772 * parameter type, so just invert back.
774 fs_reg limit
= vgrf(glsl_type::float_type
);
775 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
776 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
778 set_condmod(BRW_CONDITIONAL_L
,
779 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
784 if (coord_components
> 0 && needs_gl_clamp
) {
785 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
786 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
787 fs_reg chan
= coordinate
;
788 chan
= offset(chan
, i
);
789 set_saturate(true, bld
.MOV(chan
, chan
));
796 /* Sample from the MCS surface attached to this multisample texture. */
798 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
800 int reg_width
= dispatch_width
/ 8;
801 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(components
* reg_width
),
802 BRW_REGISTER_TYPE_F
, dispatch_width
);
803 fs_reg dest
= vgrf(glsl_type::uvec4_type
);
804 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
806 /* parameters are: u, v, r; missing parameters are treated as zero */
807 for (int i
= 0; i
< components
; i
++) {
808 sources
[i
] = vgrf(glsl_type::float_type
);
809 bld
.MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
);
810 coordinate
= offset(coordinate
, 1);
813 bld
.LOAD_PAYLOAD(payload
, sources
, components
, 0);
815 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
817 inst
->mlen
= components
* reg_width
;
818 inst
->header_size
= 0;
819 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
820 * response, but the sampler always
828 fs_visitor::emit_texture(ir_texture_opcode op
,
829 const glsl_type
*dest_type
,
830 fs_reg coordinate
, int coord_components
,
832 fs_reg lod
, fs_reg lod2
, int grad_components
,
836 int gather_component
,
840 fs_reg sampler_reg
, int texunit
)
842 fs_inst
*inst
= NULL
;
845 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
846 * emitting anything other than setting up the constant result.
848 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
849 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
851 fs_reg res
= vgrf(glsl_type::vec4_type
);
854 for (int i
=0; i
<4; i
++) {
855 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
856 res
= offset(res
, 1);
862 if (coordinate
.file
!= BAD_FILE
) {
863 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
864 * samplers. This should only be a problem with GL_CLAMP on Gen7.
866 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
870 /* Writemasking doesn't eliminate channels on SIMD8 texture
871 * samples, so don't worry about them.
873 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
875 if (devinfo
->gen
>= 7) {
876 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
877 shadow_c
, lod
, lod2
, grad_components
,
878 sample_index
, mcs
, sampler_reg
,
880 } else if (devinfo
->gen
>= 5) {
881 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
882 shadow_c
, lod
, lod2
, grad_components
,
883 sample_index
, sampler
,
884 offset_value
.file
!= BAD_FILE
);
885 } else if (dispatch_width
== 16) {
886 inst
= emit_texture_gen4_simd16(op
, dst
, coordinate
, coord_components
,
887 shadow_c
, lod
, sampler
);
889 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
890 shadow_c
, lod
, lod2
, grad_components
,
894 if (shadow_c
.file
!= BAD_FILE
)
895 inst
->shadow_compare
= true;
897 if (offset_value
.file
== IMM
)
898 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
902 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
904 if (devinfo
->gen
== 6)
905 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
908 /* fixup #layers for cube map arrays */
909 if (op
== ir_txs
&& is_cube_array
) {
910 fs_reg depth
= offset(dst
, 2);
911 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
912 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
914 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
915 int components
= inst
->regs_written
/ (dst
.width
/ 8);
916 for (int i
= 0; i
< components
; i
++) {
918 fixed_payload
[i
] = fixed_depth
;
920 fixed_payload
[i
] = offset(dst
, i
);
923 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
926 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
930 * Apply workarounds for Gen6 gather with UINT/SINT
933 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
938 int width
= (wa
& WA_8BIT
) ? 8 : 16;
940 for (int i
= 0; i
< 4; i
++) {
941 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
942 /* Convert from UNORM to UINT */
943 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
947 /* Reinterpret the UINT value as a signed INT value by
948 * shifting the sign bit into place, then shifting back
951 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
952 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
955 dst
= offset(dst
, 1);
960 * Set up the gather channel based on the swizzle, for gather4.
963 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
965 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
967 case SWIZZLE_X
: return 0;
969 /* gather4 sampler is broken for green channel on RG32F --
970 * we must ask for blue instead.
972 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
975 case SWIZZLE_Z
: return 2;
976 case SWIZZLE_W
: return 3;
978 unreachable("Not reached"); /* zero, one swizzles handled already */
983 * Swizzle the result of a texture result. This is necessary for
984 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
987 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
988 fs_reg orig_val
, uint32_t sampler
)
990 if (op
== ir_query_levels
) {
991 /* # levels is in .w */
992 this->result
= offset(orig_val
, 3);
996 this->result
= orig_val
;
998 /* txs,lod don't actually sample the texture, so swizzling the result
1001 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
1004 if (dest_components
== 1) {
1005 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1006 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
1007 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
1008 swizzled_result
.type
= orig_val
.type
;
1010 for (int i
= 0; i
< 4; i
++) {
1011 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
1012 fs_reg l
= swizzled_result
;
1015 if (swiz
== SWIZZLE_ZERO
) {
1016 bld
.MOV(l
, fs_reg(0.0f
));
1017 } else if (swiz
== SWIZZLE_ONE
) {
1018 bld
.MOV(l
, fs_reg(1.0f
));
1020 bld
.MOV(l
, offset(orig_val
,
1021 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
1024 this->result
= swizzled_result
;
1029 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1031 * Many GLSL shaders contain the following pattern:
1033 * x = condition ? foo : bar
1035 * The compiler emits an ir_if tree for this, since each subexpression might be
1036 * a complex tree that could have side-effects or short-circuit logic.
1038 * However, the common case is to simply select one of two constants or
1039 * variable values---which is exactly what SEL is for. In this case, the
1040 * assembly looks like:
1048 * which can be easily translated into:
1050 * (+f0) SEL dst src0 src1
1052 * If src0 is an immediate value, we promote it to a temporary GRF.
1055 fs_visitor::try_replace_with_sel()
1057 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
1058 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
1060 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1062 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
1065 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
1066 for (int i
= 0; i
< 4; i
++) {
1067 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
1069 match
= (fs_inst
*) match
->prev
;
1072 /* The opcodes match; it looks like the right sequence of instructions. */
1073 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
1074 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
1075 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
1077 /* Check that the MOVs are the right form. */
1078 if (then_mov
->dst
.equals(else_mov
->dst
) &&
1079 !then_mov
->is_partial_write() &&
1080 !else_mov
->is_partial_write()) {
1082 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1083 while (!if_inst
->next
->is_tail_sentinel())
1084 if_inst
->next
->exec_node::remove();
1085 if_inst
->exec_node::remove();
1087 /* Only the last source register can be a constant, so if the MOV in
1088 * the "then" clause uses a constant, we need to put it in a temporary.
1090 fs_reg
src0(then_mov
->src
[0]);
1091 if (src0
.file
== IMM
) {
1092 src0
= vgrf(glsl_type::float_type
);
1093 src0
.type
= then_mov
->src
[0].type
;
1094 bld
.MOV(src0
, then_mov
->src
[0]);
1097 if (if_inst
->conditional_mod
) {
1098 /* Sandybridge-specific IF with embedded comparison */
1099 bld
.CMP(bld
.null_reg_d(), if_inst
->src
[0], if_inst
->src
[1],
1100 if_inst
->conditional_mod
);
1101 set_predicate(BRW_PREDICATE_NORMAL
,
1102 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1103 src0
, else_mov
->src
[0]));
1105 /* Separate CMP and IF instructions */
1106 set_predicate_inv(if_inst
->predicate
, if_inst
->predicate_inverse
,
1107 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1108 src0
, else_mov
->src
[0]));
1118 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
1119 fs_reg dst
, fs_reg offset
, fs_reg src0
,
1122 int reg_width
= dispatch_width
/ 8;
1125 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
1127 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1128 /* Initialize the sample mask in the message header. */
1129 bld
.exec_all().MOV(sources
[0], fs_reg(0u));
1131 if (stage
== MESA_SHADER_FRAGMENT
) {
1132 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1134 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1137 .MOV(component(sources
[0], 7),
1138 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1141 /* The execution mask is part of the side-band information sent together with
1142 * the message payload to the data port. It's implicitly ANDed with the sample
1143 * mask sent in the header to compute the actual set of channels that execute
1144 * the atomic operation.
1146 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1148 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1152 /* Set the atomic operation offset. */
1153 sources
[1] = vgrf(glsl_type::uint_type
);
1154 bld
.MOV(sources
[1], offset
);
1157 /* Set the atomic operation arguments. */
1158 if (src0
.file
!= BAD_FILE
) {
1159 sources
[length
] = vgrf(glsl_type::uint_type
);
1160 bld
.MOV(sources
[length
], src0
);
1164 if (src1
.file
!= BAD_FILE
) {
1165 sources
[length
] = vgrf(glsl_type::uint_type
);
1166 bld
.MOV(sources
[length
], src1
);
1170 int mlen
= 1 + (length
- 1) * reg_width
;
1171 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1172 BRW_REGISTER_TYPE_UD
, dispatch_width
);
1173 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, 1);
1175 /* Emit the instruction. */
1176 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
1177 fs_reg(surf_index
), fs_reg(atomic_op
));
1182 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
1185 int reg_width
= dispatch_width
/ 8;
1187 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1189 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1190 /* Initialize the sample mask in the message header. */
1192 .MOV(sources
[0], fs_reg(0u));
1194 if (stage
== MESA_SHADER_FRAGMENT
) {
1195 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1197 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1200 .MOV(component(sources
[0], 7),
1201 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1204 /* The execution mask is part of the side-band information sent together with
1205 * the message payload to the data port. It's implicitly ANDed with the sample
1206 * mask sent in the header to compute the actual set of channels that execute
1207 * the atomic operation.
1209 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1211 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1214 /* Set the surface read offset. */
1215 sources
[1] = vgrf(glsl_type::uint_type
);
1216 bld
.MOV(sources
[1], offset
);
1218 int mlen
= 1 + reg_width
;
1219 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1220 BRW_REGISTER_TYPE_UD
, dispatch_width
);
1221 fs_inst
*inst
= bld
.LOAD_PAYLOAD(src_payload
, sources
, 2, 1);
1223 /* Emit the instruction. */
1224 inst
= bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
1225 fs_reg(surf_index
), fs_reg(1));
1229 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1231 fs_visitor::emit_dummy_fs()
1233 int reg_width
= dispatch_width
/ 8;
1235 /* Everyone's favorite color. */
1236 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
1237 for (int i
= 0; i
< 4; i
++) {
1238 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
,
1239 dispatch_width
), fs_reg(color
[i
]));
1243 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
1245 if (devinfo
->gen
>= 6) {
1246 write
->base_mrf
= 2;
1247 write
->mlen
= 4 * reg_width
;
1249 write
->header_size
= 2;
1250 write
->base_mrf
= 0;
1251 write
->mlen
= 2 + 4 * reg_width
;
1254 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
1255 * varying to avoid GPU hangs, so set that.
1257 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1258 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
1259 memset(wm_prog_data
->urb_setup
, -1,
1260 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1262 /* We don't have any uniforms. */
1263 stage_prog_data
->nr_params
= 0;
1264 stage_prog_data
->nr_pull_params
= 0;
1265 stage_prog_data
->curb_read_length
= 0;
1266 stage_prog_data
->dispatch_grf_start_reg
= 2;
1267 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
1268 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
1273 /* The register location here is relative to the start of the URB
1274 * data. It will get adjusted to be a real location before
1275 * generate_code() time.
1278 fs_visitor::interp_reg(int location
, int channel
)
1280 assert(stage
== MESA_SHADER_FRAGMENT
);
1281 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1282 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
1283 int stride
= (channel
& 1) * 4;
1285 assert(prog_data
->urb_setup
[location
] != -1);
1287 return brw_vec1_grf(regnr
, stride
);
1290 /** Emits the interpolation for the varying inputs. */
1292 fs_visitor::emit_interpolation_setup_gen4()
1294 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1296 fs_builder abld
= bld
.annotate("compute pixel centers");
1297 this->pixel_x
= vgrf(glsl_type::uint_type
);
1298 this->pixel_y
= vgrf(glsl_type::uint_type
);
1299 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1300 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1301 abld
.ADD(this->pixel_x
,
1302 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1303 fs_reg(brw_imm_v(0x10101010)));
1304 abld
.ADD(this->pixel_y
,
1305 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1306 fs_reg(brw_imm_v(0x11001100)));
1308 abld
= bld
.annotate("compute pixel deltas from v0");
1310 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1311 vgrf(glsl_type::vec2_type
);
1312 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1313 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
1314 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
1316 if (devinfo
->has_pln
&& dispatch_width
== 16) {
1317 for (unsigned i
= 0; i
< 2; i
++) {
1318 abld
.half(i
).ADD(half(offset(delta_xy
, i
), 0),
1319 half(this->pixel_x
, i
), xstart
);
1320 abld
.half(i
).ADD(half(offset(delta_xy
, i
), 1),
1321 half(this->pixel_y
, i
), ystart
);
1324 abld
.ADD(offset(delta_xy
, 0), this->pixel_x
, xstart
);
1325 abld
.ADD(offset(delta_xy
, 1), this->pixel_y
, ystart
);
1328 abld
= bld
.annotate("compute pos.w and 1/pos.w");
1329 /* Compute wpos.w. It's always in our setup, since it's needed to
1330 * interpolate the other attributes.
1332 this->wpos_w
= vgrf(glsl_type::float_type
);
1333 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
1334 interp_reg(VARYING_SLOT_POS
, 3));
1335 /* Compute the pixel 1/W value from wpos.w. */
1336 this->pixel_w
= vgrf(glsl_type::float_type
);
1337 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1340 /** Emits the interpolation for the varying inputs. */
1342 fs_visitor::emit_interpolation_setup_gen6()
1344 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1346 fs_builder abld
= bld
.annotate("compute pixel centers");
1347 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1348 /* The "Register Region Restrictions" page says for BDW (and newer,
1351 * "When destination spans two registers, the source may be one or
1352 * two registers. The destination elements must be evenly split
1353 * between the two registers."
1355 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
1356 * compute our pixel centers.
1358 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
1359 BRW_REGISTER_TYPE_UW
, dispatch_width
* 2);
1362 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
1363 fs_reg(brw_imm_v(0x11001010)));
1365 this->pixel_x
= vgrf(glsl_type::float_type
);
1366 this->pixel_y
= vgrf(glsl_type::float_type
);
1367 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
1368 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
1370 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
1372 * "When destination spans two registers, the source MUST span two
1375 * Since the GRF source of the ADD will only read a single register, we
1376 * must do two separate ADDs in SIMD16.
1378 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
1379 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
1380 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1381 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1382 abld
.ADD(int_pixel_x
,
1383 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1384 fs_reg(brw_imm_v(0x10101010)));
1385 abld
.ADD(int_pixel_y
,
1386 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1387 fs_reg(brw_imm_v(0x11001100)));
1389 /* As of gen6, we can no longer mix float and int sources. We have
1390 * to turn the integer pixel centers into floats for their actual
1393 this->pixel_x
= vgrf(glsl_type::float_type
);
1394 this->pixel_y
= vgrf(glsl_type::float_type
);
1395 abld
.MOV(this->pixel_x
, int_pixel_x
);
1396 abld
.MOV(this->pixel_y
, int_pixel_y
);
1399 abld
= bld
.annotate("compute pos.w");
1400 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
1401 this->wpos_w
= vgrf(glsl_type::float_type
);
1402 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1404 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1405 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
1406 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
1411 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
,
1412 unsigned exec_size
, bool use_2nd_half
)
1414 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1417 if (key
->clamp_fragment_color
) {
1418 fs_reg tmp
= vgrf(glsl_type::vec4_type
);
1419 assert(color
.type
== BRW_REGISTER_TYPE_F
);
1420 for (unsigned i
= 0; i
< components
; i
++) {
1421 inst
= bld
.MOV(offset(tmp
, i
), offset(color
, i
));
1422 inst
->saturate
= true;
1427 if (exec_size
< dispatch_width
) {
1428 unsigned half_idx
= use_2nd_half
? 1 : 0;
1429 for (unsigned i
= 0; i
< components
; i
++)
1430 dst
[i
] = half(offset(color
, i
), half_idx
);
1432 for (unsigned i
= 0; i
< components
; i
++)
1433 dst
[i
] = offset(color
, i
);
1437 static enum brw_conditional_mod
1438 cond_for_alpha_func(GLenum func
)
1442 return BRW_CONDITIONAL_G
;
1444 return BRW_CONDITIONAL_GE
;
1446 return BRW_CONDITIONAL_L
;
1448 return BRW_CONDITIONAL_LE
;
1450 return BRW_CONDITIONAL_EQ
;
1452 return BRW_CONDITIONAL_NEQ
;
1454 unreachable("Not reached");
1459 * Alpha test support for when we compile it into the shader instead
1460 * of using the normal fixed-function alpha test.
1463 fs_visitor::emit_alpha_test()
1465 assert(stage
== MESA_SHADER_FRAGMENT
);
1466 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1467 const fs_builder abld
= bld
.annotate("Alpha test");
1470 if (key
->alpha_test_func
== GL_ALWAYS
)
1473 if (key
->alpha_test_func
== GL_NEVER
) {
1475 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1476 BRW_REGISTER_TYPE_UW
));
1477 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
1478 BRW_CONDITIONAL_NEQ
);
1481 fs_reg color
= offset(outputs
[0], 3);
1483 /* f0.1 &= func(color, ref) */
1484 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
1485 cond_for_alpha_func(key
->alpha_test_func
));
1487 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1488 cmp
->flag_subreg
= 1;
1492 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
1493 fs_reg color0
, fs_reg color1
,
1494 fs_reg src0_alpha
, unsigned components
,
1495 unsigned exec_size
, bool use_2nd_half
)
1497 assert(stage
== MESA_SHADER_FRAGMENT
);
1498 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1499 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1500 int header_size
= 2, payload_header_size
;
1502 /* We can potentially have a message length of up to 15, so we have to set
1503 * base_mrf to either 0 or 1 in order to fit in m0..m15.
1505 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
1508 /* From the Sandy Bridge PRM, volume 4, page 198:
1510 * "Dispatched Pixel Enables. One bit per pixel indicating
1511 * which pixels were originally enabled when the thread was
1512 * dispatched. This field is only required for the end-of-
1513 * thread message and on all dual-source messages."
1515 if (devinfo
->gen
>= 6 &&
1516 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
1517 color1
.file
== BAD_FILE
&&
1518 key
->nr_color_regions
== 1) {
1522 if (header_size
!= 0) {
1523 assert(header_size
== 2);
1524 /* Allocate 2 registers for a header */
1528 if (payload
.aa_dest_stencil_reg
) {
1529 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1));
1530 bld
.exec_all().annotate("FB write stencil/AA alpha")
1531 .MOV(sources
[length
],
1532 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
1536 prog_data
->uses_omask
=
1537 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
1538 if (prog_data
->uses_omask
) {
1539 assert(this->sample_mask
.file
!= BAD_FILE
);
1540 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
1541 * it's unsinged single words, one vgrf is always 16-wide.
1543 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1),
1544 BRW_REGISTER_TYPE_UW
, 16);
1545 bld
.exec_all().annotate("FB write oMask")
1546 .emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
1550 payload_header_size
= length
;
1552 if (color0
.file
== BAD_FILE
) {
1553 /* Even if there's no color buffers enabled, we still need to send
1554 * alpha out the pipeline to our null renderbuffer to support
1555 * alpha-testing, alpha-to-coverage, and so on.
1557 if (this->outputs
[0].file
!= BAD_FILE
)
1558 setup_color_payload(&sources
[length
+ 3], offset(this->outputs
[0], 3),
1559 1, exec_size
, false);
1561 } else if (color1
.file
== BAD_FILE
) {
1562 if (src0_alpha
.file
!= BAD_FILE
) {
1563 setup_color_payload(&sources
[length
], src0_alpha
, 1, exec_size
, false);
1567 setup_color_payload(&sources
[length
], color0
, components
,
1568 exec_size
, use_2nd_half
);
1571 setup_color_payload(&sources
[length
], color0
, components
,
1572 exec_size
, use_2nd_half
);
1574 setup_color_payload(&sources
[length
], color1
, components
,
1575 exec_size
, use_2nd_half
);
1579 if (source_depth_to_render_target
) {
1580 if (devinfo
->gen
== 6) {
1581 /* For outputting oDepth on gen6, SIMD8 writes have to be
1582 * used. This would require SIMD8 moves of each half to
1583 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1584 * Just bail on doing so for now.
1586 no16("Missing support for simd16 depth writes on gen6\n");
1589 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
1590 /* Hand over gl_FragDepth. */
1591 assert(this->frag_depth
.file
!= BAD_FILE
);
1592 if (exec_size
< dispatch_width
) {
1593 sources
[length
] = half(this->frag_depth
, use_2nd_half
);
1595 sources
[length
] = this->frag_depth
;
1598 /* Pass through the payload depth. */
1599 sources
[length
] = fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
1604 if (payload
.dest_depth_reg
)
1605 sources
[length
++] = fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0));
1607 const fs_builder ubld
= bld
.group(exec_size
, use_2nd_half
);
1610 if (devinfo
->gen
>= 7) {
1611 /* Send from the GRF */
1612 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
, exec_size
);
1613 load
= ubld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
1614 payload
.reg
= alloc
.allocate(load
->regs_written
);
1615 load
->dst
= payload
;
1616 write
= ubld
.emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
1617 write
->base_mrf
= -1;
1619 /* Send from the MRF */
1620 load
= ubld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
, exec_size
),
1621 sources
, length
, payload_header_size
);
1623 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
1624 * will do this for us if we just give it a COMPR4 destination.
1626 if (devinfo
->gen
< 6 && exec_size
== 16)
1627 load
->dst
.reg
|= BRW_MRF_COMPR4
;
1629 write
= ubld
.emit(FS_OPCODE_FB_WRITE
);
1630 write
->exec_size
= exec_size
;
1631 write
->base_mrf
= 1;
1634 write
->mlen
= load
->regs_written
;
1635 write
->header_size
= header_size
;
1636 if (prog_data
->uses_kill
) {
1637 write
->predicate
= BRW_PREDICATE_NORMAL
;
1638 write
->flag_subreg
= 1;
1644 fs_visitor::emit_fb_writes()
1646 assert(stage
== MESA_SHADER_FRAGMENT
);
1647 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1648 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1650 fs_inst
*inst
= NULL
;
1652 const fs_builder abld
= bld
.annotate("FB dual-source write");
1654 inst
= emit_single_fb_write(abld
, this->outputs
[0],
1655 this->dual_src_output
, reg_undef
, 4, 8);
1658 /* SIMD16 dual source blending requires to send two SIMD8 dual source
1659 * messages, where each message contains color data for 8 pixels. Color
1660 * data for the first group of pixels is stored in the "lower" half of
1661 * the color registers, so in SIMD16, the previous message did:
1667 * Here goes the second message, which packs color data for the
1668 * remaining 8 pixels. Color data for these pixels is stored in the
1669 * "upper" half of the color registers, so we need to do:
1675 if (dispatch_width
== 16) {
1676 inst
= emit_single_fb_write(abld
, this->outputs
[0],
1677 this->dual_src_output
, reg_undef
, 4, 8,
1682 prog_data
->dual_src_blend
= true;
1684 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
1685 /* Skip over outputs that weren't written. */
1686 if (this->outputs
[target
].file
== BAD_FILE
)
1689 const fs_builder abld
= bld
.annotate(
1690 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
1693 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
1694 src0_alpha
= offset(outputs
[0], 3);
1696 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
1698 this->output_components
[target
],
1700 inst
->target
= target
;
1705 /* Even if there's no color buffers enabled, we still need to send
1706 * alpha out the pipeline to our null renderbuffer to support
1707 * alpha-testing, alpha-to-coverage, and so on.
1709 inst
= emit_single_fb_write(bld
, reg_undef
, reg_undef
, reg_undef
, 0,
1718 fs_visitor::setup_uniform_clipplane_values()
1720 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
1721 const struct brw_vue_prog_key
*key
=
1722 (const struct brw_vue_prog_key
*) this->key
;
1724 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1725 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
1726 for (int j
= 0; j
< 4; ++j
) {
1727 stage_prog_data
->param
[uniforms
+ j
] =
1728 (gl_constant_value
*) &clip_planes
[i
][j
];
1734 void fs_visitor::compute_clip_distance()
1736 struct brw_vue_prog_data
*vue_prog_data
=
1737 (struct brw_vue_prog_data
*) prog_data
;
1738 const struct brw_vue_prog_key
*key
=
1739 (const struct brw_vue_prog_key
*) this->key
;
1741 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
1743 * "If a linked set of shaders forming the vertex stage contains no
1744 * static write to gl_ClipVertex or gl_ClipDistance, but the
1745 * application has requested clipping against user clip planes through
1746 * the API, then the coordinate written to gl_Position is used for
1747 * comparison against the user clip planes."
1749 * This function is only called if the shader didn't write to
1750 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
1751 * if the user wrote to it; otherwise we use gl_Position.
1754 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
1755 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
1756 clip_vertex
= VARYING_SLOT_POS
;
1758 /* If the clip vertex isn't written, skip this. Typically this means
1759 * the GS will set up clipping. */
1760 if (outputs
[clip_vertex
].file
== BAD_FILE
)
1763 setup_uniform_clipplane_values();
1765 const fs_builder abld
= bld
.annotate("user clip distances");
1767 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
1768 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
1770 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1771 fs_reg u
= userplane
[i
];
1772 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
1773 output
.reg_offset
= i
& 3;
1775 abld
.MUL(output
, outputs
[clip_vertex
], u
);
1776 for (int j
= 1; j
< 4; j
++) {
1777 u
.reg
= userplane
[i
].reg
+ j
;
1778 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], j
), u
);
1784 fs_visitor::emit_urb_writes()
1786 int slot
, urb_offset
, length
;
1787 struct brw_vs_prog_data
*vs_prog_data
=
1788 (struct brw_vs_prog_data
*) prog_data
;
1789 const struct brw_vs_prog_key
*key
=
1790 (const struct brw_vs_prog_key
*) this->key
;
1791 const GLbitfield64 psiz_mask
=
1792 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
1793 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
1797 /* Lower legacy ff and ClipVertex clipping to clip distances */
1798 if (key
->base
.userclip_active
&& !prog
->UsesClipDistanceOut
)
1799 compute_clip_distance();
1801 /* If we don't have any valid slots to write, just do a minimal urb write
1802 * send to terminate the shader. */
1803 if (vue_map
->slots_valid
== 0) {
1805 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1806 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
1807 BRW_REGISTER_TYPE_UD
)));
1809 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1819 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
1820 fs_reg reg
, src
, zero
;
1822 int varying
= vue_map
->slot_to_varying
[slot
];
1824 case VARYING_SLOT_PSIZ
:
1826 /* The point size varying slot is the vue header and is always in the
1827 * vue map. But often none of the special varyings that live there
1828 * are written and in that case we can skip writing to the vue
1829 * header, provided the corresponding state properly clamps the
1830 * values further down the pipeline. */
1831 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
1832 assert(length
== 0);
1837 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1838 bld
.MOV(zero
, fs_reg(0u));
1840 sources
[length
++] = zero
;
1841 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
1842 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
1844 sources
[length
++] = zero
;
1846 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
1847 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
1849 sources
[length
++] = zero
;
1851 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
1852 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
1854 sources
[length
++] = zero
;
1857 case BRW_VARYING_SLOT_NDC
:
1858 case VARYING_SLOT_EDGE
:
1859 unreachable("unexpected scalar vs output");
1862 case BRW_VARYING_SLOT_PAD
:
1866 /* gl_Position is always in the vue map, but isn't always written by
1867 * the shader. Other varyings (clip distances) get added to the vue
1868 * map but don't always get written. In those cases, the
1869 * corresponding this->output[] slot will be invalid we and can skip
1870 * the urb write for the varying. If we've already queued up a vue
1871 * slot for writing we flush a mlen 5 urb write, otherwise we just
1872 * advance the urb_offset.
1874 if (this->outputs
[varying
].file
== BAD_FILE
) {
1882 if ((varying
== VARYING_SLOT_COL0
||
1883 varying
== VARYING_SLOT_COL1
||
1884 varying
== VARYING_SLOT_BFC0
||
1885 varying
== VARYING_SLOT_BFC1
) &&
1886 key
->clamp_vertex_color
) {
1887 /* We need to clamp these guys, so do a saturating MOV into a
1888 * temp register and use that for the payload.
1890 for (int i
= 0; i
< 4; i
++) {
1891 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
1892 src
= offset(this->outputs
[varying
], i
);
1893 set_saturate(true, bld
.MOV(reg
, src
));
1894 sources
[length
++] = reg
;
1897 for (int i
= 0; i
< 4; i
++)
1898 sources
[length
++] = offset(this->outputs
[varying
], i
);
1903 const fs_builder abld
= bld
.annotate("URB write");
1905 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
1906 * the last slot or if we need to flush (see BAD_FILE varying case
1907 * above), emit a URB write send now to flush out the data.
1909 int last
= slot
== vue_map
->num_slots
- 1;
1910 if (length
== 8 || last
)
1913 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
1914 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
1915 BRW_REGISTER_TYPE_F
, dispatch_width
);
1916 payload_sources
[0] =
1917 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1919 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
1920 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1923 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1925 inst
->mlen
= length
+ 1;
1926 inst
->offset
= urb_offset
;
1927 urb_offset
= slot
+ 1;
1935 fs_visitor::emit_cs_terminate()
1937 assert(devinfo
->gen
>= 7);
1939 /* We are getting the thread ID from the compute shader header */
1940 assert(stage
== MESA_SHADER_COMPUTE
);
1942 /* We can't directly send from g0, since sends with EOT have to use
1943 * g112-127. So, copy it to a virtual register, The register allocator will
1944 * make sure it uses the appropriate register range.
1946 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1947 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1948 bld
.exec_all().MOV(payload
, g0
);
1950 /* Send a message to the thread spawner to terminate the thread. */
1951 fs_inst
*inst
= bld
.exec_all()
1952 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1957 fs_visitor::emit_barrier()
1959 assert(devinfo
->gen
>= 7);
1961 /* We are getting the barrier ID from the compute shader header */
1962 assert(stage
== MESA_SHADER_COMPUTE
);
1964 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1966 /* Clear the message payload */
1967 fs_inst
*inst
= bld
.exec_all().MOV(payload
, fs_reg(0u));
1969 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1970 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1971 inst
= bld
.exec_all().AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1973 /* Emit a gateway "barrier" message using the payload we set up, followed
1974 * by a wait instruction.
1976 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1979 fs_visitor::fs_visitor(struct brw_context
*brw
,
1981 gl_shader_stage stage
,
1983 struct brw_stage_prog_data
*prog_data
,
1984 struct gl_shader_program
*shader_prog
,
1985 struct gl_program
*prog
,
1986 unsigned dispatch_width
,
1987 int shader_time_index
)
1988 : backend_shader(brw
, mem_ctx
, shader_prog
, prog
, prog_data
, stage
),
1989 key(key
), prog_data(prog_data
),
1990 dispatch_width(dispatch_width
),
1991 shader_time_index(shader_time_index
),
1992 promoted_constants(0),
1993 bld(fs_builder(this, dispatch_width
).at_end())
1996 case MESA_SHADER_FRAGMENT
:
1997 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1999 case MESA_SHADER_VERTEX
:
2000 case MESA_SHADER_GEOMETRY
:
2001 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
2003 case MESA_SHADER_COMPUTE
:
2004 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
2007 unreachable("unhandled shader stage");
2010 this->failed
= false;
2011 this->simd16_unsupported
= false;
2012 this->no16_msg
= NULL
;
2014 this->nir_locals
= NULL
;
2015 this->nir_globals
= NULL
;
2017 memset(&this->payload
, 0, sizeof(this->payload
));
2018 memset(this->outputs
, 0, sizeof(this->outputs
));
2019 memset(this->output_components
, 0, sizeof(this->output_components
));
2020 this->source_depth_to_render_target
= false;
2021 this->runtime_check_aads_emit
= false;
2022 this->first_non_payload_grf
= 0;
2023 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2025 this->virtual_grf_start
= NULL
;
2026 this->virtual_grf_end
= NULL
;
2027 this->live_intervals
= NULL
;
2028 this->regs_live_at_ip
= NULL
;
2031 this->last_scratch
= 0;
2032 this->pull_constant_loc
= NULL
;
2033 this->push_constant_loc
= NULL
;
2035 this->spilled_any_registers
= false;
2036 this->do_dual_src
= false;
2038 if (dispatch_width
== 8)
2039 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
2042 fs_visitor::~fs_visitor()