2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "util/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation();
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 assert(stage
== MESA_SHADER_FRAGMENT
);
81 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
82 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
83 this->outputs
[i
] = *reg
;
84 this->output_components
[i
] = 4;
86 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
87 this->frag_depth
= *reg
;
88 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
89 this->sample_mask
= *reg
;
91 /* gl_FragData or a user-defined FS output */
92 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
93 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
96 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
97 : ir
->type
->vector_elements
;
99 /* General color output. */
100 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
101 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
102 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
103 this->output_components
[output
] = vector_elements
;
106 } else if (ir
->data
.mode
== ir_var_uniform
) {
107 int param_index
= uniforms
;
109 /* Thanks to the lower_ubo_reference pass, we will see only
110 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
111 * variables, so no need for them to be in variable_ht.
113 * Some uniforms, such as samplers and atomic counters, have no actual
114 * storage, so we should ignore them.
116 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
119 if (dispatch_width
== 16) {
120 if (!variable_storage(ir
)) {
121 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
126 param_size
[param_index
] = type_size(ir
->type
);
127 if (!strncmp(ir
->name
, "gl_", 3)) {
128 setup_builtin_uniform_values(ir
);
130 setup_uniform_values(ir
);
133 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
134 reg
->type
= brw_type_for_base_type(ir
->type
);
136 } else if (ir
->data
.mode
== ir_var_system_value
) {
137 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
138 reg
= emit_samplepos_setup();
139 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
140 reg
= emit_sampleid_setup(ir
);
141 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
142 assert(brw
->gen
>= 7);
144 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
145 BRW_REGISTER_TYPE_D
));
150 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
152 hash_table_insert(this->variable_ht
, reg
, ir
);
156 fs_visitor::visit(ir_dereference_variable
*ir
)
158 fs_reg
*reg
= variable_storage(ir
->var
);
161 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
162 this->result
= fs_reg(reg_null_d
);
169 fs_visitor::visit(ir_dereference_record
*ir
)
171 const glsl_type
*struct_type
= ir
->record
->type
;
173 ir
->record
->accept(this);
175 unsigned int off
= 0;
176 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
177 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
179 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
181 this->result
= offset(this->result
, off
);
182 this->result
.type
= brw_type_for_base_type(ir
->type
);
186 fs_visitor::visit(ir_dereference_array
*ir
)
188 ir_constant
*constant_index
;
190 int element_size
= type_size(ir
->type
);
192 constant_index
= ir
->array_index
->as_constant();
194 ir
->array
->accept(this);
196 src
.type
= brw_type_for_base_type(ir
->type
);
198 if (constant_index
) {
199 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
200 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
202 /* Variable index array dereference. We attach the variable index
203 * component to the reg as a pointer to a register containing the
204 * offset. Currently only uniform arrays are supported in this patch,
205 * and that reladdr pointer is resolved by
206 * move_uniform_array_access_to_pull_constants(). All other array types
207 * are lowered by lower_variable_index_to_cond_assign().
209 ir
->array_index
->accept(this);
212 index_reg
= fs_reg(this, glsl_type::int_type
);
213 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
216 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
219 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
220 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
226 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
230 !x
.is_valid_3src() ||
231 !y
.is_valid_3src() ||
232 !a
.is_valid_3src()) {
233 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
234 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
235 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
236 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
238 emit(MUL(y_times_a
, y
, a
));
240 fs_reg negative_a
= a
;
241 negative_a
.negate
= !a
.negate
;
242 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
243 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
245 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
247 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
248 * we need to reorder the operands.
250 emit(LRP(dst
, a
, y
, x
));
255 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
256 const fs_reg
&src0
, const fs_reg
&src1
)
261 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
262 inst
->conditional_mod
= conditionalmod
;
264 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
266 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
267 inst
->predicate
= BRW_PREDICATE_NORMAL
;
272 fs_visitor::try_emit_saturate(ir_expression
*ir
)
274 if (ir
->operation
!= ir_unop_saturate
)
277 ir_rvalue
*sat_val
= ir
->operands
[0];
279 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
281 sat_val
->accept(this);
282 fs_reg src
= this->result
;
284 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
286 /* If the last instruction from our accept() generated our
287 * src, just set the saturate flag instead of emmitting a separate mov.
289 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
290 if (modify
&& modify
->regs_written
== modify
->dst
.width
/ 8 &&
291 modify
->can_do_saturate()) {
292 modify
->saturate
= true;
301 fs_visitor::try_emit_mad(ir_expression
*ir
)
303 /* 3-src instructions were introduced in gen6. */
307 /* MAD can only handle floating-point data. */
308 if (ir
->type
!= glsl_type::float_type
)
311 ir_rvalue
*nonmul
= ir
->operands
[1];
312 ir_expression
*mul
= ir
->operands
[0]->as_expression();
314 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
315 nonmul
= ir
->operands
[0];
316 mul
= ir
->operands
[1]->as_expression();
318 if (!mul
|| mul
->operation
!= ir_binop_mul
)
322 if (nonmul
->as_constant() ||
323 mul
->operands
[0]->as_constant() ||
324 mul
->operands
[1]->as_constant())
327 nonmul
->accept(this);
328 fs_reg src0
= this->result
;
330 mul
->operands
[0]->accept(this);
331 fs_reg src1
= this->result
;
333 mul
->operands
[1]->accept(this);
334 fs_reg src2
= this->result
;
336 this->result
= fs_reg(this, ir
->type
);
337 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
343 pack_pixel_offset(float x
)
345 /* Clamp upper end of the range to +7/16. See explanation in non-constant
346 * offset case below. */
347 int n
= MIN2((int)(x
* 16), 7);
352 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
354 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
355 * 8 channels at a time, same as the barycentric coords presented in
356 * the FS payload. this requires a bit of extra work to support.
358 no16("interpolate_at_* not yet supported in SIMD16 mode.");
360 assert(stage
== MESA_SHADER_FRAGMENT
);
361 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
363 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
364 ir_swizzle
* swiz
= NULL
;
366 /* the api does not allow a swizzle here, but the varying packing code
367 * may have pushed one into here.
369 swiz
= ir
->operands
[0]->as_swizzle();
371 deref
= swiz
->val
->as_dereference();
374 ir_variable
* var
= deref
->variable_referenced();
377 /* 1. collect interpolation factors */
379 fs_reg dst_x
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
380 fs_reg dst_y
= offset(dst_x
, 1);
382 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
383 * even when there is no payload. in the per-slot offset case, we'll replace this with
384 * the proper source data. */
385 fs_reg src
= fs_reg(this, glsl_type::float_type
);
386 int mlen
= 1; /* one reg unless overriden */
387 int reg_width
= dispatch_width
/ 8;
390 switch (ir
->operation
) {
391 case ir_unop_interpolate_at_centroid
:
392 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
395 case ir_binop_interpolate_at_sample
: {
396 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
397 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
399 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
400 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
404 case ir_binop_interpolate_at_offset
: {
405 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
407 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
408 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
409 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
412 /* pack the operands: hw wants offsets as 4 bit signed ints */
413 ir
->operands
[1]->accept(this);
414 src
= fs_reg(this, glsl_type::ivec2_type
);
416 for (int i
= 0; i
< 2; i
++) {
417 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
418 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
419 emit(MOV(src2
, temp
)); /* float to int */
421 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
422 * that we support a maximum offset of +0.5, which isn't representable
423 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
424 * which is the opposite of what the shader author wanted.
426 * This is legal due to ARB_gpu_shader5's quantization rules:
428 * "Not all values of <offset> may be supported; x and y offsets may
429 * be rounded to fixed-point values with the number of fraction bits
430 * given by the implementation-dependent constant
431 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
434 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
435 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
437 src2
= offset(src2
, 1);
438 this->result
= offset(this->result
, 1);
441 mlen
= 2 * reg_width
;
442 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
449 unreachable("not reached");
453 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
454 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
455 INTERP_QUALIFIER_NOPERSPECTIVE
;
457 /* 2. emit linterp */
459 fs_reg
res(this, ir
->type
);
462 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
463 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
464 emit(FS_OPCODE_LINTERP
, res
,
466 fs_reg(interp_reg(var
->data
.location
, ch
)));
467 res
= offset(res
, 1);
472 fs_visitor::visit(ir_expression
*ir
)
474 unsigned int operand
;
478 assert(ir
->get_num_operands() <= 3);
480 if (try_emit_saturate(ir
))
483 /* Deal with the real oddball stuff first */
484 switch (ir
->operation
) {
486 if (try_emit_mad(ir
))
490 case ir_unop_interpolate_at_centroid
:
491 case ir_binop_interpolate_at_offset
:
492 case ir_binop_interpolate_at_sample
:
493 emit_interpolate_expression(ir
);
500 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
501 ir
->operands
[operand
]->accept(this);
502 if (this->result
.file
== BAD_FILE
) {
503 fail("Failed to get tree for expression operand:\n");
504 ir
->operands
[operand
]->fprint(stderr
);
505 fprintf(stderr
, "\n");
507 assert(this->result
.is_valid_3src());
508 op
[operand
] = this->result
;
510 /* Matrix expression operands should have been broken down to vector
511 * operations already.
513 assert(!ir
->operands
[operand
]->type
->is_matrix());
514 /* And then those vector operands should have been broken down to scalar.
516 assert(!ir
->operands
[operand
]->type
->is_vector());
519 /* Storage for our result. If our result goes into an assignment, it will
520 * just get copy-propagated out, so no worries.
522 this->result
= fs_reg(this, ir
->type
);
524 switch (ir
->operation
) {
525 case ir_unop_logic_not
:
526 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
527 emit(NOT(this->result
, op
[0]));
529 emit(XOR(this->result
, op
[0], fs_reg(1)));
533 op
[0].negate
= !op
[0].negate
;
534 emit(MOV(this->result
, op
[0]));
538 op
[0].negate
= false;
539 emit(MOV(this->result
, op
[0]));
542 if (ir
->type
->is_float()) {
543 /* AND(val, 0x80000000) gives the sign bit.
545 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
548 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
550 op
[0].type
= BRW_REGISTER_TYPE_UD
;
551 this->result
.type
= BRW_REGISTER_TYPE_UD
;
552 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
554 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
555 inst
->predicate
= BRW_PREDICATE_NORMAL
;
557 this->result
.type
= BRW_REGISTER_TYPE_F
;
559 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
560 * -> non-negative val generates 0x00000000.
561 * Predicated OR sets 1 if val is positive.
563 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
565 emit(ASR(this->result
, op
[0], fs_reg(31)));
567 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
568 inst
->predicate
= BRW_PREDICATE_NORMAL
;
572 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
576 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
579 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
583 unreachable("not reached: should be handled by ir_explog_to_explog2");
585 case ir_unop_sin_reduced
:
586 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
589 case ir_unop_cos_reduced
:
590 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
594 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
596 case ir_unop_dFdx_coarse
:
597 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
599 case ir_unop_dFdx_fine
:
600 emit(FS_OPCODE_DDX
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
603 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_BY_HINT
));
605 case ir_unop_dFdy_coarse
:
606 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_COARSE
));
608 case ir_unop_dFdy_fine
:
609 emit(FS_OPCODE_DDY
, this->result
, op
[0], fs_reg(BRW_DERIVATIVE_FINE
));
613 emit(ADD(this->result
, op
[0], op
[1]));
616 unreachable("not reached: should be handled by ir_sub_to_add_neg");
619 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
620 /* For integer multiplication, the MUL uses the low 16 bits
621 * of one of the operands (src0 on gen6, src1 on gen7). The
622 * MACH accumulates in the contribution of the upper 16 bits
625 if (ir
->operands
[0]->is_uint16_constant()) {
627 emit(MUL(this->result
, op
[0], op
[1]));
629 emit(MUL(this->result
, op
[1], op
[0]));
630 } else if (ir
->operands
[1]->is_uint16_constant()) {
632 emit(MUL(this->result
, op
[1], op
[0]));
634 emit(MUL(this->result
, op
[0], op
[1]));
637 no16("SIMD16 explicit accumulator operands unsupported\n");
639 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
642 emit(MUL(acc
, op
[0], op
[1]));
643 emit(MACH(reg_null_d
, op
[0], op
[1]));
644 emit(MOV(this->result
, fs_reg(acc
)));
647 emit(MUL(this->result
, op
[0], op
[1]));
650 case ir_binop_imul_high
: {
652 no16("SIMD16 explicit accumulator operands unsupported\n");
654 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
657 fs_inst
*mul
= emit(MUL(acc
, op
[0], op
[1]));
658 emit(MACH(this->result
, op
[0], op
[1]));
660 /* Until Gen8, integer multiplies read 32-bits from one source, and
661 * 16-bits from the other, and relying on the MACH instruction to
662 * generate the high bits of the result.
664 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
665 * but in order to do a 64x64-bit multiply we have to simulate the
666 * previous behavior and then use a MACH instruction.
668 * FINISHME: Don't use source modifiers on src1.
671 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
672 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
673 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
674 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
676 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
683 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
684 assert(ir
->type
->is_integer());
685 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
687 case ir_binop_carry
: {
689 no16("SIMD16 explicit accumulator operands unsupported\n");
691 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
692 BRW_REGISTER_TYPE_UD
);
694 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
695 emit(MOV(this->result
, fs_reg(acc
)));
698 case ir_binop_borrow
: {
700 no16("SIMD16 explicit accumulator operands unsupported\n");
702 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
703 BRW_REGISTER_TYPE_UD
);
705 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
706 emit(MOV(this->result
, fs_reg(acc
)));
710 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
711 assert(ir
->type
->is_integer());
712 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
716 case ir_binop_greater
:
717 case ir_binop_lequal
:
718 case ir_binop_gequal
:
720 case ir_binop_all_equal
:
721 case ir_binop_nequal
:
722 case ir_binop_any_nequal
:
723 if (ctx
->Const
.UniformBooleanTrue
== 1) {
724 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
725 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
728 emit(CMP(this->result
, op
[0], op
[1],
729 brw_conditional_for_comparison(ir
->operation
)));
732 case ir_binop_logic_xor
:
733 emit(XOR(this->result
, op
[0], op
[1]));
736 case ir_binop_logic_or
:
737 emit(OR(this->result
, op
[0], op
[1]));
740 case ir_binop_logic_and
:
741 emit(AND(this->result
, op
[0], op
[1]));
746 unreachable("not reached: should be handled by brw_fs_channel_expressions");
749 unreachable("not reached: should be handled by lower_noise");
751 case ir_quadop_vector
:
752 unreachable("not reached: should be handled by lower_quadop_vector");
754 case ir_binop_vector_extract
:
755 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
757 case ir_triop_vector_insert
:
758 unreachable("not reached: should be handled by lower_vector_insert()");
761 unreachable("not reached: should be handled by ldexp_to_arith()");
764 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
768 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
771 case ir_unop_bitcast_i2f
:
772 case ir_unop_bitcast_u2f
:
773 op
[0].type
= BRW_REGISTER_TYPE_F
;
774 this->result
= op
[0];
777 case ir_unop_bitcast_f2u
:
778 op
[0].type
= BRW_REGISTER_TYPE_UD
;
779 this->result
= op
[0];
782 case ir_unop_bitcast_f2i
:
783 op
[0].type
= BRW_REGISTER_TYPE_D
;
784 this->result
= op
[0];
790 emit(MOV(this->result
, op
[0]));
794 emit(AND(this->result
, op
[0], fs_reg(1)));
797 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
798 op
[0].type
= BRW_REGISTER_TYPE_UD
;
799 this->result
.type
= BRW_REGISTER_TYPE_UD
;
800 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
801 this->result
.type
= BRW_REGISTER_TYPE_F
;
803 temp
= fs_reg(this, glsl_type::int_type
);
804 emit(AND(temp
, op
[0], fs_reg(1)));
805 emit(MOV(this->result
, temp
));
810 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
813 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
817 emit(RNDZ(this->result
, op
[0]));
820 op
[0].negate
= !op
[0].negate
;
821 emit(RNDD(this->result
, op
[0]));
822 this->result
.negate
= true;
825 emit(RNDD(this->result
, op
[0]));
828 emit(FRC(this->result
, op
[0]));
830 case ir_unop_round_even
:
831 emit(RNDE(this->result
, op
[0]));
836 resolve_ud_negate(&op
[0]);
837 resolve_ud_negate(&op
[1]);
838 emit_minmax(ir
->operation
== ir_binop_min
?
839 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
840 this->result
, op
[0], op
[1]);
842 case ir_unop_pack_snorm_2x16
:
843 case ir_unop_pack_snorm_4x8
:
844 case ir_unop_pack_unorm_2x16
:
845 case ir_unop_pack_unorm_4x8
:
846 case ir_unop_unpack_snorm_2x16
:
847 case ir_unop_unpack_snorm_4x8
:
848 case ir_unop_unpack_unorm_2x16
:
849 case ir_unop_unpack_unorm_4x8
:
850 case ir_unop_unpack_half_2x16
:
851 case ir_unop_pack_half_2x16
:
852 unreachable("not reached: should be handled by lower_packing_builtins");
853 case ir_unop_unpack_half_2x16_split_x
:
854 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
856 case ir_unop_unpack_half_2x16_split_y
:
857 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
860 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
863 case ir_unop_bitfield_reverse
:
864 emit(BFREV(this->result
, op
[0]));
866 case ir_unop_bit_count
:
867 emit(CBIT(this->result
, op
[0]));
869 case ir_unop_find_msb
:
870 temp
= fs_reg(this, glsl_type::uint_type
);
871 emit(FBH(temp
, op
[0]));
873 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
874 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
875 * subtract the result from 31 to convert the MSB count into an LSB count.
878 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
879 emit(MOV(this->result
, temp
));
880 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
883 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
884 inst
->predicate
= BRW_PREDICATE_NORMAL
;
886 case ir_unop_find_lsb
:
887 emit(FBL(this->result
, op
[0]));
889 case ir_unop_saturate
:
890 inst
= emit(MOV(this->result
, op
[0]));
891 inst
->saturate
= true;
893 case ir_triop_bitfield_extract
:
894 /* Note that the instruction's argument order is reversed from GLSL
897 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
900 emit(BFI1(this->result
, op
[0], op
[1]));
903 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
905 case ir_quadop_bitfield_insert
:
906 unreachable("not reached: should be handled by "
907 "lower_instructions::bitfield_insert_to_bfm_bfi");
909 case ir_unop_bit_not
:
910 emit(NOT(this->result
, op
[0]));
912 case ir_binop_bit_and
:
913 emit(AND(this->result
, op
[0], op
[1]));
915 case ir_binop_bit_xor
:
916 emit(XOR(this->result
, op
[0], op
[1]));
918 case ir_binop_bit_or
:
919 emit(OR(this->result
, op
[0], op
[1]));
922 case ir_binop_lshift
:
923 emit(SHL(this->result
, op
[0], op
[1]));
926 case ir_binop_rshift
:
927 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
928 emit(ASR(this->result
, op
[0], op
[1]));
930 emit(SHR(this->result
, op
[0], op
[1]));
932 case ir_binop_pack_half_2x16_split
:
933 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
935 case ir_binop_ubo_load
: {
936 /* This IR node takes a constant uniform block and a constant or
937 * variable byte offset within the block and loads a vector from that.
939 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
940 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
943 if (const_uniform_block
) {
944 /* The block index is a constant, so just emit the binding table entry
947 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
948 const_uniform_block
->value
.u
[0]);
950 /* The block index is not a constant. Evaluate the index expression
951 * per-channel and add the base UBO index; the generator will select
952 * a value from any live channel.
954 surf_index
= fs_reg(this, glsl_type::uint_type
);
955 emit(ADD(surf_index
, op
[0],
956 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
957 ->force_writemask_all
= true;
959 /* Assume this may touch any UBO. It would be nice to provide
960 * a tighter bound, but the array information is already lowered away.
962 brw_mark_surface_used(prog_data
,
963 stage_prog_data
->binding_table
.ubo_start
+
964 shader_prog
->NumUniformBlocks
- 1);
968 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
969 packed_consts
.type
= result
.type
;
971 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
972 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
973 packed_consts
, surf_index
, const_offset_reg
));
975 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
976 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
978 /* The std140 packing rules don't allow vectors to cross 16-byte
979 * boundaries, and a reg is 32 bytes.
981 assert(packed_consts
.subreg_offset
< 32);
983 /* UBO bools are any nonzero value. We consider bools to be
984 * values with the low bit set to 1. Convert them using CMP.
986 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
987 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
989 emit(MOV(result
, packed_consts
));
992 result
= offset(result
, 1);
995 /* Turn the byte offset into a dword offset. */
996 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
997 emit(SHR(base_offset
, op
[1], fs_reg(2)));
999 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1000 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
1003 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
1004 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
1006 result
= offset(result
, 1);
1010 result
.reg_offset
= 0;
1015 /* Note that the instruction's argument order is reversed from GLSL
1018 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
1022 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1026 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1027 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
1028 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1031 case ir_unop_interpolate_at_centroid
:
1032 case ir_binop_interpolate_at_offset
:
1033 case ir_binop_interpolate_at_sample
:
1034 unreachable("already handled above");
1040 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1041 const glsl_type
*type
, bool predicated
)
1043 switch (type
->base_type
) {
1044 case GLSL_TYPE_FLOAT
:
1045 case GLSL_TYPE_UINT
:
1047 case GLSL_TYPE_BOOL
:
1048 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1049 l
.type
= brw_type_for_base_type(type
);
1050 r
.type
= brw_type_for_base_type(type
);
1052 if (predicated
|| !l
.equals(r
)) {
1053 fs_inst
*inst
= emit(MOV(l
, r
));
1054 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1061 case GLSL_TYPE_ARRAY
:
1062 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1063 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1067 case GLSL_TYPE_STRUCT
:
1068 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1069 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1074 case GLSL_TYPE_SAMPLER
:
1075 case GLSL_TYPE_IMAGE
:
1076 case GLSL_TYPE_ATOMIC_UINT
:
1079 case GLSL_TYPE_VOID
:
1080 case GLSL_TYPE_ERROR
:
1081 case GLSL_TYPE_INTERFACE
:
1082 unreachable("not reached");
1086 /* If the RHS processing resulted in an instruction generating a
1087 * temporary value, and it would be easy to rewrite the instruction to
1088 * generate its result right into the LHS instead, do so. This ends
1089 * up reliably removing instructions where it can be tricky to do so
1090 * later without real UD chain information.
1093 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1096 fs_inst
*pre_rhs_inst
,
1097 fs_inst
*last_rhs_inst
)
1099 /* Only attempt if we're doing a direct assignment. */
1100 if (ir
->condition
||
1101 !(ir
->lhs
->type
->is_scalar() ||
1102 (ir
->lhs
->type
->is_vector() &&
1103 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1106 /* Make sure the last instruction generated our source reg. */
1107 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1113 /* If last_rhs_inst wrote a different number of components than our LHS,
1114 * we can't safely rewrite it.
1116 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
1119 /* Success! Rewrite the instruction. */
1126 fs_visitor::visit(ir_assignment
*ir
)
1131 /* FINISHME: arrays on the lhs */
1132 ir
->lhs
->accept(this);
1135 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1137 ir
->rhs
->accept(this);
1140 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1142 assert(l
.file
!= BAD_FILE
);
1143 assert(r
.file
!= BAD_FILE
);
1145 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1148 if (ir
->condition
) {
1149 emit_bool_to_cond_code(ir
->condition
);
1152 if (ir
->lhs
->type
->is_scalar() ||
1153 ir
->lhs
->type
->is_vector()) {
1154 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1155 if (ir
->write_mask
& (1 << i
)) {
1156 inst
= emit(MOV(l
, r
));
1158 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1164 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1169 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1170 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
,
1175 bool simd16
= false;
1181 if (shadow_c
.file
!= BAD_FILE
) {
1182 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1183 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1184 coordinate
= offset(coordinate
, 1);
1187 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1188 * the unused slots must be zeroed.
1190 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1191 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1195 if (ir
->op
== ir_tex
) {
1196 /* There's no plain shadow compare message, so we use shadow
1197 * compare with a bias of 0.0.
1199 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1201 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
1202 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1205 unreachable("Should not get here.");
1208 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1210 } else if (ir
->op
== ir_tex
) {
1211 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1212 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1213 coordinate
= offset(coordinate
, 1);
1215 /* zero the others. */
1216 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
1217 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1219 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1221 } else if (ir
->op
== ir_txd
) {
1224 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1225 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1226 coordinate
= offset(coordinate
, 1);
1228 /* the slots for u and v are always present, but r is optional */
1229 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
1232 * dPdx = dudx, dvdx, drdx
1233 * dPdy = dudy, dvdy, drdy
1235 * 1-arg: Does not exist.
1237 * 2-arg: dudx dvdx dudy dvdy
1238 * dPdx.x dPdx.y dPdy.x dPdy.y
1241 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1242 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1243 * m5 m6 m7 m8 m9 m10
1245 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1246 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1247 dPdx
= offset(dPdx
, 1);
1249 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
1251 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
1252 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1253 dPdy
= offset(dPdy
, 1);
1255 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
1256 } else if (ir
->op
== ir_txs
) {
1257 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1259 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1262 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1263 * instructions. We'll need to do SIMD16 here.
1266 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1268 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1269 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1271 coordinate
= offset(coordinate
, 1);
1274 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1275 * be necessary for TXF (ld), but seems wise to do for all messages.
1277 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1278 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1281 /* lod/bias appears after u/v/r. */
1284 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1287 /* The unused upper half. */
1292 /* Now, since we're doing simd16, the return is 2 interleaved
1293 * vec4s where the odd-indexed ones are junk. We'll need to move
1294 * this weirdness around to the expected layout.
1297 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1299 brw_type_for_base_type(ir
->type
) :
1300 BRW_REGISTER_TYPE_F
));
1306 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1307 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1308 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1309 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1310 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1311 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1313 unreachable("not reached");
1316 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1317 inst
->base_mrf
= base_mrf
;
1319 inst
->header_present
= true;
1320 inst
->regs_written
= simd16
? 8 : 4;
1323 for (int i
= 0; i
< 4; i
++) {
1324 emit(MOV(orig_dst
, dst
));
1325 orig_dst
= offset(orig_dst
, 1);
1326 dst
= offset(dst
, 2);
1333 /* gen5's sampler has slots for u, v, r, array index, then optional
1334 * parameters like shadow comparitor or LOD bias. If optional
1335 * parameters aren't present, those base slots are optional and don't
1336 * need to be included in the message.
1338 * We don't fill in the unnecessary slots regardless, which may look
1339 * surprising in the disassembly.
1342 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1343 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1344 fs_reg sample_index
, uint32_t sampler
)
1346 int reg_width
= dispatch_width
/ 8;
1347 bool header_present
= false;
1348 const int vector_elements
=
1349 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1351 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1352 fs_reg msg_coords
= message
;
1355 /* The offsets set up by the ir_texture visitor are in the
1356 * m1 header, so we can't go headerless.
1358 header_present
= true;
1362 for (int i
= 0; i
< vector_elements
; i
++) {
1363 emit(MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
));
1364 coordinate
= offset(coordinate
, 1);
1366 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
1367 fs_reg msg_lod
= offset(msg_coords
, 4);
1369 if (shadow_c
.file
!= BAD_FILE
) {
1370 fs_reg msg_shadow
= msg_lod
;
1371 emit(MOV(msg_shadow
, shadow_c
));
1372 msg_lod
= offset(msg_shadow
, 1);
1379 opcode
= SHADER_OPCODE_TEX
;
1382 emit(MOV(msg_lod
, lod
));
1383 msg_end
= offset(msg_lod
, 1);
1385 opcode
= FS_OPCODE_TXB
;
1388 emit(MOV(msg_lod
, lod
));
1389 msg_end
= offset(msg_lod
, 1);
1391 opcode
= SHADER_OPCODE_TXL
;
1396 * dPdx = dudx, dvdx, drdx
1397 * dPdy = dudy, dvdy, drdy
1399 * Load up these values:
1400 * - dudx dudy dvdx dvdy drdx drdy
1401 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1404 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1405 emit(MOV(msg_end
, lod
));
1406 lod
= offset(lod
, 1);
1407 msg_end
= offset(msg_end
, 1);
1409 emit(MOV(msg_end
, lod2
));
1410 lod2
= offset(lod2
, 1);
1411 msg_end
= offset(msg_end
, 1);
1414 opcode
= SHADER_OPCODE_TXD
;
1418 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
1419 emit(MOV(msg_lod
, lod
));
1420 msg_end
= offset(msg_lod
, 1);
1422 opcode
= SHADER_OPCODE_TXS
;
1424 case ir_query_levels
:
1426 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1427 msg_end
= offset(msg_lod
, 1);
1429 opcode
= SHADER_OPCODE_TXS
;
1432 msg_lod
= offset(msg_coords
, 3);
1433 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
));
1434 msg_end
= offset(msg_lod
, 1);
1436 opcode
= SHADER_OPCODE_TXF
;
1439 msg_lod
= offset(msg_coords
, 3);
1441 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1443 emit(MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
));
1444 msg_end
= offset(msg_lod
, 2);
1446 opcode
= SHADER_OPCODE_TXF_CMS
;
1449 opcode
= SHADER_OPCODE_LOD
;
1452 opcode
= SHADER_OPCODE_TG4
;
1455 unreachable("not reached");
1458 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1459 inst
->base_mrf
= message
.reg
;
1460 inst
->mlen
= msg_end
.reg
- message
.reg
;
1461 inst
->header_present
= header_present
;
1462 inst
->regs_written
= 4 * reg_width
;
1464 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1465 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1466 " disallowed by hardware\n");
1473 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1475 if (brw
->gen
< 8 && !brw
->is_haswell
)
1478 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1482 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1483 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1484 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
1485 fs_reg offset_value
)
1487 int reg_width
= dispatch_width
/ 8;
1488 bool header_present
= false;
1490 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1491 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1492 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1496 if (ir
->op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
1497 is_high_sampler(brw
, sampler
)) {
1498 /* For general texture offsets (no txf workaround), we need a header to
1499 * put them in. Note that for SIMD16 we're making space for two actual
1500 * hardware registers here, so the emit will have to fix up for this.
1502 * * ir4_tg4 needs to place its channel select in the header,
1503 * for interaction with ARB_texture_swizzle
1505 * The sampler index is only 4-bits, so for larger sampler numbers we
1506 * need to offset the Sampler State Pointer in the header.
1508 header_present
= true;
1509 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
1513 if (shadow_c
.file
!= BAD_FILE
) {
1514 emit(MOV(sources
[length
], shadow_c
));
1518 bool has_nonconstant_offset
=
1519 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
1520 bool coordinate_done
= false;
1522 /* Set up the LOD info */
1528 emit(MOV(sources
[length
], lod
));
1532 emit(MOV(sources
[length
], lod
));
1536 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1538 /* Load dPdx and the coordinate together:
1539 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1541 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1542 emit(MOV(sources
[length
], coordinate
));
1543 coordinate
= offset(coordinate
, 1);
1546 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1547 * only derivatives for (u, v, r).
1549 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1550 emit(MOV(sources
[length
], lod
));
1551 lod
= offset(lod
, 1);
1554 emit(MOV(sources
[length
], lod2
));
1555 lod2
= offset(lod2
, 1);
1560 coordinate_done
= true;
1564 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1567 case ir_query_levels
:
1568 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1572 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1573 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1574 coordinate
= offset(coordinate
, 1);
1577 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1580 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1581 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1582 coordinate
= offset(coordinate
, 1);
1586 coordinate_done
= true;
1589 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1592 /* data from the multisample control surface */
1593 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1596 /* there is no offsetting for this message; just copy in the integer
1597 * texture coordinates
1599 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1600 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1601 coordinate
= offset(coordinate
, 1);
1605 coordinate_done
= true;
1608 if (has_nonconstant_offset
) {
1609 if (shadow_c
.file
!= BAD_FILE
)
1610 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1612 /* More crazy intermixing */
1613 for (int i
= 0; i
< 2; i
++) { /* u, v */
1614 emit(MOV(sources
[length
], coordinate
));
1615 coordinate
= offset(coordinate
, 1);
1619 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1620 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1621 offset_value
= offset(offset_value
, 1);
1625 if (ir
->coordinate
->type
->vector_elements
== 3) { /* r if present */
1626 emit(MOV(sources
[length
], coordinate
));
1627 coordinate
= offset(coordinate
, 1);
1631 coordinate_done
= true;
1636 /* Set up the coordinate (except for cases where it was done above) */
1637 if (ir
->coordinate
&& !coordinate_done
) {
1638 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1639 emit(MOV(sources
[length
], coordinate
));
1640 coordinate
= offset(coordinate
, 1);
1647 mlen
= length
* reg_width
- header_present
;
1649 mlen
= length
* reg_width
;
1651 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
1652 BRW_REGISTER_TYPE_F
);
1653 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1655 /* Generate the SEND */
1658 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1659 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1660 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1661 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1662 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1663 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1664 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1665 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1666 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1668 if (has_nonconstant_offset
)
1669 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1671 opcode
= SHADER_OPCODE_TG4
;
1674 unreachable("not reached");
1676 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1677 inst
->base_mrf
= -1;
1679 inst
->header_present
= header_present
;
1680 inst
->regs_written
= 4 * reg_width
;
1682 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1683 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1684 " disallowed by hardware\n");
1691 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1692 bool is_rect
, uint32_t sampler
, int texunit
)
1694 fs_inst
*inst
= NULL
;
1695 bool needs_gl_clamp
= true;
1696 fs_reg scale_x
, scale_y
;
1697 const struct brw_sampler_prog_key_data
*tex
=
1698 (stage
== MESA_SHADER_FRAGMENT
) ?
1699 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1702 /* The 965 requires the EU to do the normalization of GL rectangle
1703 * texture coordinates. We use the program parameter state
1704 * tracking to get the scaling factor.
1708 (brw
->gen
>= 6 && (tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
1709 tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
1710 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1711 int tokens
[STATE_LENGTH
] = {
1713 STATE_TEXRECT_SCALE
,
1719 no16("rectangle scale uniform setup not supported on SIMD16\n");
1720 if (dispatch_width
== 16) {
1724 GLuint index
= _mesa_add_state_reference(params
,
1725 (gl_state_index
*)tokens
);
1726 /* Try to find existing copies of the texrect scale uniforms. */
1727 for (unsigned i
= 0; i
< uniforms
; i
++) {
1728 if (stage_prog_data
->param
[i
] ==
1729 &prog
->Parameters
->ParameterValues
[index
][0]) {
1730 scale_x
= fs_reg(UNIFORM
, i
);
1731 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1736 /* If we didn't already set them up, do so now. */
1737 if (scale_x
.file
== BAD_FILE
) {
1738 scale_x
= fs_reg(UNIFORM
, uniforms
);
1739 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1741 stage_prog_data
->param
[uniforms
++] =
1742 &prog
->Parameters
->ParameterValues
[index
][0];
1743 stage_prog_data
->param
[uniforms
++] =
1744 &prog
->Parameters
->ParameterValues
[index
][1];
1748 /* The 965 requires the EU to do the normalization of GL rectangle
1749 * texture coordinates. We use the program parameter state
1750 * tracking to get the scaling factor.
1752 if (brw
->gen
< 6 && is_rect
) {
1753 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1754 fs_reg src
= coordinate
;
1757 emit(MUL(dst
, src
, scale_x
));
1758 dst
= offset(dst
, 1);
1759 src
= offset(src
, 1);
1760 emit(MUL(dst
, src
, scale_y
));
1761 } else if (is_rect
) {
1762 /* On gen6+, the sampler handles the rectangle coordinates
1763 * natively, without needing rescaling. But that means we have
1764 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1765 * not [0, 1] like the default case below.
1767 needs_gl_clamp
= false;
1769 for (int i
= 0; i
< 2; i
++) {
1770 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1771 fs_reg chan
= coordinate
;
1772 chan
= offset(chan
, i
);
1774 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1775 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1777 /* Our parameter comes in as 1.0/width or 1.0/height,
1778 * because that's what people normally want for doing
1779 * texture rectangle handling. We need width or height
1780 * for clamping, but we don't care enough to make a new
1781 * parameter type, so just invert back.
1783 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1784 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1785 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1787 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1788 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1793 if (ir
->coordinate
&& needs_gl_clamp
) {
1794 for (unsigned int i
= 0;
1795 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1796 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1797 fs_reg chan
= coordinate
;
1798 chan
= offset(chan
, i
);
1800 fs_inst
*inst
= emit(MOV(chan
, chan
));
1801 inst
->saturate
= true;
1808 /* Sample from the MCS surface attached to this multisample texture. */
1810 fs_visitor::emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, fs_reg sampler
)
1812 int reg_width
= dispatch_width
/ 8;
1813 int length
= ir
->coordinate
->type
->vector_elements
;
1814 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(length
* reg_width
),
1815 BRW_REGISTER_TYPE_F
);
1816 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1817 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, length
);
1819 /* parameters are: u, v, r; missing parameters are treated as zero */
1820 for (int i
= 0; i
< length
; i
++) {
1821 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1822 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1823 coordinate
= offset(coordinate
, 1);
1826 emit(LOAD_PAYLOAD(payload
, sources
, length
));
1828 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
1829 inst
->base_mrf
= -1;
1830 inst
->mlen
= length
* reg_width
;
1831 inst
->header_present
= false;
1832 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
1833 * response, but the sampler always
1841 fs_visitor::visit(ir_texture
*ir
)
1843 const struct brw_sampler_prog_key_data
*tex
=
1844 (stage
== MESA_SHADER_FRAGMENT
) ?
1845 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1847 fs_inst
*inst
= NULL
;
1850 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1852 ir_rvalue
*nonconst_sampler_index
=
1853 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
1855 /* Handle non-constant sampler array indexing */
1857 if (nonconst_sampler_index
) {
1858 /* The highest sampler which may be used by this operation is
1859 * the last element of the array. Mark it here, because the generator
1860 * doesn't have enough information to determine the bound.
1862 uint32_t array_size
= ir
->sampler
->as_dereference_array()
1863 ->array
->type
->array_size();
1865 uint32_t max_used
= sampler
+ array_size
- 1;
1866 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
1867 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1869 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1872 brw_mark_surface_used(prog_data
, max_used
);
1874 /* Emit code to evaluate the actual indexing expression */
1875 nonconst_sampler_index
->accept(this);
1876 fs_reg
temp(this, glsl_type::uint_type
);
1877 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
1878 ->force_writemask_all
= true;
1881 /* Single sampler, or constant array index; the indexing expression
1882 * is just an immediate.
1884 sampler_reg
= fs_reg(sampler
);
1887 /* FINISHME: We're failing to recompile our programs when the sampler is
1888 * updated. This only matters for the texture rectangle scale parameters
1889 * (pre-gen6, or gen6+ with GL_CLAMP).
1891 int texunit
= prog
->SamplerUnits
[sampler
];
1893 if (ir
->op
== ir_tg4
) {
1894 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1895 * emitting anything other than setting up the constant result.
1897 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1898 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], chan
->value
.i
[0]);
1899 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1901 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1904 for (int i
=0; i
<4; i
++) {
1905 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1906 res
= offset(res
, 1);
1912 /* Should be lowered by do_lower_texture_projection */
1913 assert(!ir
->projector
);
1915 /* Should be lowered */
1916 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
1918 /* Generate code to compute all the subexpression trees. This has to be
1919 * done before loading any values into MRFs for the sampler message since
1920 * generating these values may involve SEND messages that need the MRFs.
1923 if (ir
->coordinate
) {
1924 ir
->coordinate
->accept(this);
1926 coordinate
= rescale_texcoord(ir
, this->result
,
1927 ir
->sampler
->type
->sampler_dimensionality
==
1928 GLSL_SAMPLER_DIM_RECT
,
1932 fs_reg shadow_comparitor
;
1933 if (ir
->shadow_comparitor
) {
1934 ir
->shadow_comparitor
->accept(this);
1935 shadow_comparitor
= this->result
;
1938 fs_reg offset_value
;
1940 ir_constant
*const_offset
= ir
->offset
->as_constant();
1942 /* Store the header bitfield in an IMM register. This allows us to
1943 * use offset_value.file to distinguish between no offset, a constant
1944 * offset, and a non-constant offset.
1946 offset_value
= fs_reg(brw_texture_offset(ctx
, const_offset
));
1948 ir
->offset
->accept(this);
1949 offset_value
= this->result
;
1953 fs_reg lod
, lod2
, sample_index
, mcs
;
1958 case ir_query_levels
:
1961 ir
->lod_info
.bias
->accept(this);
1965 ir
->lod_info
.grad
.dPdx
->accept(this);
1968 ir
->lod_info
.grad
.dPdy
->accept(this);
1969 lod2
= this->result
;
1974 ir
->lod_info
.lod
->accept(this);
1978 ir
->lod_info
.sample_index
->accept(this);
1979 sample_index
= this->result
;
1981 if (brw
->gen
>= 7 && tex
->compressed_multisample_layout_mask
& (1<<sampler
))
1982 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
1987 unreachable("Unrecognized texture opcode");
1990 /* Writemasking doesn't eliminate channels on SIMD8 texture
1991 * samples, so don't worry about them.
1993 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1995 if (brw
->gen
>= 7) {
1996 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1997 lod
, lod2
, sample_index
, mcs
, sampler_reg
,
1999 } else if (brw
->gen
>= 5) {
2000 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
2001 lod
, lod2
, sample_index
, sampler
);
2003 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
2004 lod
, lod2
, sampler
);
2007 if (offset_value
.file
== IMM
)
2008 inst
->texture_offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
2010 if (ir
->op
== ir_tg4
)
2011 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
2013 if (ir
->shadow_comparitor
)
2014 inst
->shadow_compare
= true;
2016 /* fixup #layers for cube map arrays */
2017 if (ir
->op
== ir_txs
) {
2018 glsl_type
const *type
= ir
->sampler
->type
;
2019 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2020 type
->sampler_array
) {
2021 fs_reg depth
= offset(dst
, 2);
2022 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
2023 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
2025 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
2026 int components
= inst
->regs_written
/ (dst
.width
/ 8);
2027 for (int i
= 0; i
< components
; i
++) {
2029 fixed_payload
[i
] = fixed_depth
;
2031 fixed_payload
[i
] = offset(dst
, i
);
2034 emit(LOAD_PAYLOAD(dst
, fixed_payload
, components
));
2038 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2039 emit_gen6_gather_wa(tex
->gen6_gather_wa
[sampler
], dst
);
2042 swizzle_result(ir
, dst
, sampler
);
2046 * Apply workarounds for Gen6 gather with UINT/SINT
2049 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2054 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2056 for (int i
= 0; i
< 4; i
++) {
2057 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2058 /* Convert from UNORM to UINT */
2059 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2060 emit(MOV(dst
, dst_f
));
2063 /* Reinterpret the UINT value as a signed INT value by
2064 * shifting the sign bit into place, then shifting back
2067 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2068 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2071 dst
= offset(dst
, 1);
2076 * Set up the gather channel based on the swizzle, for gather4.
2079 fs_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2081 const struct brw_sampler_prog_key_data
*tex
=
2082 (stage
== MESA_SHADER_FRAGMENT
) ?
2083 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2085 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2086 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], chan
->value
.i
[0]);
2088 case SWIZZLE_X
: return 0;
2090 /* gather4 sampler is broken for green channel on RG32F --
2091 * we must ask for blue instead.
2093 if (tex
->gather_channel_quirk_mask
& (1<<sampler
))
2096 case SWIZZLE_Z
: return 2;
2097 case SWIZZLE_W
: return 3;
2099 unreachable("Not reached"); /* zero, one swizzles handled already */
2104 * Swizzle the result of a texture result. This is necessary for
2105 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2108 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, uint32_t sampler
)
2110 if (ir
->op
== ir_query_levels
) {
2111 /* # levels is in .w */
2112 this->result
= offset(orig_val
, 3);
2116 this->result
= orig_val
;
2118 /* txs,lod don't actually sample the texture, so swizzling the result
2121 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
2124 const struct brw_sampler_prog_key_data
*tex
=
2125 (stage
== MESA_SHADER_FRAGMENT
) ?
2126 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2129 if (ir
->type
== glsl_type::float_type
) {
2130 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2131 assert(ir
->sampler
->type
->sampler_shadow
);
2132 } else if (tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2133 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
2135 for (int i
= 0; i
< 4; i
++) {
2136 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], i
);
2137 fs_reg l
= swizzled_result
;
2140 if (swiz
== SWIZZLE_ZERO
) {
2141 emit(MOV(l
, fs_reg(0.0f
)));
2142 } else if (swiz
== SWIZZLE_ONE
) {
2143 emit(MOV(l
, fs_reg(1.0f
)));
2145 emit(MOV(l
, offset(orig_val
,
2146 GET_SWZ(tex
->swizzles
[sampler
], i
))));
2149 this->result
= swizzled_result
;
2154 fs_visitor::visit(ir_swizzle
*ir
)
2156 ir
->val
->accept(this);
2157 fs_reg val
= this->result
;
2159 if (ir
->type
->vector_elements
== 1) {
2160 this->result
= offset(this->result
, ir
->mask
.x
);
2164 fs_reg result
= fs_reg(this, ir
->type
);
2165 this->result
= result
;
2167 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2168 fs_reg channel
= val
;
2186 emit(MOV(result
, offset(channel
, swiz
)));
2187 result
= offset(result
, 1);
2192 fs_visitor::visit(ir_discard
*ir
)
2194 assert(ir
->condition
== NULL
); /* FINISHME */
2196 /* We track our discarded pixels in f0.1. By predicating on it, we can
2197 * update just the flag bits that aren't yet discarded. By emitting a
2198 * CMP of g0 != g0, all our currently executing channels will get turned
2201 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2202 BRW_REGISTER_TYPE_UW
));
2203 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2204 BRW_CONDITIONAL_NZ
));
2205 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2206 cmp
->flag_subreg
= 1;
2208 if (brw
->gen
>= 6) {
2209 /* For performance, after a discard, jump to the end of the shader.
2210 * Only jump if all relevant channels have been discarded.
2212 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2213 discard_jump
->flag_subreg
= 1;
2215 discard_jump
->predicate
= (dispatch_width
== 8)
2216 ? BRW_PREDICATE_ALIGN1_ANY8H
2217 : BRW_PREDICATE_ALIGN1_ANY16H
;
2218 discard_jump
->predicate_inverse
= true;
2223 fs_visitor::visit(ir_constant
*ir
)
2225 /* Set this->result to reg at the bottom of the function because some code
2226 * paths will cause this visitor to be applied to other fields. This will
2227 * cause the value stored in this->result to be modified.
2229 * Make reg constant so that it doesn't get accidentally modified along the
2230 * way. Yes, I actually had this problem. :(
2232 const fs_reg
reg(this, ir
->type
);
2233 fs_reg dst_reg
= reg
;
2235 if (ir
->type
->is_array()) {
2236 const unsigned size
= type_size(ir
->type
->fields
.array
);
2238 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2239 ir
->array_elements
[i
]->accept(this);
2240 fs_reg src_reg
= this->result
;
2242 dst_reg
.type
= src_reg
.type
;
2243 for (unsigned j
= 0; j
< size
; j
++) {
2244 emit(MOV(dst_reg
, src_reg
));
2245 src_reg
= offset(src_reg
, 1);
2246 dst_reg
= offset(dst_reg
, 1);
2249 } else if (ir
->type
->is_record()) {
2250 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2251 const unsigned size
= type_size(field
->type
);
2253 field
->accept(this);
2254 fs_reg src_reg
= this->result
;
2256 dst_reg
.type
= src_reg
.type
;
2257 for (unsigned j
= 0; j
< size
; j
++) {
2258 emit(MOV(dst_reg
, src_reg
));
2259 src_reg
= offset(src_reg
, 1);
2260 dst_reg
= offset(dst_reg
, 1);
2264 const unsigned size
= type_size(ir
->type
);
2266 for (unsigned i
= 0; i
< size
; i
++) {
2267 switch (ir
->type
->base_type
) {
2268 case GLSL_TYPE_FLOAT
:
2269 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2271 case GLSL_TYPE_UINT
:
2272 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2275 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2277 case GLSL_TYPE_BOOL
:
2279 fs_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2283 unreachable("Non-float/uint/int/bool constant");
2285 dst_reg
= offset(dst_reg
, 1);
2293 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2295 ir_expression
*expr
= ir
->as_expression();
2297 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2300 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2301 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2308 assert(expr
->get_num_operands() <= 3);
2309 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2310 assert(expr
->operands
[i
]->type
->is_scalar());
2312 expr
->operands
[i
]->accept(this);
2313 op
[i
] = this->result
;
2315 resolve_ud_negate(&op
[i
]);
2318 switch (expr
->operation
) {
2319 case ir_unop_logic_not
:
2320 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2321 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2324 case ir_binop_logic_xor
:
2325 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2326 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2327 emit(XOR(dst
, op
[0], op
[1]));
2328 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2329 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2331 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2332 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2336 case ir_binop_logic_or
:
2337 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2338 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2339 emit(OR(dst
, op
[0], op
[1]));
2340 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2341 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2343 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2344 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2348 case ir_binop_logic_and
:
2349 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2350 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2351 emit(AND(dst
, op
[0], op
[1]));
2352 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1)));
2353 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2355 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2356 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2361 if (brw
->gen
>= 6) {
2362 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2364 inst
= emit(MOV(reg_null_f
, op
[0]));
2365 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2370 if (brw
->gen
>= 6) {
2371 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2373 inst
= emit(MOV(reg_null_d
, op
[0]));
2374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2378 case ir_binop_greater
:
2379 case ir_binop_gequal
:
2381 case ir_binop_lequal
:
2382 case ir_binop_equal
:
2383 case ir_binop_all_equal
:
2384 case ir_binop_nequal
:
2385 case ir_binop_any_nequal
:
2386 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2387 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2388 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2391 emit(CMP(reg_null_d
, op
[0], op
[1],
2392 brw_conditional_for_comparison(expr
->operation
)));
2395 case ir_triop_csel
: {
2396 /* Expand the boolean condition into the flag register. */
2397 inst
= emit(MOV(reg_null_d
, op
[0]));
2398 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2400 /* Select which boolean to return. */
2401 fs_reg
temp(this, expr
->operands
[1]->type
);
2402 inst
= emit(SEL(temp
, op
[1], op
[2]));
2403 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2405 /* Expand the result to a condition code. */
2406 inst
= emit(MOV(reg_null_d
, temp
));
2407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2412 unreachable("not reached");
2417 * Emit a gen6 IF statement with the comparison folded into the IF
2421 fs_visitor::emit_if_gen6(ir_if
*ir
)
2423 ir_expression
*expr
= ir
->condition
->as_expression();
2425 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2430 assert(expr
->get_num_operands() <= 3);
2431 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2432 assert(expr
->operands
[i
]->type
->is_scalar());
2434 expr
->operands
[i
]->accept(this);
2435 op
[i
] = this->result
;
2438 switch (expr
->operation
) {
2439 case ir_unop_logic_not
:
2440 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2443 case ir_binop_logic_xor
:
2444 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2447 case ir_binop_logic_or
:
2448 temp
= fs_reg(this, glsl_type::bool_type
);
2449 emit(OR(temp
, op
[0], op
[1]));
2450 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2453 case ir_binop_logic_and
:
2454 temp
= fs_reg(this, glsl_type::bool_type
);
2455 emit(AND(temp
, op
[0], op
[1]));
2456 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2460 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2461 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2465 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2468 case ir_binop_greater
:
2469 case ir_binop_gequal
:
2471 case ir_binop_lequal
:
2472 case ir_binop_equal
:
2473 case ir_binop_all_equal
:
2474 case ir_binop_nequal
:
2475 case ir_binop_any_nequal
:
2476 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2477 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2478 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2481 emit(IF(op
[0], op
[1],
2482 brw_conditional_for_comparison(expr
->operation
)));
2485 case ir_triop_csel
: {
2486 /* Expand the boolean condition into the flag register. */
2487 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2488 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2490 /* Select which boolean to use as the result. */
2491 fs_reg
temp(this, expr
->operands
[1]->type
);
2492 inst
= emit(SEL(temp
, op
[1], op
[2]));
2493 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2495 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2500 unreachable("not reached");
2504 ir
->condition
->accept(this);
2505 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2509 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2511 * Many GLSL shaders contain the following pattern:
2513 * x = condition ? foo : bar
2515 * The compiler emits an ir_if tree for this, since each subexpression might be
2516 * a complex tree that could have side-effects or short-circuit logic.
2518 * However, the common case is to simply select one of two constants or
2519 * variable values---which is exactly what SEL is for. In this case, the
2520 * assembly looks like:
2528 * which can be easily translated into:
2530 * (+f0) SEL dst src0 src1
2532 * If src0 is an immediate value, we promote it to a temporary GRF.
2535 fs_visitor::try_replace_with_sel()
2537 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2538 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2540 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2542 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2545 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2546 for (int i
= 0; i
< 4; i
++) {
2547 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2549 match
= (fs_inst
*) match
->prev
;
2552 /* The opcodes match; it looks like the right sequence of instructions. */
2553 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2554 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2555 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2557 /* Check that the MOVs are the right form. */
2558 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2559 !then_mov
->is_partial_write() &&
2560 !else_mov
->is_partial_write()) {
2562 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2563 while (!if_inst
->next
->is_tail_sentinel())
2564 if_inst
->next
->exec_node::remove();
2565 if_inst
->exec_node::remove();
2567 /* Only the last source register can be a constant, so if the MOV in
2568 * the "then" clause uses a constant, we need to put it in a temporary.
2570 fs_reg
src0(then_mov
->src
[0]);
2571 if (src0
.file
== IMM
) {
2572 src0
= fs_reg(this, glsl_type::float_type
);
2573 src0
.type
= then_mov
->src
[0].type
;
2574 emit(MOV(src0
, then_mov
->src
[0]));
2578 if (if_inst
->conditional_mod
) {
2579 /* Sandybridge-specific IF with embedded comparison */
2580 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2581 if_inst
->conditional_mod
));
2582 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2583 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2585 /* Separate CMP and IF instructions */
2586 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2587 sel
->predicate
= if_inst
->predicate
;
2588 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2594 fs_visitor::visit(ir_if
*ir
)
2597 no16("Can't support (non-uniform) control flow on SIMD16\n");
2600 /* Don't point the annotation at the if statement, because then it plus
2601 * the then and else blocks get printed.
2603 this->base_ir
= ir
->condition
;
2605 if (brw
->gen
== 6) {
2608 emit_bool_to_cond_code(ir
->condition
);
2610 emit(IF(BRW_PREDICATE_NORMAL
));
2613 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2614 this->base_ir
= ir_
;
2618 if (!ir
->else_instructions
.is_empty()) {
2619 emit(BRW_OPCODE_ELSE
);
2621 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2622 this->base_ir
= ir_
;
2627 emit(BRW_OPCODE_ENDIF
);
2629 try_replace_with_sel();
2633 fs_visitor::visit(ir_loop
*ir
)
2636 no16("Can't support (non-uniform) control flow on SIMD16\n");
2639 this->base_ir
= NULL
;
2640 emit(BRW_OPCODE_DO
);
2642 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2643 this->base_ir
= ir_
;
2647 this->base_ir
= NULL
;
2648 emit(BRW_OPCODE_WHILE
);
2652 fs_visitor::visit(ir_loop_jump
*ir
)
2655 case ir_loop_jump::jump_break
:
2656 emit(BRW_OPCODE_BREAK
);
2658 case ir_loop_jump::jump_continue
:
2659 emit(BRW_OPCODE_CONTINUE
);
2665 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2667 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2668 ir
->actual_parameters
.get_head());
2669 ir_variable
*location
= deref
->variable_referenced();
2670 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2671 location
->data
.binding
);
2673 /* Calculate the surface offset */
2674 fs_reg
offset(this, glsl_type::uint_type
);
2675 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2678 deref_array
->array_index
->accept(this);
2680 fs_reg
tmp(this, glsl_type::uint_type
);
2681 emit(MUL(tmp
, this->result
, fs_reg(ATOMIC_COUNTER_SIZE
)));
2682 emit(ADD(offset
, tmp
, fs_reg(location
->data
.atomic
.offset
)));
2684 offset
= fs_reg(location
->data
.atomic
.offset
);
2687 /* Emit the appropriate machine instruction */
2688 const char *callee
= ir
->callee
->function_name();
2689 ir
->return_deref
->accept(this);
2690 fs_reg dst
= this->result
;
2692 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2693 emit_untyped_surface_read(surf_index
, dst
, offset
);
2695 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2696 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2697 fs_reg(), fs_reg());
2699 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2700 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2701 fs_reg(), fs_reg());
2706 fs_visitor::visit(ir_call
*ir
)
2708 const char *callee
= ir
->callee
->function_name();
2710 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2711 !strcmp("__intrinsic_atomic_increment", callee
) ||
2712 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2713 visit_atomic_counter_intrinsic(ir
);
2715 unreachable("Unsupported intrinsic.");
2720 fs_visitor::visit(ir_return
*)
2722 unreachable("FINISHME");
2726 fs_visitor::visit(ir_function
*ir
)
2728 /* Ignore function bodies other than main() -- we shouldn't see calls to
2729 * them since they should all be inlined before we get to ir_to_mesa.
2731 if (strcmp(ir
->name
, "main") == 0) {
2732 const ir_function_signature
*sig
;
2735 sig
= ir
->matching_signature(NULL
, &empty
, false);
2739 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2740 this->base_ir
= ir_
;
2747 fs_visitor::visit(ir_function_signature
*)
2749 unreachable("not reached");
2753 fs_visitor::visit(ir_emit_vertex
*)
2755 unreachable("not reached");
2759 fs_visitor::visit(ir_end_primitive
*)
2761 unreachable("not reached");
2765 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2766 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2770 (stage
== MESA_SHADER_FRAGMENT
) &&
2771 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2772 int reg_width
= dispatch_width
/ 8;
2775 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
2777 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2778 /* Initialize the sample mask in the message header. */
2779 emit(MOV(sources
[0], fs_reg(0u)))
2780 ->force_writemask_all
= true;
2783 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2784 ->force_writemask_all
= true;
2786 emit(MOV(component(sources
[0], 7),
2787 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2788 ->force_writemask_all
= true;
2792 /* Set the atomic operation offset. */
2793 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2794 emit(MOV(sources
[1], offset
));
2797 /* Set the atomic operation arguments. */
2798 if (src0
.file
!= BAD_FILE
) {
2799 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2800 emit(MOV(sources
[length
], src0
));
2804 if (src1
.file
!= BAD_FILE
) {
2805 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2806 emit(MOV(sources
[length
], src1
));
2810 int mlen
= 1 + (length
- 1) * reg_width
;
2811 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2812 BRW_REGISTER_TYPE_UD
);
2813 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
2815 /* Emit the instruction. */
2816 fs_inst
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
2817 fs_reg(atomic_op
), fs_reg(surf_index
));
2822 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2826 (stage
== MESA_SHADER_FRAGMENT
) &&
2827 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2828 int reg_width
= dispatch_width
/ 8;
2830 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
2832 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2833 /* Initialize the sample mask in the message header. */
2834 emit(MOV(sources
[0], fs_reg(0u)))
2835 ->force_writemask_all
= true;
2838 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2839 ->force_writemask_all
= true;
2841 emit(MOV(component(sources
[0], 7),
2842 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2843 ->force_writemask_all
= true;
2846 /* Set the surface read offset. */
2847 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2848 emit(MOV(sources
[1], offset
));
2850 int mlen
= 1 + reg_width
;
2851 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2852 BRW_REGISTER_TYPE_UD
);
2853 fs_inst
*inst
= emit(LOAD_PAYLOAD(src_payload
, sources
, 2));
2855 /* Emit the instruction. */
2856 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
2857 fs_reg(surf_index
));
2862 fs_visitor::emit(fs_inst
*inst
)
2864 if (force_uncompressed_stack
> 0)
2865 inst
->exec_size
= 8;
2867 if (dispatch_width
== 16 && inst
->exec_size
== 8)
2868 inst
->force_uncompressed
= true;
2870 inst
->annotation
= this->current_annotation
;
2871 inst
->ir
= this->base_ir
;
2873 this->instructions
.push_tail(inst
);
2879 fs_visitor::emit(exec_list list
)
2881 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2882 inst
->exec_node::remove();
2887 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2889 fs_visitor::emit_dummy_fs()
2891 int reg_width
= dispatch_width
/ 8;
2893 /* Everyone's favorite color. */
2894 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2895 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2896 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2897 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2900 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2901 write
->base_mrf
= 2;
2902 write
->mlen
= 4 * reg_width
;
2906 /* The register location here is relative to the start of the URB
2907 * data. It will get adjusted to be a real location before
2908 * generate_code() time.
2911 fs_visitor::interp_reg(int location
, int channel
)
2913 assert(stage
== MESA_SHADER_FRAGMENT
);
2914 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
2915 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
2916 int stride
= (channel
& 1) * 4;
2918 assert(prog_data
->urb_setup
[location
] != -1);
2920 return brw_vec1_grf(regnr
, stride
);
2923 /** Emits the interpolation for the varying inputs. */
2925 fs_visitor::emit_interpolation_setup_gen4()
2927 this->current_annotation
= "compute pixel centers";
2928 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2929 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2930 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2931 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2933 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2934 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2936 this->current_annotation
= "compute pixel deltas from v0";
2938 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2939 fs_reg(this, glsl_type::vec2_type
);
2940 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2941 offset(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
], 1);
2943 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2944 fs_reg(this, glsl_type::float_type
);
2945 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2946 fs_reg(this, glsl_type::float_type
);
2948 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2949 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2950 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2951 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2953 this->current_annotation
= "compute pos.w and 1/pos.w";
2954 /* Compute wpos.w. It's always in our setup, since it's needed to
2955 * interpolate the other attributes.
2957 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2958 emit(FS_OPCODE_LINTERP
, wpos_w
,
2959 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2960 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2961 interp_reg(VARYING_SLOT_POS
, 3));
2962 /* Compute the pixel 1/W value from wpos.w. */
2963 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2964 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2965 this->current_annotation
= NULL
;
2968 /** Emits the interpolation for the varying inputs. */
2970 fs_visitor::emit_interpolation_setup_gen6()
2972 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2974 /* If the pixel centers end up used, the setup is the same as for gen4. */
2975 this->current_annotation
= "compute pixel centers";
2976 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2977 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2978 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2979 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2980 emit(ADD(int_pixel_x
,
2981 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2982 fs_reg(brw_imm_v(0x10101010))));
2983 emit(ADD(int_pixel_y
,
2984 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2985 fs_reg(brw_imm_v(0x11001100))));
2987 /* As of gen6, we can no longer mix float and int sources. We have
2988 * to turn the integer pixel centers into floats for their actual
2991 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2992 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2993 emit(MOV(this->pixel_x
, int_pixel_x
));
2994 emit(MOV(this->pixel_y
, int_pixel_y
));
2996 this->current_annotation
= "compute pos.w";
2997 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
2998 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2999 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
3001 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3002 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
3003 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
3004 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
3007 this->current_annotation
= NULL
;
3011 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
)
3013 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3016 if (color
.file
== BAD_FILE
) {
3017 return 4 * (dispatch_width
/ 8);
3020 uint8_t colors_enabled
;
3021 if (components
== 0) {
3022 /* We want to write one component to the alpha channel */
3023 colors_enabled
= 0x8;
3025 /* Enable the first components-many channels */
3026 colors_enabled
= (1 << components
) - 1;
3029 if (dispatch_width
== 8 || brw
->gen
>= 6) {
3030 /* SIMD8 write looks like:
3036 * gen6 SIMD16 DP write looks like:
3047 for (unsigned i
= 0; i
< 4; ++i
) {
3048 if (colors_enabled
& (1 << i
)) {
3049 dst
[len
] = fs_reg(GRF
, virtual_grf_alloc(color
.width
/ 8),
3050 color
.type
, color
.width
);
3051 inst
= emit(MOV(dst
[len
], offset(color
, i
)));
3052 inst
->saturate
= key
->clamp_fragment_color
;
3053 } else if (color
.width
== 16) {
3054 /* We need two BAD_FILE slots for a 16-wide color */
3061 /* pre-gen6 SIMD16 single source DP write looks like:
3071 for (unsigned i
= 0; i
< 4; ++i
) {
3072 if (colors_enabled
& (1 << i
)) {
3073 dst
[i
] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3074 inst
= emit(MOV(dst
[i
], half(offset(color
, i
), 0)));
3075 inst
->saturate
= key
->clamp_fragment_color
;
3077 dst
[i
+ 4] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3078 inst
= emit(MOV(dst
[i
+ 4], half(offset(color
, i
), 1)));
3079 inst
->saturate
= key
->clamp_fragment_color
;
3080 inst
->force_sechalf
= true;
3087 static enum brw_conditional_mod
3088 cond_for_alpha_func(GLenum func
)
3092 return BRW_CONDITIONAL_G
;
3094 return BRW_CONDITIONAL_GE
;
3096 return BRW_CONDITIONAL_L
;
3098 return BRW_CONDITIONAL_LE
;
3100 return BRW_CONDITIONAL_EQ
;
3102 return BRW_CONDITIONAL_NEQ
;
3104 unreachable("Not reached");
3109 * Alpha test support for when we compile it into the shader instead
3110 * of using the normal fixed-function alpha test.
3113 fs_visitor::emit_alpha_test()
3115 assert(stage
== MESA_SHADER_FRAGMENT
);
3116 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3117 this->current_annotation
= "Alpha test";
3120 if (key
->alpha_test_func
== GL_ALWAYS
)
3123 if (key
->alpha_test_func
== GL_NEVER
) {
3125 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3126 BRW_REGISTER_TYPE_UW
));
3127 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3128 BRW_CONDITIONAL_NEQ
));
3131 fs_reg color
= offset(outputs
[0], 3);
3133 /* f0.1 &= func(color, ref) */
3134 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3135 cond_for_alpha_func(key
->alpha_test_func
)));
3137 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3138 cmp
->flag_subreg
= 1;
3142 fs_visitor::emit_single_fb_write(fs_reg color0
, fs_reg color1
,
3143 fs_reg src0_alpha
, unsigned components
)
3145 assert(stage
== MESA_SHADER_FRAGMENT
);
3146 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3147 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3149 this->current_annotation
= "FB write header";
3150 bool header_present
= true;
3151 int reg_size
= dispatch_width
/ 8;
3153 /* We can potentially have a message length of up to 15, so we have to set
3154 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3156 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
3159 /* From the Sandy Bridge PRM, volume 4, page 198:
3161 * "Dispatched Pixel Enables. One bit per pixel indicating
3162 * which pixels were originally enabled when the thread was
3163 * dispatched. This field is only required for the end-of-
3164 * thread message and on all dual-source messages."
3166 if (brw
->gen
>= 6 &&
3167 (brw
->is_haswell
|| brw
->gen
>= 8 || !prog_data
->uses_kill
) &&
3168 color1
.file
== BAD_FILE
&&
3169 key
->nr_color_regions
== 1) {
3170 header_present
= false;
3174 /* Allocate 2 registers for a header */
3177 if (payload
.aa_dest_stencil_reg
) {
3178 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1));
3179 emit(MOV(sources
[length
],
3180 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3184 prog_data
->uses_omask
=
3185 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3186 if (prog_data
->uses_omask
) {
3187 this->current_annotation
= "FB write oMask";
3188 assert(this->sample_mask
.file
!= BAD_FILE
);
3189 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
3190 * it's unsinged single words, one vgrf is always 16-wide.
3192 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1),
3193 BRW_REGISTER_TYPE_UW
, 16);
3194 emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
3198 if (color0
.file
== BAD_FILE
) {
3199 /* Even if there's no color buffers enabled, we still need to send
3200 * alpha out the pipeline to our null renderbuffer to support
3201 * alpha-testing, alpha-to-coverage, and so on.
3203 length
+= setup_color_payload(sources
+ length
, this->outputs
[0], 0);
3204 } else if (color1
.file
== BAD_FILE
) {
3205 if (src0_alpha
.file
!= BAD_FILE
) {
3206 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(reg_size
),
3207 src0_alpha
.type
, src0_alpha
.width
);
3208 fs_inst
*inst
= emit(MOV(sources
[length
], src0_alpha
));
3209 inst
->saturate
= key
->clamp_fragment_color
;
3213 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3215 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3216 length
+= setup_color_payload(sources
+ length
, color1
, components
);
3219 if (source_depth_to_render_target
) {
3220 if (brw
->gen
== 6) {
3221 /* For outputting oDepth on gen6, SIMD8 writes have to be
3222 * used. This would require SIMD8 moves of each half to
3223 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3224 * Just bail on doing so for now.
3226 no16("Missing support for simd16 depth writes on gen6\n");
3229 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3230 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3231 /* Hand over gl_FragDepth. */
3232 assert(this->frag_depth
.file
!= BAD_FILE
);
3233 emit(MOV(sources
[length
], this->frag_depth
));
3235 /* Pass through the payload depth. */
3236 emit(MOV(sources
[length
],
3237 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3242 if (payload
.dest_depth_reg
) {
3243 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3244 emit(MOV(sources
[length
],
3245 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3251 if (brw
->gen
>= 7) {
3252 /* Send from the GRF */
3253 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3254 load
= emit(LOAD_PAYLOAD(payload
, sources
, length
));
3255 payload
.reg
= virtual_grf_alloc(load
->regs_written
);
3256 load
->dst
= payload
;
3257 write
= emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
3258 write
->base_mrf
= -1;
3260 /* Send from the MRF */
3261 load
= emit(LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3263 write
= emit(FS_OPCODE_FB_WRITE
);
3264 write
->base_mrf
= 1;
3267 write
->mlen
= load
->regs_written
;
3268 write
->header_present
= header_present
;
3269 if ((brw
->gen
>= 8 || brw
->is_haswell
) && prog_data
->uses_kill
) {
3270 write
->predicate
= BRW_PREDICATE_NORMAL
;
3271 write
->flag_subreg
= 1;
3277 fs_visitor::emit_fb_writes()
3279 assert(stage
== MESA_SHADER_FRAGMENT
);
3280 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3281 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3284 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
3285 if (dispatch_width
== 16)
3286 do_dual_src
= false;
3291 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3292 emit_shader_time_end();
3294 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3295 "FB dual-source write");
3296 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3299 prog_data
->dual_src_blend
= true;
3300 } else if (key
->nr_color_regions
> 0) {
3301 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3302 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3303 "FB write target %d",
3306 if (brw
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
3307 src0_alpha
= offset(outputs
[0], 3);
3309 if (target
== key
->nr_color_regions
- 1 &&
3310 (INTEL_DEBUG
& DEBUG_SHADER_TIME
))
3311 emit_shader_time_end();
3313 inst
= emit_single_fb_write(this->outputs
[target
], reg_undef
,
3315 this->output_components
[target
]);
3316 inst
->target
= target
;
3319 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3320 emit_shader_time_end();
3322 /* Even if there's no color buffers enabled, we still need to send
3323 * alpha out the pipeline to our null renderbuffer to support
3324 * alpha-testing, alpha-to-coverage, and so on.
3326 inst
= emit_single_fb_write(reg_undef
, reg_undef
, reg_undef
, 0);
3331 this->current_annotation
= NULL
;
3335 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3337 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3341 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
3342 emit(MOV(temp
, *reg
));
3347 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3349 assert(ctx
->Const
.UniformBooleanTrue
== 1);
3351 if (rvalue
->type
!= glsl_type::bool_type
)
3354 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
3355 emit(AND(temp
, *reg
, fs_reg(1)));
3359 fs_visitor::fs_visitor(struct brw_context
*brw
,
3361 const struct brw_wm_prog_key
*key
,
3362 struct brw_wm_prog_data
*prog_data
,
3363 struct gl_shader_program
*shader_prog
,
3364 struct gl_fragment_program
*fp
,
3365 unsigned dispatch_width
)
3366 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3367 MESA_SHADER_FRAGMENT
),
3368 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
3369 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
3370 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
3371 key(key
), prog_data(&prog_data
->base
),
3372 dispatch_width(dispatch_width
)
3374 this->mem_ctx
= mem_ctx
;
3381 this->failed
= false;
3382 this->simd16_unsupported
= false;
3383 this->no16_msg
= NULL
;
3384 this->variable_ht
= hash_table_ctor(0,
3385 hash_table_pointer_hash
,
3386 hash_table_pointer_compare
);
3388 memset(&this->payload
, 0, sizeof(this->payload
));
3389 memset(this->outputs
, 0, sizeof(this->outputs
));
3390 memset(this->output_components
, 0, sizeof(this->output_components
));
3391 this->source_depth_to_render_target
= false;
3392 this->runtime_check_aads_emit
= false;
3393 this->first_non_payload_grf
= 0;
3394 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3396 this->current_annotation
= NULL
;
3397 this->base_ir
= NULL
;
3399 this->virtual_grf_sizes
= NULL
;
3400 this->virtual_grf_count
= 0;
3401 this->virtual_grf_array_size
= 0;
3402 this->virtual_grf_start
= NULL
;
3403 this->virtual_grf_end
= NULL
;
3404 this->live_intervals
= NULL
;
3405 this->regs_live_at_ip
= NULL
;
3408 this->last_scratch
= 0;
3409 this->pull_constant_loc
= NULL
;
3410 this->push_constant_loc
= NULL
;
3412 this->force_uncompressed_stack
= 0;
3414 this->spilled_any_registers
= false;
3415 this->do_dual_src
= false;
3417 if (dispatch_width
== 8)
3418 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3421 fs_visitor::~fs_visitor()
3423 hash_table_dtor(this->variable_ht
);