2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation(ir
);
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
74 assert(ir
->location
== FRAG_RESULT_DATA0
);
75 assert(ir
->index
== 1);
76 this->dual_src_output
= *reg
;
77 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
80 this->outputs
[i
] = *reg
;
81 this->output_components
[i
] = 4;
83 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
84 this->frag_depth
= *reg
;
86 /* gl_FragData or a user-defined FS output */
87 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
88 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
91 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
92 : ir
->type
->vector_elements
;
94 /* General color output. */
95 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
96 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
97 this->outputs
[output
] = *reg
;
98 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
99 this->output_components
[output
] = vector_elements
;
102 } else if (ir
->mode
== ir_var_uniform
) {
103 int param_index
= c
->prog_data
.nr_params
;
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
109 if (ir
->is_in_uniform_block())
112 if (dispatch_width
== 16) {
113 if (!variable_storage(ir
)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
119 param_size
[param_index
] = type_size(ir
->type
);
120 if (!strncmp(ir
->name
, "gl_", 3)) {
121 setup_builtin_uniform_values(ir
);
123 setup_uniform_values(ir
);
126 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
127 reg
->type
= brw_type_for_base_type(ir
->type
);
131 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
133 hash_table_insert(this->variable_ht
, reg
, ir
);
137 fs_visitor::visit(ir_dereference_variable
*ir
)
139 fs_reg
*reg
= variable_storage(ir
->var
);
144 fs_visitor::visit(ir_dereference_record
*ir
)
146 const glsl_type
*struct_type
= ir
->record
->type
;
148 ir
->record
->accept(this);
150 unsigned int offset
= 0;
151 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
152 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
154 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
156 this->result
.reg_offset
+= offset
;
157 this->result
.type
= brw_type_for_base_type(ir
->type
);
161 fs_visitor::visit(ir_dereference_array
*ir
)
163 ir_constant
*constant_index
;
165 int element_size
= type_size(ir
->type
);
167 constant_index
= ir
->array_index
->as_constant();
169 ir
->array
->accept(this);
171 src
.type
= brw_type_for_base_type(ir
->type
);
173 if (constant_index
) {
174 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
175 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
184 ir
->array_index
->accept(this);
187 index_reg
= fs_reg(this, glsl_type::int_type
);
188 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
191 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
194 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
195 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
201 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
204 !x
.is_valid_3src() ||
205 !y
.is_valid_3src() ||
206 !a
.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
209 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
210 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
212 emit(MUL(y_times_a
, y
, a
));
214 a
.negate
= !a
.negate
;
215 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
216 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
218 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
223 emit(LRP(dst
, a
, y
, x
));
228 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
229 fs_reg src0
, fs_reg src1
)
234 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
235 inst
->conditional_mod
= conditionalmod
;
237 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
239 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
240 inst
->predicate
= BRW_PREDICATE_NORMAL
;
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
248 fs_visitor::try_emit_saturate(ir_expression
*ir
)
250 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
255 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
257 sat_val
->accept(this);
258 fs_reg src
= this->result
;
260 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
265 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
266 if (!modify
|| modify
->regs_written
!= 1) {
267 this->result
= fs_reg(this, ir
->type
);
268 fs_inst
*inst
= emit(MOV(this->result
, src
));
269 inst
->saturate
= true;
271 modify
->saturate
= true;
280 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
282 /* 3-src instructions were introduced in gen6. */
286 /* MAD can only handle floating-point data. */
287 if (ir
->type
!= glsl_type::float_type
)
290 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
291 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
293 if (!mul
|| mul
->operation
!= ir_binop_mul
)
296 if (nonmul
->as_constant() ||
297 mul
->operands
[0]->as_constant() ||
298 mul
->operands
[1]->as_constant())
301 nonmul
->accept(this);
302 fs_reg src0
= this->result
;
304 mul
->operands
[0]->accept(this);
305 fs_reg src1
= this->result
;
307 mul
->operands
[1]->accept(this);
308 fs_reg src2
= this->result
;
310 this->result
= fs_reg(this, ir
->type
);
311 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
317 fs_visitor::visit(ir_expression
*ir
)
319 unsigned int operand
;
323 assert(ir
->get_num_operands() <= 3);
325 if (try_emit_saturate(ir
))
327 if (ir
->operation
== ir_binop_add
) {
328 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
332 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
333 ir
->operands
[operand
]->accept(this);
334 if (this->result
.file
== BAD_FILE
) {
335 fail("Failed to get tree for expression operand:\n");
336 ir
->operands
[operand
]->print();
339 assert(this->result
.is_valid_3src());
340 op
[operand
] = this->result
;
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
345 assert(!ir
->operands
[operand
]->type
->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
348 assert(!ir
->operands
[operand
]->type
->is_vector());
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
354 this->result
= fs_reg(this, ir
->type
);
356 switch (ir
->operation
) {
357 case ir_unop_logic_not
:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
361 emit(XOR(this->result
, op
[0], fs_reg(1)));
364 op
[0].negate
= !op
[0].negate
;
365 emit(MOV(this->result
, op
[0]));
369 op
[0].negate
= false;
370 emit(MOV(this->result
, op
[0]));
373 temp
= fs_reg(this, ir
->type
);
375 emit(MOV(this->result
, fs_reg(0.0f
)));
377 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
378 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
379 inst
->predicate
= BRW_PREDICATE_NORMAL
;
381 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
382 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
383 inst
->predicate
= BRW_PREDICATE_NORMAL
;
387 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
391 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
394 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
401 case ir_unop_sin_reduced
:
402 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
405 case ir_unop_cos_reduced
:
406 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
410 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
413 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
417 emit(ADD(this->result
, op
[0], op
[1]));
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
424 if (ir
->type
->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
430 * FINISHME: Emit just the MUL if we know an operand is small
433 if (brw
->gen
>= 7 && dispatch_width
== 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
436 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
438 emit(MUL(acc
, op
[0], op
[1]));
439 emit(MACH(reg_null_d
, op
[0], op
[1]));
440 emit(MOV(this->result
, fs_reg(acc
)));
442 emit(MUL(this->result
, op
[0], op
[1]));
445 case ir_binop_imul_high
: {
446 if (brw
->gen
>= 7 && dispatch_width
== 16)
447 fail("16-wide explicit accumulator operands unsupported\n");
449 struct brw_reg acc
= retype(brw_acc_reg(), this->result
.type
);
451 emit(MUL(acc
, op
[0], op
[1]));
452 emit(MACH(this->result
, op
[0], op
[1]));
456 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
457 assert(ir
->type
->is_integer());
458 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
460 case ir_binop_carry
: {
461 if (brw
->gen
>= 7 && dispatch_width
== 16)
462 fail("16-wide explicit accumulator operands unsupported\n");
464 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
466 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
467 emit(MOV(this->result
, fs_reg(acc
)));
470 case ir_binop_borrow
: {
471 if (brw
->gen
>= 7 && dispatch_width
== 16)
472 fail("16-wide explicit accumulator operands unsupported\n");
474 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
476 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
477 emit(MOV(this->result
, fs_reg(acc
)));
481 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
482 assert(ir
->type
->is_integer());
483 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
487 case ir_binop_greater
:
488 case ir_binop_lequal
:
489 case ir_binop_gequal
:
491 case ir_binop_all_equal
:
492 case ir_binop_nequal
:
493 case ir_binop_any_nequal
:
494 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
495 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
497 emit(CMP(this->result
, op
[0], op
[1],
498 brw_conditional_for_comparison(ir
->operation
)));
501 case ir_binop_logic_xor
:
502 emit(XOR(this->result
, op
[0], op
[1]));
505 case ir_binop_logic_or
:
506 emit(OR(this->result
, op
[0], op
[1]));
509 case ir_binop_logic_and
:
510 emit(AND(this->result
, op
[0], op
[1]));
515 assert(!"not reached: should be handled by brw_fs_channel_expressions");
519 assert(!"not reached: should be handled by lower_noise");
522 case ir_quadop_vector
:
523 assert(!"not reached: should be handled by lower_quadop_vector");
526 case ir_binop_vector_extract
:
527 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
530 case ir_triop_vector_insert
:
531 assert(!"not reached: should be handled by lower_vector_insert()");
535 assert(!"not reached: should be handled by ldexp_to_arith()");
539 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
543 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
546 case ir_unop_bitcast_i2f
:
547 case ir_unop_bitcast_u2f
:
548 op
[0].type
= BRW_REGISTER_TYPE_F
;
549 this->result
= op
[0];
552 case ir_unop_bitcast_f2u
:
553 op
[0].type
= BRW_REGISTER_TYPE_UD
;
554 this->result
= op
[0];
557 case ir_unop_bitcast_f2i
:
558 op
[0].type
= BRW_REGISTER_TYPE_D
;
559 this->result
= op
[0];
565 emit(MOV(this->result
, op
[0]));
569 emit(AND(this->result
, op
[0], fs_reg(1)));
572 temp
= fs_reg(this, glsl_type::int_type
);
573 emit(AND(temp
, op
[0], fs_reg(1)));
574 emit(MOV(this->result
, temp
));
578 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
581 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
585 emit(RNDZ(this->result
, op
[0]));
588 op
[0].negate
= !op
[0].negate
;
589 emit(RNDD(this->result
, op
[0]));
590 this->result
.negate
= true;
593 emit(RNDD(this->result
, op
[0]));
596 emit(FRC(this->result
, op
[0]));
598 case ir_unop_round_even
:
599 emit(RNDE(this->result
, op
[0]));
604 resolve_ud_negate(&op
[0]);
605 resolve_ud_negate(&op
[1]);
606 emit_minmax(ir
->operation
== ir_binop_min
?
607 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
608 this->result
, op
[0], op
[1]);
610 case ir_unop_pack_snorm_2x16
:
611 case ir_unop_pack_snorm_4x8
:
612 case ir_unop_pack_unorm_2x16
:
613 case ir_unop_pack_unorm_4x8
:
614 case ir_unop_unpack_snorm_2x16
:
615 case ir_unop_unpack_snorm_4x8
:
616 case ir_unop_unpack_unorm_2x16
:
617 case ir_unop_unpack_unorm_4x8
:
618 case ir_unop_unpack_half_2x16
:
619 case ir_unop_pack_half_2x16
:
620 assert(!"not reached: should be handled by lower_packing_builtins");
622 case ir_unop_unpack_half_2x16_split_x
:
623 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
625 case ir_unop_unpack_half_2x16_split_y
:
626 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
629 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
632 case ir_unop_bitfield_reverse
:
633 emit(BFREV(this->result
, op
[0]));
635 case ir_unop_bit_count
:
636 emit(CBIT(this->result
, op
[0]));
638 case ir_unop_find_msb
:
639 temp
= fs_reg(this, glsl_type::uint_type
);
640 emit(FBH(temp
, op
[0]));
642 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
643 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
644 * subtract the result from 31 to convert the MSB count into an LSB count.
647 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
648 emit(MOV(this->result
, temp
));
649 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
652 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
653 inst
->predicate
= BRW_PREDICATE_NORMAL
;
655 case ir_unop_find_lsb
:
656 emit(FBL(this->result
, op
[0]));
658 case ir_triop_bitfield_extract
:
659 /* Note that the instruction's argument order is reversed from GLSL
662 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
665 emit(BFI1(this->result
, op
[0], op
[1]));
668 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
670 case ir_quadop_bitfield_insert
:
671 assert(!"not reached: should be handled by "
672 "lower_instructions::bitfield_insert_to_bfm_bfi");
675 case ir_unop_bit_not
:
676 emit(NOT(this->result
, op
[0]));
678 case ir_binop_bit_and
:
679 emit(AND(this->result
, op
[0], op
[1]));
681 case ir_binop_bit_xor
:
682 emit(XOR(this->result
, op
[0], op
[1]));
684 case ir_binop_bit_or
:
685 emit(OR(this->result
, op
[0], op
[1]));
688 case ir_binop_lshift
:
689 emit(SHL(this->result
, op
[0], op
[1]));
692 case ir_binop_rshift
:
693 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
694 emit(ASR(this->result
, op
[0], op
[1]));
696 emit(SHR(this->result
, op
[0], op
[1]));
698 case ir_binop_pack_half_2x16_split
:
699 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
701 case ir_binop_ubo_load
: {
702 /* This IR node takes a constant uniform block and a constant or
703 * variable byte offset within the block and loads a vector from that.
705 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
706 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
707 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
709 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
710 packed_consts
.type
= result
.type
;
712 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
713 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
714 packed_consts
, surf_index
, const_offset_reg
));
716 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
717 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
718 /* UBO bools are any nonzero value. We consider bools to be
719 * values with the low bit set to 1. Convert them using CMP.
721 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
722 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
724 emit(MOV(result
, packed_consts
));
727 packed_consts
.smear
++;
730 /* The std140 packing rules don't allow vectors to cross 16-byte
731 * boundaries, and a reg is 32 bytes.
733 assert(packed_consts
.smear
< 8);
736 /* Turn the byte offset into a dword offset. */
737 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
738 emit(SHR(base_offset
, op
[1], fs_reg(2)));
740 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
741 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
744 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
745 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
751 result
.reg_offset
= 0;
756 /* Note that the instruction's argument order is reversed from GLSL
759 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
763 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
767 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
768 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[1], op
[2]);
769 inst
->predicate
= BRW_PREDICATE_NORMAL
;
775 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
776 const glsl_type
*type
, bool predicated
)
778 switch (type
->base_type
) {
779 case GLSL_TYPE_FLOAT
:
783 for (unsigned int i
= 0; i
< type
->components(); i
++) {
784 l
.type
= brw_type_for_base_type(type
);
785 r
.type
= brw_type_for_base_type(type
);
787 if (predicated
|| !l
.equals(r
)) {
788 fs_inst
*inst
= emit(MOV(l
, r
));
789 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
796 case GLSL_TYPE_ARRAY
:
797 for (unsigned int i
= 0; i
< type
->length
; i
++) {
798 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
802 case GLSL_TYPE_STRUCT
:
803 for (unsigned int i
= 0; i
< type
->length
; i
++) {
804 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
809 case GLSL_TYPE_SAMPLER
:
813 case GLSL_TYPE_ERROR
:
814 case GLSL_TYPE_INTERFACE
:
815 assert(!"not reached");
820 /* If the RHS processing resulted in an instruction generating a
821 * temporary value, and it would be easy to rewrite the instruction to
822 * generate its result right into the LHS instead, do so. This ends
823 * up reliably removing instructions where it can be tricky to do so
824 * later without real UD chain information.
827 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
830 fs_inst
*pre_rhs_inst
,
831 fs_inst
*last_rhs_inst
)
833 /* Only attempt if we're doing a direct assignment. */
835 !(ir
->lhs
->type
->is_scalar() ||
836 (ir
->lhs
->type
->is_vector() &&
837 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
840 /* Make sure the last instruction generated our source reg. */
841 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
847 /* If last_rhs_inst wrote a different number of components than our LHS,
848 * we can't safely rewrite it.
850 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
853 /* Success! Rewrite the instruction. */
860 fs_visitor::visit(ir_assignment
*ir
)
865 /* FINISHME: arrays on the lhs */
866 ir
->lhs
->accept(this);
869 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
871 ir
->rhs
->accept(this);
874 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
876 assert(l
.file
!= BAD_FILE
);
877 assert(r
.file
!= BAD_FILE
);
879 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
883 emit_bool_to_cond_code(ir
->condition
);
886 if (ir
->lhs
->type
->is_scalar() ||
887 ir
->lhs
->type
->is_vector()) {
888 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
889 if (ir
->write_mask
& (1 << i
)) {
890 inst
= emit(MOV(l
, r
));
892 inst
->predicate
= BRW_PREDICATE_NORMAL
;
898 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
903 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
904 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
914 if (ir
->shadow_comparitor
) {
915 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
916 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
917 coordinate
.reg_offset
++;
920 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
921 * the unused slots must be zeroed.
923 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
924 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
928 if (ir
->op
== ir_tex
) {
929 /* There's no plain shadow compare message, so we use shadow
930 * compare with a bias of 0.0.
932 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
934 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
935 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
938 assert(!"Should not get here.");
941 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
943 } else if (ir
->op
== ir_tex
) {
944 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
945 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
946 coordinate
.reg_offset
++;
948 /* zero the others. */
949 for (int i
= ir
->coordinate
->type
->vector_elements
; i
<3; i
++) {
950 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
952 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
954 } else if (ir
->op
== ir_txd
) {
957 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
958 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
959 coordinate
.reg_offset
++;
961 /* the slots for u and v are always present, but r is optional */
962 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
965 * dPdx = dudx, dvdx, drdx
966 * dPdy = dudy, dvdy, drdy
968 * 1-arg: Does not exist.
970 * 2-arg: dudx dvdx dudy dvdy
971 * dPdx.x dPdx.y dPdy.x dPdy.y
974 * 3-arg: dudx dvdx drdx dudy dvdy drdy
975 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
978 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
979 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
982 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
984 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
985 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
988 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
989 } else if (ir
->op
== ir_txs
) {
990 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
992 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
995 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
996 * instructions. We'll need to do SIMD16 here.
999 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
1001 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1002 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1004 coordinate
.reg_offset
++;
1007 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1008 * be necessary for TXF (ld), but seems wise to do for all messages.
1010 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
1011 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1014 /* lod/bias appears after u/v/r. */
1017 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1020 /* The unused upper half. */
1025 /* Now, since we're doing simd16, the return is 2 interleaved
1026 * vec4s where the odd-indexed ones are junk. We'll need to move
1027 * this weirdness around to the expected layout.
1030 dst
= fs_reg(GRF
, virtual_grf_alloc(8),
1032 brw_type_for_base_type(ir
->type
) :
1033 BRW_REGISTER_TYPE_F
));
1036 fs_inst
*inst
= NULL
;
1039 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1042 inst
= emit(FS_OPCODE_TXB
, dst
);
1045 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1048 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1051 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1054 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1057 fail("unrecognized texture opcode");
1059 inst
->base_mrf
= base_mrf
;
1061 inst
->header_present
= true;
1062 inst
->regs_written
= simd16
? 8 : 4;
1065 for (int i
= 0; i
< 4; i
++) {
1066 emit(MOV(orig_dst
, dst
));
1067 orig_dst
.reg_offset
++;
1068 dst
.reg_offset
+= 2;
1075 /* gen5's sampler has slots for u, v, r, array index, then optional
1076 * parameters like shadow comparitor or LOD bias. If optional
1077 * parameters aren't present, those base slots are optional and don't
1078 * need to be included in the message.
1080 * We don't fill in the unnecessary slots regardless, which may look
1081 * surprising in the disassembly.
1084 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1085 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1086 fs_reg sample_index
)
1090 int reg_width
= dispatch_width
/ 8;
1091 bool header_present
= false;
1092 const int vector_elements
=
1093 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
1095 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
1096 /* It appears that the ld instruction used for txf does its
1097 * address bounds check before adding in the offset. To work
1098 * around this, just add the integer offset to the integer texel
1099 * coordinate, and don't put the offset in the header.
1101 ir_constant
*offset
= ir
->offset
->as_constant();
1102 for (int i
= 0; i
< vector_elements
; i
++) {
1103 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1105 offset
->value
.i
[i
]));
1106 coordinate
.reg_offset
++;
1110 /* The offsets set up by the ir_texture visitor are in the
1111 * m1 header, so we can't go headerless.
1113 header_present
= true;
1118 for (int i
= 0; i
< vector_elements
; i
++) {
1119 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1121 coordinate
.reg_offset
++;
1124 mlen
+= vector_elements
* reg_width
;
1126 if (ir
->shadow_comparitor
) {
1127 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1129 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1133 fs_inst
*inst
= NULL
;
1136 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1139 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1140 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1143 inst
= emit(FS_OPCODE_TXB
, dst
);
1146 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1147 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1150 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1153 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1157 * dPdx = dudx, dvdx, drdx
1158 * dPdy = dudy, dvdy, drdy
1160 * Load up these values:
1161 * - dudx dudy dvdx dvdy drdx drdy
1162 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1164 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1165 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1169 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1174 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1178 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1180 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1182 case ir_query_levels
:
1183 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1185 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1188 mlen
= header_present
+ 4 * reg_width
;
1189 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1190 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1193 mlen
= header_present
+ 4 * reg_width
;
1196 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1198 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1200 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1203 inst
= emit(SHADER_OPCODE_LOD
, dst
);
1206 inst
= emit(SHADER_OPCODE_TG4
, dst
);
1209 fail("unrecognized texture opcode");
1212 inst
->base_mrf
= base_mrf
;
1214 inst
->header_present
= header_present
;
1215 inst
->regs_written
= 4;
1218 fail("Message length >11 disallowed by hardware\n");
1225 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1226 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1227 fs_reg sample_index
)
1229 int reg_width
= dispatch_width
/ 8;
1230 bool header_present
= false;
1233 fs_reg payload
= fs_reg(this, glsl_type::float_type
);
1234 fs_reg next
= payload
;
1236 if (ir
->op
== ir_tg4
|| (ir
->offset
&& ir
->op
!= ir_txf
)) {
1237 /* For general texture offsets (no txf workaround), we need a header to
1238 * put them in. Note that for 16-wide we're making space for two actual
1239 * hardware registers here, so the emit will have to fix up for this.
1241 * * ir4_tg4 needs to place its channel select in the header,
1242 * for interaction with ARB_texture_swizzle
1244 header_present
= true;
1248 if (ir
->shadow_comparitor
) {
1249 emit(MOV(next
, shadow_c
));
1253 /* Set up the LOD info */
1260 emit(MOV(next
, lod
));
1264 emit(MOV(next
, lod
));
1268 if (dispatch_width
== 16)
1269 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1271 /* Load dPdx and the coordinate together:
1272 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1274 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1275 emit(MOV(next
, coordinate
));
1276 coordinate
.reg_offset
++;
1279 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1280 * only derivatives for (u, v, r).
1282 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1283 emit(MOV(next
, lod
));
1287 emit(MOV(next
, lod2
));
1295 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), lod
));
1298 case ir_query_levels
:
1299 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1303 /* It appears that the ld instruction used for txf does its
1304 * address bounds check before adding in the offset. To work
1305 * around this, just add the integer offset to the integer texel
1306 * coordinate, and don't put the offset in the header.
1309 ir_constant
*offset
= ir
->offset
->as_constant();
1310 offsets
[0] = offset
->value
.i
[0];
1311 offsets
[1] = offset
->value
.i
[1];
1312 offsets
[2] = offset
->value
.i
[2];
1314 memset(offsets
, 0, sizeof(offsets
));
1317 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1318 emit(ADD(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
, offsets
[0]));
1319 coordinate
.reg_offset
++;
1322 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), lod
));
1325 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1326 emit(ADD(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
, offsets
[i
]));
1327 coordinate
.reg_offset
++;
1332 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), sample_index
));
1335 /* constant zero MCS; we arrange to never actually have a compressed
1336 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1337 * if we ever support texturing from compressed multisample surfaces
1339 emit(MOV(next
.retype(BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1342 /* there is no offsetting for this message; just copy in the integer
1343 * texture coordinates
1345 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1346 emit(MOV(next
.retype(BRW_REGISTER_TYPE_D
), coordinate
));
1347 coordinate
.reg_offset
++;
1353 /* Set up the coordinate (except for cases where it was done above) */
1354 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
&& ir
->op
!= ir_txf_ms
&& ir
->op
!= ir_query_levels
) {
1355 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1356 emit(MOV(next
, coordinate
));
1357 coordinate
.reg_offset
++;
1362 /* Generate the SEND */
1363 fs_inst
*inst
= NULL
;
1365 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
, payload
); break;
1366 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
, payload
); break;
1367 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
, payload
); break;
1368 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
, payload
); break;
1369 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
, payload
); break;
1370 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
, payload
); break;
1371 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1372 case ir_query_levels
: inst
= emit(SHADER_OPCODE_TXS
, dst
, payload
); break;
1373 case ir_lod
: inst
= emit(SHADER_OPCODE_LOD
, dst
, payload
); break;
1374 case ir_tg4
: inst
= emit(SHADER_OPCODE_TG4
, dst
, payload
); break;
1376 inst
->base_mrf
= -1;
1378 inst
->mlen
= next
.reg_offset
* reg_width
- header_present
;
1380 inst
->mlen
= next
.reg_offset
* reg_width
;
1382 inst
->header_present
= header_present
;
1383 inst
->regs_written
= 4;
1385 virtual_grf_sizes
[payload
.reg
] = next
.reg_offset
;
1386 if (inst
->mlen
> 11) {
1387 fail("Message length >11 disallowed by hardware\n");
1394 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1395 bool is_rect
, int sampler
, int texunit
)
1397 fs_inst
*inst
= NULL
;
1398 bool needs_gl_clamp
= true;
1399 fs_reg scale_x
, scale_y
;
1401 /* The 965 requires the EU to do the normalization of GL rectangle
1402 * texture coordinates. We use the program parameter state
1403 * tracking to get the scaling factor.
1407 (brw
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1408 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1409 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1410 int tokens
[STATE_LENGTH
] = {
1412 STATE_TEXRECT_SCALE
,
1418 if (dispatch_width
== 16) {
1419 fail("rectangle scale uniform setup not supported on 16-wide\n");
1423 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1424 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1426 GLuint index
= _mesa_add_state_reference(params
,
1427 (gl_state_index
*)tokens
);
1428 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1429 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1430 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1431 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1434 /* The 965 requires the EU to do the normalization of GL rectangle
1435 * texture coordinates. We use the program parameter state
1436 * tracking to get the scaling factor.
1438 if (brw
->gen
< 6 && is_rect
) {
1439 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1440 fs_reg src
= coordinate
;
1443 emit(MUL(dst
, src
, scale_x
));
1446 emit(MUL(dst
, src
, scale_y
));
1447 } else if (is_rect
) {
1448 /* On gen6+, the sampler handles the rectangle coordinates
1449 * natively, without needing rescaling. But that means we have
1450 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1451 * not [0, 1] like the default case below.
1453 needs_gl_clamp
= false;
1455 for (int i
= 0; i
< 2; i
++) {
1456 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1457 fs_reg chan
= coordinate
;
1458 chan
.reg_offset
+= i
;
1460 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1461 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1463 /* Our parameter comes in as 1.0/width or 1.0/height,
1464 * because that's what people normally want for doing
1465 * texture rectangle handling. We need width or height
1466 * for clamping, but we don't care enough to make a new
1467 * parameter type, so just invert back.
1469 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1470 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1471 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1473 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1474 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1479 if (ir
->coordinate
&& needs_gl_clamp
) {
1480 for (unsigned int i
= 0;
1481 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1482 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1483 fs_reg chan
= coordinate
;
1484 chan
.reg_offset
+= i
;
1486 fs_inst
*inst
= emit(MOV(chan
, chan
));
1487 inst
->saturate
= true;
1495 fs_visitor::visit(ir_texture
*ir
)
1497 fs_inst
*inst
= NULL
;
1500 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, &fp
->Base
);
1501 /* FINISHME: We're failing to recompile our programs when the sampler is
1502 * updated. This only matters for the texture rectangle scale parameters
1503 * (pre-gen6, or gen6+ with GL_CLAMP).
1505 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1507 if (ir
->op
== ir_tg4
) {
1508 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1509 * emitting anything other than setting up the constant result.
1511 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1512 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1513 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1515 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1518 for (int i
=0; i
<4; i
++) {
1519 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1526 /* Should be lowered by do_lower_texture_projection */
1527 assert(!ir
->projector
);
1529 /* Generate code to compute all the subexpression trees. This has to be
1530 * done before loading any values into MRFs for the sampler message since
1531 * generating these values may involve SEND messages that need the MRFs.
1534 if (ir
->coordinate
) {
1535 ir
->coordinate
->accept(this);
1537 coordinate
= rescale_texcoord(ir
, this->result
,
1538 ir
->sampler
->type
->sampler_dimensionality
==
1539 GLSL_SAMPLER_DIM_RECT
,
1543 fs_reg shadow_comparitor
;
1544 if (ir
->shadow_comparitor
) {
1545 ir
->shadow_comparitor
->accept(this);
1546 shadow_comparitor
= this->result
;
1549 fs_reg lod
, lod2
, sample_index
;
1554 case ir_query_levels
:
1557 ir
->lod_info
.bias
->accept(this);
1561 ir
->lod_info
.grad
.dPdx
->accept(this);
1564 ir
->lod_info
.grad
.dPdy
->accept(this);
1565 lod2
= this->result
;
1570 ir
->lod_info
.lod
->accept(this);
1574 ir
->lod_info
.sample_index
->accept(this);
1575 sample_index
= this->result
;
1578 assert(!"Unrecognized texture opcode");
1581 /* Writemasking doesn't eliminate channels on SIMD8 texture
1582 * samples, so don't worry about them.
1584 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1586 if (brw
->gen
>= 7) {
1587 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1588 lod
, lod2
, sample_index
);
1589 } else if (brw
->gen
>= 5) {
1590 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1591 lod
, lod2
, sample_index
);
1593 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1597 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1598 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1600 if (ir
->op
== ir_tg4
)
1601 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16; // M0.2:16-17
1603 inst
->sampler
= sampler
;
1605 if (ir
->shadow_comparitor
)
1606 inst
->shadow_compare
= true;
1608 /* fixup #layers for cube map arrays */
1609 if (ir
->op
== ir_txs
) {
1610 glsl_type
const *type
= ir
->sampler
->type
;
1611 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1612 type
->sampler_array
) {
1614 depth
.reg_offset
= 2;
1615 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1619 swizzle_result(ir
, dst
, sampler
);
1623 * Set up the gather channel based on the swizzle, for gather4.
1626 fs_visitor::gather_channel(ir_texture
*ir
, int sampler
)
1628 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
1629 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], chan
->value
.i
[0]);
1631 case SWIZZLE_X
: return 0;
1633 /* gather4 sampler is broken for green channel on RG32F --
1634 * we must ask for blue instead.
1636 if (c
->key
.tex
.gather_channel_quirk_mask
& (1<<sampler
))
1639 case SWIZZLE_Z
: return 2;
1640 case SWIZZLE_W
: return 3;
1642 assert(!"Not reached"); /* zero, one swizzles handled already */
1648 * Swizzle the result of a texture result. This is necessary for
1649 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1652 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1654 if (ir
->op
== ir_query_levels
) {
1655 /* # levels is in .w */
1656 orig_val
.reg_offset
+= 3;
1657 this->result
= orig_val
;
1661 this->result
= orig_val
;
1663 /* txs,lod don't actually sample the texture, so swizzling the result
1666 if (ir
->op
== ir_txs
|| ir
->op
== ir_lod
|| ir
->op
== ir_tg4
)
1669 if (ir
->type
== glsl_type::float_type
) {
1670 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1671 assert(ir
->sampler
->type
->sampler_shadow
);
1672 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1673 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1675 for (int i
= 0; i
< 4; i
++) {
1676 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1677 fs_reg l
= swizzled_result
;
1680 if (swiz
== SWIZZLE_ZERO
) {
1681 emit(MOV(l
, fs_reg(0.0f
)));
1682 } else if (swiz
== SWIZZLE_ONE
) {
1683 emit(MOV(l
, fs_reg(1.0f
)));
1685 fs_reg r
= orig_val
;
1686 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1690 this->result
= swizzled_result
;
1695 fs_visitor::visit(ir_swizzle
*ir
)
1697 ir
->val
->accept(this);
1698 fs_reg val
= this->result
;
1700 if (ir
->type
->vector_elements
== 1) {
1701 this->result
.reg_offset
+= ir
->mask
.x
;
1705 fs_reg result
= fs_reg(this, ir
->type
);
1706 this->result
= result
;
1708 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1709 fs_reg channel
= val
;
1727 channel
.reg_offset
+= swiz
;
1728 emit(MOV(result
, channel
));
1729 result
.reg_offset
++;
1734 fs_visitor::visit(ir_discard
*ir
)
1736 assert(ir
->condition
== NULL
); /* FINISHME */
1738 /* We track our discarded pixels in f0.1. By predicating on it, we can
1739 * update just the flag bits that aren't yet discarded. By emitting a
1740 * CMP of g0 != g0, all our currently executing channels will get turned
1743 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1744 BRW_REGISTER_TYPE_UW
));
1745 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1746 BRW_CONDITIONAL_NZ
));
1747 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1748 cmp
->flag_subreg
= 1;
1750 if (brw
->gen
>= 6) {
1751 /* For performance, after a discard, jump to the end of the shader.
1752 * However, many people will do foliage by discarding based on a
1753 * texture's alpha mask, and then continue on to texture with the
1754 * remaining pixels. To avoid trashing the derivatives for those
1755 * texture samples, we'll only jump if all of the pixels in the subspan
1756 * have been discarded.
1758 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1759 discard_jump
->flag_subreg
= 1;
1760 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1761 discard_jump
->predicate_inverse
= true;
1766 fs_visitor::visit(ir_constant
*ir
)
1768 /* Set this->result to reg at the bottom of the function because some code
1769 * paths will cause this visitor to be applied to other fields. This will
1770 * cause the value stored in this->result to be modified.
1772 * Make reg constant so that it doesn't get accidentally modified along the
1773 * way. Yes, I actually had this problem. :(
1775 const fs_reg
reg(this, ir
->type
);
1776 fs_reg dst_reg
= reg
;
1778 if (ir
->type
->is_array()) {
1779 const unsigned size
= type_size(ir
->type
->fields
.array
);
1781 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1782 ir
->array_elements
[i
]->accept(this);
1783 fs_reg src_reg
= this->result
;
1785 dst_reg
.type
= src_reg
.type
;
1786 for (unsigned j
= 0; j
< size
; j
++) {
1787 emit(MOV(dst_reg
, src_reg
));
1788 src_reg
.reg_offset
++;
1789 dst_reg
.reg_offset
++;
1792 } else if (ir
->type
->is_record()) {
1793 foreach_list(node
, &ir
->components
) {
1794 ir_constant
*const field
= (ir_constant
*) node
;
1795 const unsigned size
= type_size(field
->type
);
1797 field
->accept(this);
1798 fs_reg src_reg
= this->result
;
1800 dst_reg
.type
= src_reg
.type
;
1801 for (unsigned j
= 0; j
< size
; j
++) {
1802 emit(MOV(dst_reg
, src_reg
));
1803 src_reg
.reg_offset
++;
1804 dst_reg
.reg_offset
++;
1808 const unsigned size
= type_size(ir
->type
);
1810 for (unsigned i
= 0; i
< size
; i
++) {
1811 switch (ir
->type
->base_type
) {
1812 case GLSL_TYPE_FLOAT
:
1813 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1815 case GLSL_TYPE_UINT
:
1816 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1819 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1821 case GLSL_TYPE_BOOL
:
1822 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1825 assert(!"Non-float/uint/int/bool constant");
1827 dst_reg
.reg_offset
++;
1835 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1837 ir_expression
*expr
= ir
->as_expression();
1840 expr
->operation
!= ir_binop_logic_and
&&
1841 expr
->operation
!= ir_binop_logic_or
&&
1842 expr
->operation
!= ir_binop_logic_xor
) {
1846 assert(expr
->get_num_operands() <= 2);
1847 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1848 assert(expr
->operands
[i
]->type
->is_scalar());
1850 expr
->operands
[i
]->accept(this);
1851 op
[i
] = this->result
;
1853 resolve_ud_negate(&op
[i
]);
1856 switch (expr
->operation
) {
1857 case ir_unop_logic_not
:
1858 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1859 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1863 if (brw
->gen
>= 6) {
1864 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1866 inst
= emit(MOV(reg_null_f
, op
[0]));
1867 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1872 if (brw
->gen
>= 6) {
1873 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1875 inst
= emit(MOV(reg_null_d
, op
[0]));
1876 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1880 case ir_binop_greater
:
1881 case ir_binop_gequal
:
1883 case ir_binop_lequal
:
1884 case ir_binop_equal
:
1885 case ir_binop_all_equal
:
1886 case ir_binop_nequal
:
1887 case ir_binop_any_nequal
:
1888 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1889 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1891 emit(CMP(reg_null_d
, op
[0], op
[1],
1892 brw_conditional_for_comparison(expr
->operation
)));
1896 assert(!"not reached");
1897 fail("bad cond code\n");
1905 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1906 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1910 * Emit a gen6 IF statement with the comparison folded into the IF
1914 fs_visitor::emit_if_gen6(ir_if
*ir
)
1916 ir_expression
*expr
= ir
->condition
->as_expression();
1923 assert(expr
->get_num_operands() <= 2);
1924 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1925 assert(expr
->operands
[i
]->type
->is_scalar());
1927 expr
->operands
[i
]->accept(this);
1928 op
[i
] = this->result
;
1931 switch (expr
->operation
) {
1932 case ir_unop_logic_not
:
1933 case ir_binop_logic_xor
:
1934 case ir_binop_logic_or
:
1935 case ir_binop_logic_and
:
1936 /* For operations on bool arguments, only the low bit of the bool is
1937 * valid, and the others are undefined. Fall back to the condition
1943 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1944 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1948 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1951 case ir_binop_greater
:
1952 case ir_binop_gequal
:
1954 case ir_binop_lequal
:
1955 case ir_binop_equal
:
1956 case ir_binop_all_equal
:
1957 case ir_binop_nequal
:
1958 case ir_binop_any_nequal
:
1959 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1960 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1962 emit(IF(op
[0], op
[1],
1963 brw_conditional_for_comparison(expr
->operation
)));
1966 assert(!"not reached");
1967 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1968 fail("bad condition\n");
1973 emit_bool_to_cond_code(ir
->condition
);
1974 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1975 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1979 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1981 * Many GLSL shaders contain the following pattern:
1983 * x = condition ? foo : bar
1985 * The compiler emits an ir_if tree for this, since each subexpression might be
1986 * a complex tree that could have side-effects or short-circuit logic.
1988 * However, the common case is to simply select one of two constants or
1989 * variable values---which is exactly what SEL is for. In this case, the
1990 * assembly looks like:
1998 * which can be easily translated into:
2000 * (+f0) SEL dst src0 src1
2002 * If src0 is an immediate value, we promote it to a temporary GRF.
2005 fs_visitor::try_replace_with_sel()
2007 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2008 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2010 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2012 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2015 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2016 for (int i
= 0; i
< 4; i
++) {
2017 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2019 match
= (fs_inst
*) match
->prev
;
2022 /* The opcodes match; it looks like the right sequence of instructions. */
2023 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2024 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2025 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2027 /* Check that the MOVs are the right form. */
2028 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2029 !then_mov
->is_partial_write() &&
2030 !else_mov
->is_partial_write()) {
2032 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2033 while (!if_inst
->next
->is_tail_sentinel())
2034 if_inst
->next
->remove();
2037 /* Only the last source register can be a constant, so if the MOV in
2038 * the "then" clause uses a constant, we need to put it in a temporary.
2040 fs_reg
src0(then_mov
->src
[0]);
2041 if (src0
.file
== IMM
) {
2042 src0
= fs_reg(this, glsl_type::float_type
);
2043 src0
.type
= then_mov
->src
[0].type
;
2044 emit(MOV(src0
, then_mov
->src
[0]));
2048 if (if_inst
->conditional_mod
) {
2049 /* Sandybridge-specific IF with embedded comparison */
2050 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2051 if_inst
->conditional_mod
));
2052 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2053 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2055 /* Separate CMP and IF instructions */
2056 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2057 sel
->predicate
= if_inst
->predicate
;
2058 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2064 fs_visitor::visit(ir_if
*ir
)
2066 if (brw
->gen
< 6 && dispatch_width
== 16) {
2067 fail("Can't support (non-uniform) control flow on 16-wide\n");
2070 /* Don't point the annotation at the if statement, because then it plus
2071 * the then and else blocks get printed.
2073 this->base_ir
= ir
->condition
;
2075 if (brw
->gen
== 6) {
2078 emit_bool_to_cond_code(ir
->condition
);
2080 emit(IF(BRW_PREDICATE_NORMAL
));
2083 foreach_list(node
, &ir
->then_instructions
) {
2084 ir_instruction
*ir
= (ir_instruction
*)node
;
2090 if (!ir
->else_instructions
.is_empty()) {
2091 emit(BRW_OPCODE_ELSE
);
2093 foreach_list(node
, &ir
->else_instructions
) {
2094 ir_instruction
*ir
= (ir_instruction
*)node
;
2101 emit(BRW_OPCODE_ENDIF
);
2103 try_replace_with_sel();
2107 fs_visitor::visit(ir_loop
*ir
)
2109 fs_reg counter
= reg_undef
;
2111 if (brw
->gen
< 6 && dispatch_width
== 16) {
2112 fail("Can't support (non-uniform) control flow on 16-wide\n");
2116 this->base_ir
= ir
->counter
;
2117 ir
->counter
->accept(this);
2118 counter
= *(variable_storage(ir
->counter
));
2121 this->base_ir
= ir
->from
;
2122 ir
->from
->accept(this);
2124 emit(MOV(counter
, this->result
));
2128 this->base_ir
= NULL
;
2129 emit(BRW_OPCODE_DO
);
2132 this->base_ir
= ir
->to
;
2133 ir
->to
->accept(this);
2135 emit(CMP(reg_null_d
, counter
, this->result
,
2136 brw_conditional_for_comparison(ir
->cmp
)));
2138 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
2139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2142 foreach_list(node
, &ir
->body_instructions
) {
2143 ir_instruction
*ir
= (ir_instruction
*)node
;
2149 if (ir
->increment
) {
2150 this->base_ir
= ir
->increment
;
2151 ir
->increment
->accept(this);
2152 emit(ADD(counter
, counter
, this->result
));
2155 this->base_ir
= NULL
;
2156 emit(BRW_OPCODE_WHILE
);
2160 fs_visitor::visit(ir_loop_jump
*ir
)
2163 case ir_loop_jump::jump_break
:
2164 emit(BRW_OPCODE_BREAK
);
2166 case ir_loop_jump::jump_continue
:
2167 emit(BRW_OPCODE_CONTINUE
);
2173 fs_visitor::visit(ir_call
*ir
)
2175 assert(!"FINISHME");
2179 fs_visitor::visit(ir_return
*ir
)
2181 assert(!"FINISHME");
2185 fs_visitor::visit(ir_function
*ir
)
2187 /* Ignore function bodies other than main() -- we shouldn't see calls to
2188 * them since they should all be inlined before we get to ir_to_mesa.
2190 if (strcmp(ir
->name
, "main") == 0) {
2191 const ir_function_signature
*sig
;
2194 sig
= ir
->matching_signature(NULL
, &empty
);
2198 foreach_list(node
, &sig
->body
) {
2199 ir_instruction
*ir
= (ir_instruction
*)node
;
2208 fs_visitor::visit(ir_function_signature
*ir
)
2210 assert(!"not reached");
2215 fs_visitor::visit(ir_emit_vertex
*)
2217 assert(!"not reached");
2221 fs_visitor::visit(ir_end_primitive
*)
2223 assert(!"not reached");
2227 fs_visitor::emit(fs_inst inst
)
2229 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
2236 fs_visitor::emit(fs_inst
*inst
)
2238 if (force_uncompressed_stack
> 0)
2239 inst
->force_uncompressed
= true;
2240 else if (force_sechalf_stack
> 0)
2241 inst
->force_sechalf
= true;
2243 inst
->annotation
= this->current_annotation
;
2244 inst
->ir
= this->base_ir
;
2246 this->instructions
.push_tail(inst
);
2252 fs_visitor::emit(exec_list list
)
2254 foreach_list_safe(node
, &list
) {
2255 fs_inst
*inst
= (fs_inst
*)node
;
2261 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2263 fs_visitor::emit_dummy_fs()
2265 int reg_width
= dispatch_width
/ 8;
2267 /* Everyone's favorite color. */
2268 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2269 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2270 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2271 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2274 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2275 write
->base_mrf
= 2;
2276 write
->mlen
= 4 * reg_width
;
2280 /* The register location here is relative to the start of the URB
2281 * data. It will get adjusted to be a real location before
2282 * generate_code() time.
2285 fs_visitor::interp_reg(int location
, int channel
)
2287 int regnr
= c
->prog_data
.urb_setup
[location
] * 2 + channel
/ 2;
2288 int stride
= (channel
& 1) * 4;
2290 assert(c
->prog_data
.urb_setup
[location
] != -1);
2292 return brw_vec1_grf(regnr
, stride
);
2295 /** Emits the interpolation for the varying inputs. */
2297 fs_visitor::emit_interpolation_setup_gen4()
2299 this->current_annotation
= "compute pixel centers";
2300 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2301 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2302 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2303 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2305 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2306 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2308 this->current_annotation
= "compute pixel deltas from v0";
2310 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2311 fs_reg(this, glsl_type::vec2_type
);
2312 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2313 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2314 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2316 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2317 fs_reg(this, glsl_type::float_type
);
2318 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2319 fs_reg(this, glsl_type::float_type
);
2321 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2322 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2323 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2324 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2326 this->current_annotation
= "compute pos.w and 1/pos.w";
2327 /* Compute wpos.w. It's always in our setup, since it's needed to
2328 * interpolate the other attributes.
2330 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2331 emit(FS_OPCODE_LINTERP
, wpos_w
,
2332 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2333 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2334 interp_reg(VARYING_SLOT_POS
, 3));
2335 /* Compute the pixel 1/W value from wpos.w. */
2336 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2337 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2338 this->current_annotation
= NULL
;
2341 /** Emits the interpolation for the varying inputs. */
2343 fs_visitor::emit_interpolation_setup_gen6()
2345 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2347 /* If the pixel centers end up used, the setup is the same as for gen4. */
2348 this->current_annotation
= "compute pixel centers";
2349 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2350 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2351 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2352 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2353 emit(ADD(int_pixel_x
,
2354 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2355 fs_reg(brw_imm_v(0x10101010))));
2356 emit(ADD(int_pixel_y
,
2357 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2358 fs_reg(brw_imm_v(0x11001100))));
2360 /* As of gen6, we can no longer mix float and int sources. We have
2361 * to turn the integer pixel centers into floats for their actual
2364 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2365 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2366 emit(MOV(this->pixel_x
, int_pixel_x
));
2367 emit(MOV(this->pixel_y
, int_pixel_y
));
2369 this->current_annotation
= "compute pos.w";
2370 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2371 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2372 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2374 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2375 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2376 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2377 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2380 this->current_annotation
= NULL
;
2384 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2386 int reg_width
= dispatch_width
/ 8;
2388 fs_reg color
= outputs
[target
];
2391 /* If there's no color data to be written, skip it. */
2392 if (color
.file
== BAD_FILE
)
2395 color
.reg_offset
+= index
;
2397 if (dispatch_width
== 8 || brw
->gen
>= 6) {
2398 /* SIMD8 write looks like:
2404 * gen6 SIMD16 DP write looks like:
2414 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2417 inst
->saturate
= c
->key
.clamp_fragment_color
;
2419 /* pre-gen6 SIMD16 single source DP write looks like:
2429 if (brw
->has_compr4
) {
2430 /* By setting the high bit of the MRF register number, we
2431 * indicate that we want COMPR4 mode - instead of doing the
2432 * usual destination + 1 for the second half we get
2435 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2438 inst
->saturate
= c
->key
.clamp_fragment_color
;
2440 push_force_uncompressed();
2441 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2443 inst
->saturate
= c
->key
.clamp_fragment_color
;
2444 pop_force_uncompressed();
2446 push_force_sechalf();
2447 color
.sechalf
= true;
2448 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2450 inst
->saturate
= c
->key
.clamp_fragment_color
;
2451 pop_force_sechalf();
2452 color
.sechalf
= false;
2458 fs_visitor::emit_fb_writes()
2460 this->current_annotation
= "FB write header";
2461 bool header_present
= true;
2462 /* We can potentially have a message length of up to 15, so we have to set
2463 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2467 int reg_width
= dispatch_width
/ 8;
2468 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2469 bool src0_alpha_to_render_target
= false;
2471 if (dispatch_width
== 16 && do_dual_src
) {
2472 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2473 do_dual_src
= false;
2476 /* From the Sandy Bridge PRM, volume 4, page 198:
2478 * "Dispatched Pixel Enables. One bit per pixel indicating
2479 * which pixels were originally enabled when the thread was
2480 * dispatched. This field is only required for the end-of-
2481 * thread message and on all dual-source messages."
2483 if (brw
->gen
>= 6 &&
2484 !this->fp
->UsesKill
&&
2486 c
->key
.nr_color_regions
== 1) {
2487 header_present
= false;
2490 if (header_present
) {
2491 src0_alpha_to_render_target
= brw
->gen
>= 6 &&
2493 c
->key
.replicate_alpha
;
2498 if (c
->aa_dest_stencil_reg
) {
2499 push_force_uncompressed();
2500 emit(MOV(fs_reg(MRF
, nr
++),
2501 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2502 pop_force_uncompressed();
2505 /* Reserve space for color. It'll be filled in per MRT below. */
2507 nr
+= 4 * reg_width
;
2510 if (src0_alpha_to_render_target
)
2513 if (c
->source_depth_to_render_target
) {
2514 if (brw
->gen
== 6 && dispatch_width
== 16) {
2515 /* For outputting oDepth on gen6, SIMD8 writes have to be
2516 * used. This would require 8-wide moves of each half to
2517 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2518 * Just bail on doing so for now.
2520 fail("Missing support for simd16 depth writes on gen6\n");
2523 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2524 /* Hand over gl_FragDepth. */
2525 assert(this->frag_depth
.file
!= BAD_FILE
);
2526 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2528 /* Pass through the payload depth. */
2529 emit(MOV(fs_reg(MRF
, nr
),
2530 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2535 if (c
->dest_depth_reg
) {
2536 emit(MOV(fs_reg(MRF
, nr
),
2537 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2542 fs_reg src0
= this->outputs
[0];
2543 fs_reg src1
= this->dual_src_output
;
2545 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2547 for (int i
= 0; i
< 4; i
++) {
2548 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2550 inst
->saturate
= c
->key
.clamp_fragment_color
;
2553 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2555 for (int i
= 0; i
< 4; i
++) {
2556 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2559 inst
->saturate
= c
->key
.clamp_fragment_color
;
2562 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2563 emit_shader_time_end();
2565 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2567 inst
->base_mrf
= base_mrf
;
2568 inst
->mlen
= nr
- base_mrf
;
2570 inst
->header_present
= header_present
;
2572 c
->prog_data
.dual_src_blend
= true;
2573 this->current_annotation
= NULL
;
2577 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2578 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2579 "FB write target %d",
2581 /* If src0_alpha_to_render_target is true, include source zero alpha
2582 * data in RenderTargetWrite message for targets > 0.
2584 int write_color_mrf
= color_mrf
;
2585 if (src0_alpha_to_render_target
&& target
!= 0) {
2587 fs_reg color
= outputs
[0];
2588 color
.reg_offset
+= 3;
2590 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2592 inst
->saturate
= c
->key
.clamp_fragment_color
;
2593 write_color_mrf
= color_mrf
+ reg_width
;
2596 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2597 emit_color_write(target
, i
, write_color_mrf
);
2600 if (target
== c
->key
.nr_color_regions
- 1) {
2603 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2604 emit_shader_time_end();
2607 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2608 inst
->target
= target
;
2609 inst
->base_mrf
= base_mrf
;
2610 if (src0_alpha_to_render_target
&& target
== 0)
2611 inst
->mlen
= nr
- base_mrf
- reg_width
;
2613 inst
->mlen
= nr
- base_mrf
;
2615 inst
->header_present
= header_present
;
2618 if (c
->key
.nr_color_regions
== 0) {
2619 /* Even if there's no color buffers enabled, we still need to send
2620 * alpha out the pipeline to our null renderbuffer to support
2621 * alpha-testing, alpha-to-coverage, and so on.
2623 emit_color_write(0, 3, color_mrf
);
2625 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2626 emit_shader_time_end();
2628 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2629 inst
->base_mrf
= base_mrf
;
2630 inst
->mlen
= nr
- base_mrf
;
2632 inst
->header_present
= header_present
;
2635 this->current_annotation
= NULL
;
2639 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2641 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2645 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2646 emit(MOV(temp
, *reg
));
2651 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2653 if (rvalue
->type
!= glsl_type::bool_type
)
2656 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2657 emit(AND(temp
, *reg
, fs_reg(1)));
2661 fs_visitor::fs_visitor(struct brw_context
*brw
,
2662 struct brw_wm_compile
*c
,
2663 struct gl_shader_program
*shader_prog
,
2664 struct gl_fragment_program
*fp
,
2665 unsigned dispatch_width
)
2666 : dispatch_width(dispatch_width
)
2671 this->shader_prog
= shader_prog
;
2672 this->ctx
= &brw
->ctx
;
2673 this->mem_ctx
= ralloc_context(NULL
);
2675 shader
= (struct brw_shader
*)
2676 shader_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2679 this->failed
= false;
2680 this->variable_ht
= hash_table_ctor(0,
2681 hash_table_pointer_hash
,
2682 hash_table_pointer_compare
);
2684 memset(this->outputs
, 0, sizeof(this->outputs
));
2685 memset(this->output_components
, 0, sizeof(this->output_components
));
2686 this->first_non_payload_grf
= 0;
2687 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2689 this->current_annotation
= NULL
;
2690 this->base_ir
= NULL
;
2692 this->virtual_grf_sizes
= NULL
;
2693 this->virtual_grf_count
= 0;
2694 this->virtual_grf_array_size
= 0;
2695 this->virtual_grf_start
= NULL
;
2696 this->virtual_grf_end
= NULL
;
2697 this->live_intervals
= NULL
;
2699 this->params_remap
= NULL
;
2700 this->nr_params_remap
= 0;
2702 this->force_uncompressed_stack
= 0;
2703 this->force_sechalf_stack
= 0;
2705 memset(&this->param_size
, 0, sizeof(this->param_size
));
2708 fs_visitor::~fs_visitor()
2710 ralloc_free(this->mem_ctx
);
2711 hash_table_dtor(this->variable_ht
);