2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_optimization.h"
51 #include "glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (ir
->mode
== ir_var_in
) {
62 if (!strcmp(ir
->name
, "gl_FragCoord")) {
63 reg
= emit_fragcoord_interpolation(ir
);
64 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
65 reg
= emit_frontfacing_interpolation(ir
);
67 reg
= emit_general_interpolation(ir
);
70 hash_table_insert(this->variable_ht
, reg
, ir
);
72 } else if (ir
->mode
== ir_var_out
) {
73 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
76 assert(ir
->location
== FRAG_RESULT_DATA0
);
77 assert(ir
->index
== 1);
78 this->dual_src_output
= *reg
;
79 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
80 /* Writing gl_FragColor outputs to all color regions. */
81 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
82 this->outputs
[i
] = *reg
;
83 this->output_components
[i
] = 4;
85 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
86 this->frag_depth
= *reg
;
88 /* gl_FragData or a user-defined FS output */
89 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
90 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
93 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
94 : ir
->type
->vector_elements
;
96 /* General color output. */
97 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
98 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
99 this->outputs
[output
] = *reg
;
100 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
101 this->output_components
[output
] = vector_elements
;
104 } else if (ir
->mode
== ir_var_uniform
) {
105 int param_index
= c
->prog_data
.nr_params
;
107 /* Thanks to the lower_ubo_reference pass, we will see only
108 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
109 * variables, so no need for them to be in variable_ht.
111 if (ir
->uniform_block
!= -1)
114 if (c
->dispatch_width
== 16) {
115 if (!variable_storage(ir
)) {
116 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
->location
, ir
->type
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
167 ir
->array
->accept(this);
168 index
= ir
->array_index
->as_constant();
170 element_size
= type_size(ir
->type
);
171 this->result
.type
= brw_type_for_base_type(ir
->type
);
174 assert(this->result
.file
== UNIFORM
|| this->result
.file
== GRF
);
175 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
177 assert(!"FINISHME: non-constant array element");
182 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
183 fs_reg src0
, fs_reg src1
)
187 if (intel
->gen
>= 6) {
188 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
189 inst
->conditional_mod
= conditionalmod
;
191 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, src0
, src1
);
192 inst
->conditional_mod
= conditionalmod
;
194 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
195 inst
->predicated
= true;
199 /* Instruction selection: Produce a MOV.sat instead of
200 * MIN(MAX(val, 0), 1) when possible.
203 fs_visitor::try_emit_saturate(ir_expression
*ir
)
205 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
210 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
212 sat_val
->accept(this);
213 fs_reg src
= this->result
;
215 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
217 /* If the last instruction from our accept() didn't generate our
218 * src, generate a saturated MOV
220 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
221 if (!modify
|| modify
->regs_written() != 1) {
222 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
223 inst
->saturate
= true;
225 modify
->saturate
= true;
234 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
236 /* 3-src instructions were introduced in gen6. */
240 /* MAD can only handle floating-point data. */
241 if (ir
->type
!= glsl_type::float_type
)
244 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
245 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
247 if (!mul
|| mul
->operation
!= ir_binop_mul
)
250 if (nonmul
->as_constant() ||
251 mul
->operands
[0]->as_constant() ||
252 mul
->operands
[1]->as_constant())
255 nonmul
->accept(this);
256 fs_reg src0
= this->result
;
258 mul
->operands
[0]->accept(this);
259 fs_reg src1
= this->result
;
261 mul
->operands
[1]->accept(this);
262 fs_reg src2
= this->result
;
264 this->result
= fs_reg(this, ir
->type
);
265 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
271 fs_visitor::visit(ir_expression
*ir
)
273 unsigned int operand
;
277 assert(ir
->get_num_operands() <= 2);
279 if (try_emit_saturate(ir
))
281 if (ir
->operation
== ir_binop_add
) {
282 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
286 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
287 ir
->operands
[operand
]->accept(this);
288 if (this->result
.file
== BAD_FILE
) {
290 fail("Failed to get tree for expression operand:\n");
291 ir
->operands
[operand
]->accept(&v
);
293 op
[operand
] = this->result
;
295 /* Matrix expression operands should have been broken down to vector
296 * operations already.
298 assert(!ir
->operands
[operand
]->type
->is_matrix());
299 /* And then those vector operands should have been broken down to scalar.
301 assert(!ir
->operands
[operand
]->type
->is_vector());
304 /* Storage for our result. If our result goes into an assignment, it will
305 * just get copy-propagated out, so no worries.
307 this->result
= fs_reg(this, ir
->type
);
309 switch (ir
->operation
) {
310 case ir_unop_logic_not
:
311 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
312 * ones complement of the whole register, not just bit 0.
314 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
317 op
[0].negate
= !op
[0].negate
;
318 this->result
= op
[0];
322 op
[0].negate
= false;
323 this->result
= op
[0];
326 temp
= fs_reg(this, ir
->type
);
328 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
330 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
331 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
332 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
333 inst
->predicated
= true;
335 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
336 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
337 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
338 inst
->predicated
= true;
342 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
346 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
349 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
353 assert(!"not reached: should be handled by ir_explog_to_explog2");
356 case ir_unop_sin_reduced
:
357 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
360 case ir_unop_cos_reduced
:
361 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
365 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
368 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
372 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
375 assert(!"not reached: should be handled by ir_sub_to_add_neg");
379 if (ir
->type
->is_integer()) {
380 /* For integer multiplication, the MUL uses the low 16 bits
381 * of one of the operands (src0 on gen6, src1 on gen7). The
382 * MACH accumulates in the contribution of the upper 16 bits
385 * FINISHME: Emit just the MUL if we know an operand is small
388 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
389 fail("16-wide explicit accumulator operands unsupported\n");
391 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
393 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
394 emit(BRW_OPCODE_MACH
, reg_null_d
, op
[0], op
[1]);
395 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(acc
));
397 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
401 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
402 fail("16-wide INTDIV unsupported\n");
404 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
405 assert(ir
->type
->is_integer());
406 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
409 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
410 fail("16-wide INTDIV unsupported\n");
412 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
413 assert(ir
->type
->is_integer());
414 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
418 case ir_binop_greater
:
419 case ir_binop_lequal
:
420 case ir_binop_gequal
:
422 case ir_binop_all_equal
:
423 case ir_binop_nequal
:
424 case ir_binop_any_nequal
:
426 /* original gen4 does implicit conversion before comparison. */
428 temp
.type
= op
[0].type
;
430 resolve_ud_negate(&op
[0]);
431 resolve_ud_negate(&op
[1]);
433 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
434 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
436 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
437 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
440 case ir_binop_logic_xor
:
441 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
444 case ir_binop_logic_or
:
445 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
448 case ir_binop_logic_and
:
449 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
454 assert(!"not reached: should be handled by brw_fs_channel_expressions");
458 assert(!"not reached: should be handled by lower_noise");
461 case ir_quadop_vector
:
462 assert(!"not reached: should be handled by lower_quadop_vector");
466 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
470 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
473 case ir_unop_bitcast_i2f
:
474 case ir_unop_bitcast_u2f
:
475 op
[0].type
= BRW_REGISTER_TYPE_F
;
476 this->result
= op
[0];
479 case ir_unop_bitcast_f2u
:
480 op
[0].type
= BRW_REGISTER_TYPE_UD
;
481 this->result
= op
[0];
484 case ir_unop_bitcast_f2i
:
485 op
[0].type
= BRW_REGISTER_TYPE_D
;
486 this->result
= op
[0];
492 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
496 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], fs_reg(1));
499 temp
= fs_reg(this, glsl_type::int_type
);
500 emit(BRW_OPCODE_AND
, temp
, op
[0], fs_reg(1));
501 emit(BRW_OPCODE_MOV
, this->result
, temp
);
505 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
));
506 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
507 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
510 assert(op
[0].type
== BRW_REGISTER_TYPE_D
);
512 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0));
513 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
514 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
518 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
521 op
[0].negate
= !op
[0].negate
;
522 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
523 this->result
.negate
= true;
526 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
529 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
531 case ir_unop_round_even
:
532 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
537 resolve_ud_negate(&op
[0]);
538 resolve_ud_negate(&op
[1]);
539 emit_minmax(ir
->operation
== ir_binop_min
?
540 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
541 this->result
, op
[0], op
[1]);
545 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
548 case ir_unop_bit_not
:
549 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
551 case ir_binop_bit_and
:
552 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
554 case ir_binop_bit_xor
:
555 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
557 case ir_binop_bit_or
:
558 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
561 case ir_binop_lshift
:
562 inst
= emit(BRW_OPCODE_SHL
, this->result
, op
[0], op
[1]);
565 case ir_binop_rshift
:
566 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
567 inst
= emit(BRW_OPCODE_ASR
, this->result
, op
[0], op
[1]);
569 inst
= emit(BRW_OPCODE_SHR
, this->result
, op
[0], op
[1]);
572 case ir_binop_ubo_load
:
573 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
574 ir_constant
*offset
= ir
->operands
[1]->as_constant();
576 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
577 packed_consts
.type
= result
.type
;
578 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
579 fs_inst
*pull
= emit(fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
582 fs_reg(offset
->value
.u
[0])));
586 packed_consts
.smear
= offset
->value
.u
[0] % 16 / 4;
587 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
588 /* UBO bools are any nonzero value. We consider bools to be
589 * values with the low bit set to 1. Convert them using CMP.
591 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
592 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, result
,
593 packed_consts
, fs_reg(0u)));
594 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
596 emit(fs_inst(BRW_OPCODE_MOV
, result
, packed_consts
));
599 packed_consts
.smear
++;
602 /* The std140 packing rules don't allow vectors to cross 16-byte
603 * boundaries, and a reg is 32 bytes.
605 assert(packed_consts
.smear
< 8);
607 result
.reg_offset
= 0;
613 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
614 const glsl_type
*type
, bool predicated
)
616 switch (type
->base_type
) {
617 case GLSL_TYPE_FLOAT
:
621 for (unsigned int i
= 0; i
< type
->components(); i
++) {
622 l
.type
= brw_type_for_base_type(type
);
623 r
.type
= brw_type_for_base_type(type
);
625 if (predicated
|| !l
.equals(r
)) {
626 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
627 inst
->predicated
= predicated
;
634 case GLSL_TYPE_ARRAY
:
635 for (unsigned int i
= 0; i
< type
->length
; i
++) {
636 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
640 case GLSL_TYPE_STRUCT
:
641 for (unsigned int i
= 0; i
< type
->length
; i
++) {
642 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
647 case GLSL_TYPE_SAMPLER
:
651 assert(!"not reached");
656 /* If the RHS processing resulted in an instruction generating a
657 * temporary value, and it would be easy to rewrite the instruction to
658 * generate its result right into the LHS instead, do so. This ends
659 * up reliably removing instructions where it can be tricky to do so
660 * later without real UD chain information.
663 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
666 fs_inst
*pre_rhs_inst
,
667 fs_inst
*last_rhs_inst
)
669 /* Only attempt if we're doing a direct assignment. */
671 !(ir
->lhs
->type
->is_scalar() ||
672 (ir
->lhs
->type
->is_vector() &&
673 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
676 /* Make sure the last instruction generated our source reg. */
677 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
683 /* If last_rhs_inst wrote a different number of components than our LHS,
684 * we can't safely rewrite it.
686 if (ir
->lhs
->type
->vector_elements
!= modify
->regs_written())
689 /* Success! Rewrite the instruction. */
696 fs_visitor::visit(ir_assignment
*ir
)
701 /* FINISHME: arrays on the lhs */
702 ir
->lhs
->accept(this);
705 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
707 ir
->rhs
->accept(this);
710 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
712 assert(l
.file
!= BAD_FILE
);
713 assert(r
.file
!= BAD_FILE
);
715 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
719 emit_bool_to_cond_code(ir
->condition
);
722 if (ir
->lhs
->type
->is_scalar() ||
723 ir
->lhs
->type
->is_vector()) {
724 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
725 if (ir
->write_mask
& (1 << i
)) {
726 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
728 inst
->predicated
= true;
734 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
739 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
740 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
750 if (ir
->shadow_comparitor
) {
751 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
752 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
753 coordinate
.reg_offset
++;
755 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
758 if (ir
->op
== ir_tex
) {
759 /* There's no plain shadow compare message, so we use shadow
760 * compare with a bias of 0.0.
762 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
764 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
765 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
768 assert(!"Should not get here.");
771 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
773 } else if (ir
->op
== ir_tex
) {
774 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
775 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
776 coordinate
.reg_offset
++;
778 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
780 } else if (ir
->op
== ir_txd
) {
783 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
784 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
785 coordinate
.reg_offset
++;
787 /* the slots for u and v are always present, but r is optional */
788 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
791 * dPdx = dudx, dvdx, drdx
792 * dPdy = dudy, dvdy, drdy
794 * 1-arg: Does not exist.
796 * 2-arg: dudx dvdx dudy dvdy
797 * dPdx.x dPdx.y dPdy.x dPdy.y
800 * 3-arg: dudx dvdx drdx dudy dvdy drdy
801 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
804 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
805 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
808 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
810 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
811 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
814 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
815 } else if (ir
->op
== ir_txs
) {
816 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
818 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
821 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
822 * instructions. We'll need to do SIMD16 here.
825 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
827 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
828 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
830 coordinate
.reg_offset
++;
833 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
834 * be necessary for TXF (ld), but seems wise to do for all messages.
836 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
837 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
840 /* lod/bias appears after u/v/r. */
843 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
);
846 /* The unused upper half. */
851 /* Now, since we're doing simd16, the return is 2 interleaved
852 * vec4s where the odd-indexed ones are junk. We'll need to move
853 * this weirdness around to the expected layout.
856 const glsl_type
*vec_type
=
857 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
858 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
859 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
860 : BRW_REGISTER_TYPE_F
;
863 fs_inst
*inst
= NULL
;
866 inst
= emit(SHADER_OPCODE_TEX
, dst
);
869 inst
= emit(FS_OPCODE_TXB
, dst
);
872 inst
= emit(SHADER_OPCODE_TXL
, dst
);
875 inst
= emit(SHADER_OPCODE_TXD
, dst
);
878 inst
= emit(SHADER_OPCODE_TXS
, dst
);
881 inst
= emit(SHADER_OPCODE_TXF
, dst
);
884 inst
->base_mrf
= base_mrf
;
886 inst
->header_present
= true;
889 for (int i
= 0; i
< 4; i
++) {
890 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
891 orig_dst
.reg_offset
++;
899 /* gen5's sampler has slots for u, v, r, array index, then optional
900 * parameters like shadow comparitor or LOD bias. If optional
901 * parameters aren't present, those base slots are optional and don't
902 * need to be included in the message.
904 * We don't fill in the unnecessary slots regardless, which may look
905 * surprising in the disassembly.
908 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
909 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
913 int reg_width
= c
->dispatch_width
/ 8;
914 bool header_present
= false;
915 const int vector_elements
=
916 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
918 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
919 /* It appears that the ld instruction used for txf does its
920 * address bounds check before adding in the offset. To work
921 * around this, just add the integer offset to the integer texel
922 * coordinate, and don't put the offset in the header.
924 ir_constant
*offset
= ir
->offset
->as_constant();
925 for (int i
= 0; i
< vector_elements
; i
++) {
927 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
930 coordinate
.reg_offset
++;
934 /* The offsets set up by the ir_texture visitor are in the
935 * m1 header, so we can't go headerless.
937 header_present
= true;
942 for (int i
= 0; i
< vector_elements
; i
++) {
944 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
946 coordinate
.reg_offset
++;
949 mlen
+= vector_elements
* reg_width
;
951 if (ir
->shadow_comparitor
) {
952 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
954 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
958 fs_inst
*inst
= NULL
;
961 inst
= emit(SHADER_OPCODE_TEX
, dst
);
964 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
965 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
968 inst
= emit(FS_OPCODE_TXB
, dst
);
971 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
972 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
975 inst
= emit(SHADER_OPCODE_TXL
, dst
);
978 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
982 * dPdx = dudx, dvdx, drdx
983 * dPdy = dudy, dvdy, drdy
985 * Load up these values:
986 * - dudx dudy dvdx dvdy drdx drdy
987 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
989 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
990 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
994 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod2
);
999 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1003 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
1005 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1008 mlen
= header_present
+ 4 * reg_width
;
1010 emit(BRW_OPCODE_MOV
,
1011 fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
1013 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1016 inst
->base_mrf
= base_mrf
;
1018 inst
->header_present
= header_present
;
1021 fail("Message length >11 disallowed by hardware\n");
1028 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1029 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
1033 int reg_width
= c
->dispatch_width
/ 8;
1034 bool header_present
= false;
1037 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1038 /* The offsets set up by the ir_texture visitor are in the
1039 * m1 header, so we can't go headerless.
1041 header_present
= true;
1046 if (ir
->shadow_comparitor
) {
1047 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
1051 /* Set up the LOD info */
1056 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
1060 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
1064 if (c
->dispatch_width
== 16)
1065 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1067 /* Load dPdx and the coordinate together:
1068 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1070 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1071 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
);
1072 coordinate
.reg_offset
++;
1075 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod
);
1079 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), lod2
);
1086 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
1090 /* It appears that the ld instruction used for txf does its
1091 * address bounds check before adding in the offset. To work
1092 * around this, just add the integer offset to the integer texel
1093 * coordinate, and don't put the offset in the header.
1096 ir_constant
*offset
= ir
->offset
->as_constant();
1097 offsets
[0] = offset
->value
.i
[0];
1098 offsets
[1] = offset
->value
.i
[1];
1099 offsets
[2] = offset
->value
.i
[2];
1101 memset(offsets
, 0, sizeof(offsets
));
1104 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1105 emit(BRW_OPCODE_ADD
,
1106 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
, offsets
[0]);
1107 coordinate
.reg_offset
++;
1110 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
);
1113 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1114 emit(BRW_OPCODE_ADD
,
1115 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
, offsets
[i
]);
1116 coordinate
.reg_offset
++;
1122 /* Set up the coordinate (except for cases where it was done above) */
1123 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1124 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1125 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
);
1126 coordinate
.reg_offset
++;
1131 /* Generate the SEND */
1132 fs_inst
*inst
= NULL
;
1134 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1135 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1136 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1137 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1138 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1139 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1141 inst
->base_mrf
= base_mrf
;
1143 inst
->header_present
= header_present
;
1146 fail("Message length >11 disallowed by hardware\n");
1153 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1154 bool is_rect
, int sampler
, int texunit
)
1156 fs_inst
*inst
= NULL
;
1157 bool needs_gl_clamp
= true;
1158 fs_reg scale_x
, scale_y
;
1160 /* The 965 requires the EU to do the normalization of GL rectangle
1161 * texture coordinates. We use the program parameter state
1162 * tracking to get the scaling factor.
1166 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1167 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1168 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1169 int tokens
[STATE_LENGTH
] = {
1171 STATE_TEXRECT_SCALE
,
1177 if (c
->dispatch_width
== 16) {
1178 fail("rectangle scale uniform setup not supported on 16-wide\n");
1179 return fs_reg(this, ir
->type
);
1182 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1183 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1185 GLuint index
= _mesa_add_state_reference(params
,
1186 (gl_state_index
*)tokens
);
1188 this->param_index
[c
->prog_data
.nr_params
] = index
;
1189 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1190 c
->prog_data
.nr_params
++;
1191 this->param_index
[c
->prog_data
.nr_params
] = index
;
1192 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1193 c
->prog_data
.nr_params
++;
1196 /* The 965 requires the EU to do the normalization of GL rectangle
1197 * texture coordinates. We use the program parameter state
1198 * tracking to get the scaling factor.
1200 if (intel
->gen
< 6 && is_rect
) {
1201 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1202 fs_reg src
= coordinate
;
1205 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1208 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1209 } else if (is_rect
) {
1210 /* On gen6+, the sampler handles the rectangle coordinates
1211 * natively, without needing rescaling. But that means we have
1212 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1213 * not [0, 1] like the default case below.
1215 needs_gl_clamp
= false;
1217 for (int i
= 0; i
< 2; i
++) {
1218 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1219 fs_reg chan
= coordinate
;
1220 chan
.reg_offset
+= i
;
1222 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1223 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1225 /* Our parameter comes in as 1.0/width or 1.0/height,
1226 * because that's what people normally want for doing
1227 * texture rectangle handling. We need width or height
1228 * for clamping, but we don't care enough to make a new
1229 * parameter type, so just invert back.
1231 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1232 emit(BRW_OPCODE_MOV
, limit
, i
== 0 ? scale_x
: scale_y
);
1233 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1235 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1236 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1241 if (ir
->coordinate
&& needs_gl_clamp
) {
1242 for (unsigned int i
= 0;
1243 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1244 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1245 fs_reg chan
= coordinate
;
1246 chan
.reg_offset
+= i
;
1248 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, chan
, chan
);
1249 inst
->saturate
= true;
1257 fs_visitor::visit(ir_texture
*ir
)
1259 fs_inst
*inst
= NULL
;
1261 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1262 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1264 /* Should be lowered by do_lower_texture_projection */
1265 assert(!ir
->projector
);
1267 /* Generate code to compute all the subexpression trees. This has to be
1268 * done before loading any values into MRFs for the sampler message since
1269 * generating these values may involve SEND messages that need the MRFs.
1272 if (ir
->coordinate
) {
1273 ir
->coordinate
->accept(this);
1275 coordinate
= rescale_texcoord(ir
, this->result
,
1276 ir
->sampler
->type
->sampler_dimensionality
==
1277 GLSL_SAMPLER_DIM_RECT
,
1281 fs_reg shadow_comparitor
;
1282 if (ir
->shadow_comparitor
) {
1283 ir
->shadow_comparitor
->accept(this);
1284 shadow_comparitor
= this->result
;
1292 ir
->lod_info
.bias
->accept(this);
1296 ir
->lod_info
.grad
.dPdx
->accept(this);
1299 ir
->lod_info
.grad
.dPdy
->accept(this);
1300 lod2
= this->result
;
1305 ir
->lod_info
.lod
->accept(this);
1310 /* Writemasking doesn't eliminate channels on SIMD8 texture
1311 * samples, so don't worry about them.
1313 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1315 if (intel
->gen
>= 7) {
1316 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1318 } else if (intel
->gen
>= 5) {
1319 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1322 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1326 /* The header is set up by generate_tex() when necessary. */
1327 inst
->src
[0] = reg_undef
;
1329 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1330 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1332 inst
->sampler
= sampler
;
1334 if (ir
->shadow_comparitor
)
1335 inst
->shadow_compare
= true;
1337 swizzle_result(ir
, dst
, sampler
);
1341 * Swizzle the result of a texture result. This is necessary for
1342 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1345 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1347 this->result
= orig_val
;
1349 if (ir
->op
== ir_txs
)
1352 if (ir
->type
== glsl_type::float_type
) {
1353 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1354 assert(ir
->sampler
->type
->sampler_shadow
);
1355 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1356 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1358 for (int i
= 0; i
< 4; i
++) {
1359 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1360 fs_reg l
= swizzled_result
;
1363 if (swiz
== SWIZZLE_ZERO
) {
1364 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1365 } else if (swiz
== SWIZZLE_ONE
) {
1366 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1368 fs_reg r
= orig_val
;
1369 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1370 emit(BRW_OPCODE_MOV
, l
, r
);
1373 this->result
= swizzled_result
;
1378 fs_visitor::visit(ir_swizzle
*ir
)
1380 ir
->val
->accept(this);
1381 fs_reg val
= this->result
;
1383 if (ir
->type
->vector_elements
== 1) {
1384 this->result
.reg_offset
+= ir
->mask
.x
;
1388 fs_reg result
= fs_reg(this, ir
->type
);
1389 this->result
= result
;
1391 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1392 fs_reg channel
= val
;
1410 channel
.reg_offset
+= swiz
;
1411 emit(BRW_OPCODE_MOV
, result
, channel
);
1412 result
.reg_offset
++;
1417 fs_visitor::visit(ir_discard
*ir
)
1419 assert(ir
->condition
== NULL
); /* FINISHME */
1421 emit(FS_OPCODE_DISCARD
);
1425 fs_visitor::visit(ir_constant
*ir
)
1427 /* Set this->result to reg at the bottom of the function because some code
1428 * paths will cause this visitor to be applied to other fields. This will
1429 * cause the value stored in this->result to be modified.
1431 * Make reg constant so that it doesn't get accidentally modified along the
1432 * way. Yes, I actually had this problem. :(
1434 const fs_reg
reg(this, ir
->type
);
1435 fs_reg dst_reg
= reg
;
1437 if (ir
->type
->is_array()) {
1438 const unsigned size
= type_size(ir
->type
->fields
.array
);
1440 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1441 ir
->array_elements
[i
]->accept(this);
1442 fs_reg src_reg
= this->result
;
1444 dst_reg
.type
= src_reg
.type
;
1445 for (unsigned j
= 0; j
< size
; j
++) {
1446 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1447 src_reg
.reg_offset
++;
1448 dst_reg
.reg_offset
++;
1451 } else if (ir
->type
->is_record()) {
1452 foreach_list(node
, &ir
->components
) {
1453 ir_constant
*const field
= (ir_constant
*) node
;
1454 const unsigned size
= type_size(field
->type
);
1456 field
->accept(this);
1457 fs_reg src_reg
= this->result
;
1459 dst_reg
.type
= src_reg
.type
;
1460 for (unsigned j
= 0; j
< size
; j
++) {
1461 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1462 src_reg
.reg_offset
++;
1463 dst_reg
.reg_offset
++;
1467 const unsigned size
= type_size(ir
->type
);
1469 for (unsigned i
= 0; i
< size
; i
++) {
1470 switch (ir
->type
->base_type
) {
1471 case GLSL_TYPE_FLOAT
:
1472 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1474 case GLSL_TYPE_UINT
:
1475 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1478 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1480 case GLSL_TYPE_BOOL
:
1481 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1484 assert(!"Non-float/uint/int/bool constant");
1486 dst_reg
.reg_offset
++;
1494 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1496 ir_expression
*expr
= ir
->as_expression();
1502 assert(expr
->get_num_operands() <= 2);
1503 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1504 assert(expr
->operands
[i
]->type
->is_scalar());
1506 expr
->operands
[i
]->accept(this);
1507 op
[i
] = this->result
;
1509 resolve_ud_negate(&op
[i
]);
1512 switch (expr
->operation
) {
1513 case ir_unop_logic_not
:
1514 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1515 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1518 case ir_binop_logic_xor
:
1519 case ir_binop_logic_or
:
1520 case ir_binop_logic_and
:
1524 if (intel
->gen
>= 6) {
1525 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1527 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1529 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 if (intel
->gen
>= 6) {
1534 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1536 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1538 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1541 case ir_binop_greater
:
1542 case ir_binop_gequal
:
1544 case ir_binop_lequal
:
1545 case ir_binop_equal
:
1546 case ir_binop_all_equal
:
1547 case ir_binop_nequal
:
1548 case ir_binop_any_nequal
:
1549 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1550 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1552 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1553 inst
->conditional_mod
=
1554 brw_conditional_for_comparison(expr
->operation
);
1558 assert(!"not reached");
1559 fail("bad cond code\n");
1568 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1569 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1573 * Emit a gen6 IF statement with the comparison folded into the IF
1577 fs_visitor::emit_if_gen6(ir_if
*ir
)
1579 ir_expression
*expr
= ir
->condition
->as_expression();
1586 assert(expr
->get_num_operands() <= 2);
1587 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1588 assert(expr
->operands
[i
]->type
->is_scalar());
1590 expr
->operands
[i
]->accept(this);
1591 op
[i
] = this->result
;
1594 switch (expr
->operation
) {
1595 case ir_unop_logic_not
:
1596 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1597 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1600 case ir_binop_logic_xor
:
1601 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1605 case ir_binop_logic_or
:
1606 temp
= fs_reg(this, glsl_type::bool_type
);
1607 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1608 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1609 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1612 case ir_binop_logic_and
:
1613 temp
= fs_reg(this, glsl_type::bool_type
);
1614 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1615 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1616 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1620 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1621 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1625 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1626 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1629 case ir_binop_greater
:
1630 case ir_binop_gequal
:
1632 case ir_binop_lequal
:
1633 case ir_binop_equal
:
1634 case ir_binop_all_equal
:
1635 case ir_binop_nequal
:
1636 case ir_binop_any_nequal
:
1637 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1638 inst
->conditional_mod
=
1639 brw_conditional_for_comparison(expr
->operation
);
1642 assert(!"not reached");
1643 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1644 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1645 fail("bad condition\n");
1651 ir
->condition
->accept(this);
1653 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1654 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1658 fs_visitor::visit(ir_if
*ir
)
1662 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1663 fail("Can't support (non-uniform) control flow on 16-wide\n");
1666 /* Don't point the annotation at the if statement, because then it plus
1667 * the then and else blocks get printed.
1669 this->base_ir
= ir
->condition
;
1671 if (intel
->gen
== 6) {
1674 emit_bool_to_cond_code(ir
->condition
);
1676 inst
= emit(BRW_OPCODE_IF
);
1677 inst
->predicated
= true;
1680 foreach_list(node
, &ir
->then_instructions
) {
1681 ir_instruction
*ir
= (ir_instruction
*)node
;
1687 if (!ir
->else_instructions
.is_empty()) {
1688 emit(BRW_OPCODE_ELSE
);
1690 foreach_list(node
, &ir
->else_instructions
) {
1691 ir_instruction
*ir
= (ir_instruction
*)node
;
1698 emit(BRW_OPCODE_ENDIF
);
1702 fs_visitor::visit(ir_loop
*ir
)
1704 fs_reg counter
= reg_undef
;
1706 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1707 fail("Can't support (non-uniform) control flow on 16-wide\n");
1711 this->base_ir
= ir
->counter
;
1712 ir
->counter
->accept(this);
1713 counter
= *(variable_storage(ir
->counter
));
1716 this->base_ir
= ir
->from
;
1717 ir
->from
->accept(this);
1719 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1723 this->base_ir
= NULL
;
1724 emit(BRW_OPCODE_DO
);
1727 this->base_ir
= ir
->to
;
1728 ir
->to
->accept(this);
1730 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1731 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1733 inst
= emit(BRW_OPCODE_BREAK
);
1734 inst
->predicated
= true;
1737 foreach_list(node
, &ir
->body_instructions
) {
1738 ir_instruction
*ir
= (ir_instruction
*)node
;
1744 if (ir
->increment
) {
1745 this->base_ir
= ir
->increment
;
1746 ir
->increment
->accept(this);
1747 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1750 this->base_ir
= NULL
;
1751 emit(BRW_OPCODE_WHILE
);
1755 fs_visitor::visit(ir_loop_jump
*ir
)
1758 case ir_loop_jump::jump_break
:
1759 emit(BRW_OPCODE_BREAK
);
1761 case ir_loop_jump::jump_continue
:
1762 emit(BRW_OPCODE_CONTINUE
);
1768 fs_visitor::visit(ir_call
*ir
)
1770 assert(!"FINISHME");
1774 fs_visitor::visit(ir_return
*ir
)
1776 assert(!"FINISHME");
1780 fs_visitor::visit(ir_function
*ir
)
1782 /* Ignore function bodies other than main() -- we shouldn't see calls to
1783 * them since they should all be inlined before we get to ir_to_mesa.
1785 if (strcmp(ir
->name
, "main") == 0) {
1786 const ir_function_signature
*sig
;
1789 sig
= ir
->matching_signature(&empty
);
1793 foreach_list(node
, &sig
->body
) {
1794 ir_instruction
*ir
= (ir_instruction
*)node
;
1803 fs_visitor::visit(ir_function_signature
*ir
)
1805 assert(!"not reached");
1810 fs_visitor::emit(fs_inst inst
)
1812 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1815 if (force_uncompressed_stack
> 0)
1816 list_inst
->force_uncompressed
= true;
1817 else if (force_sechalf_stack
> 0)
1818 list_inst
->force_sechalf
= true;
1820 list_inst
->annotation
= this->current_annotation
;
1821 list_inst
->ir
= this->base_ir
;
1823 this->instructions
.push_tail(list_inst
);
1828 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1830 fs_visitor::emit_dummy_fs()
1832 int reg_width
= c
->dispatch_width
/ 8;
1834 /* Everyone's favorite color. */
1835 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
));
1836 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
));
1837 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
));
1838 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
));
1841 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1842 write
->base_mrf
= 2;
1843 write
->mlen
= 4 * reg_width
;
1847 /* The register location here is relative to the start of the URB
1848 * data. It will get adjusted to be a real location before
1849 * generate_code() time.
1852 fs_visitor::interp_reg(int location
, int channel
)
1854 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1855 int stride
= (channel
& 1) * 4;
1857 assert(urb_setup
[location
] != -1);
1859 return brw_vec1_grf(regnr
, stride
);
1862 /** Emits the interpolation for the varying inputs. */
1864 fs_visitor::emit_interpolation_setup_gen4()
1866 this->current_annotation
= "compute pixel centers";
1867 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1868 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1869 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1870 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1872 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1873 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1875 this->current_annotation
= "compute pixel deltas from v0";
1877 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1878 fs_reg(this, glsl_type::vec2_type
);
1879 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1880 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1881 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1883 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1884 fs_reg(this, glsl_type::float_type
);
1885 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1886 fs_reg(this, glsl_type::float_type
);
1888 emit(BRW_OPCODE_ADD
, this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1889 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1890 emit(BRW_OPCODE_ADD
, this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1891 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1893 this->current_annotation
= "compute pos.w and 1/pos.w";
1894 /* Compute wpos.w. It's always in our setup, since it's needed to
1895 * interpolate the other attributes.
1897 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1898 emit(FS_OPCODE_LINTERP
, wpos_w
,
1899 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1900 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1901 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1902 /* Compute the pixel 1/W value from wpos.w. */
1903 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1904 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1905 this->current_annotation
= NULL
;
1908 /** Emits the interpolation for the varying inputs. */
1910 fs_visitor::emit_interpolation_setup_gen6()
1912 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1914 /* If the pixel centers end up used, the setup is the same as for gen4. */
1915 this->current_annotation
= "compute pixel centers";
1916 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1917 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1918 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1919 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1920 emit(BRW_OPCODE_ADD
,
1922 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1923 fs_reg(brw_imm_v(0x10101010)));
1924 emit(BRW_OPCODE_ADD
,
1926 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1927 fs_reg(brw_imm_v(0x11001100)));
1929 /* As of gen6, we can no longer mix float and int sources. We have
1930 * to turn the integer pixel centers into floats for their actual
1933 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1934 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1935 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1936 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1938 this->current_annotation
= "compute pos.w";
1939 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1940 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1941 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1943 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1944 uint8_t reg
= c
->barycentric_coord_reg
[i
];
1945 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
1946 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
1949 this->current_annotation
= NULL
;
1953 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
1955 int reg_width
= c
->dispatch_width
/ 8;
1957 fs_reg color
= outputs
[target
];
1960 /* If there's no color data to be written, skip it. */
1961 if (color
.file
== BAD_FILE
)
1964 color
.reg_offset
+= index
;
1966 if (c
->dispatch_width
== 8 || intel
->gen
>= 6) {
1967 /* SIMD8 write looks like:
1973 * gen6 SIMD16 DP write looks like:
1983 inst
= emit(BRW_OPCODE_MOV
,
1984 fs_reg(MRF
, first_color_mrf
+ index
* reg_width
, color
.type
),
1986 inst
->saturate
= c
->key
.clamp_fragment_color
;
1988 /* pre-gen6 SIMD16 single source DP write looks like:
1998 if (brw
->has_compr4
) {
1999 /* By setting the high bit of the MRF register number, we
2000 * indicate that we want COMPR4 mode - instead of doing the
2001 * usual destination + 1 for the second half we get
2004 inst
= emit(BRW_OPCODE_MOV
,
2005 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2008 inst
->saturate
= c
->key
.clamp_fragment_color
;
2010 push_force_uncompressed();
2011 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
,
2014 inst
->saturate
= c
->key
.clamp_fragment_color
;
2015 pop_force_uncompressed();
2017 push_force_sechalf();
2018 color
.sechalf
= true;
2019 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4,
2022 inst
->saturate
= c
->key
.clamp_fragment_color
;
2023 pop_force_sechalf();
2024 color
.sechalf
= false;
2030 fs_visitor::emit_fb_writes()
2032 this->current_annotation
= "FB write header";
2033 bool header_present
= true;
2034 /* We can potentially have a message length of up to 15, so we have to set
2035 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2039 int reg_width
= c
->dispatch_width
/ 8;
2040 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2041 bool src0_alpha_to_render_target
= false;
2043 if (c
->dispatch_width
== 16 && do_dual_src
) {
2044 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2045 do_dual_src
= false;
2048 /* From the Sandy Bridge PRM, volume 4, page 198:
2050 * "Dispatched Pixel Enables. One bit per pixel indicating
2051 * which pixels were originally enabled when the thread was
2052 * dispatched. This field is only required for the end-of-
2053 * thread message and on all dual-source messages."
2055 if (intel
->gen
>= 6 &&
2056 !this->fp
->UsesKill
&&
2058 c
->key
.nr_color_regions
== 1) {
2059 header_present
= false;
2062 if (header_present
) {
2063 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2065 c
->key
.nr_color_regions
> 1 &&
2066 c
->key
.sample_alpha_to_coverage
;
2071 if (c
->aa_dest_stencil_reg
) {
2072 push_force_uncompressed();
2073 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2074 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
2075 pop_force_uncompressed();
2078 /* Reserve space for color. It'll be filled in per MRT below. */
2080 nr
+= 4 * reg_width
;
2083 if (src0_alpha_to_render_target
)
2086 if (c
->source_depth_to_render_target
) {
2087 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
2088 /* For outputting oDepth on gen6, SIMD8 writes have to be
2089 * used. This would require 8-wide moves of each half to
2090 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2091 * Just bail on doing so for now.
2093 fail("Missing support for simd16 depth writes on gen6\n");
2096 if (c
->computes_depth
) {
2097 /* Hand over gl_FragDepth. */
2098 assert(this->frag_depth
.file
!= BAD_FILE
);
2099 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), this->frag_depth
);
2101 /* Pass through the payload depth. */
2102 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2103 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
2108 if (c
->dest_depth_reg
) {
2109 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2110 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
2115 fs_reg src0
= this->outputs
[0];
2116 fs_reg src1
= this->dual_src_output
;
2118 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2120 for (int i
= 0; i
< 4; i
++) {
2121 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
2122 fs_reg(MRF
, color_mrf
+ i
, src0
.type
),
2125 inst
->saturate
= c
->key
.clamp_fragment_color
;
2128 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2130 for (int i
= 0; i
< 4; i
++) {
2131 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
2132 fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2135 inst
->saturate
= c
->key
.clamp_fragment_color
;
2138 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2140 inst
->base_mrf
= base_mrf
;
2141 inst
->mlen
= nr
- base_mrf
;
2143 inst
->header_present
= header_present
;
2145 c
->prog_data
.dual_src_blend
= true;
2146 this->current_annotation
= NULL
;
2150 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2151 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2152 "FB write target %d",
2154 /* If src0_alpha_to_render_target is true, include source zero alpha
2155 * data in RenderTargetWrite message for targets > 0.
2157 int write_color_mrf
= color_mrf
;
2158 if (src0_alpha_to_render_target
&& target
!= 0) {
2160 fs_reg color
= outputs
[0];
2161 color
.reg_offset
+= 3;
2163 inst
= emit(BRW_OPCODE_MOV
,
2164 fs_reg(MRF
, write_color_mrf
, color
.type
),
2166 inst
->saturate
= c
->key
.clamp_fragment_color
;
2167 write_color_mrf
= color_mrf
+ reg_width
;
2170 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2171 emit_color_write(target
, i
, write_color_mrf
);
2173 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2174 inst
->target
= target
;
2175 inst
->base_mrf
= base_mrf
;
2176 if (src0_alpha_to_render_target
&& target
== 0)
2177 inst
->mlen
= nr
- base_mrf
- reg_width
;
2179 inst
->mlen
= nr
- base_mrf
;
2180 if (target
== c
->key
.nr_color_regions
- 1)
2182 inst
->header_present
= header_present
;
2185 if (c
->key
.nr_color_regions
== 0) {
2186 /* Even if there's no color buffers enabled, we still need to send
2187 * alpha out the pipeline to our null renderbuffer to support
2188 * alpha-testing, alpha-to-coverage, and so on.
2190 emit_color_write(0, 3, color_mrf
);
2192 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2193 inst
->base_mrf
= base_mrf
;
2194 inst
->mlen
= nr
- base_mrf
;
2196 inst
->header_present
= header_present
;
2199 this->current_annotation
= NULL
;
2203 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2205 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2209 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2210 emit(BRW_OPCODE_MOV
, temp
, *reg
);
2215 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2217 if (rvalue
->type
!= glsl_type::bool_type
)
2220 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2221 emit(BRW_OPCODE_AND
, temp
, *reg
, fs_reg(1));
2225 fs_visitor::fs_visitor(struct brw_wm_compile
*c
, struct gl_shader_program
*prog
,
2226 struct brw_shader
*shader
)
2231 this->fp
= &c
->fp
->program
;
2233 this->intel
= &brw
->intel
;
2234 this->ctx
= &intel
->ctx
;
2235 this->mem_ctx
= ralloc_context(NULL
);
2236 this->shader
= shader
;
2237 this->failed
= false;
2238 this->variable_ht
= hash_table_ctor(0,
2239 hash_table_pointer_hash
,
2240 hash_table_pointer_compare
);
2242 /* There's a question that appears to be left open in the spec:
2243 * How do implicit dst conversions interact with the CMP
2244 * instruction or conditional mods? On gen6, the instruction:
2246 * CMP null<d> src0<f> src1<f>
2248 * will do src1 - src0 and compare that result as if it was an
2249 * integer. On gen4, it will do src1 - src0 as float, convert
2250 * the result to int, and compare as int. In between, it
2251 * appears that it does src1 - src0 and does the compare in the
2252 * execution type so dst type doesn't matter.
2254 if (this->intel
->gen
> 4)
2255 this->reg_null_cmp
= reg_null_d
;
2257 this->reg_null_cmp
= reg_null_f
;
2259 memset(this->outputs
, 0, sizeof(this->outputs
));
2260 memset(this->output_components
, 0, sizeof(this->output_components
));
2261 this->first_non_payload_grf
= 0;
2262 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2264 this->current_annotation
= NULL
;
2265 this->base_ir
= NULL
;
2267 this->virtual_grf_sizes
= NULL
;
2268 this->virtual_grf_count
= 0;
2269 this->virtual_grf_array_size
= 0;
2270 this->virtual_grf_def
= NULL
;
2271 this->virtual_grf_use
= NULL
;
2272 this->live_intervals_valid
= false;
2274 this->force_uncompressed_stack
= 0;
2275 this->force_sechalf_stack
= 0;
2278 fs_visitor::~fs_visitor()
2280 ralloc_free(this->mem_ctx
);
2281 hash_table_dtor(this->variable_ht
);