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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "glsl/nir/glsl_types.h"
36 fs_visitor::emit_vs_system_value(int location
)
38 fs_reg
*reg
= new(this->mem_ctx
)
39 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
41 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
44 case SYSTEM_VALUE_BASE_VERTEX
:
46 vs_prog_data
->uses_vertexid
= true;
48 case SYSTEM_VALUE_VERTEX_ID
:
49 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
51 vs_prog_data
->uses_vertexid
= true;
53 case SYSTEM_VALUE_INSTANCE_ID
:
55 vs_prog_data
->uses_instanceid
= true;
58 unreachable("not reached");
64 /* Sample from the MCS surface attached to this multisample texture. */
66 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
67 const fs_reg
&sampler
)
69 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
70 const fs_reg srcs
[] = {
71 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
72 sampler
, fs_reg(), brw_imm_ud(components
), brw_imm_d(0)
74 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
77 /* We only care about one or two regs of response, but the sampler always
80 inst
->regs_written
= 4 * dispatch_width
/ 8;
86 fs_visitor::emit_texture(ir_texture_opcode op
,
87 const glsl_type
*dest_type
,
88 fs_reg coordinate
, int coord_components
,
90 fs_reg lod
, fs_reg lod2
, int grad_components
,
101 if (op
== ir_query_levels
) {
102 /* textureQueryLevels() is implemented in terms of TXS so we need to
103 * pass a valid LOD argument.
105 assert(lod
.file
== BAD_FILE
);
106 lod
= brw_imm_ud(0u);
109 if (op
== ir_samples_identical
) {
110 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
112 /* If mcs is an immediate value, it means there is no MCS. In that case
115 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
116 bld
.MOV(dst
, brw_imm_ud(0u));
117 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
118 fs_reg tmp
= vgrf(glsl_type::uint_type
);
119 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
120 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
122 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
129 /* Writemasking doesn't eliminate channels on SIMD8 texture
130 * samples, so don't worry about them.
132 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
133 const fs_reg srcs
[] = {
134 coordinate
, shadow_c
, lod
, lod2
,
135 sample_index
, mcs
, sampler_reg
, offset_value
,
136 brw_imm_d(coord_components
), brw_imm_d(grad_components
)
142 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
145 opcode
= FS_OPCODE_TXB_LOGICAL
;
148 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
151 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
154 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
157 if ((key_tex
->msaa_16
& (1 << sampler
)))
158 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
160 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
163 case ir_query_levels
:
164 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
167 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
170 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
171 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
174 unreachable("Invalid texture opcode.");
177 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
178 inst
->regs_written
= 4 * dispatch_width
/ 8;
180 if (shadow_c
.file
!= BAD_FILE
)
181 inst
->shadow_compare
= true;
183 if (offset_value
.file
== IMM
)
184 inst
->offset
= offset_value
.ud
;
187 if (gather_component
== 1 &&
188 key_tex
->gather_channel_quirk_mask
& (1 << sampler
)) {
189 /* gather4 sampler is broken for green channel on RG32F --
190 * we must ask for blue instead.
192 inst
->offset
|= 2 << 16;
194 inst
->offset
|= gather_component
<< 16;
197 if (devinfo
->gen
== 6)
198 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
201 /* fixup #layers for cube map arrays */
202 if (op
== ir_txs
&& is_cube_array
) {
203 fs_reg depth
= offset(dst
, bld
, 2);
204 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
205 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
207 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
208 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
209 for (int i
= 0; i
< components
; i
++) {
211 fixed_payload
[i
] = fixed_depth
;
213 fixed_payload
[i
] = offset(dst
, bld
, i
);
216 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
219 if (op
== ir_query_levels
) {
220 /* # levels is in .w */
221 dst
= offset(dst
, bld
, 3);
228 * Apply workarounds for Gen6 gather with UINT/SINT
231 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
236 int width
= (wa
& WA_8BIT
) ? 8 : 16;
238 for (int i
= 0; i
< 4; i
++) {
239 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
240 /* Convert from UNORM to UINT */
241 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
245 /* Reinterpret the UINT value as a signed INT value by
246 * shifting the sign bit into place, then shifting back
249 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
250 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
253 dst
= offset(dst
, bld
, 1);
257 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
259 fs_visitor::emit_dummy_fs()
261 int reg_width
= dispatch_width
/ 8;
263 /* Everyone's favorite color. */
264 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
265 for (int i
= 0; i
< 4; i
++) {
266 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
267 brw_imm_f(color
[i
]));
271 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
273 if (devinfo
->gen
>= 6) {
275 write
->mlen
= 4 * reg_width
;
277 write
->header_size
= 2;
279 write
->mlen
= 2 + 4 * reg_width
;
282 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
283 * varying to avoid GPU hangs, so set that.
285 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
286 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
287 memset(wm_prog_data
->urb_setup
, -1,
288 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
290 /* We don't have any uniforms. */
291 stage_prog_data
->nr_params
= 0;
292 stage_prog_data
->nr_pull_params
= 0;
293 stage_prog_data
->curb_read_length
= 0;
294 stage_prog_data
->dispatch_grf_start_reg
= 2;
295 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
296 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
301 /* The register location here is relative to the start of the URB
302 * data. It will get adjusted to be a real location before
303 * generate_code() time.
306 fs_visitor::interp_reg(int location
, int channel
)
308 assert(stage
== MESA_SHADER_FRAGMENT
);
309 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
310 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
311 int stride
= (channel
& 1) * 4;
313 assert(prog_data
->urb_setup
[location
] != -1);
315 return brw_vec1_grf(regnr
, stride
);
318 /** Emits the interpolation for the varying inputs. */
320 fs_visitor::emit_interpolation_setup_gen4()
322 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
324 fs_builder abld
= bld
.annotate("compute pixel centers");
325 this->pixel_x
= vgrf(glsl_type::uint_type
);
326 this->pixel_y
= vgrf(glsl_type::uint_type
);
327 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
328 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
329 abld
.ADD(this->pixel_x
,
330 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
331 fs_reg(brw_imm_v(0x10101010)));
332 abld
.ADD(this->pixel_y
,
333 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
334 fs_reg(brw_imm_v(0x11001100)));
336 abld
= bld
.annotate("compute pixel deltas from v0");
338 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
339 vgrf(glsl_type::vec2_type
);
340 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
341 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
342 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
344 if (devinfo
->has_pln
&& dispatch_width
== 16) {
345 for (unsigned i
= 0; i
< 2; i
++) {
346 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
347 half(this->pixel_x
, i
), xstart
);
348 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
349 half(this->pixel_y
, i
), ystart
);
352 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
353 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
356 abld
= bld
.annotate("compute pos.w and 1/pos.w");
357 /* Compute wpos.w. It's always in our setup, since it's needed to
358 * interpolate the other attributes.
360 this->wpos_w
= vgrf(glsl_type::float_type
);
361 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
362 interp_reg(VARYING_SLOT_POS
, 3));
363 /* Compute the pixel 1/W value from wpos.w. */
364 this->pixel_w
= vgrf(glsl_type::float_type
);
365 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
368 /** Emits the interpolation for the varying inputs. */
370 fs_visitor::emit_interpolation_setup_gen6()
372 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
374 fs_builder abld
= bld
.annotate("compute pixel centers");
375 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
376 /* The "Register Region Restrictions" page says for BDW (and newer,
379 * "When destination spans two registers, the source may be one or
380 * two registers. The destination elements must be evenly split
381 * between the two registers."
383 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
384 * compute our pixel centers.
386 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
387 BRW_REGISTER_TYPE_UW
);
389 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
390 dbld
.ADD(int_pixel_xy
,
391 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
392 fs_reg(brw_imm_v(0x11001010)));
394 this->pixel_x
= vgrf(glsl_type::float_type
);
395 this->pixel_y
= vgrf(glsl_type::float_type
);
396 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
397 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
399 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
401 * "When destination spans two registers, the source MUST span two
404 * Since the GRF source of the ADD will only read a single register, we
405 * must do two separate ADDs in SIMD16.
407 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
408 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
409 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
410 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
411 abld
.ADD(int_pixel_x
,
412 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
413 fs_reg(brw_imm_v(0x10101010)));
414 abld
.ADD(int_pixel_y
,
415 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
416 fs_reg(brw_imm_v(0x11001100)));
418 /* As of gen6, we can no longer mix float and int sources. We have
419 * to turn the integer pixel centers into floats for their actual
422 this->pixel_x
= vgrf(glsl_type::float_type
);
423 this->pixel_y
= vgrf(glsl_type::float_type
);
424 abld
.MOV(this->pixel_x
, int_pixel_x
);
425 abld
.MOV(this->pixel_y
, int_pixel_y
);
428 abld
= bld
.annotate("compute pos.w");
429 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
430 this->wpos_w
= vgrf(glsl_type::float_type
);
431 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
433 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
434 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
435 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
439 static enum brw_conditional_mod
440 cond_for_alpha_func(GLenum func
)
444 return BRW_CONDITIONAL_G
;
446 return BRW_CONDITIONAL_GE
;
448 return BRW_CONDITIONAL_L
;
450 return BRW_CONDITIONAL_LE
;
452 return BRW_CONDITIONAL_EQ
;
454 return BRW_CONDITIONAL_NEQ
;
456 unreachable("Not reached");
461 * Alpha test support for when we compile it into the shader instead
462 * of using the normal fixed-function alpha test.
465 fs_visitor::emit_alpha_test()
467 assert(stage
== MESA_SHADER_FRAGMENT
);
468 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
469 const fs_builder abld
= bld
.annotate("Alpha test");
472 if (key
->alpha_test_func
== GL_ALWAYS
)
475 if (key
->alpha_test_func
== GL_NEVER
) {
477 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
478 BRW_REGISTER_TYPE_UW
));
479 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
480 BRW_CONDITIONAL_NEQ
);
483 fs_reg color
= offset(outputs
[0], bld
, 3);
485 /* f0.1 &= func(color, ref) */
486 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
487 cond_for_alpha_func(key
->alpha_test_func
));
489 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
490 cmp
->flag_subreg
= 1;
494 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
495 fs_reg color0
, fs_reg color1
,
496 fs_reg src0_alpha
, unsigned components
)
498 assert(stage
== MESA_SHADER_FRAGMENT
);
499 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
501 /* Hand over gl_FragDepth or the payload depth. */
502 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
503 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
505 fs_reg src_depth
, src_stencil
;
507 if (source_depth_to_render_target
) {
508 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
509 src_depth
= frag_depth
;
511 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
514 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
515 src_stencil
= frag_stencil
;
517 const fs_reg sources
[] = {
518 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
519 sample_mask
, brw_imm_ud(components
)
521 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
522 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
523 sources
, ARRAY_SIZE(sources
));
525 if (prog_data
->uses_kill
) {
526 write
->predicate
= BRW_PREDICATE_NORMAL
;
527 write
->flag_subreg
= 1;
534 fs_visitor::emit_fb_writes()
536 assert(stage
== MESA_SHADER_FRAGMENT
);
537 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
538 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
540 fs_inst
*inst
= NULL
;
542 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
543 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
544 * would require SIMD8 moves of each half to message regs, e.g. by using
545 * the SIMD lowering pass. Unfortunately this is more difficult than it
546 * sounds because the SIMD8 single-source message lacks channel selects
547 * for the second and third subspans.
549 no16("Missing support for simd16 depth writes on gen6\n");
552 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
553 /* From the 'Render Target Write message' section of the docs:
554 * "Output Stencil is not supported with SIMD16 Render Target Write
557 * FINISHME: split 16 into 2 8s
559 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
563 const fs_builder abld
= bld
.annotate("FB dual-source write");
565 inst
= emit_single_fb_write(abld
, this->outputs
[0],
566 this->dual_src_output
, reg_undef
, 4);
569 prog_data
->dual_src_blend
= true;
571 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
572 /* Skip over outputs that weren't written. */
573 if (this->outputs
[target
].file
== BAD_FILE
)
576 const fs_builder abld
= bld
.annotate(
577 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
580 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
581 src0_alpha
= offset(outputs
[0], bld
, 3);
583 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
585 this->output_components
[target
]);
586 inst
->target
= target
;
591 /* Even if there's no color buffers enabled, we still need to send
592 * alpha out the pipeline to our null renderbuffer to support
593 * alpha-testing, alpha-to-coverage, and so on.
595 /* FINISHME: Factor out this frequently recurring pattern into a
598 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
599 reg_undef
, offset(this->outputs
[0], bld
, 3) };
600 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
601 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
603 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
611 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
613 const struct brw_vs_prog_key
*key
=
614 (const struct brw_vs_prog_key
*) this->key
;
616 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
617 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
618 for (int j
= 0; j
< 4; ++j
) {
619 stage_prog_data
->param
[uniforms
+ j
] =
620 (gl_constant_value
*) &clip_planes
[i
][j
];
627 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
629 * This does nothing if the shader uses gl_ClipDistance or user clipping is
630 * disabled altogether.
632 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
634 struct brw_vue_prog_data
*vue_prog_data
=
635 (struct brw_vue_prog_data
*) prog_data
;
636 const struct brw_vs_prog_key
*key
=
637 (const struct brw_vs_prog_key
*) this->key
;
639 /* Bail unless some sort of legacy clipping is enabled */
640 if (key
->nr_userclip_plane_consts
== 0)
643 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
645 * "If a linked set of shaders forming the vertex stage contains no
646 * static write to gl_ClipVertex or gl_ClipDistance, but the
647 * application has requested clipping against user clip planes through
648 * the API, then the coordinate written to gl_Position is used for
649 * comparison against the user clip planes."
651 * This function is only called if the shader didn't write to
652 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
653 * if the user wrote to it; otherwise we use gl_Position.
656 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
657 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
658 clip_vertex
= VARYING_SLOT_POS
;
660 /* If the clip vertex isn't written, skip this. Typically this means
661 * the GS will set up clipping. */
662 if (outputs
[clip_vertex
].file
== BAD_FILE
)
665 setup_uniform_clipplane_values(clip_planes
);
667 const fs_builder abld
= bld
.annotate("user clip distances");
669 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
670 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
671 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
672 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
674 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
675 fs_reg u
= userplane
[i
];
676 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
677 output
.reg_offset
= i
& 3;
679 abld
.MUL(output
, outputs
[clip_vertex
], u
);
680 for (int j
= 1; j
< 4; j
++) {
681 u
.nr
= userplane
[i
].nr
+ j
;
682 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
688 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
690 int slot
, urb_offset
, length
;
691 int starting_urb_offset
= 0;
692 const struct brw_vue_prog_data
*vue_prog_data
=
693 (const struct brw_vue_prog_data
*) this->prog_data
;
694 const struct brw_vs_prog_key
*vs_key
=
695 (const struct brw_vs_prog_key
*) this->key
;
696 const GLbitfield64 psiz_mask
=
697 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
698 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
703 if (stage
== MESA_SHADER_TESS_EVAL
)
704 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
706 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
708 /* If we don't have any valid slots to write, just do a minimal urb write
709 * send to terminate the shader. This includes 1 slot of undefined data,
710 * because it's invalid to write 0 data:
712 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
713 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
714 * Write Data Payload:
716 * "The write data payload can be between 1 and 8 message phases long."
718 if (vue_map
->slots_valid
== 0) {
719 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
720 bld
.exec_all().MOV(payload
, urb_handle
);
722 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
729 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
731 fs_reg per_slot_offsets
;
733 if (stage
== MESA_SHADER_GEOMETRY
) {
734 const struct brw_gs_prog_data
*gs_prog_data
=
735 (const struct brw_gs_prog_data
*) this->prog_data
;
737 /* We need to increment the Global Offset to skip over the control data
738 * header and the extra "Vertex Count" field (1 HWord) at the beginning
739 * of the VUE. We're counting in OWords, so the units are doubled.
741 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
742 if (gs_prog_data
->static_vertex_count
== -1)
743 starting_urb_offset
+= 2;
745 /* We also need to use per-slot offsets. The per-slot offset is the
746 * Vertex Count. SIMD8 mode processes 8 different primitives at a
747 * time; each may output a different number of vertices.
749 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
752 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
753 const int output_vertex_size_owords
=
754 gs_prog_data
->output_vertex_size_hwords
* 2;
756 if (gs_vertex_count
.file
== IMM
) {
757 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
760 per_slot_offsets
= vgrf(glsl_type::int_type
);
761 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
762 brw_imm_ud(output_vertex_size_owords
));
767 urb_offset
= starting_urb_offset
;
769 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
770 int varying
= vue_map
->slot_to_varying
[slot
];
772 case VARYING_SLOT_PSIZ
: {
773 /* The point size varying slot is the vue header and is always in the
774 * vue map. But often none of the special varyings that live there
775 * are written and in that case we can skip writing to the vue
776 * header, provided the corresponding state properly clamps the
777 * values further down the pipeline. */
778 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
784 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
785 bld
.MOV(zero
, brw_imm_ud(0u));
787 sources
[length
++] = zero
;
788 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
789 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
791 sources
[length
++] = zero
;
793 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
794 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
796 sources
[length
++] = zero
;
798 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
799 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
801 sources
[length
++] = zero
;
804 case BRW_VARYING_SLOT_NDC
:
805 case VARYING_SLOT_EDGE
:
806 unreachable("unexpected scalar vs output");
810 /* gl_Position is always in the vue map, but isn't always written by
811 * the shader. Other varyings (clip distances) get added to the vue
812 * map but don't always get written. In those cases, the
813 * corresponding this->output[] slot will be invalid we and can skip
814 * the urb write for the varying. If we've already queued up a vue
815 * slot for writing we flush a mlen 5 urb write, otherwise we just
816 * advance the urb_offset.
818 if (varying
== BRW_VARYING_SLOT_PAD
||
819 this->outputs
[varying
].file
== BAD_FILE
) {
827 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
828 (varying
== VARYING_SLOT_COL0
||
829 varying
== VARYING_SLOT_COL1
||
830 varying
== VARYING_SLOT_BFC0
||
831 varying
== VARYING_SLOT_BFC1
)) {
832 /* We need to clamp these guys, so do a saturating MOV into a
833 * temp register and use that for the payload.
835 for (int i
= 0; i
< 4; i
++) {
836 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
837 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
838 set_saturate(true, bld
.MOV(reg
, src
));
839 sources
[length
++] = reg
;
842 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
843 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
844 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
845 sources
[length
++] = brw_imm_d(0);
850 const fs_builder abld
= bld
.annotate("URB write");
852 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
853 * the last slot or if we need to flush (see BAD_FILE varying case
854 * above), emit a URB write send now to flush out the data.
856 int last
= slot
== vue_map
->num_slots
- 1;
857 if (length
== 8 || last
)
860 fs_reg
*payload_sources
=
861 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
862 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
863 BRW_REGISTER_TYPE_F
);
864 payload_sources
[0] = urb_handle
;
866 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
867 payload_sources
[1] = per_slot_offsets
;
869 memcpy(&payload_sources
[header_size
], sources
,
870 length
* sizeof sources
[0]);
872 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
875 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
876 inst
->eot
= last
&& stage
!= MESA_SHADER_GEOMETRY
;
877 inst
->mlen
= length
+ header_size
;
878 inst
->offset
= urb_offset
;
879 urb_offset
= starting_urb_offset
+ slot
+ 1;
887 fs_visitor::emit_cs_terminate()
889 assert(devinfo
->gen
>= 7);
891 /* We are getting the thread ID from the compute shader header */
892 assert(stage
== MESA_SHADER_COMPUTE
);
894 /* We can't directly send from g0, since sends with EOT have to use
895 * g112-127. So, copy it to a virtual register, The register allocator will
896 * make sure it uses the appropriate register range.
898 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
899 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
900 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
902 /* Send a message to the thread spawner to terminate the thread. */
903 fs_inst
*inst
= bld
.exec_all()
904 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
909 fs_visitor::emit_barrier()
911 assert(devinfo
->gen
>= 7);
913 /* We are getting the barrier ID from the compute shader header */
914 assert(stage
== MESA_SHADER_COMPUTE
);
916 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
918 const fs_builder pbld
= bld
.exec_all().group(8, 0);
920 /* Clear the message payload */
921 pbld
.MOV(payload
, brw_imm_ud(0u));
923 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
924 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
925 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(0x0f000000u
));
927 /* Emit a gateway "barrier" message using the payload we set up, followed
928 * by a wait instruction.
930 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
933 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
936 struct brw_stage_prog_data
*prog_data
,
937 struct gl_program
*prog
,
938 const nir_shader
*shader
,
939 unsigned dispatch_width
,
940 int shader_time_index
,
941 const struct brw_vue_map
*input_vue_map
)
942 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
943 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
944 input_vue_map(input_vue_map
),
945 dispatch_width(dispatch_width
),
946 shader_time_index(shader_time_index
),
947 bld(fs_builder(this, dispatch_width
).at_end())
952 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
954 struct brw_gs_compile
*c
,
955 struct brw_gs_prog_data
*prog_data
,
956 const nir_shader
*shader
,
957 int shader_time_index
)
958 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
959 &prog_data
->base
.base
),
960 key(&c
->key
), gs_compile(c
),
961 prog_data(&prog_data
->base
.base
), prog(NULL
),
963 shader_time_index(shader_time_index
),
964 bld(fs_builder(this, dispatch_width
).at_end())
974 case MESA_SHADER_FRAGMENT
:
975 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
977 case MESA_SHADER_VERTEX
:
978 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
980 case MESA_SHADER_TESS_EVAL
:
981 key_tex
= &((const brw_tes_prog_key
*) key
)->tex
;
983 case MESA_SHADER_GEOMETRY
:
984 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
986 case MESA_SHADER_COMPUTE
:
987 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
990 unreachable("unhandled shader stage");
993 this->prog_data
= this->stage_prog_data
;
995 this->failed
= false;
996 this->simd16_unsupported
= false;
997 this->no16_msg
= NULL
;
999 this->nir_locals
= NULL
;
1000 this->nir_ssa_values
= NULL
;
1002 memset(&this->payload
, 0, sizeof(this->payload
));
1003 memset(this->output_components
, 0, sizeof(this->output_components
));
1004 this->source_depth_to_render_target
= false;
1005 this->runtime_check_aads_emit
= false;
1006 this->first_non_payload_grf
= 0;
1007 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1009 this->virtual_grf_start
= NULL
;
1010 this->virtual_grf_end
= NULL
;
1011 this->live_intervals
= NULL
;
1012 this->regs_live_at_ip
= NULL
;
1015 this->last_scratch
= 0;
1016 this->pull_constant_loc
= NULL
;
1017 this->push_constant_loc
= NULL
;
1019 this->promoted_constants
= 0,
1021 this->spilled_any_registers
= false;
1022 this->do_dual_src
= false;
1024 if (dispatch_width
== 8)
1025 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1028 fs_visitor::~fs_visitor()