2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
44 #include "brw_vec4_gs_visitor.h"
46 #include "main/uniforms.h"
47 #include "glsl/nir/glsl_types.h"
48 #include "glsl/ir_optimization.h"
49 #include "program/sampler.h"
54 fs_visitor::emit_vs_system_value(int location
)
56 fs_reg
*reg
= new(this->mem_ctx
)
57 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
59 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
62 case SYSTEM_VALUE_BASE_VERTEX
:
64 vs_prog_data
->uses_vertexid
= true;
66 case SYSTEM_VALUE_VERTEX_ID
:
67 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
69 vs_prog_data
->uses_vertexid
= true;
71 case SYSTEM_VALUE_INSTANCE_ID
:
73 vs_prog_data
->uses_instanceid
= true;
76 unreachable("not reached");
83 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
84 bool is_rect
, uint32_t sampler
)
86 bool needs_gl_clamp
= true;
87 fs_reg scale_x
, scale_y
;
89 /* The 965 requires the EU to do the normalization of GL rectangle
90 * texture coordinates. We use the program parameter state
91 * tracking to get the scaling factor.
95 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
96 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
97 struct gl_program_parameter_list
*params
= prog
->Parameters
;
100 /* FINISHME: We're failing to recompile our programs when the sampler is
101 * updated. This only matters for the texture rectangle scale
102 * parameters (pre-gen6, or gen6+ with GL_CLAMP).
104 int tokens
[STATE_LENGTH
] = {
107 prog
->SamplerUnits
[sampler
],
112 no16("rectangle scale uniform setup not supported on SIMD16\n");
113 if (dispatch_width
== 16) {
117 GLuint index
= _mesa_add_state_reference(params
,
118 (gl_state_index
*)tokens
);
119 /* Try to find existing copies of the texrect scale uniforms. */
120 for (unsigned i
= 0; i
< uniforms
; i
++) {
121 if (stage_prog_data
->param
[i
] ==
122 &prog
->Parameters
->ParameterValues
[index
][0]) {
123 scale_x
= fs_reg(UNIFORM
, i
);
124 scale_y
= fs_reg(UNIFORM
, i
+ 1);
129 /* If we didn't already set them up, do so now. */
130 if (scale_x
.file
== BAD_FILE
) {
131 scale_x
= fs_reg(UNIFORM
, uniforms
);
132 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
134 stage_prog_data
->param
[uniforms
++] =
135 &prog
->Parameters
->ParameterValues
[index
][0];
136 stage_prog_data
->param
[uniforms
++] =
137 &prog
->Parameters
->ParameterValues
[index
][1];
141 /* The 965 requires the EU to do the normalization of GL rectangle
142 * texture coordinates. We use the program parameter state
143 * tracking to get the scaling factor.
145 if (devinfo
->gen
< 6 && is_rect
) {
146 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(coord_components
));
147 fs_reg src
= coordinate
;
150 bld
.MUL(dst
, src
, scale_x
);
151 dst
= offset(dst
, bld
, 1);
152 src
= offset(src
, bld
, 1);
153 bld
.MUL(dst
, src
, scale_y
);
154 } else if (is_rect
) {
155 /* On gen6+, the sampler handles the rectangle coordinates
156 * natively, without needing rescaling. But that means we have
157 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
158 * not [0, 1] like the default case below.
160 needs_gl_clamp
= false;
162 for (int i
= 0; i
< 2; i
++) {
163 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
164 fs_reg chan
= coordinate
;
165 chan
= offset(chan
, bld
, i
);
167 set_condmod(BRW_CONDITIONAL_GE
,
168 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
170 /* Our parameter comes in as 1.0/width or 1.0/height,
171 * because that's what people normally want for doing
172 * texture rectangle handling. We need width or height
173 * for clamping, but we don't care enough to make a new
174 * parameter type, so just invert back.
176 fs_reg limit
= vgrf(glsl_type::float_type
);
177 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
178 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
180 set_condmod(BRW_CONDITIONAL_L
,
181 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
186 if (coord_components
> 0 && needs_gl_clamp
) {
187 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
188 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
189 fs_reg chan
= coordinate
;
190 chan
= offset(chan
, bld
, i
);
191 set_saturate(true, bld
.MOV(chan
, chan
));
198 /* Sample from the MCS surface attached to this multisample texture. */
200 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
201 const fs_reg
&sampler
)
203 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
204 const fs_reg srcs
[] = {
205 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
206 sampler
, fs_reg(), fs_reg(components
), fs_reg(0)
208 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
211 /* We only care about one or two regs of response, but the sampler always
214 inst
->regs_written
= 4 * dispatch_width
/ 8;
220 fs_visitor::emit_texture(ir_texture_opcode op
,
221 const glsl_type
*dest_type
,
222 fs_reg coordinate
, int coord_components
,
224 fs_reg lod
, fs_reg lod2
, int grad_components
,
228 int gather_component
,
234 fs_inst
*inst
= NULL
;
237 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
238 * emitting anything other than setting up the constant result.
240 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
241 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
243 fs_reg res
= vgrf(glsl_type::vec4_type
);
246 for (int i
=0; i
<4; i
++) {
247 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
248 res
= offset(res
, bld
, 1);
254 if (op
== ir_query_levels
) {
255 /* textureQueryLevels() is implemented in terms of TXS so we need to
256 * pass a valid LOD argument.
258 assert(lod
.file
== BAD_FILE
);
262 if (coordinate
.file
!= BAD_FILE
) {
263 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
264 * samplers. This should only be a problem with GL_CLAMP on Gen7.
266 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
270 /* Writemasking doesn't eliminate channels on SIMD8 texture
271 * samples, so don't worry about them.
273 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
274 const fs_reg srcs
[] = {
275 coordinate
, shadow_c
, lod
, lod2
,
276 sample_index
, mcs
, sampler_reg
, offset_value
,
277 fs_reg(coord_components
), fs_reg(grad_components
)
283 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
286 opcode
= FS_OPCODE_TXB_LOGICAL
;
289 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
292 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
295 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
298 if ((key_tex
->msaa_16
& (1 << sampler
)))
299 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
301 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
304 case ir_query_levels
:
305 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
308 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
311 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
312 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
315 unreachable("Invalid texture opcode.");
318 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
319 inst
->regs_written
= 4 * dispatch_width
/ 8;
321 if (shadow_c
.file
!= BAD_FILE
)
322 inst
->shadow_compare
= true;
324 if (offset_value
.file
== IMM
)
325 inst
->offset
= offset_value
.ud
;
329 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
331 if (devinfo
->gen
== 6)
332 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
335 /* fixup #layers for cube map arrays */
336 if (op
== ir_txs
&& is_cube_array
) {
337 fs_reg depth
= offset(dst
, bld
, 2);
338 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
339 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
341 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
342 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
343 for (int i
= 0; i
< components
; i
++) {
345 fixed_payload
[i
] = fixed_depth
;
347 fixed_payload
[i
] = offset(dst
, bld
, i
);
350 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
353 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
357 * Apply workarounds for Gen6 gather with UINT/SINT
360 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
365 int width
= (wa
& WA_8BIT
) ? 8 : 16;
367 for (int i
= 0; i
< 4; i
++) {
368 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
369 /* Convert from UNORM to UINT */
370 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
374 /* Reinterpret the UINT value as a signed INT value by
375 * shifting the sign bit into place, then shifting back
378 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
379 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
382 dst
= offset(dst
, bld
, 1);
387 * Set up the gather channel based on the swizzle, for gather4.
390 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
392 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
394 case SWIZZLE_X
: return 0;
396 /* gather4 sampler is broken for green channel on RG32F --
397 * we must ask for blue instead.
399 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
402 case SWIZZLE_Z
: return 2;
403 case SWIZZLE_W
: return 3;
405 unreachable("Not reached"); /* zero, one swizzles handled already */
410 * Swizzle the result of a texture result. This is necessary for
411 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
414 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
415 fs_reg orig_val
, uint32_t sampler
)
417 if (op
== ir_query_levels
) {
418 /* # levels is in .w */
419 this->result
= offset(orig_val
, bld
, 3);
423 this->result
= orig_val
;
425 /* txs,lod don't actually sample the texture, so swizzling the result
428 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
431 if (dest_components
== 1) {
432 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
433 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
434 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
435 swizzled_result
.type
= orig_val
.type
;
437 for (int i
= 0; i
< 4; i
++) {
438 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
439 fs_reg l
= swizzled_result
;
440 l
= offset(l
, bld
, i
);
442 if (swiz
== SWIZZLE_ZERO
) {
443 bld
.MOV(l
, fs_reg(0.0f
));
444 } else if (swiz
== SWIZZLE_ONE
) {
445 bld
.MOV(l
, fs_reg(1.0f
));
447 bld
.MOV(l
, offset(orig_val
, bld
,
448 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
451 this->result
= swizzled_result
;
455 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
457 fs_visitor::emit_dummy_fs()
459 int reg_width
= dispatch_width
/ 8;
461 /* Everyone's favorite color. */
462 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
463 for (int i
= 0; i
< 4; i
++) {
464 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
469 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
471 if (devinfo
->gen
>= 6) {
473 write
->mlen
= 4 * reg_width
;
475 write
->header_size
= 2;
477 write
->mlen
= 2 + 4 * reg_width
;
480 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
481 * varying to avoid GPU hangs, so set that.
483 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
484 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
485 memset(wm_prog_data
->urb_setup
, -1,
486 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
488 /* We don't have any uniforms. */
489 stage_prog_data
->nr_params
= 0;
490 stage_prog_data
->nr_pull_params
= 0;
491 stage_prog_data
->curb_read_length
= 0;
492 stage_prog_data
->dispatch_grf_start_reg
= 2;
493 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
494 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
499 /* The register location here is relative to the start of the URB
500 * data. It will get adjusted to be a real location before
501 * generate_code() time.
504 fs_visitor::interp_reg(int location
, int channel
)
506 assert(stage
== MESA_SHADER_FRAGMENT
);
507 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
508 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
509 int stride
= (channel
& 1) * 4;
511 assert(prog_data
->urb_setup
[location
] != -1);
513 return brw_vec1_grf(regnr
, stride
);
516 /** Emits the interpolation for the varying inputs. */
518 fs_visitor::emit_interpolation_setup_gen4()
520 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
522 fs_builder abld
= bld
.annotate("compute pixel centers");
523 this->pixel_x
= vgrf(glsl_type::uint_type
);
524 this->pixel_y
= vgrf(glsl_type::uint_type
);
525 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
526 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
527 abld
.ADD(this->pixel_x
,
528 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
529 fs_reg(brw_imm_v(0x10101010)));
530 abld
.ADD(this->pixel_y
,
531 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
532 fs_reg(brw_imm_v(0x11001100)));
534 abld
= bld
.annotate("compute pixel deltas from v0");
536 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
537 vgrf(glsl_type::vec2_type
);
538 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
539 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
540 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
542 if (devinfo
->has_pln
&& dispatch_width
== 16) {
543 for (unsigned i
= 0; i
< 2; i
++) {
544 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
545 half(this->pixel_x
, i
), xstart
);
546 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
547 half(this->pixel_y
, i
), ystart
);
550 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
551 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
554 abld
= bld
.annotate("compute pos.w and 1/pos.w");
555 /* Compute wpos.w. It's always in our setup, since it's needed to
556 * interpolate the other attributes.
558 this->wpos_w
= vgrf(glsl_type::float_type
);
559 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
560 interp_reg(VARYING_SLOT_POS
, 3));
561 /* Compute the pixel 1/W value from wpos.w. */
562 this->pixel_w
= vgrf(glsl_type::float_type
);
563 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
566 /** Emits the interpolation for the varying inputs. */
568 fs_visitor::emit_interpolation_setup_gen6()
570 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
572 fs_builder abld
= bld
.annotate("compute pixel centers");
573 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
574 /* The "Register Region Restrictions" page says for BDW (and newer,
577 * "When destination spans two registers, the source may be one or
578 * two registers. The destination elements must be evenly split
579 * between the two registers."
581 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
582 * compute our pixel centers.
584 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
585 BRW_REGISTER_TYPE_UW
);
587 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
588 dbld
.ADD(int_pixel_xy
,
589 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
590 fs_reg(brw_imm_v(0x11001010)));
592 this->pixel_x
= vgrf(glsl_type::float_type
);
593 this->pixel_y
= vgrf(glsl_type::float_type
);
594 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
595 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
597 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
599 * "When destination spans two registers, the source MUST span two
602 * Since the GRF source of the ADD will only read a single register, we
603 * must do two separate ADDs in SIMD16.
605 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
606 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
607 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
608 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
609 abld
.ADD(int_pixel_x
,
610 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
611 fs_reg(brw_imm_v(0x10101010)));
612 abld
.ADD(int_pixel_y
,
613 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
614 fs_reg(brw_imm_v(0x11001100)));
616 /* As of gen6, we can no longer mix float and int sources. We have
617 * to turn the integer pixel centers into floats for their actual
620 this->pixel_x
= vgrf(glsl_type::float_type
);
621 this->pixel_y
= vgrf(glsl_type::float_type
);
622 abld
.MOV(this->pixel_x
, int_pixel_x
);
623 abld
.MOV(this->pixel_y
, int_pixel_y
);
626 abld
= bld
.annotate("compute pos.w");
627 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
628 this->wpos_w
= vgrf(glsl_type::float_type
);
629 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
631 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
632 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
633 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
637 static enum brw_conditional_mod
638 cond_for_alpha_func(GLenum func
)
642 return BRW_CONDITIONAL_G
;
644 return BRW_CONDITIONAL_GE
;
646 return BRW_CONDITIONAL_L
;
648 return BRW_CONDITIONAL_LE
;
650 return BRW_CONDITIONAL_EQ
;
652 return BRW_CONDITIONAL_NEQ
;
654 unreachable("Not reached");
659 * Alpha test support for when we compile it into the shader instead
660 * of using the normal fixed-function alpha test.
663 fs_visitor::emit_alpha_test()
665 assert(stage
== MESA_SHADER_FRAGMENT
);
666 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
667 const fs_builder abld
= bld
.annotate("Alpha test");
670 if (key
->alpha_test_func
== GL_ALWAYS
)
673 if (key
->alpha_test_func
== GL_NEVER
) {
675 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
676 BRW_REGISTER_TYPE_UW
));
677 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
678 BRW_CONDITIONAL_NEQ
);
681 fs_reg color
= offset(outputs
[0], bld
, 3);
683 /* f0.1 &= func(color, ref) */
684 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
685 cond_for_alpha_func(key
->alpha_test_func
));
687 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
688 cmp
->flag_subreg
= 1;
692 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
693 fs_reg color0
, fs_reg color1
,
694 fs_reg src0_alpha
, unsigned components
)
696 assert(stage
== MESA_SHADER_FRAGMENT
);
697 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
699 /* Hand over gl_FragDepth or the payload depth. */
700 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
701 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
703 fs_reg src_depth
, src_stencil
;
705 if (source_depth_to_render_target
) {
706 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
707 src_depth
= frag_depth
;
709 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
712 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
713 src_stencil
= frag_stencil
;
715 const fs_reg sources
[] = {
716 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
717 sample_mask
, fs_reg(components
)
719 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
720 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
721 sources
, ARRAY_SIZE(sources
));
723 if (prog_data
->uses_kill
) {
724 write
->predicate
= BRW_PREDICATE_NORMAL
;
725 write
->flag_subreg
= 1;
732 fs_visitor::emit_fb_writes()
734 assert(stage
== MESA_SHADER_FRAGMENT
);
735 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
736 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
738 fs_inst
*inst
= NULL
;
740 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
741 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
742 * would require SIMD8 moves of each half to message regs, e.g. by using
743 * the SIMD lowering pass. Unfortunately this is more difficult than it
744 * sounds because the SIMD8 single-source message lacks channel selects
745 * for the second and third subspans.
747 no16("Missing support for simd16 depth writes on gen6\n");
750 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
751 /* From the 'Render Target Write message' section of the docs:
752 * "Output Stencil is not supported with SIMD16 Render Target Write
755 * FINISHME: split 16 into 2 8s
757 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
761 const fs_builder abld
= bld
.annotate("FB dual-source write");
763 inst
= emit_single_fb_write(abld
, this->outputs
[0],
764 this->dual_src_output
, reg_undef
, 4);
767 prog_data
->dual_src_blend
= true;
769 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
770 /* Skip over outputs that weren't written. */
771 if (this->outputs
[target
].file
== BAD_FILE
)
774 const fs_builder abld
= bld
.annotate(
775 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
778 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
779 src0_alpha
= offset(outputs
[0], bld
, 3);
781 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
783 this->output_components
[target
]);
784 inst
->target
= target
;
789 /* Even if there's no color buffers enabled, we still need to send
790 * alpha out the pipeline to our null renderbuffer to support
791 * alpha-testing, alpha-to-coverage, and so on.
793 /* FINISHME: Factor out this frequently recurring pattern into a
796 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
797 reg_undef
, offset(this->outputs
[0], bld
, 3) };
798 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
799 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
801 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
809 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
811 const struct brw_vs_prog_key
*key
=
812 (const struct brw_vs_prog_key
*) this->key
;
814 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
815 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
816 for (int j
= 0; j
< 4; ++j
) {
817 stage_prog_data
->param
[uniforms
+ j
] =
818 (gl_constant_value
*) &clip_planes
[i
][j
];
825 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
827 * This does nothing if the shader uses gl_ClipDistance or user clipping is
828 * disabled altogether.
830 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
832 struct brw_vue_prog_data
*vue_prog_data
=
833 (struct brw_vue_prog_data
*) prog_data
;
834 const struct brw_vs_prog_key
*key
=
835 (const struct brw_vs_prog_key
*) this->key
;
837 /* Bail unless some sort of legacy clipping is enabled */
838 if (key
->nr_userclip_plane_consts
== 0)
841 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
843 * "If a linked set of shaders forming the vertex stage contains no
844 * static write to gl_ClipVertex or gl_ClipDistance, but the
845 * application has requested clipping against user clip planes through
846 * the API, then the coordinate written to gl_Position is used for
847 * comparison against the user clip planes."
849 * This function is only called if the shader didn't write to
850 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
851 * if the user wrote to it; otherwise we use gl_Position.
854 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
855 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
856 clip_vertex
= VARYING_SLOT_POS
;
858 /* If the clip vertex isn't written, skip this. Typically this means
859 * the GS will set up clipping. */
860 if (outputs
[clip_vertex
].file
== BAD_FILE
)
863 setup_uniform_clipplane_values(clip_planes
);
865 const fs_builder abld
= bld
.annotate("user clip distances");
867 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
868 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
869 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
870 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
872 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
873 fs_reg u
= userplane
[i
];
874 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
875 output
.reg_offset
= i
& 3;
877 abld
.MUL(output
, outputs
[clip_vertex
], u
);
878 for (int j
= 1; j
< 4; j
++) {
879 u
.nr
= userplane
[i
].nr
+ j
;
880 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
886 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
888 int slot
, urb_offset
, length
;
889 int starting_urb_offset
= 0;
890 const struct brw_vue_prog_data
*vue_prog_data
=
891 (const struct brw_vue_prog_data
*) this->prog_data
;
892 const struct brw_vs_prog_key
*vs_key
=
893 (const struct brw_vs_prog_key
*) this->key
;
894 const GLbitfield64 psiz_mask
=
895 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
896 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
900 /* If we don't have any valid slots to write, just do a minimal urb write
901 * send to terminate the shader. This includes 1 slot of undefined data,
902 * because it's invalid to write 0 data:
904 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
905 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
906 * Write Data Payload:
908 * "The write data payload can be between 1 and 8 message phases long."
910 if (vue_map
->slots_valid
== 0) {
911 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
912 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
913 BRW_REGISTER_TYPE_UD
)));
915 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
922 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
924 fs_reg per_slot_offsets
;
926 if (stage
== MESA_SHADER_GEOMETRY
) {
927 const struct brw_gs_prog_data
*gs_prog_data
=
928 (const struct brw_gs_prog_data
*) this->prog_data
;
930 /* We need to increment the Global Offset to skip over the control data
931 * header and the extra "Vertex Count" field (1 HWord) at the beginning
932 * of the VUE. We're counting in OWords, so the units are doubled.
934 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
935 if (gs_prog_data
->static_vertex_count
== -1)
936 starting_urb_offset
+= 2;
938 /* We also need to use per-slot offsets. The per-slot offset is the
939 * Vertex Count. SIMD8 mode processes 8 different primitives at a
940 * time; each may output a different number of vertices.
942 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
945 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
946 const int output_vertex_size_owords
=
947 gs_prog_data
->output_vertex_size_hwords
* 2;
950 if (gs_vertex_count
.file
== IMM
) {
951 per_slot_offsets
= fs_reg(output_vertex_size_owords
*
954 per_slot_offsets
= vgrf(glsl_type::int_type
);
955 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
956 fs_reg(output_vertex_size_owords
));
961 urb_offset
= starting_urb_offset
;
963 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
964 int varying
= vue_map
->slot_to_varying
[slot
];
966 case VARYING_SLOT_PSIZ
: {
967 /* The point size varying slot is the vue header and is always in the
968 * vue map. But often none of the special varyings that live there
969 * are written and in that case we can skip writing to the vue
970 * header, provided the corresponding state properly clamps the
971 * values further down the pipeline. */
972 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
978 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
979 bld
.MOV(zero
, fs_reg(0u));
981 sources
[length
++] = zero
;
982 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
983 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
985 sources
[length
++] = zero
;
987 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
988 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
990 sources
[length
++] = zero
;
992 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
993 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
995 sources
[length
++] = zero
;
998 case BRW_VARYING_SLOT_NDC
:
999 case VARYING_SLOT_EDGE
:
1000 unreachable("unexpected scalar vs output");
1004 /* gl_Position is always in the vue map, but isn't always written by
1005 * the shader. Other varyings (clip distances) get added to the vue
1006 * map but don't always get written. In those cases, the
1007 * corresponding this->output[] slot will be invalid we and can skip
1008 * the urb write for the varying. If we've already queued up a vue
1009 * slot for writing we flush a mlen 5 urb write, otherwise we just
1010 * advance the urb_offset.
1012 if (varying
== BRW_VARYING_SLOT_PAD
||
1013 this->outputs
[varying
].file
== BAD_FILE
) {
1021 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
1022 (varying
== VARYING_SLOT_COL0
||
1023 varying
== VARYING_SLOT_COL1
||
1024 varying
== VARYING_SLOT_BFC0
||
1025 varying
== VARYING_SLOT_BFC1
)) {
1026 /* We need to clamp these guys, so do a saturating MOV into a
1027 * temp register and use that for the payload.
1029 for (int i
= 0; i
< 4; i
++) {
1030 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
1031 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
1032 set_saturate(true, bld
.MOV(reg
, src
));
1033 sources
[length
++] = reg
;
1036 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
1037 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
1038 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
1039 sources
[length
++] = fs_reg(0);
1044 const fs_builder abld
= bld
.annotate("URB write");
1046 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
1047 * the last slot or if we need to flush (see BAD_FILE varying case
1048 * above), emit a URB write send now to flush out the data.
1050 int last
= slot
== vue_map
->num_slots
- 1;
1051 if (length
== 8 || last
)
1054 fs_reg
*payload_sources
=
1055 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
1056 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
1057 BRW_REGISTER_TYPE_F
);
1058 payload_sources
[0] =
1059 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1061 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
1062 payload_sources
[1] = per_slot_offsets
;
1064 memcpy(&payload_sources
[header_size
], sources
,
1065 length
* sizeof sources
[0]);
1067 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
1070 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1071 inst
->eot
= last
&& stage
== MESA_SHADER_VERTEX
;
1072 inst
->mlen
= length
+ header_size
;
1073 inst
->offset
= urb_offset
;
1074 urb_offset
= starting_urb_offset
+ slot
+ 1;
1082 fs_visitor::emit_cs_terminate()
1084 assert(devinfo
->gen
>= 7);
1086 /* We are getting the thread ID from the compute shader header */
1087 assert(stage
== MESA_SHADER_COMPUTE
);
1089 /* We can't directly send from g0, since sends with EOT have to use
1090 * g112-127. So, copy it to a virtual register, The register allocator will
1091 * make sure it uses the appropriate register range.
1093 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1094 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1095 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
1097 /* Send a message to the thread spawner to terminate the thread. */
1098 fs_inst
*inst
= bld
.exec_all()
1099 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1104 fs_visitor::emit_barrier()
1106 assert(devinfo
->gen
>= 7);
1108 /* We are getting the barrier ID from the compute shader header */
1109 assert(stage
== MESA_SHADER_COMPUTE
);
1111 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1113 const fs_builder pbld
= bld
.exec_all().group(8, 0);
1115 /* Clear the message payload */
1116 pbld
.MOV(payload
, fs_reg(0u));
1118 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1119 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1120 pbld
.AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1122 /* Emit a gateway "barrier" message using the payload we set up, followed
1123 * by a wait instruction.
1125 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1128 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1131 struct brw_stage_prog_data
*prog_data
,
1132 struct gl_program
*prog
,
1133 const nir_shader
*shader
,
1134 unsigned dispatch_width
,
1135 int shader_time_index
)
1136 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
1137 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
1138 dispatch_width(dispatch_width
),
1139 shader_time_index(shader_time_index
),
1140 bld(fs_builder(this, dispatch_width
).at_end())
1145 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1147 struct brw_gs_compile
*c
,
1148 struct brw_gs_prog_data
*prog_data
,
1149 const nir_shader
*shader
,
1150 int shader_time_index
)
1151 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
1152 &prog_data
->base
.base
),
1153 key(&c
->key
), gs_compile(c
),
1154 prog_data(&prog_data
->base
.base
), prog(NULL
),
1156 shader_time_index(shader_time_index
),
1157 bld(fs_builder(this, dispatch_width
).at_end())
1167 case MESA_SHADER_FRAGMENT
:
1168 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1170 case MESA_SHADER_VERTEX
:
1171 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
1173 case MESA_SHADER_GEOMETRY
:
1174 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
1176 case MESA_SHADER_COMPUTE
:
1177 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1180 unreachable("unhandled shader stage");
1183 this->prog_data
= this->stage_prog_data
;
1185 this->failed
= false;
1186 this->simd16_unsupported
= false;
1187 this->no16_msg
= NULL
;
1189 this->nir_locals
= NULL
;
1190 this->nir_ssa_values
= NULL
;
1192 memset(&this->payload
, 0, sizeof(this->payload
));
1193 memset(this->output_components
, 0, sizeof(this->output_components
));
1194 this->source_depth_to_render_target
= false;
1195 this->runtime_check_aads_emit
= false;
1196 this->first_non_payload_grf
= 0;
1197 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1199 this->virtual_grf_start
= NULL
;
1200 this->virtual_grf_end
= NULL
;
1201 this->live_intervals
= NULL
;
1202 this->regs_live_at_ip
= NULL
;
1205 this->last_scratch
= 0;
1206 this->pull_constant_loc
= NULL
;
1207 this->push_constant_loc
= NULL
;
1209 this->promoted_constants
= 0,
1211 this->spilled_any_registers
= false;
1212 this->do_dual_src
= false;
1214 if (dispatch_width
== 8)
1215 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1218 fs_visitor::~fs_visitor()