2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
82 bool is_rect
, uint32_t sampler
)
84 bool needs_gl_clamp
= true;
85 fs_reg scale_x
, scale_y
;
87 /* The 965 requires the EU to do the normalization of GL rectangle
88 * texture coordinates. We use the program parameter state
89 * tracking to get the scaling factor.
93 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
94 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
95 struct gl_program_parameter_list
*params
= prog
->Parameters
;
98 /* FINISHME: We're failing to recompile our programs when the sampler is
99 * updated. This only matters for the texture rectangle scale
100 * parameters (pre-gen6, or gen6+ with GL_CLAMP).
102 int tokens
[STATE_LENGTH
] = {
105 prog
->SamplerUnits
[sampler
],
110 no16("rectangle scale uniform setup not supported on SIMD16\n");
111 if (dispatch_width
== 16) {
115 GLuint index
= _mesa_add_state_reference(params
,
116 (gl_state_index
*)tokens
);
117 /* Try to find existing copies of the texrect scale uniforms. */
118 for (unsigned i
= 0; i
< uniforms
; i
++) {
119 if (stage_prog_data
->param
[i
] ==
120 &prog
->Parameters
->ParameterValues
[index
][0]) {
121 scale_x
= fs_reg(UNIFORM
, i
);
122 scale_y
= fs_reg(UNIFORM
, i
+ 1);
127 /* If we didn't already set them up, do so now. */
128 if (scale_x
.file
== BAD_FILE
) {
129 scale_x
= fs_reg(UNIFORM
, uniforms
);
130 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
132 stage_prog_data
->param
[uniforms
++] =
133 &prog
->Parameters
->ParameterValues
[index
][0];
134 stage_prog_data
->param
[uniforms
++] =
135 &prog
->Parameters
->ParameterValues
[index
][1];
139 /* The 965 requires the EU to do the normalization of GL rectangle
140 * texture coordinates. We use the program parameter state
141 * tracking to get the scaling factor.
143 if (devinfo
->gen
< 6 && is_rect
) {
144 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
145 fs_reg src
= coordinate
;
148 bld
.MUL(dst
, src
, scale_x
);
149 dst
= offset(dst
, bld
, 1);
150 src
= offset(src
, bld
, 1);
151 bld
.MUL(dst
, src
, scale_y
);
152 } else if (is_rect
) {
153 /* On gen6+, the sampler handles the rectangle coordinates
154 * natively, without needing rescaling. But that means we have
155 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
156 * not [0, 1] like the default case below.
158 needs_gl_clamp
= false;
160 for (int i
= 0; i
< 2; i
++) {
161 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
162 fs_reg chan
= coordinate
;
163 chan
= offset(chan
, bld
, i
);
165 set_condmod(BRW_CONDITIONAL_GE
,
166 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
168 /* Our parameter comes in as 1.0/width or 1.0/height,
169 * because that's what people normally want for doing
170 * texture rectangle handling. We need width or height
171 * for clamping, but we don't care enough to make a new
172 * parameter type, so just invert back.
174 fs_reg limit
= vgrf(glsl_type::float_type
);
175 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
176 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
178 set_condmod(BRW_CONDITIONAL_L
,
179 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
184 if (coord_components
> 0 && needs_gl_clamp
) {
185 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
186 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
187 fs_reg chan
= coordinate
;
188 chan
= offset(chan
, bld
, i
);
189 set_saturate(true, bld
.MOV(chan
, chan
));
196 /* Sample from the MCS surface attached to this multisample texture. */
198 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
199 const fs_reg
&sampler
)
201 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
202 const fs_reg srcs
[] = {
203 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
204 sampler
, fs_reg(), fs_reg(components
), fs_reg(0)
206 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
209 /* We only care about one reg of response, but the sampler always writes
212 inst
->regs_written
= 4 * dispatch_width
/ 8;
218 fs_visitor::emit_texture(ir_texture_opcode op
,
219 const glsl_type
*dest_type
,
220 fs_reg coordinate
, int coord_components
,
222 fs_reg lod
, fs_reg lod2
, int grad_components
,
226 int gather_component
,
232 fs_inst
*inst
= NULL
;
235 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
236 * emitting anything other than setting up the constant result.
238 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
239 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
241 fs_reg res
= vgrf(glsl_type::vec4_type
);
244 for (int i
=0; i
<4; i
++) {
245 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
246 res
= offset(res
, bld
, 1);
252 if (op
== ir_query_levels
) {
253 /* textureQueryLevels() is implemented in terms of TXS so we need to
254 * pass a valid LOD argument.
256 assert(lod
.file
== BAD_FILE
);
260 if (coordinate
.file
!= BAD_FILE
) {
261 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
262 * samplers. This should only be a problem with GL_CLAMP on Gen7.
264 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
268 /* Writemasking doesn't eliminate channels on SIMD8 texture
269 * samples, so don't worry about them.
271 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
272 const fs_reg srcs
[] = {
273 coordinate
, shadow_c
, lod
, lod2
,
274 sample_index
, mcs
, sampler_reg
, offset_value
,
275 fs_reg(coord_components
), fs_reg(grad_components
)
281 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
284 opcode
= FS_OPCODE_TXB_LOGICAL
;
287 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
290 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
293 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
296 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
299 case ir_query_levels
:
300 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
303 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
306 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
307 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
310 unreachable("Invalid texture opcode.");
313 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
314 inst
->regs_written
= 4 * dispatch_width
/ 8;
316 if (shadow_c
.file
!= BAD_FILE
)
317 inst
->shadow_compare
= true;
319 if (offset_value
.file
== IMM
)
320 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
324 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
326 if (devinfo
->gen
== 6)
327 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
330 /* fixup #layers for cube map arrays */
331 if (op
== ir_txs
&& is_cube_array
) {
332 fs_reg depth
= offset(dst
, bld
, 2);
333 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
334 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
336 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
337 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
338 for (int i
= 0; i
< components
; i
++) {
340 fixed_payload
[i
] = fixed_depth
;
342 fixed_payload
[i
] = offset(dst
, bld
, i
);
345 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
348 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
352 * Apply workarounds for Gen6 gather with UINT/SINT
355 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
360 int width
= (wa
& WA_8BIT
) ? 8 : 16;
362 for (int i
= 0; i
< 4; i
++) {
363 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
364 /* Convert from UNORM to UINT */
365 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
369 /* Reinterpret the UINT value as a signed INT value by
370 * shifting the sign bit into place, then shifting back
373 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
374 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
377 dst
= offset(dst
, bld
, 1);
382 * Set up the gather channel based on the swizzle, for gather4.
385 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
387 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
389 case SWIZZLE_X
: return 0;
391 /* gather4 sampler is broken for green channel on RG32F --
392 * we must ask for blue instead.
394 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
397 case SWIZZLE_Z
: return 2;
398 case SWIZZLE_W
: return 3;
400 unreachable("Not reached"); /* zero, one swizzles handled already */
405 * Swizzle the result of a texture result. This is necessary for
406 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
409 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
410 fs_reg orig_val
, uint32_t sampler
)
412 if (op
== ir_query_levels
) {
413 /* # levels is in .w */
414 this->result
= offset(orig_val
, bld
, 3);
418 this->result
= orig_val
;
420 /* txs,lod don't actually sample the texture, so swizzling the result
423 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
426 if (dest_components
== 1) {
427 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
428 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
429 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
430 swizzled_result
.type
= orig_val
.type
;
432 for (int i
= 0; i
< 4; i
++) {
433 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
434 fs_reg l
= swizzled_result
;
435 l
= offset(l
, bld
, i
);
437 if (swiz
== SWIZZLE_ZERO
) {
438 bld
.MOV(l
, fs_reg(0.0f
));
439 } else if (swiz
== SWIZZLE_ONE
) {
440 bld
.MOV(l
, fs_reg(1.0f
));
442 bld
.MOV(l
, offset(orig_val
, bld
,
443 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
446 this->result
= swizzled_result
;
450 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
452 fs_visitor::emit_dummy_fs()
454 int reg_width
= dispatch_width
/ 8;
456 /* Everyone's favorite color. */
457 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
458 for (int i
= 0; i
< 4; i
++) {
459 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
464 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
466 if (devinfo
->gen
>= 6) {
468 write
->mlen
= 4 * reg_width
;
470 write
->header_size
= 2;
472 write
->mlen
= 2 + 4 * reg_width
;
475 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
476 * varying to avoid GPU hangs, so set that.
478 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
479 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
480 memset(wm_prog_data
->urb_setup
, -1,
481 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
483 /* We don't have any uniforms. */
484 stage_prog_data
->nr_params
= 0;
485 stage_prog_data
->nr_pull_params
= 0;
486 stage_prog_data
->curb_read_length
= 0;
487 stage_prog_data
->dispatch_grf_start_reg
= 2;
488 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
489 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
494 /* The register location here is relative to the start of the URB
495 * data. It will get adjusted to be a real location before
496 * generate_code() time.
499 fs_visitor::interp_reg(int location
, int channel
)
501 assert(stage
== MESA_SHADER_FRAGMENT
);
502 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
503 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
504 int stride
= (channel
& 1) * 4;
506 assert(prog_data
->urb_setup
[location
] != -1);
508 return brw_vec1_grf(regnr
, stride
);
511 /** Emits the interpolation for the varying inputs. */
513 fs_visitor::emit_interpolation_setup_gen4()
515 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
517 fs_builder abld
= bld
.annotate("compute pixel centers");
518 this->pixel_x
= vgrf(glsl_type::uint_type
);
519 this->pixel_y
= vgrf(glsl_type::uint_type
);
520 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
521 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
522 abld
.ADD(this->pixel_x
,
523 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
524 fs_reg(brw_imm_v(0x10101010)));
525 abld
.ADD(this->pixel_y
,
526 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
527 fs_reg(brw_imm_v(0x11001100)));
529 abld
= bld
.annotate("compute pixel deltas from v0");
531 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
532 vgrf(glsl_type::vec2_type
);
533 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
534 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
535 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
537 if (devinfo
->has_pln
&& dispatch_width
== 16) {
538 for (unsigned i
= 0; i
< 2; i
++) {
539 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
540 half(this->pixel_x
, i
), xstart
);
541 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
542 half(this->pixel_y
, i
), ystart
);
545 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
546 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
549 abld
= bld
.annotate("compute pos.w and 1/pos.w");
550 /* Compute wpos.w. It's always in our setup, since it's needed to
551 * interpolate the other attributes.
553 this->wpos_w
= vgrf(glsl_type::float_type
);
554 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
555 interp_reg(VARYING_SLOT_POS
, 3));
556 /* Compute the pixel 1/W value from wpos.w. */
557 this->pixel_w
= vgrf(glsl_type::float_type
);
558 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
561 /** Emits the interpolation for the varying inputs. */
563 fs_visitor::emit_interpolation_setup_gen6()
565 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
567 fs_builder abld
= bld
.annotate("compute pixel centers");
568 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
569 /* The "Register Region Restrictions" page says for BDW (and newer,
572 * "When destination spans two registers, the source may be one or
573 * two registers. The destination elements must be evenly split
574 * between the two registers."
576 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
577 * compute our pixel centers.
579 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
580 BRW_REGISTER_TYPE_UW
);
582 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
583 dbld
.ADD(int_pixel_xy
,
584 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
585 fs_reg(brw_imm_v(0x11001010)));
587 this->pixel_x
= vgrf(glsl_type::float_type
);
588 this->pixel_y
= vgrf(glsl_type::float_type
);
589 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
590 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
592 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
594 * "When destination spans two registers, the source MUST span two
597 * Since the GRF source of the ADD will only read a single register, we
598 * must do two separate ADDs in SIMD16.
600 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
601 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
602 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
603 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
604 abld
.ADD(int_pixel_x
,
605 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
606 fs_reg(brw_imm_v(0x10101010)));
607 abld
.ADD(int_pixel_y
,
608 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
609 fs_reg(brw_imm_v(0x11001100)));
611 /* As of gen6, we can no longer mix float and int sources. We have
612 * to turn the integer pixel centers into floats for their actual
615 this->pixel_x
= vgrf(glsl_type::float_type
);
616 this->pixel_y
= vgrf(glsl_type::float_type
);
617 abld
.MOV(this->pixel_x
, int_pixel_x
);
618 abld
.MOV(this->pixel_y
, int_pixel_y
);
621 abld
= bld
.annotate("compute pos.w");
622 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
623 this->wpos_w
= vgrf(glsl_type::float_type
);
624 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
626 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
627 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
628 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
632 static enum brw_conditional_mod
633 cond_for_alpha_func(GLenum func
)
637 return BRW_CONDITIONAL_G
;
639 return BRW_CONDITIONAL_GE
;
641 return BRW_CONDITIONAL_L
;
643 return BRW_CONDITIONAL_LE
;
645 return BRW_CONDITIONAL_EQ
;
647 return BRW_CONDITIONAL_NEQ
;
649 unreachable("Not reached");
654 * Alpha test support for when we compile it into the shader instead
655 * of using the normal fixed-function alpha test.
658 fs_visitor::emit_alpha_test()
660 assert(stage
== MESA_SHADER_FRAGMENT
);
661 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
662 const fs_builder abld
= bld
.annotate("Alpha test");
665 if (key
->alpha_test_func
== GL_ALWAYS
)
668 if (key
->alpha_test_func
== GL_NEVER
) {
670 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
671 BRW_REGISTER_TYPE_UW
));
672 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
673 BRW_CONDITIONAL_NEQ
);
676 fs_reg color
= offset(outputs
[0], bld
, 3);
678 /* f0.1 &= func(color, ref) */
679 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
680 cond_for_alpha_func(key
->alpha_test_func
));
682 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
683 cmp
->flag_subreg
= 1;
687 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
688 fs_reg color0
, fs_reg color1
,
689 fs_reg src0_alpha
, unsigned components
)
691 assert(stage
== MESA_SHADER_FRAGMENT
);
692 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
694 /* Hand over gl_FragDepth or the payload depth. */
695 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
696 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
700 if (source_depth_to_render_target
) {
701 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
702 src_depth
= frag_depth
;
704 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
707 const fs_reg sources
[] = {
708 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, sample_mask
,
711 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
712 sources
, ARRAY_SIZE(sources
));
714 if (prog_data
->uses_kill
) {
715 write
->predicate
= BRW_PREDICATE_NORMAL
;
716 write
->flag_subreg
= 1;
723 fs_visitor::emit_fb_writes()
725 assert(stage
== MESA_SHADER_FRAGMENT
);
726 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
727 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
729 fs_inst
*inst
= NULL
;
731 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
732 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
733 * would require SIMD8 moves of each half to message regs, e.g. by using
734 * the SIMD lowering pass. Unfortunately this is more difficult than it
735 * sounds because the SIMD8 single-source message lacks channel selects
736 * for the second and third subspans.
738 no16("Missing support for simd16 depth writes on gen6\n");
742 const fs_builder abld
= bld
.annotate("FB dual-source write");
744 inst
= emit_single_fb_write(abld
, this->outputs
[0],
745 this->dual_src_output
, reg_undef
, 4);
748 prog_data
->dual_src_blend
= true;
750 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
751 /* Skip over outputs that weren't written. */
752 if (this->outputs
[target
].file
== BAD_FILE
)
755 const fs_builder abld
= bld
.annotate(
756 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
759 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
760 src0_alpha
= offset(outputs
[0], bld
, 3);
762 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
764 this->output_components
[target
]);
765 inst
->target
= target
;
770 /* Even if there's no color buffers enabled, we still need to send
771 * alpha out the pipeline to our null renderbuffer to support
772 * alpha-testing, alpha-to-coverage, and so on.
774 /* FINISHME: Factor out this frequently recurring pattern into a
777 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
778 reg_undef
, offset(this->outputs
[0], bld
, 3) };
779 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
780 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
782 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
790 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
792 const struct brw_vs_prog_key
*key
=
793 (const struct brw_vs_prog_key
*) this->key
;
795 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
796 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
797 for (int j
= 0; j
< 4; ++j
) {
798 stage_prog_data
->param
[uniforms
+ j
] =
799 (gl_constant_value
*) &clip_planes
[i
][j
];
806 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
808 * This does nothing if the shader uses gl_ClipDistance or user clipping is
809 * disabled altogether.
811 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
813 struct brw_vue_prog_data
*vue_prog_data
=
814 (struct brw_vue_prog_data
*) prog_data
;
815 const struct brw_vs_prog_key
*key
=
816 (const struct brw_vs_prog_key
*) this->key
;
818 /* Bail unless some sort of legacy clipping is enabled */
819 if (key
->nr_userclip_plane_consts
== 0)
822 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
824 * "If a linked set of shaders forming the vertex stage contains no
825 * static write to gl_ClipVertex or gl_ClipDistance, but the
826 * application has requested clipping against user clip planes through
827 * the API, then the coordinate written to gl_Position is used for
828 * comparison against the user clip planes."
830 * This function is only called if the shader didn't write to
831 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
832 * if the user wrote to it; otherwise we use gl_Position.
835 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
836 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
837 clip_vertex
= VARYING_SLOT_POS
;
839 /* If the clip vertex isn't written, skip this. Typically this means
840 * the GS will set up clipping. */
841 if (outputs
[clip_vertex
].file
== BAD_FILE
)
844 setup_uniform_clipplane_values(clip_planes
);
846 const fs_builder abld
= bld
.annotate("user clip distances");
848 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
849 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
850 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
851 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
853 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
854 fs_reg u
= userplane
[i
];
855 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
856 output
.reg_offset
= i
& 3;
858 abld
.MUL(output
, outputs
[clip_vertex
], u
);
859 for (int j
= 1; j
< 4; j
++) {
860 u
.reg
= userplane
[i
].reg
+ j
;
861 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
867 fs_visitor::emit_urb_writes()
869 int slot
, urb_offset
, length
;
870 struct brw_vs_prog_data
*vs_prog_data
=
871 (struct brw_vs_prog_data
*) prog_data
;
872 const struct brw_vs_prog_key
*key
=
873 (const struct brw_vs_prog_key
*) this->key
;
874 const GLbitfield64 psiz_mask
=
875 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
876 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
880 /* If we don't have any valid slots to write, just do a minimal urb write
881 * send to terminate the shader. This includes 1 slot of undefined data,
882 * because it's invalid to write 0 data:
884 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
885 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
886 * Write Data Payload:
888 * "The write data payload can be between 1 and 8 message phases long."
890 if (vue_map
->slots_valid
== 0) {
891 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
892 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
893 BRW_REGISTER_TYPE_UD
)));
895 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
905 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
906 fs_reg reg
, src
, zero
;
908 int varying
= vue_map
->slot_to_varying
[slot
];
910 case VARYING_SLOT_PSIZ
:
912 /* The point size varying slot is the vue header and is always in the
913 * vue map. But often none of the special varyings that live there
914 * are written and in that case we can skip writing to the vue
915 * header, provided the corresponding state properly clamps the
916 * values further down the pipeline. */
917 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
923 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
924 bld
.MOV(zero
, fs_reg(0u));
926 sources
[length
++] = zero
;
927 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
928 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
930 sources
[length
++] = zero
;
932 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
933 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
935 sources
[length
++] = zero
;
937 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
938 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
940 sources
[length
++] = zero
;
943 case BRW_VARYING_SLOT_NDC
:
944 case VARYING_SLOT_EDGE
:
945 unreachable("unexpected scalar vs output");
949 /* gl_Position is always in the vue map, but isn't always written by
950 * the shader. Other varyings (clip distances) get added to the vue
951 * map but don't always get written. In those cases, the
952 * corresponding this->output[] slot will be invalid we and can skip
953 * the urb write for the varying. If we've already queued up a vue
954 * slot for writing we flush a mlen 5 urb write, otherwise we just
955 * advance the urb_offset.
957 if (varying
== BRW_VARYING_SLOT_PAD
||
958 this->outputs
[varying
].file
== BAD_FILE
) {
966 if ((varying
== VARYING_SLOT_COL0
||
967 varying
== VARYING_SLOT_COL1
||
968 varying
== VARYING_SLOT_BFC0
||
969 varying
== VARYING_SLOT_BFC1
) &&
970 key
->clamp_vertex_color
) {
971 /* We need to clamp these guys, so do a saturating MOV into a
972 * temp register and use that for the payload.
974 for (int i
= 0; i
< 4; i
++) {
975 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
976 src
= offset(this->outputs
[varying
], bld
, i
);
977 set_saturate(true, bld
.MOV(reg
, src
));
978 sources
[length
++] = reg
;
981 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
982 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
983 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
984 sources
[length
++] = fs_reg(0);
989 const fs_builder abld
= bld
.annotate("URB write");
991 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
992 * the last slot or if we need to flush (see BAD_FILE varying case
993 * above), emit a URB write send now to flush out the data.
995 int last
= slot
== vue_map
->num_slots
- 1;
996 if (length
== 8 || last
)
999 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
1000 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
1001 BRW_REGISTER_TYPE_F
);
1002 payload_sources
[0] =
1003 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1005 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
1006 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1009 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1011 inst
->mlen
= length
+ 1;
1012 inst
->offset
= urb_offset
;
1013 urb_offset
= slot
+ 1;
1021 fs_visitor::emit_cs_terminate()
1023 assert(devinfo
->gen
>= 7);
1025 /* We are getting the thread ID from the compute shader header */
1026 assert(stage
== MESA_SHADER_COMPUTE
);
1028 /* We can't directly send from g0, since sends with EOT have to use
1029 * g112-127. So, copy it to a virtual register, The register allocator will
1030 * make sure it uses the appropriate register range.
1032 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1033 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1034 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
1036 /* Send a message to the thread spawner to terminate the thread. */
1037 fs_inst
*inst
= bld
.exec_all()
1038 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1043 fs_visitor::emit_barrier()
1045 assert(devinfo
->gen
>= 7);
1047 /* We are getting the barrier ID from the compute shader header */
1048 assert(stage
== MESA_SHADER_COMPUTE
);
1050 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1052 const fs_builder pbld
= bld
.exec_all().group(8, 0);
1054 /* Clear the message payload */
1055 pbld
.MOV(payload
, fs_reg(0u));
1057 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1058 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1059 pbld
.AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1061 /* Emit a gateway "barrier" message using the payload we set up, followed
1062 * by a wait instruction.
1064 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1067 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1069 gl_shader_stage stage
,
1071 struct brw_stage_prog_data
*prog_data
,
1072 struct gl_shader_program
*shader_prog
,
1073 struct gl_program
*prog
,
1074 unsigned dispatch_width
,
1075 int shader_time_index
)
1076 : backend_shader(compiler
, log_data
, mem_ctx
,
1077 shader_prog
, prog
, prog_data
, stage
),
1078 key(key
), prog_data(prog_data
),
1079 dispatch_width(dispatch_width
),
1080 shader_time_index(shader_time_index
),
1081 promoted_constants(0),
1082 bld(fs_builder(this, dispatch_width
).at_end())
1085 case MESA_SHADER_FRAGMENT
:
1086 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1088 case MESA_SHADER_VERTEX
:
1089 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
1091 case MESA_SHADER_GEOMETRY
:
1092 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
1094 case MESA_SHADER_COMPUTE
:
1095 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1098 unreachable("unhandled shader stage");
1101 this->failed
= false;
1102 this->simd16_unsupported
= false;
1103 this->no16_msg
= NULL
;
1105 this->nir_locals
= NULL
;
1106 this->nir_ssa_values
= NULL
;
1108 memset(&this->payload
, 0, sizeof(this->payload
));
1109 memset(this->outputs
, 0, sizeof(this->outputs
));
1110 memset(this->output_components
, 0, sizeof(this->output_components
));
1111 this->source_depth_to_render_target
= false;
1112 this->runtime_check_aads_emit
= false;
1113 this->first_non_payload_grf
= 0;
1114 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1116 this->virtual_grf_start
= NULL
;
1117 this->virtual_grf_end
= NULL
;
1118 this->live_intervals
= NULL
;
1119 this->regs_live_at_ip
= NULL
;
1122 this->last_scratch
= 0;
1123 this->pull_constant_loc
= NULL
;
1124 this->push_constant_loc
= NULL
;
1126 this->spilled_any_registers
= false;
1127 this->do_dual_src
= false;
1129 if (dispatch_width
== 8)
1130 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1133 fs_visitor::~fs_visitor()