2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
53 fs_visitor::emit_vs_system_value(int location
)
55 fs_reg
*reg
= new(this->mem_ctx
)
56 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
57 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
60 case SYSTEM_VALUE_BASE_VERTEX
:
62 vs_prog_data
->uses_vertexid
= true;
64 case SYSTEM_VALUE_VERTEX_ID
:
65 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
67 vs_prog_data
->uses_vertexid
= true;
69 case SYSTEM_VALUE_INSTANCE_ID
:
71 vs_prog_data
->uses_instanceid
= true;
74 unreachable("not reached");
81 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
82 fs_reg coordinate
, int coord_components
,
84 fs_reg lod
, fs_reg dPdy
, int grad_components
,
95 if (shadow_c
.file
!= BAD_FILE
) {
96 for (int i
= 0; i
< coord_components
; i
++) {
97 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
98 coordinate
= offset(coordinate
, bld
, 1);
101 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
102 * the unused slots must be zeroed.
104 for (int i
= coord_components
; i
< 3; i
++) {
105 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
110 /* There's no plain shadow compare message, so we use shadow
111 * compare with a bias of 0.0.
113 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
115 } else if (op
== ir_txb
|| op
== ir_txl
) {
116 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
);
119 unreachable("Should not get here.");
122 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
);
124 } else if (op
== ir_tex
) {
125 for (int i
= 0; i
< coord_components
; i
++) {
126 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
127 coordinate
= offset(coordinate
, bld
, 1);
129 /* zero the others. */
130 for (int i
= coord_components
; i
<3; i
++) {
131 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
));
133 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
135 } else if (op
== ir_txd
) {
138 for (int i
= 0; i
< coord_components
; i
++) {
139 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
140 coordinate
= offset(coordinate
, bld
, 1);
142 /* the slots for u and v are always present, but r is optional */
143 mlen
+= MAX2(coord_components
, 2);
146 * dPdx = dudx, dvdx, drdx
147 * dPdy = dudy, dvdy, drdy
149 * 1-arg: Does not exist.
151 * 2-arg: dudx dvdx dudy dvdy
152 * dPdx.x dPdx.y dPdy.x dPdy.y
155 * 3-arg: dudx dvdx drdx dudy dvdy drdy
156 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
159 for (int i
= 0; i
< grad_components
; i
++) {
160 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
161 dPdx
= offset(dPdx
, bld
, 1);
163 mlen
+= MAX2(grad_components
, 2);
165 for (int i
= 0; i
< grad_components
; i
++) {
166 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
167 dPdy
= offset(dPdy
, bld
, 1);
169 mlen
+= MAX2(grad_components
, 2);
170 } else if (op
== ir_txs
) {
171 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
173 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
);
176 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
177 * instructions. We'll need to do SIMD16 here.
180 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
182 for (int i
= 0; i
< coord_components
; i
++) {
183 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
185 coordinate
= offset(coordinate
, bld
, 1);
188 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
189 * be necessary for TXF (ld), but seems wise to do for all messages.
191 for (int i
= coord_components
; i
< 3; i
++) {
192 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
195 /* lod/bias appears after u/v/r. */
198 bld
.MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
);
201 /* The unused upper half. */
206 /* Now, since we're doing simd16, the return is 2 interleaved
207 * vec4s where the odd-indexed ones are junk. We'll need to move
208 * this weirdness around to the expected layout.
211 dst
= fs_reg(GRF
, alloc
.allocate(8), orig_dst
.type
);
216 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
217 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
218 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
219 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
220 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
221 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
223 unreachable("not reached");
226 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
227 inst
->base_mrf
= base_mrf
;
229 inst
->header_size
= 1;
230 inst
->regs_written
= simd16
? 8 : 4;
233 for (int i
= 0; i
< 4; i
++) {
234 bld
.MOV(orig_dst
, dst
);
235 orig_dst
= offset(orig_dst
, bld
, 1);
236 dst
= offset(dst
, bld
, 2);
244 fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op
, fs_reg dst
,
245 fs_reg coordinate
, int vector_elements
,
246 fs_reg shadow_c
, fs_reg lod
,
249 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
250 bool has_lod
= op
== ir_txl
|| op
== ir_txb
|| op
== ir_txf
|| op
== ir_txs
;
252 if (has_lod
&& shadow_c
.file
!= BAD_FILE
)
253 no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
256 no16("textureGrad unsupported in SIMD16.");
258 /* Copy the coordinates. */
259 for (int i
= 0; i
< vector_elements
; i
++) {
260 bld
.MOV(retype(offset(message
, bld
, i
), coordinate
.type
), coordinate
);
261 coordinate
= offset(coordinate
, bld
, 1);
264 fs_reg msg_end
= offset(message
, bld
, vector_elements
);
266 /* Messages other than sample and ld require all three components */
267 if (vector_elements
> 0 && (has_lod
|| shadow_c
.file
!= BAD_FILE
)) {
268 for (int i
= vector_elements
; i
< 3; i
++) {
269 bld
.MOV(offset(message
, bld
, i
), fs_reg(0.0f
));
271 msg_end
= offset(message
, bld
, 3);
275 fs_reg msg_lod
= retype(msg_end
, op
== ir_txf
?
276 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
277 bld
.MOV(msg_lod
, lod
);
278 msg_end
= offset(msg_lod
, bld
, 1);
281 if (shadow_c
.file
!= BAD_FILE
) {
282 fs_reg msg_ref
= offset(message
, bld
, 3 + has_lod
);
283 bld
.MOV(msg_ref
, shadow_c
);
284 msg_end
= offset(msg_ref
, bld
, 1);
289 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
290 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
291 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
292 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
293 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
294 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
295 default: unreachable("not reached");
298 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
299 inst
->base_mrf
= message
.reg
- 1;
300 inst
->mlen
= msg_end
.reg
- inst
->base_mrf
;
301 inst
->header_size
= 1;
302 inst
->regs_written
= 8;
307 /* gen5's sampler has slots for u, v, r, array index, then optional
308 * parameters like shadow comparitor or LOD bias. If optional
309 * parameters aren't present, those base slots are optional and don't
310 * need to be included in the message.
312 * We don't fill in the unnecessary slots regardless, which may look
313 * surprising in the disassembly.
316 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
317 fs_reg coordinate
, int vector_elements
,
319 fs_reg lod
, fs_reg lod2
, int grad_components
,
320 fs_reg sample_index
, uint32_t sampler
,
323 int reg_width
= dispatch_width
/ 8;
324 unsigned header_size
= 0;
326 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
327 fs_reg msg_coords
= message
;
330 /* The offsets set up by the ir_texture visitor are in the
331 * m1 header, so we can't go headerless.
337 for (int i
= 0; i
< vector_elements
; i
++) {
338 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
339 coordinate
= offset(coordinate
, bld
, 1);
341 fs_reg msg_end
= offset(msg_coords
, bld
, vector_elements
);
342 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
344 if (shadow_c
.file
!= BAD_FILE
) {
345 fs_reg msg_shadow
= msg_lod
;
346 bld
.MOV(msg_shadow
, shadow_c
);
347 msg_lod
= offset(msg_shadow
, bld
, 1);
354 opcode
= SHADER_OPCODE_TEX
;
357 bld
.MOV(msg_lod
, lod
);
358 msg_end
= offset(msg_lod
, bld
, 1);
360 opcode
= FS_OPCODE_TXB
;
363 bld
.MOV(msg_lod
, lod
);
364 msg_end
= offset(msg_lod
, bld
, 1);
366 opcode
= SHADER_OPCODE_TXL
;
371 * dPdx = dudx, dvdx, drdx
372 * dPdy = dudy, dvdy, drdy
374 * Load up these values:
375 * - dudx dudy dvdx dvdy drdx drdy
376 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
379 for (int i
= 0; i
< grad_components
; i
++) {
380 bld
.MOV(msg_end
, lod
);
381 lod
= offset(lod
, bld
, 1);
382 msg_end
= offset(msg_end
, bld
, 1);
384 bld
.MOV(msg_end
, lod2
);
385 lod2
= offset(lod2
, bld
, 1);
386 msg_end
= offset(msg_end
, bld
, 1);
389 opcode
= SHADER_OPCODE_TXD
;
393 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
394 bld
.MOV(msg_lod
, lod
);
395 msg_end
= offset(msg_lod
, bld
, 1);
397 opcode
= SHADER_OPCODE_TXS
;
399 case ir_query_levels
:
401 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
402 msg_end
= offset(msg_lod
, bld
, 1);
404 opcode
= SHADER_OPCODE_TXS
;
407 msg_lod
= offset(msg_coords
, bld
, 3);
408 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
409 msg_end
= offset(msg_lod
, bld
, 1);
411 opcode
= SHADER_OPCODE_TXF
;
414 msg_lod
= offset(msg_coords
, bld
, 3);
416 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
418 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
419 msg_end
= offset(msg_lod
, bld
, 2);
421 opcode
= SHADER_OPCODE_TXF_CMS
;
424 opcode
= SHADER_OPCODE_LOD
;
427 opcode
= SHADER_OPCODE_TG4
;
430 unreachable("not reached");
433 fs_inst
*inst
= bld
.emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
434 inst
->base_mrf
= message
.reg
;
435 inst
->mlen
= msg_end
.reg
- message
.reg
;
436 inst
->header_size
= header_size
;
437 inst
->regs_written
= 4 * reg_width
;
439 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
440 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
441 " disallowed by hardware\n");
448 is_high_sampler(const struct brw_device_info
*devinfo
, fs_reg sampler
)
450 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
453 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
457 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
458 fs_reg coordinate
, int coord_components
,
460 fs_reg lod
, fs_reg lod2
, int grad_components
,
461 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
464 int reg_width
= dispatch_width
/ 8;
465 unsigned header_size
= 0;
467 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
468 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
469 sources
[i
] = vgrf(glsl_type::float_type
);
473 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
474 is_high_sampler(devinfo
, sampler
)) {
475 /* For general texture offsets (no txf workaround), we need a header to
476 * put them in. Note that we're only reserving space for it in the
477 * message payload as it will be initialized implicitly by the
480 * * ir4_tg4 needs to place its channel select in the header,
481 * for interaction with ARB_texture_swizzle
483 * The sampler index is only 4-bits, so for larger sampler numbers we
484 * need to offset the Sampler State Pointer in the header.
487 sources
[0] = fs_reg();
491 if (shadow_c
.file
!= BAD_FILE
) {
492 bld
.MOV(sources
[length
], shadow_c
);
496 bool has_nonconstant_offset
=
497 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
498 bool coordinate_done
= false;
500 /* The sampler can only meaningfully compute LOD for fragment shader
501 * messages. For all other stages, we change the opcode to ir_txl and
502 * hardcode the LOD to 0.
504 if (stage
!= MESA_SHADER_FRAGMENT
&& op
== ir_tex
) {
509 /* Set up the LOD info */
515 bld
.MOV(sources
[length
], lod
);
519 bld
.MOV(sources
[length
], lod
);
523 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
525 /* Load dPdx and the coordinate together:
526 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
528 for (int i
= 0; i
< coord_components
; i
++) {
529 bld
.MOV(sources
[length
], coordinate
);
530 coordinate
= offset(coordinate
, bld
, 1);
533 /* For cube map array, the coordinate is (u,v,r,ai) but there are
534 * only derivatives for (u, v, r).
536 if (i
< grad_components
) {
537 bld
.MOV(sources
[length
], lod
);
538 lod
= offset(lod
, bld
, 1);
541 bld
.MOV(sources
[length
], lod2
);
542 lod2
= offset(lod2
, bld
, 1);
547 coordinate_done
= true;
551 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
554 case ir_query_levels
:
555 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u));
559 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
560 * On Gen9 they are u, v, lod, r
563 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
564 coordinate
= offset(coordinate
, bld
, 1);
567 if (devinfo
->gen
>= 9) {
568 if (coord_components
>= 2) {
569 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
570 coordinate
= offset(coordinate
, bld
, 1);
575 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
578 for (int i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
579 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
580 coordinate
= offset(coordinate
, bld
, 1);
584 coordinate_done
= true;
587 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
590 /* data from the multisample control surface */
591 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
594 /* there is no offsetting for this message; just copy in the integer
595 * texture coordinates
597 for (int i
= 0; i
< coord_components
; i
++) {
598 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
599 coordinate
= offset(coordinate
, bld
, 1);
603 coordinate_done
= true;
606 if (has_nonconstant_offset
) {
607 if (shadow_c
.file
!= BAD_FILE
)
608 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
610 /* More crazy intermixing */
611 for (int i
= 0; i
< 2; i
++) { /* u, v */
612 bld
.MOV(sources
[length
], coordinate
);
613 coordinate
= offset(coordinate
, bld
, 1);
617 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
618 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
619 offset_value
= offset(offset_value
, bld
, 1);
623 if (coord_components
== 3) { /* r if present */
624 bld
.MOV(sources
[length
], coordinate
);
625 coordinate
= offset(coordinate
, bld
, 1);
629 coordinate_done
= true;
634 /* Set up the coordinate (except for cases where it was done above) */
635 if (!coordinate_done
) {
636 for (int i
= 0; i
< coord_components
; i
++) {
637 bld
.MOV(sources
[length
], coordinate
);
638 coordinate
= offset(coordinate
, bld
, 1);
645 mlen
= length
* reg_width
- header_size
;
647 mlen
= length
* reg_width
;
649 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
650 BRW_REGISTER_TYPE_F
);
651 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
653 /* Generate the SEND */
656 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
657 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
658 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
659 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
660 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
661 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
662 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
663 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
664 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
666 if (has_nonconstant_offset
)
667 opcode
= SHADER_OPCODE_TG4_OFFSET
;
669 opcode
= SHADER_OPCODE_TG4
;
672 unreachable("not reached");
674 fs_inst
*inst
= bld
.emit(opcode
, dst
, src_payload
, sampler
);
677 inst
->header_size
= header_size
;
678 inst
->regs_written
= 4 * reg_width
;
680 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
681 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
682 " disallowed by hardware\n");
689 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
690 bool is_rect
, uint32_t sampler
, int texunit
)
692 bool needs_gl_clamp
= true;
693 fs_reg scale_x
, scale_y
;
695 /* The 965 requires the EU to do the normalization of GL rectangle
696 * texture coordinates. We use the program parameter state
697 * tracking to get the scaling factor.
701 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
702 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
703 struct gl_program_parameter_list
*params
= prog
->Parameters
;
704 int tokens
[STATE_LENGTH
] = {
712 no16("rectangle scale uniform setup not supported on SIMD16\n");
713 if (dispatch_width
== 16) {
717 GLuint index
= _mesa_add_state_reference(params
,
718 (gl_state_index
*)tokens
);
719 /* Try to find existing copies of the texrect scale uniforms. */
720 for (unsigned i
= 0; i
< uniforms
; i
++) {
721 if (stage_prog_data
->param
[i
] ==
722 &prog
->Parameters
->ParameterValues
[index
][0]) {
723 scale_x
= fs_reg(UNIFORM
, i
);
724 scale_y
= fs_reg(UNIFORM
, i
+ 1);
729 /* If we didn't already set them up, do so now. */
730 if (scale_x
.file
== BAD_FILE
) {
731 scale_x
= fs_reg(UNIFORM
, uniforms
);
732 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
734 stage_prog_data
->param
[uniforms
++] =
735 &prog
->Parameters
->ParameterValues
[index
][0];
736 stage_prog_data
->param
[uniforms
++] =
737 &prog
->Parameters
->ParameterValues
[index
][1];
741 /* The 965 requires the EU to do the normalization of GL rectangle
742 * texture coordinates. We use the program parameter state
743 * tracking to get the scaling factor.
745 if (devinfo
->gen
< 6 && is_rect
) {
746 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
747 fs_reg src
= coordinate
;
750 bld
.MUL(dst
, src
, scale_x
);
751 dst
= offset(dst
, bld
, 1);
752 src
= offset(src
, bld
, 1);
753 bld
.MUL(dst
, src
, scale_y
);
754 } else if (is_rect
) {
755 /* On gen6+, the sampler handles the rectangle coordinates
756 * natively, without needing rescaling. But that means we have
757 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
758 * not [0, 1] like the default case below.
760 needs_gl_clamp
= false;
762 for (int i
= 0; i
< 2; i
++) {
763 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
764 fs_reg chan
= coordinate
;
765 chan
= offset(chan
, bld
, i
);
767 set_condmod(BRW_CONDITIONAL_GE
,
768 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
)));
770 /* Our parameter comes in as 1.0/width or 1.0/height,
771 * because that's what people normally want for doing
772 * texture rectangle handling. We need width or height
773 * for clamping, but we don't care enough to make a new
774 * parameter type, so just invert back.
776 fs_reg limit
= vgrf(glsl_type::float_type
);
777 bld
.MOV(limit
, i
== 0 ? scale_x
: scale_y
);
778 bld
.emit(SHADER_OPCODE_RCP
, limit
, limit
);
780 set_condmod(BRW_CONDITIONAL_L
,
781 bld
.emit(BRW_OPCODE_SEL
, chan
, chan
, limit
));
786 if (coord_components
> 0 && needs_gl_clamp
) {
787 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
788 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
789 fs_reg chan
= coordinate
;
790 chan
= offset(chan
, bld
, i
);
791 set_saturate(true, bld
.MOV(chan
, chan
));
798 /* Sample from the MCS surface attached to this multisample texture. */
800 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
802 int reg_width
= dispatch_width
/ 8;
803 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(components
* reg_width
),
804 BRW_REGISTER_TYPE_F
);
805 fs_reg dest
= vgrf(glsl_type::uvec4_type
);
806 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
808 /* parameters are: u, v, r; missing parameters are treated as zero */
809 for (int i
= 0; i
< components
; i
++) {
810 sources
[i
] = vgrf(glsl_type::float_type
);
811 bld
.MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
);
812 coordinate
= offset(coordinate
, bld
, 1);
815 bld
.LOAD_PAYLOAD(payload
, sources
, components
, 0);
817 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
819 inst
->mlen
= components
* reg_width
;
820 inst
->header_size
= 0;
821 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
822 * response, but the sampler always
830 fs_visitor::emit_texture(ir_texture_opcode op
,
831 const glsl_type
*dest_type
,
832 fs_reg coordinate
, int coord_components
,
834 fs_reg lod
, fs_reg lod2
, int grad_components
,
838 int gather_component
,
842 fs_reg sampler_reg
, int texunit
)
844 fs_inst
*inst
= NULL
;
847 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
848 * emitting anything other than setting up the constant result.
850 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
851 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
853 fs_reg res
= vgrf(glsl_type::vec4_type
);
856 for (int i
=0; i
<4; i
++) {
857 bld
.MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
));
858 res
= offset(res
, bld
, 1);
864 if (op
== ir_query_levels
) {
865 /* textureQueryLevels() is implemented in terms of TXS so we need to
866 * pass a valid LOD argument.
868 assert(lod
.file
== BAD_FILE
);
872 if (coordinate
.file
!= BAD_FILE
) {
873 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
874 * samplers. This should only be a problem with GL_CLAMP on Gen7.
876 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
880 /* Writemasking doesn't eliminate channels on SIMD8 texture
881 * samples, so don't worry about them.
883 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
884 const fs_reg srcs
[] = {
885 coordinate
, shadow_c
, lod
, lod2
,
886 sample_index
, mcs
, sampler_reg
, offset_value
,
887 fs_reg(coord_components
), fs_reg(grad_components
)
893 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
896 opcode
= FS_OPCODE_TXB_LOGICAL
;
899 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
902 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
905 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
908 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
911 case ir_query_levels
:
912 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
915 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
918 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
919 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
922 unreachable("Invalid texture opcode.");
925 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
926 inst
->regs_written
= 4 * dispatch_width
/ 8;
928 if (shadow_c
.file
!= BAD_FILE
)
929 inst
->shadow_compare
= true;
931 if (offset_value
.file
== IMM
)
932 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
936 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
938 if (devinfo
->gen
== 6)
939 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
942 /* fixup #layers for cube map arrays */
943 if (op
== ir_txs
&& is_cube_array
) {
944 fs_reg depth
= offset(dst
, bld
, 2);
945 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
946 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
948 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
949 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
950 for (int i
= 0; i
< components
; i
++) {
952 fixed_payload
[i
] = fixed_depth
;
954 fixed_payload
[i
] = offset(dst
, bld
, i
);
957 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
960 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
964 * Apply workarounds for Gen6 gather with UINT/SINT
967 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
972 int width
= (wa
& WA_8BIT
) ? 8 : 16;
974 for (int i
= 0; i
< 4; i
++) {
975 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
976 /* Convert from UNORM to UINT */
977 bld
.MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1)));
981 /* Reinterpret the UINT value as a signed INT value by
982 * shifting the sign bit into place, then shifting back
985 bld
.SHL(dst
, dst
, fs_reg(32 - width
));
986 bld
.ASR(dst
, dst
, fs_reg(32 - width
));
989 dst
= offset(dst
, bld
, 1);
994 * Set up the gather channel based on the swizzle, for gather4.
997 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
999 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
1001 case SWIZZLE_X
: return 0;
1003 /* gather4 sampler is broken for green channel on RG32F --
1004 * we must ask for blue instead.
1006 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
1009 case SWIZZLE_Z
: return 2;
1010 case SWIZZLE_W
: return 3;
1012 unreachable("Not reached"); /* zero, one swizzles handled already */
1017 * Swizzle the result of a texture result. This is necessary for
1018 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1021 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
1022 fs_reg orig_val
, uint32_t sampler
)
1024 if (op
== ir_query_levels
) {
1025 /* # levels is in .w */
1026 this->result
= offset(orig_val
, bld
, 3);
1030 this->result
= orig_val
;
1032 /* txs,lod don't actually sample the texture, so swizzling the result
1035 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
1038 if (dest_components
== 1) {
1039 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1040 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
1041 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
1042 swizzled_result
.type
= orig_val
.type
;
1044 for (int i
= 0; i
< 4; i
++) {
1045 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
1046 fs_reg l
= swizzled_result
;
1047 l
= offset(l
, bld
, i
);
1049 if (swiz
== SWIZZLE_ZERO
) {
1050 bld
.MOV(l
, fs_reg(0.0f
));
1051 } else if (swiz
== SWIZZLE_ONE
) {
1052 bld
.MOV(l
, fs_reg(1.0f
));
1054 bld
.MOV(l
, offset(orig_val
, bld
,
1055 GET_SWZ(key_tex
->swizzles
[sampler
], i
)));
1058 this->result
= swizzled_result
;
1063 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1065 * Many GLSL shaders contain the following pattern:
1067 * x = condition ? foo : bar
1069 * The compiler emits an ir_if tree for this, since each subexpression might be
1070 * a complex tree that could have side-effects or short-circuit logic.
1072 * However, the common case is to simply select one of two constants or
1073 * variable values---which is exactly what SEL is for. In this case, the
1074 * assembly looks like:
1082 * which can be easily translated into:
1084 * (+f0) SEL dst src0 src1
1086 * If src0 is an immediate value, we promote it to a temporary GRF.
1089 fs_visitor::try_replace_with_sel()
1091 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
1092 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
1094 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1096 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
1099 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
1100 for (int i
= 0; i
< 4; i
++) {
1101 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
1103 match
= (fs_inst
*) match
->prev
;
1106 /* The opcodes match; it looks like the right sequence of instructions. */
1107 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
1108 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
1109 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
1111 /* Check that the MOVs are the right form. */
1112 if (then_mov
->dst
.equals(else_mov
->dst
) &&
1113 !then_mov
->is_partial_write() &&
1114 !else_mov
->is_partial_write()) {
1116 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1117 while (!if_inst
->next
->is_tail_sentinel())
1118 if_inst
->next
->exec_node::remove();
1119 if_inst
->exec_node::remove();
1121 /* Only the last source register can be a constant, so if the MOV in
1122 * the "then" clause uses a constant, we need to put it in a temporary.
1124 fs_reg
src0(then_mov
->src
[0]);
1125 if (src0
.file
== IMM
) {
1126 src0
= vgrf(glsl_type::float_type
);
1127 src0
.type
= then_mov
->src
[0].type
;
1128 bld
.MOV(src0
, then_mov
->src
[0]);
1131 if (if_inst
->conditional_mod
) {
1132 /* Sandybridge-specific IF with embedded comparison */
1133 bld
.CMP(bld
.null_reg_d(), if_inst
->src
[0], if_inst
->src
[1],
1134 if_inst
->conditional_mod
);
1135 set_predicate(BRW_PREDICATE_NORMAL
,
1136 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1137 src0
, else_mov
->src
[0]));
1139 /* Separate CMP and IF instructions */
1140 set_predicate_inv(if_inst
->predicate
, if_inst
->predicate_inverse
,
1141 bld
.emit(BRW_OPCODE_SEL
, then_mov
->dst
,
1142 src0
, else_mov
->src
[0]));
1152 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
1153 fs_reg dst
, fs_reg offset
, fs_reg src0
,
1156 int reg_width
= dispatch_width
/ 8;
1159 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
1161 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1162 /* Initialize the sample mask in the message header. */
1163 bld
.exec_all().MOV(sources
[0], fs_reg(0u));
1165 if (stage
== MESA_SHADER_FRAGMENT
) {
1166 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1168 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1171 .MOV(component(sources
[0], 7),
1172 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1175 /* The execution mask is part of the side-band information sent together with
1176 * the message payload to the data port. It's implicitly ANDed with the sample
1177 * mask sent in the header to compute the actual set of channels that execute
1178 * the atomic operation.
1180 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1182 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1186 /* Set the atomic operation offset. */
1187 sources
[1] = vgrf(glsl_type::uint_type
);
1188 bld
.MOV(sources
[1], offset
);
1191 /* Set the atomic operation arguments. */
1192 if (src0
.file
!= BAD_FILE
) {
1193 sources
[length
] = vgrf(glsl_type::uint_type
);
1194 bld
.MOV(sources
[length
], src0
);
1198 if (src1
.file
!= BAD_FILE
) {
1199 sources
[length
] = vgrf(glsl_type::uint_type
);
1200 bld
.MOV(sources
[length
], src1
);
1204 int mlen
= 1 + (length
- 1) * reg_width
;
1205 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1206 BRW_REGISTER_TYPE_UD
);
1207 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, 1);
1209 /* Emit the instruction. */
1210 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
1211 fs_reg(surf_index
), fs_reg(atomic_op
));
1216 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
1219 int reg_width
= dispatch_width
/ 8;
1221 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1223 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1224 /* Initialize the sample mask in the message header. */
1226 .MOV(sources
[0], fs_reg(0u));
1228 if (stage
== MESA_SHADER_FRAGMENT
) {
1229 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
1231 .MOV(component(sources
[0], 7), brw_flag_reg(0, 1));
1234 .MOV(component(sources
[0], 7),
1235 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
));
1238 /* The execution mask is part of the side-band information sent together with
1239 * the message payload to the data port. It's implicitly ANDed with the sample
1240 * mask sent in the header to compute the actual set of channels that execute
1241 * the atomic operation.
1243 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
1245 .MOV(component(sources
[0], 7), fs_reg(0xffffu
));
1248 /* Set the surface read offset. */
1249 sources
[1] = vgrf(glsl_type::uint_type
);
1250 bld
.MOV(sources
[1], offset
);
1252 int mlen
= 1 + reg_width
;
1253 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1254 BRW_REGISTER_TYPE_UD
);
1255 fs_inst
*inst
= bld
.LOAD_PAYLOAD(src_payload
, sources
, 2, 1);
1257 /* Emit the instruction. */
1258 inst
= bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
1259 fs_reg(surf_index
), fs_reg(1));
1263 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1265 fs_visitor::emit_dummy_fs()
1267 int reg_width
= dispatch_width
/ 8;
1269 /* Everyone's favorite color. */
1270 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
1271 for (int i
= 0; i
< 4; i
++) {
1272 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
1277 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
1279 if (devinfo
->gen
>= 6) {
1280 write
->base_mrf
= 2;
1281 write
->mlen
= 4 * reg_width
;
1283 write
->header_size
= 2;
1284 write
->base_mrf
= 0;
1285 write
->mlen
= 2 + 4 * reg_width
;
1288 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
1289 * varying to avoid GPU hangs, so set that.
1291 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1292 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
1293 memset(wm_prog_data
->urb_setup
, -1,
1294 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1296 /* We don't have any uniforms. */
1297 stage_prog_data
->nr_params
= 0;
1298 stage_prog_data
->nr_pull_params
= 0;
1299 stage_prog_data
->curb_read_length
= 0;
1300 stage_prog_data
->dispatch_grf_start_reg
= 2;
1301 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
1302 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
1307 /* The register location here is relative to the start of the URB
1308 * data. It will get adjusted to be a real location before
1309 * generate_code() time.
1312 fs_visitor::interp_reg(int location
, int channel
)
1314 assert(stage
== MESA_SHADER_FRAGMENT
);
1315 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1316 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
1317 int stride
= (channel
& 1) * 4;
1319 assert(prog_data
->urb_setup
[location
] != -1);
1321 return brw_vec1_grf(regnr
, stride
);
1324 /** Emits the interpolation for the varying inputs. */
1326 fs_visitor::emit_interpolation_setup_gen4()
1328 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1330 fs_builder abld
= bld
.annotate("compute pixel centers");
1331 this->pixel_x
= vgrf(glsl_type::uint_type
);
1332 this->pixel_y
= vgrf(glsl_type::uint_type
);
1333 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1334 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1335 abld
.ADD(this->pixel_x
,
1336 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1337 fs_reg(brw_imm_v(0x10101010)));
1338 abld
.ADD(this->pixel_y
,
1339 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1340 fs_reg(brw_imm_v(0x11001100)));
1342 abld
= bld
.annotate("compute pixel deltas from v0");
1344 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1345 vgrf(glsl_type::vec2_type
);
1346 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1347 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
1348 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
1350 if (devinfo
->has_pln
&& dispatch_width
== 16) {
1351 for (unsigned i
= 0; i
< 2; i
++) {
1352 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
1353 half(this->pixel_x
, i
), xstart
);
1354 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
1355 half(this->pixel_y
, i
), ystart
);
1358 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
1359 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
1362 abld
= bld
.annotate("compute pos.w and 1/pos.w");
1363 /* Compute wpos.w. It's always in our setup, since it's needed to
1364 * interpolate the other attributes.
1366 this->wpos_w
= vgrf(glsl_type::float_type
);
1367 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
1368 interp_reg(VARYING_SLOT_POS
, 3));
1369 /* Compute the pixel 1/W value from wpos.w. */
1370 this->pixel_w
= vgrf(glsl_type::float_type
);
1371 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1374 /** Emits the interpolation for the varying inputs. */
1376 fs_visitor::emit_interpolation_setup_gen6()
1378 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1380 fs_builder abld
= bld
.annotate("compute pixel centers");
1381 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1382 /* The "Register Region Restrictions" page says for BDW (and newer,
1385 * "When destination spans two registers, the source may be one or
1386 * two registers. The destination elements must be evenly split
1387 * between the two registers."
1389 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
1390 * compute our pixel centers.
1392 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
1393 BRW_REGISTER_TYPE_UW
);
1395 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
1396 dbld
.ADD(int_pixel_xy
,
1397 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
1398 fs_reg(brw_imm_v(0x11001010)));
1400 this->pixel_x
= vgrf(glsl_type::float_type
);
1401 this->pixel_y
= vgrf(glsl_type::float_type
);
1402 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
1403 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
1405 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
1407 * "When destination spans two registers, the source MUST span two
1410 * Since the GRF source of the ADD will only read a single register, we
1411 * must do two separate ADDs in SIMD16.
1413 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
1414 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
1415 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1416 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1417 abld
.ADD(int_pixel_x
,
1418 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1419 fs_reg(brw_imm_v(0x10101010)));
1420 abld
.ADD(int_pixel_y
,
1421 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1422 fs_reg(brw_imm_v(0x11001100)));
1424 /* As of gen6, we can no longer mix float and int sources. We have
1425 * to turn the integer pixel centers into floats for their actual
1428 this->pixel_x
= vgrf(glsl_type::float_type
);
1429 this->pixel_y
= vgrf(glsl_type::float_type
);
1430 abld
.MOV(this->pixel_x
, int_pixel_x
);
1431 abld
.MOV(this->pixel_y
, int_pixel_y
);
1434 abld
= bld
.annotate("compute pos.w");
1435 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
1436 this->wpos_w
= vgrf(glsl_type::float_type
);
1437 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1439 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1440 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
1441 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
1445 static enum brw_conditional_mod
1446 cond_for_alpha_func(GLenum func
)
1450 return BRW_CONDITIONAL_G
;
1452 return BRW_CONDITIONAL_GE
;
1454 return BRW_CONDITIONAL_L
;
1456 return BRW_CONDITIONAL_LE
;
1458 return BRW_CONDITIONAL_EQ
;
1460 return BRW_CONDITIONAL_NEQ
;
1462 unreachable("Not reached");
1467 * Alpha test support for when we compile it into the shader instead
1468 * of using the normal fixed-function alpha test.
1471 fs_visitor::emit_alpha_test()
1473 assert(stage
== MESA_SHADER_FRAGMENT
);
1474 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1475 const fs_builder abld
= bld
.annotate("Alpha test");
1478 if (key
->alpha_test_func
== GL_ALWAYS
)
1481 if (key
->alpha_test_func
== GL_NEVER
) {
1483 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1484 BRW_REGISTER_TYPE_UW
));
1485 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
1486 BRW_CONDITIONAL_NEQ
);
1489 fs_reg color
= offset(outputs
[0], bld
, 3);
1491 /* f0.1 &= func(color, ref) */
1492 cmp
= abld
.CMP(bld
.null_reg_f(), color
, fs_reg(key
->alpha_test_ref
),
1493 cond_for_alpha_func(key
->alpha_test_func
));
1495 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1496 cmp
->flag_subreg
= 1;
1500 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
1501 fs_reg color0
, fs_reg color1
,
1502 fs_reg src0_alpha
, unsigned components
)
1504 assert(stage
== MESA_SHADER_FRAGMENT
);
1505 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1507 /* Hand over gl_FragDepth or the payload depth. */
1508 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
1509 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
1513 if (source_depth_to_render_target
) {
1514 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
1515 src_depth
= frag_depth
;
1517 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
1520 const fs_reg sources
[] = {
1521 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, sample_mask
,
1524 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
1525 sources
, ARRAY_SIZE(sources
));
1527 if (prog_data
->uses_kill
) {
1528 write
->predicate
= BRW_PREDICATE_NORMAL
;
1529 write
->flag_subreg
= 1;
1536 fs_visitor::emit_fb_writes()
1538 assert(stage
== MESA_SHADER_FRAGMENT
);
1539 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1540 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1542 fs_inst
*inst
= NULL
;
1544 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
1545 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
1546 * would require SIMD8 moves of each half to message regs, e.g. by using
1547 * the SIMD lowering pass. Unfortunately this is more difficult than it
1548 * sounds because the SIMD8 single-source message lacks channel selects
1549 * for the second and third subspans.
1551 no16("Missing support for simd16 depth writes on gen6\n");
1555 const fs_builder abld
= bld
.annotate("FB dual-source write");
1557 inst
= emit_single_fb_write(abld
, this->outputs
[0],
1558 this->dual_src_output
, reg_undef
, 4);
1561 prog_data
->dual_src_blend
= true;
1563 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
1564 /* Skip over outputs that weren't written. */
1565 if (this->outputs
[target
].file
== BAD_FILE
)
1568 const fs_builder abld
= bld
.annotate(
1569 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
1572 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
1573 src0_alpha
= offset(outputs
[0], bld
, 3);
1575 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
1577 this->output_components
[target
]);
1578 inst
->target
= target
;
1583 /* Even if there's no color buffers enabled, we still need to send
1584 * alpha out the pipeline to our null renderbuffer to support
1585 * alpha-testing, alpha-to-coverage, and so on.
1587 /* FINISHME: Factor out this frequently recurring pattern into a
1590 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
1591 reg_undef
, offset(this->outputs
[0], bld
, 3) };
1592 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
1593 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
1595 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
1603 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
1605 const struct brw_vue_prog_key
*key
=
1606 (const struct brw_vue_prog_key
*) this->key
;
1608 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1609 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
1610 for (int j
= 0; j
< 4; ++j
) {
1611 stage_prog_data
->param
[uniforms
+ j
] =
1612 (gl_constant_value
*) &clip_planes
[i
][j
];
1619 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
1621 * This does nothing if the shader uses gl_ClipDistance or user clipping is
1622 * disabled altogether.
1624 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
1626 struct brw_vue_prog_data
*vue_prog_data
=
1627 (struct brw_vue_prog_data
*) prog_data
;
1628 const struct brw_vue_prog_key
*key
=
1629 (const struct brw_vue_prog_key
*) this->key
;
1631 /* Bail unless some sort of legacy clipping is enabled */
1632 if (!key
->userclip_active
|| prog
->UsesClipDistanceOut
)
1635 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
1637 * "If a linked set of shaders forming the vertex stage contains no
1638 * static write to gl_ClipVertex or gl_ClipDistance, but the
1639 * application has requested clipping against user clip planes through
1640 * the API, then the coordinate written to gl_Position is used for
1641 * comparison against the user clip planes."
1643 * This function is only called if the shader didn't write to
1644 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
1645 * if the user wrote to it; otherwise we use gl_Position.
1648 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
1649 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
1650 clip_vertex
= VARYING_SLOT_POS
;
1652 /* If the clip vertex isn't written, skip this. Typically this means
1653 * the GS will set up clipping. */
1654 if (outputs
[clip_vertex
].file
== BAD_FILE
)
1657 setup_uniform_clipplane_values(clip_planes
);
1659 const fs_builder abld
= bld
.annotate("user clip distances");
1661 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
1662 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
1664 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
1665 fs_reg u
= userplane
[i
];
1666 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
1667 output
.reg_offset
= i
& 3;
1669 abld
.MUL(output
, outputs
[clip_vertex
], u
);
1670 for (int j
= 1; j
< 4; j
++) {
1671 u
.reg
= userplane
[i
].reg
+ j
;
1672 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
1678 fs_visitor::emit_urb_writes()
1680 int slot
, urb_offset
, length
;
1681 struct brw_vs_prog_data
*vs_prog_data
=
1682 (struct brw_vs_prog_data
*) prog_data
;
1683 const struct brw_vs_prog_key
*key
=
1684 (const struct brw_vs_prog_key
*) this->key
;
1685 const GLbitfield64 psiz_mask
=
1686 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
1687 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
1691 /* If we don't have any valid slots to write, just do a minimal urb write
1692 * send to terminate the shader. This includes 1 slot of undefined data,
1693 * because it's invalid to write 0 data:
1695 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
1696 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
1697 * Write Data Payload:
1699 * "The write data payload can be between 1 and 8 message phases long."
1701 if (vue_map
->slots_valid
== 0) {
1702 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
1703 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
1704 BRW_REGISTER_TYPE_UD
)));
1706 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1716 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
1717 fs_reg reg
, src
, zero
;
1719 int varying
= vue_map
->slot_to_varying
[slot
];
1721 case VARYING_SLOT_PSIZ
:
1723 /* The point size varying slot is the vue header and is always in the
1724 * vue map. But often none of the special varyings that live there
1725 * are written and in that case we can skip writing to the vue
1726 * header, provided the corresponding state properly clamps the
1727 * values further down the pipeline. */
1728 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
1729 assert(length
== 0);
1734 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1735 bld
.MOV(zero
, fs_reg(0u));
1737 sources
[length
++] = zero
;
1738 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
1739 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
1741 sources
[length
++] = zero
;
1743 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
1744 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
1746 sources
[length
++] = zero
;
1748 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
1749 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
1751 sources
[length
++] = zero
;
1754 case BRW_VARYING_SLOT_NDC
:
1755 case VARYING_SLOT_EDGE
:
1756 unreachable("unexpected scalar vs output");
1759 case BRW_VARYING_SLOT_PAD
:
1763 /* gl_Position is always in the vue map, but isn't always written by
1764 * the shader. Other varyings (clip distances) get added to the vue
1765 * map but don't always get written. In those cases, the
1766 * corresponding this->output[] slot will be invalid we and can skip
1767 * the urb write for the varying. If we've already queued up a vue
1768 * slot for writing we flush a mlen 5 urb write, otherwise we just
1769 * advance the urb_offset.
1771 if (this->outputs
[varying
].file
== BAD_FILE
) {
1779 if ((varying
== VARYING_SLOT_COL0
||
1780 varying
== VARYING_SLOT_COL1
||
1781 varying
== VARYING_SLOT_BFC0
||
1782 varying
== VARYING_SLOT_BFC1
) &&
1783 key
->clamp_vertex_color
) {
1784 /* We need to clamp these guys, so do a saturating MOV into a
1785 * temp register and use that for the payload.
1787 for (int i
= 0; i
< 4; i
++) {
1788 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
1789 src
= offset(this->outputs
[varying
], bld
, i
);
1790 set_saturate(true, bld
.MOV(reg
, src
));
1791 sources
[length
++] = reg
;
1794 for (int i
= 0; i
< 4; i
++)
1795 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
1800 const fs_builder abld
= bld
.annotate("URB write");
1802 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
1803 * the last slot or if we need to flush (see BAD_FILE varying case
1804 * above), emit a URB write send now to flush out the data.
1806 int last
= slot
== vue_map
->num_slots
- 1;
1807 if (length
== 8 || last
)
1810 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
1811 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
1812 BRW_REGISTER_TYPE_F
);
1813 payload_sources
[0] =
1814 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1816 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
1817 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1, 1);
1820 abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1822 inst
->mlen
= length
+ 1;
1823 inst
->offset
= urb_offset
;
1824 urb_offset
= slot
+ 1;
1832 fs_visitor::emit_cs_terminate()
1834 assert(devinfo
->gen
>= 7);
1836 /* We are getting the thread ID from the compute shader header */
1837 assert(stage
== MESA_SHADER_COMPUTE
);
1839 /* We can't directly send from g0, since sends with EOT have to use
1840 * g112-127. So, copy it to a virtual register, The register allocator will
1841 * make sure it uses the appropriate register range.
1843 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
1844 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1845 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
1847 /* Send a message to the thread spawner to terminate the thread. */
1848 fs_inst
*inst
= bld
.exec_all()
1849 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
1854 fs_visitor::emit_barrier()
1856 assert(devinfo
->gen
>= 7);
1858 /* We are getting the barrier ID from the compute shader header */
1859 assert(stage
== MESA_SHADER_COMPUTE
);
1861 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1863 /* Clear the message payload */
1864 bld
.exec_all().MOV(payload
, fs_reg(0u));
1866 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
1867 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
1868 bld
.exec_all().AND(component(payload
, 2), r0_2
, fs_reg(0x0f000000u
));
1870 /* Emit a gateway "barrier" message using the payload we set up, followed
1871 * by a wait instruction.
1873 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
1876 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
1878 gl_shader_stage stage
,
1880 struct brw_stage_prog_data
*prog_data
,
1881 struct gl_shader_program
*shader_prog
,
1882 struct gl_program
*prog
,
1883 unsigned dispatch_width
,
1884 int shader_time_index
)
1885 : backend_shader(compiler
, log_data
, mem_ctx
,
1886 shader_prog
, prog
, prog_data
, stage
),
1887 key(key
), prog_data(prog_data
),
1888 dispatch_width(dispatch_width
),
1889 shader_time_index(shader_time_index
),
1890 promoted_constants(0),
1891 bld(fs_builder(this, dispatch_width
).at_end())
1894 case MESA_SHADER_FRAGMENT
:
1895 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
1897 case MESA_SHADER_VERTEX
:
1898 case MESA_SHADER_GEOMETRY
:
1899 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
1901 case MESA_SHADER_COMPUTE
:
1902 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1905 unreachable("unhandled shader stage");
1908 this->failed
= false;
1909 this->simd16_unsupported
= false;
1910 this->no16_msg
= NULL
;
1912 this->nir_locals
= NULL
;
1913 this->nir_ssa_values
= NULL
;
1915 memset(&this->payload
, 0, sizeof(this->payload
));
1916 memset(this->outputs
, 0, sizeof(this->outputs
));
1917 memset(this->output_components
, 0, sizeof(this->output_components
));
1918 this->source_depth_to_render_target
= false;
1919 this->runtime_check_aads_emit
= false;
1920 this->first_non_payload_grf
= 0;
1921 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1923 this->virtual_grf_start
= NULL
;
1924 this->virtual_grf_end
= NULL
;
1925 this->live_intervals
= NULL
;
1926 this->regs_live_at_ip
= NULL
;
1929 this->last_scratch
= 0;
1930 this->pull_constant_loc
= NULL
;
1931 this->push_constant_loc
= NULL
;
1933 this->spilled_any_registers
= false;
1934 this->do_dual_src
= false;
1936 if (dispatch_width
== 8)
1937 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1940 fs_visitor::~fs_visitor()