src/mesa/drivers/dri/i965/brw_fs_visitor.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_visitor.cpp
  25  *
  26  * This file supports generating the FS LIR from the GLSL IR.  The LIR
  27  * makes it easier to do backend-specific optimizations than doing so
  28  * in the GLSL IR or in the native code.
  29  */
  30 #include "brw_fs.h"
  31 #include "compiler/glsl_types.h"
  32
  33 using namespace brw;
  34
  35 fs_reg *
  36 fs_visitor::emit_vs_system_value(int location)
  37 {
  38    fs_reg *reg = new(this->mem_ctx)
  39       fs_reg(ATTR, 4 * _mesa_bitcount_64(nir->info.inputs_read),
  40              BRW_REGISTER_TYPE_D);
  41    brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
  42
  43    switch (location) {
  44    case SYSTEM_VALUE_BASE_VERTEX:
  45       reg->reg_offset = 0;
  46       vs_prog_data->uses_basevertex = true;
  47       break;
  48    case SYSTEM_VALUE_BASE_INSTANCE:
  49       reg->reg_offset = 1;
  50       vs_prog_data->uses_baseinstance = true;
  51       break;
  52    case SYSTEM_VALUE_VERTEX_ID:
  53       unreachable("should have been lowered");
  54    case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
  55       reg->reg_offset = 2;
  56       vs_prog_data->uses_vertexid = true;
  57       break;
  58    case SYSTEM_VALUE_INSTANCE_ID:
  59       reg->reg_offset = 3;
  60       vs_prog_data->uses_instanceid = true;
  61       break;
  62    case SYSTEM_VALUE_DRAW_ID:
  63       if (nir->info.system_values_read &
  64           (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
  65            BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
  66            BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
  67            BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)))
  68          reg->nr += 4;
  69       reg->reg_offset = 0;
  70       vs_prog_data->uses_drawid = true;
  71       break;
  72    default:
  73       unreachable("not reached");
  74    }
  75
  76    return reg;
  77 }
  78
  79 /* Sample from the MCS surface attached to this multisample texture. */
  80 fs_reg
  81 fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
  82                            const fs_reg &texture)
  83 {
  84    const fs_reg dest = vgrf(glsl_type::uvec4_type);
  85
  86    fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
  87    srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
  88    srcs[TEX_LOGICAL_SRC_SURFACE] = texture;
  89    srcs[TEX_LOGICAL_SRC_SAMPLER] = texture;
  90    srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components);
  91    srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
  92
  93    fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs,
  94                             ARRAY_SIZE(srcs));
  95
  96    /* We only care about one or two regs of response, but the sampler always
  97     * writes 4/8.
  98     */
  99    inst->regs_written = 4 * dispatch_width / 8;
 100
 101    return dest;
 102 }
 103
 104 /**
 105  * Apply workarounds for Gen6 gather with UINT/SINT
 106  */
 107 void
 108 fs_visitor::emit_gen6_gather_wa(uint8_t wa, fs_reg dst)
 109 {
 110    if (!wa)
 111       return;
 112
 113    int width = (wa & WA_8BIT) ? 8 : 16;
 114
 115    for (int i = 0; i < 4; i++) {
 116       fs_reg dst_f = retype(dst, BRW_REGISTER_TYPE_F);
 117       /* Convert from UNORM to UINT */
 118       bld.MUL(dst_f, dst_f, brw_imm_f((1 << width) - 1));
 119       bld.MOV(dst, dst_f);
 120
 121       if (wa & WA_SIGN) {
 122          /* Reinterpret the UINT value as a signed INT value by
 123           * shifting the sign bit into place, then shifting back
 124           * preserving sign.
 125           */
 126          bld.SHL(dst, dst, brw_imm_d(32 - width));
 127          bld.ASR(dst, dst, brw_imm_d(32 - width));
 128       }
 129
 130       dst = offset(dst, bld, 1);
 131    }
 132 }
 133
 134 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
 135 void
 136 fs_visitor::emit_dummy_fs()
 137 {
 138    int reg_width = dispatch_width / 8;
 139
 140    /* Everyone's favorite color. */
 141    const float color[4] = { 1.0, 0.0, 1.0, 0.0 };
 142    for (int i = 0; i < 4; i++) {
 143       bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F),
 144               brw_imm_f(color[i]));
 145    }
 146
 147    fs_inst *write;
 148    write = bld.emit(FS_OPCODE_FB_WRITE);
 149    write->eot = true;
 150    if (devinfo->gen >= 6) {
 151       write->base_mrf = 2;
 152       write->mlen = 4 * reg_width;
 153    } else {
 154       write->header_size = 2;
 155       write->base_mrf = 0;
 156       write->mlen = 2 + 4 * reg_width;
 157    }
 158
 159    /* Tell the SF we don't have any inputs.  Gen4-5 require at least one
 160     * varying to avoid GPU hangs, so set that.
 161     */
 162    brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
 163    wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
 164    memset(wm_prog_data->urb_setup, -1,
 165           sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
 166
 167    /* We don't have any uniforms. */
 168    stage_prog_data->nr_params = 0;
 169    stage_prog_data->nr_pull_params = 0;
 170    stage_prog_data->curb_read_length = 0;
 171    stage_prog_data->dispatch_grf_start_reg = 2;
 172    wm_prog_data->dispatch_grf_start_reg_2 = 2;
 173    grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */
 174
 175    calculate_cfg();
 176 }
 177
 178 /* The register location here is relative to the start of the URB
 179  * data.  It will get adjusted to be a real location before
 180  * generate_code() time.
 181  */
 182 struct brw_reg
 183 fs_visitor::interp_reg(int location, int channel)
 184 {
 185    assert(stage == MESA_SHADER_FRAGMENT);
 186    brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
 187    int regnr = prog_data->urb_setup[location] * 2 + channel / 2;
 188    int stride = (channel & 1) * 4;
 189
 190    assert(prog_data->urb_setup[location] != -1);
 191
 192    return brw_vec1_grf(regnr, stride);
 193 }
 194
 195 /** Emits the interpolation for the varying inputs. */
 196 void
 197 fs_visitor::emit_interpolation_setup_gen4()
 198 {
 199    struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
 200
 201    fs_builder abld = bld.annotate("compute pixel centers");
 202    this->pixel_x = vgrf(glsl_type::uint_type);
 203    this->pixel_y = vgrf(glsl_type::uint_type);
 204    this->pixel_x.type = BRW_REGISTER_TYPE_UW;
 205    this->pixel_y.type = BRW_REGISTER_TYPE_UW;
 206    abld.ADD(this->pixel_x,
 207             fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
 208             fs_reg(brw_imm_v(0x10101010)));
 209    abld.ADD(this->pixel_y,
 210             fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
 211             fs_reg(brw_imm_v(0x11001100)));
 212
 213    abld = bld.annotate("compute pixel deltas from v0");
 214
 215    this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
 216       vgrf(glsl_type::vec2_type);
 217    const fs_reg &delta_xy = this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
 218    const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
 219    const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
 220
 221    if (devinfo->has_pln && dispatch_width == 16) {
 222       for (unsigned i = 0; i < 2; i++) {
 223          abld.half(i).ADD(half(offset(delta_xy, abld, i), 0),
 224                           half(this->pixel_x, i), xstart);
 225          abld.half(i).ADD(half(offset(delta_xy, abld, i), 1),
 226                           half(this->pixel_y, i), ystart);
 227       }
 228    } else {
 229       abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
 230       abld.ADD(offset(delta_xy, abld, 1), this->pixel_y, ystart);
 231    }
 232
 233    abld = bld.annotate("compute pos.w and 1/pos.w");
 234    /* Compute wpos.w.  It's always in our setup, since it's needed to
 235     * interpolate the other attributes.
 236     */
 237    this->wpos_w = vgrf(glsl_type::float_type);
 238    abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
 239              interp_reg(VARYING_SLOT_POS, 3));
 240    /* Compute the pixel 1/W value from wpos.w. */
 241    this->pixel_w = vgrf(glsl_type::float_type);
 242    abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
 243 }
 244
 245 /** Emits the interpolation for the varying inputs. */
 246 void
 247 fs_visitor::emit_interpolation_setup_gen6()
 248 {
 249    struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
 250
 251    fs_builder abld = bld.annotate("compute pixel centers");
 252    if (devinfo->gen >= 8 || dispatch_width == 8) {
 253       /* The "Register Region Restrictions" page says for BDW (and newer,
 254        * presumably):
 255        *
 256        *     "When destination spans two registers, the source may be one or
 257        *      two registers. The destination elements must be evenly split
 258        *      between the two registers."
 259        *
 260        * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
 261        * compute our pixel centers.
 262        */
 263       fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8),
 264                           BRW_REGISTER_TYPE_UW);
 265
 266       const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0);
 267       dbld.ADD(int_pixel_xy,
 268                fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
 269                fs_reg(brw_imm_v(0x11001010)));
 270
 271       this->pixel_x = vgrf(glsl_type::float_type);
 272       this->pixel_y = vgrf(glsl_type::float_type);
 273       abld.emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy);
 274       abld.emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy);
 275    } else {
 276       /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
 277        *
 278        *     "When destination spans two registers, the source MUST span two
 279        *      registers."
 280        *
 281        * Since the GRF source of the ADD will only read a single register, we
 282        * must do two separate ADDs in SIMD16.
 283        */
 284       fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
 285       fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
 286       int_pixel_x.type = BRW_REGISTER_TYPE_UW;
 287       int_pixel_y.type = BRW_REGISTER_TYPE_UW;
 288       abld.ADD(int_pixel_x,
 289                fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
 290                fs_reg(brw_imm_v(0x10101010)));
 291       abld.ADD(int_pixel_y,
 292                fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
 293                fs_reg(brw_imm_v(0x11001100)));
 294
 295       /* As of gen6, we can no longer mix float and int sources.  We have
 296        * to turn the integer pixel centers into floats for their actual
 297        * use.
 298        */
 299       this->pixel_x = vgrf(glsl_type::float_type);
 300       this->pixel_y = vgrf(glsl_type::float_type);
 301       abld.MOV(this->pixel_x, int_pixel_x);
 302       abld.MOV(this->pixel_y, int_pixel_y);
 303    }
 304
 305    abld = bld.annotate("compute pos.w");
 306    this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0));
 307    this->wpos_w = vgrf(glsl_type::float_type);
 308    abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
 309
 310    for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
 311       uint8_t reg = payload.barycentric_coord_reg[i];
 312       this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0));
 313    }
 314 }
 315
 316 static enum brw_conditional_mod
 317 cond_for_alpha_func(GLenum func)
 318 {
 319    switch(func) {
 320       case GL_GREATER:
 321          return BRW_CONDITIONAL_G;
 322       case GL_GEQUAL:
 323          return BRW_CONDITIONAL_GE;
 324       case GL_LESS:
 325          return BRW_CONDITIONAL_L;
 326       case GL_LEQUAL:
 327          return BRW_CONDITIONAL_LE;
 328       case GL_EQUAL:
 329          return BRW_CONDITIONAL_EQ;
 330       case GL_NOTEQUAL:
 331          return BRW_CONDITIONAL_NEQ;
 332       default:
 333          unreachable("Not reached");
 334    }
 335 }
 336
 337 /**
 338  * Alpha test support for when we compile it into the shader instead
 339  * of using the normal fixed-function alpha test.
 340  */
 341 void
 342 fs_visitor::emit_alpha_test()
 343 {
 344    assert(stage == MESA_SHADER_FRAGMENT);
 345    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 346    const fs_builder abld = bld.annotate("Alpha test");
 347
 348    fs_inst *cmp;
 349    if (key->alpha_test_func == GL_ALWAYS)
 350       return;
 351
 352    if (key->alpha_test_func == GL_NEVER) {
 353       /* f0.1 = 0 */
 354       fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
 355                                       BRW_REGISTER_TYPE_UW));
 356       cmp = abld.CMP(bld.null_reg_f(), some_reg, some_reg,
 357                      BRW_CONDITIONAL_NEQ);
 358    } else {
 359       /* RT0 alpha */
 360       fs_reg color = offset(outputs[0], bld, 3);
 361
 362       /* f0.1 &= func(color, ref) */
 363       cmp = abld.CMP(bld.null_reg_f(), color, brw_imm_f(key->alpha_test_ref),
 364                      cond_for_alpha_func(key->alpha_test_func));
 365    }
 366    cmp->predicate = BRW_PREDICATE_NORMAL;
 367    cmp->flag_subreg = 1;
 368 }
 369
 370 fs_inst *
 371 fs_visitor::emit_single_fb_write(const fs_builder &bld,
 372                                  fs_reg color0, fs_reg color1,
 373                                  fs_reg src0_alpha, unsigned components)
 374 {
 375    assert(stage == MESA_SHADER_FRAGMENT);
 376    brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
 377
 378    /* Hand over gl_FragDepth or the payload depth. */
 379    const fs_reg dst_depth = (payload.dest_depth_reg ?
 380                              fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0)) :
 381                              fs_reg());
 382    fs_reg src_depth, src_stencil;
 383
 384    if (source_depth_to_render_target) {
 385       if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 386          src_depth = frag_depth;
 387       else
 388          src_depth = fs_reg(brw_vec8_grf(payload.source_depth_reg, 0));
 389    }
 390
 391    if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
 392       src_stencil = frag_stencil;
 393
 394    const fs_reg sources[] = {
 395       color0, color1, src0_alpha, src_depth, dst_depth, src_stencil,
 396       sample_mask, brw_imm_ud(components)
 397    };
 398    assert(ARRAY_SIZE(sources) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS);
 399    fs_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, fs_reg(),
 400                              sources, ARRAY_SIZE(sources));
 401
 402    if (prog_data->uses_kill) {
 403       write->predicate = BRW_PREDICATE_NORMAL;
 404       write->flag_subreg = 1;
 405    }
 406
 407    return write;
 408 }
 409
 410 void
 411 fs_visitor::emit_fb_writes()
 412 {
 413    assert(stage == MESA_SHADER_FRAGMENT);
 414    brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
 415    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 416
 417    fs_inst *inst = NULL;
 418
 419    if (source_depth_to_render_target && devinfo->gen == 6) {
 420       /* For outputting oDepth on gen6, SIMD8 writes have to be used.  This
 421        * would require SIMD8 moves of each half to message regs, e.g. by using
 422        * the SIMD lowering pass.  Unfortunately this is more difficult than it
 423        * sounds because the SIMD8 single-source message lacks channel selects
 424        * for the second and third subspans.
 425        */
 426       no16("Missing support for simd16 depth writes on gen6\n");
 427    }
 428
 429    if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) {
 430       /* From the 'Render Target Write message' section of the docs:
 431        * "Output Stencil is not supported with SIMD16 Render Target Write
 432        * Messages."
 433        *
 434        * FINISHME: split 16 into 2 8s
 435        */
 436       no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
 437    }
 438
 439    if (do_dual_src) {
 440       const fs_builder abld = bld.annotate("FB dual-source write");
 441
 442       inst = emit_single_fb_write(abld, this->outputs[0],
 443                                   this->dual_src_output, reg_undef, 4);
 444       inst->target = 0;
 445
 446       prog_data->dual_src_blend = true;
 447    } else {
 448       for (int target = 0; target < key->nr_color_regions; target++) {
 449          /* Skip over outputs that weren't written. */
 450          if (this->outputs[target].file == BAD_FILE)
 451             continue;
 452
 453          const fs_builder abld = bld.annotate(
 454             ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
 455
 456          fs_reg src0_alpha;
 457          if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
 458             src0_alpha = offset(outputs[0], bld, 3);
 459
 460          inst = emit_single_fb_write(abld, this->outputs[target], reg_undef,
 461                                      src0_alpha,
 462                                      this->output_components[target]);
 463          inst->target = target;
 464       }
 465    }
 466
 467    if (inst == NULL) {
 468       /* Even if there's no color buffers enabled, we still need to send
 469        * alpha out the pipeline to our null renderbuffer to support
 470        * alpha-testing, alpha-to-coverage, and so on.
 471        */
 472       /* FINISHME: Factor out this frequently recurring pattern into a
 473        * helper function.
 474        */
 475       const fs_reg srcs[] = { reg_undef, reg_undef,
 476                               reg_undef, offset(this->outputs[0], bld, 3) };
 477       const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
 478       bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
 479
 480       inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
 481       inst->target = 0;
 482    }
 483
 484    inst->eot = true;
 485 }
 486
 487 void
 488 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane *clip_planes)
 489 {
 490    const struct brw_vs_prog_key *key =
 491       (const struct brw_vs_prog_key *) this->key;
 492
 493    for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
 494       this->userplane[i] = fs_reg(UNIFORM, uniforms);
 495       for (int j = 0; j < 4; ++j) {
 496          stage_prog_data->param[uniforms + j] =
 497             (gl_constant_value *) &clip_planes[i][j];
 498       }
 499       uniforms += 4;
 500    }
 501 }
 502
 503 /**
 504  * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
 505  *
 506  * This does nothing if the shader uses gl_ClipDistance or user clipping is
 507  * disabled altogether.
 508  */
 509 void fs_visitor::compute_clip_distance(gl_clip_plane *clip_planes)
 510 {
 511    struct brw_vue_prog_data *vue_prog_data =
 512       (struct brw_vue_prog_data *) prog_data;
 513    const struct brw_vs_prog_key *key =
 514       (const struct brw_vs_prog_key *) this->key;
 515
 516    /* Bail unless some sort of legacy clipping is enabled */
 517    if (key->nr_userclip_plane_consts == 0)
 518       return;
 519
 520    /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
 521     *
 522     *     "If a linked set of shaders forming the vertex stage contains no
 523     *     static write to gl_ClipVertex or gl_ClipDistance, but the
 524     *     application has requested clipping against user clip planes through
 525     *     the API, then the coordinate written to gl_Position is used for
 526     *     comparison against the user clip planes."
 527     *
 528     * This function is only called if the shader didn't write to
 529     * gl_ClipDistance.  Accordingly, we use gl_ClipVertex to perform clipping
 530     * if the user wrote to it; otherwise we use gl_Position.
 531     */
 532
 533    gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX;
 534    if (!(vue_prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX))
 535       clip_vertex = VARYING_SLOT_POS;
 536
 537    /* If the clip vertex isn't written, skip this.  Typically this means
 538     * the GS will set up clipping. */
 539    if (outputs[clip_vertex].file == BAD_FILE)
 540       return;
 541
 542    setup_uniform_clipplane_values(clip_planes);
 543
 544    const fs_builder abld = bld.annotate("user clip distances");
 545
 546    this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type);
 547    this->output_components[VARYING_SLOT_CLIP_DIST0] = 4;
 548    this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type);
 549    this->output_components[VARYING_SLOT_CLIP_DIST1] = 4;
 550
 551    for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
 552       fs_reg u = userplane[i];
 553       fs_reg output = outputs[VARYING_SLOT_CLIP_DIST0 + i / 4];
 554       output.reg_offset = i & 3;
 555
 556       abld.MUL(output, outputs[clip_vertex], u);
 557       for (int j = 1; j < 4; j++) {
 558          u.nr = userplane[i].nr + j;
 559          abld.MAD(output, output, offset(outputs[clip_vertex], bld, j), u);
 560       }
 561    }
 562 }
 563
 564 void
 565 fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
 566 {
 567    int slot, urb_offset, length;
 568    int starting_urb_offset = 0;
 569    const struct brw_vue_prog_data *vue_prog_data =
 570       (const struct brw_vue_prog_data *) this->prog_data;
 571    const struct brw_vs_prog_key *vs_key =
 572       (const struct brw_vs_prog_key *) this->key;
 573    const GLbitfield64 psiz_mask =
 574       VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ;
 575    const struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
 576    bool flush;
 577    fs_reg sources[8];
 578    fs_reg urb_handle;
 579
 580    if (stage == MESA_SHADER_TESS_EVAL)
 581       urb_handle = fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD));
 582    else
 583       urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
 584
 585    /* If we don't have any valid slots to write, just do a minimal urb write
 586     * send to terminate the shader.  This includes 1 slot of undefined data,
 587     * because it's invalid to write 0 data:
 588     *
 589     * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
 590     * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
 591     * Write Data Payload:
 592     *
 593     *    "The write data payload can be between 1 and 8 message phases long."
 594     */
 595    if (vue_map->slots_valid == 0) {
 596       fs_reg payload = fs_reg(VGRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD);
 597       bld.exec_all().MOV(payload, urb_handle);
 598
 599       fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
 600       inst->eot = true;
 601       inst->mlen = 2;
 602       inst->offset = 1;
 603       return;
 604    }
 605
 606    opcode opcode = SHADER_OPCODE_URB_WRITE_SIMD8;
 607    int header_size = 1;
 608    fs_reg per_slot_offsets;
 609
 610    if (stage == MESA_SHADER_GEOMETRY) {
 611       const struct brw_gs_prog_data *gs_prog_data =
 612          (const struct brw_gs_prog_data *) this->prog_data;
 613
 614       /* We need to increment the Global Offset to skip over the control data
 615        * header and the extra "Vertex Count" field (1 HWord) at the beginning
 616        * of the VUE.  We're counting in OWords, so the units are doubled.
 617        */
 618       starting_urb_offset = 2 * gs_prog_data->control_data_header_size_hwords;
 619       if (gs_prog_data->static_vertex_count == -1)
 620          starting_urb_offset += 2;
 621
 622       /* We also need to use per-slot offsets.  The per-slot offset is the
 623        * Vertex Count.  SIMD8 mode processes 8 different primitives at a
 624        * time; each may output a different number of vertices.
 625        */
 626       opcode = SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT;
 627       header_size++;
 628
 629       /* The URB offset is in 128-bit units, so we need to multiply by 2 */
 630       const int output_vertex_size_owords =
 631          gs_prog_data->output_vertex_size_hwords * 2;
 632
 633       if (gs_vertex_count.file == IMM) {
 634          per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
 635                                        gs_vertex_count.ud);
 636       } else {
 637          per_slot_offsets = vgrf(glsl_type::int_type);
 638          bld.MUL(per_slot_offsets, gs_vertex_count,
 639                  brw_imm_ud(output_vertex_size_owords));
 640       }
 641    }
 642
 643    length = 0;
 644    urb_offset = starting_urb_offset;
 645    flush = false;
 646    for (slot = 0; slot < vue_map->num_slots; slot++) {
 647       int varying = vue_map->slot_to_varying[slot];
 648       switch (varying) {
 649       case VARYING_SLOT_PSIZ: {
 650          /* The point size varying slot is the vue header and is always in the
 651           * vue map.  But often none of the special varyings that live there
 652           * are written and in that case we can skip writing to the vue
 653           * header, provided the corresponding state properly clamps the
 654           * values further down the pipeline. */
 655          if ((vue_map->slots_valid & psiz_mask) == 0) {
 656             assert(length == 0);
 657             urb_offset++;
 658             break;
 659          }
 660
 661          fs_reg zero(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 662          bld.MOV(zero, brw_imm_ud(0u));
 663
 664          sources[length++] = zero;
 665          if (vue_map->slots_valid & VARYING_BIT_LAYER)
 666             sources[length++] = this->outputs[VARYING_SLOT_LAYER];
 667          else
 668             sources[length++] = zero;
 669
 670          if (vue_map->slots_valid & VARYING_BIT_VIEWPORT)
 671             sources[length++] = this->outputs[VARYING_SLOT_VIEWPORT];
 672          else
 673             sources[length++] = zero;
 674
 675          if (vue_map->slots_valid & VARYING_BIT_PSIZ)
 676             sources[length++] = this->outputs[VARYING_SLOT_PSIZ];
 677          else
 678             sources[length++] = zero;
 679          break;
 680       }
 681       case BRW_VARYING_SLOT_NDC:
 682       case VARYING_SLOT_EDGE:
 683          unreachable("unexpected scalar vs output");
 684          break;
 685
 686       default:
 687          /* gl_Position is always in the vue map, but isn't always written by
 688           * the shader.  Other varyings (clip distances) get added to the vue
 689           * map but don't always get written.  In those cases, the
 690           * corresponding this->output[] slot will be invalid we and can skip
 691           * the urb write for the varying.  If we've already queued up a vue
 692           * slot for writing we flush a mlen 5 urb write, otherwise we just
 693           * advance the urb_offset.
 694           */
 695          if (varying == BRW_VARYING_SLOT_PAD ||
 696              this->outputs[varying].file == BAD_FILE) {
 697             if (length > 0)
 698                flush = true;
 699             else
 700                urb_offset++;
 701             break;
 702          }
 703
 704          if (stage == MESA_SHADER_VERTEX && vs_key->clamp_vertex_color &&
 705              (varying == VARYING_SLOT_COL0 ||
 706               varying == VARYING_SLOT_COL1 ||
 707               varying == VARYING_SLOT_BFC0 ||
 708               varying == VARYING_SLOT_BFC1)) {
 709             /* We need to clamp these guys, so do a saturating MOV into a
 710              * temp register and use that for the payload.
 711              */
 712             for (int i = 0; i < 4; i++) {
 713                fs_reg reg = fs_reg(VGRF, alloc.allocate(1), outputs[varying].type);
 714                fs_reg src = offset(this->outputs[varying], bld, i);
 715                set_saturate(true, bld.MOV(reg, src));
 716                sources[length++] = reg;
 717             }
 718          } else {
 719             for (unsigned i = 0; i < output_components[varying]; i++)
 720                sources[length++] = offset(this->outputs[varying], bld, i);
 721             for (unsigned i = output_components[varying]; i < 4; i++)
 722                sources[length++] = brw_imm_d(0);
 723          }
 724          break;
 725       }
 726
 727       const fs_builder abld = bld.annotate("URB write");
 728
 729       /* If we've queued up 8 registers of payload (2 VUE slots), if this is
 730        * the last slot or if we need to flush (see BAD_FILE varying case
 731        * above), emit a URB write send now to flush out the data.
 732        */
 733       int last = slot == vue_map->num_slots - 1;
 734       if (length == 8 || last)
 735          flush = true;
 736       if (flush) {
 737          fs_reg *payload_sources =
 738             ralloc_array(mem_ctx, fs_reg, length + header_size);
 739          fs_reg payload = fs_reg(VGRF, alloc.allocate(length + header_size),
 740                                  BRW_REGISTER_TYPE_F);
 741          payload_sources[0] = urb_handle;
 742
 743          if (opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT)
 744             payload_sources[1] = per_slot_offsets;
 745
 746          memcpy(&payload_sources[header_size], sources,
 747                 length * sizeof sources[0]);
 748
 749          abld.LOAD_PAYLOAD(payload, payload_sources, length + header_size,
 750                            header_size);
 751
 752          fs_inst *inst = abld.emit(opcode, reg_undef, payload);
 753          inst->eot = last && stage != MESA_SHADER_GEOMETRY;
 754          inst->mlen = length + header_size;
 755          inst->offset = urb_offset;
 756          urb_offset = starting_urb_offset + slot + 1;
 757          length = 0;
 758          flush = false;
 759       }
 760    }
 761 }
 762
 763 void
 764 fs_visitor::emit_cs_terminate()
 765 {
 766    assert(devinfo->gen >= 7);
 767
 768    /* We are getting the thread ID from the compute shader header */
 769    assert(stage == MESA_SHADER_COMPUTE);
 770
 771    /* We can't directly send from g0, since sends with EOT have to use
 772     * g112-127. So, copy it to a virtual register, The register allocator will
 773     * make sure it uses the appropriate register range.
 774     */
 775    struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
 776    fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 777    bld.group(8, 0).exec_all().MOV(payload, g0);
 778
 779    /* Send a message to the thread spawner to terminate the thread. */
 780    fs_inst *inst = bld.exec_all()
 781                       .emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload);
 782    inst->eot = true;
 783 }
 784
 785 void
 786 fs_visitor::emit_barrier()
 787 {
 788    assert(devinfo->gen >= 7);
 789    const uint32_t barrier_id_mask =
 790       devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;
 791
 792    /* We are getting the barrier ID from the compute shader header */
 793    assert(stage == MESA_SHADER_COMPUTE);
 794
 795    fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 796
 797    const fs_builder pbld = bld.exec_all().group(8, 0);
 798
 799    /* Clear the message payload */
 800    pbld.MOV(payload, brw_imm_ud(0u));
 801
 802    /* Copy the barrier id from r0.2 to the message payload reg.2 */
 803    fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
 804    pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));
 805
 806    /* Emit a gateway "barrier" message using the payload we set up, followed
 807     * by a wait instruction.
 808     */
 809    bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
 810 }
 811
 812 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
 813                        void *mem_ctx,
 814                        const void *key,
 815                        struct brw_stage_prog_data *prog_data,
 816                        struct gl_program *prog,
 817                        const nir_shader *shader,
 818                        unsigned dispatch_width,
 819                        int shader_time_index,
 820                        const struct brw_vue_map *input_vue_map)
 821    : backend_shader(compiler, log_data, mem_ctx, shader, prog_data),
 822      key(key), gs_compile(NULL), prog_data(prog_data), prog(prog),
 823      input_vue_map(input_vue_map),
 824      dispatch_width(dispatch_width),
 825      shader_time_index(shader_time_index),
 826      bld(fs_builder(this, dispatch_width).at_end())
 827 {
 828    init();
 829 }
 830
 831 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
 832                        void *mem_ctx,
 833                        struct brw_gs_compile *c,
 834                        struct brw_gs_prog_data *prog_data,
 835                        const nir_shader *shader,
 836                        int shader_time_index)
 837    : backend_shader(compiler, log_data, mem_ctx, shader,
 838                     &prog_data->base.base),
 839      key(&c->key), gs_compile(c),
 840      prog_data(&prog_data->base.base), prog(NULL),
 841      dispatch_width(8),
 842      shader_time_index(shader_time_index),
 843      bld(fs_builder(this, dispatch_width).at_end())
 844 {
 845    init();
 846 }
 847
 848
 849 void
 850 fs_visitor::init()
 851 {
 852    switch (stage) {
 853    case MESA_SHADER_FRAGMENT:
 854       key_tex = &((const brw_wm_prog_key *) key)->tex;
 855       break;
 856    case MESA_SHADER_VERTEX:
 857       key_tex = &((const brw_vs_prog_key *) key)->tex;
 858       break;
 859    case MESA_SHADER_TESS_CTRL:
 860       key_tex = &((const brw_tcs_prog_key *) key)->tex;
 861       break;
 862    case MESA_SHADER_TESS_EVAL:
 863       key_tex = &((const brw_tes_prog_key *) key)->tex;
 864       break;
 865    case MESA_SHADER_GEOMETRY:
 866       key_tex = &((const brw_gs_prog_key *) key)->tex;
 867       break;
 868    case MESA_SHADER_COMPUTE:
 869       key_tex = &((const brw_cs_prog_key*) key)->tex;
 870       break;
 871    default:
 872       unreachable("unhandled shader stage");
 873    }
 874
 875    if (stage == MESA_SHADER_COMPUTE) {
 876       const brw_cs_prog_data *cs_prog_data =
 877          (const brw_cs_prog_data *) prog_data;
 878       unsigned size = cs_prog_data->local_size[0] *
 879                       cs_prog_data->local_size[1] *
 880                       cs_prog_data->local_size[2];
 881       size = DIV_ROUND_UP(size, devinfo->max_cs_threads);
 882       min_dispatch_width = size > 16 ? 32 : (size > 8 ? 16 : 8);
 883    } else {
 884       min_dispatch_width = 8;
 885    }
 886
 887    this->prog_data = this->stage_prog_data;
 888
 889    this->failed = false;
 890    this->simd16_unsupported = false;
 891    this->no16_msg = NULL;
 892
 893    this->nir_locals = NULL;
 894    this->nir_ssa_values = NULL;
 895
 896    memset(&this->payload, 0, sizeof(this->payload));
 897    memset(this->output_components, 0, sizeof(this->output_components));
 898    this->source_depth_to_render_target = false;
 899    this->runtime_check_aads_emit = false;
 900    this->first_non_payload_grf = 0;
 901    this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 902
 903    this->virtual_grf_start = NULL;
 904    this->virtual_grf_end = NULL;
 905    this->live_intervals = NULL;
 906    this->regs_live_at_ip = NULL;
 907
 908    this->uniforms = 0;
 909    this->last_scratch = 0;
 910    this->pull_constant_loc = NULL;
 911    this->push_constant_loc = NULL;
 912
 913    this->promoted_constants = 0,
 914
 915    this->spilled_any_registers = false;
 916    this->do_dual_src = false;
 917 }
 918
 919 fs_visitor::~fs_visitor()
 920 {
 921 }