2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->uniform_block
!= -1)
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
203 fs_reg src0
, fs_reg src1
)
207 if (intel
->gen
>= 6) {
208 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
209 inst
->conditional_mod
= conditionalmod
;
211 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
213 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
218 /* Instruction selection: Produce a MOV.sat instead of
219 * MIN(MAX(val, 0), 1) when possible.
222 fs_visitor::try_emit_saturate(ir_expression
*ir
)
224 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
229 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
231 sat_val
->accept(this);
232 fs_reg src
= this->result
;
234 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
236 /* If the last instruction from our accept() didn't generate our
237 * src, generate a saturated MOV
239 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
240 if (!modify
|| modify
->regs_written() != 1) {
241 this->result
= fs_reg(this, ir
->type
);
242 fs_inst
*inst
= emit(MOV(this->result
, src
));
243 inst
->saturate
= true;
245 modify
->saturate
= true;
254 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
256 /* 3-src instructions were introduced in gen6. */
260 /* MAD can only handle floating-point data. */
261 if (ir
->type
!= glsl_type::float_type
)
264 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
265 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
267 if (!mul
|| mul
->operation
!= ir_binop_mul
)
270 if (nonmul
->as_constant() ||
271 mul
->operands
[0]->as_constant() ||
272 mul
->operands
[1]->as_constant())
275 nonmul
->accept(this);
276 fs_reg src0
= this->result
;
278 mul
->operands
[0]->accept(this);
279 fs_reg src1
= this->result
;
281 mul
->operands
[1]->accept(this);
282 fs_reg src2
= this->result
;
284 this->result
= fs_reg(this, ir
->type
);
285 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
291 fs_visitor::visit(ir_expression
*ir
)
293 unsigned int operand
;
297 assert(ir
->get_num_operands() <= 2);
299 if (try_emit_saturate(ir
))
301 if (ir
->operation
== ir_binop_add
) {
302 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
306 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
307 ir
->operands
[operand
]->accept(this);
308 if (this->result
.file
== BAD_FILE
) {
310 fail("Failed to get tree for expression operand:\n");
311 ir
->operands
[operand
]->accept(&v
);
313 op
[operand
] = this->result
;
315 /* Matrix expression operands should have been broken down to vector
316 * operations already.
318 assert(!ir
->operands
[operand
]->type
->is_matrix());
319 /* And then those vector operands should have been broken down to scalar.
321 assert(!ir
->operands
[operand
]->type
->is_vector());
324 /* Storage for our result. If our result goes into an assignment, it will
325 * just get copy-propagated out, so no worries.
327 this->result
= fs_reg(this, ir
->type
);
329 switch (ir
->operation
) {
330 case ir_unop_logic_not
:
331 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
332 * ones complement of the whole register, not just bit 0.
334 emit(XOR(this->result
, op
[0], fs_reg(1)));
337 op
[0].negate
= !op
[0].negate
;
338 this->result
= op
[0];
342 op
[0].negate
= false;
343 this->result
= op
[0];
346 temp
= fs_reg(this, ir
->type
);
348 emit(MOV(this->result
, fs_reg(0.0f
)));
350 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
351 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
352 inst
->predicate
= BRW_PREDICATE_NORMAL
;
354 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
355 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
356 inst
->predicate
= BRW_PREDICATE_NORMAL
;
360 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
364 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
367 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
371 assert(!"not reached: should be handled by ir_explog_to_explog2");
374 case ir_unop_sin_reduced
:
375 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
378 case ir_unop_cos_reduced
:
379 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
383 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
386 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
390 emit(ADD(this->result
, op
[0], op
[1]));
393 assert(!"not reached: should be handled by ir_sub_to_add_neg");
397 if (ir
->type
->is_integer()) {
398 /* For integer multiplication, the MUL uses the low 16 bits
399 * of one of the operands (src0 on gen6, src1 on gen7). The
400 * MACH accumulates in the contribution of the upper 16 bits
403 * FINISHME: Emit just the MUL if we know an operand is small
406 if (intel
->gen
>= 7 && dispatch_width
== 16)
407 fail("16-wide explicit accumulator operands unsupported\n");
409 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
411 emit(MUL(acc
, op
[0], op
[1]));
412 emit(MACH(reg_null_d
, op
[0], op
[1]));
413 emit(MOV(this->result
, fs_reg(acc
)));
415 emit(MUL(this->result
, op
[0], op
[1]));
419 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
420 assert(ir
->type
->is_integer());
421 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
424 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
425 assert(ir
->type
->is_integer());
426 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
430 case ir_binop_greater
:
431 case ir_binop_lequal
:
432 case ir_binop_gequal
:
434 case ir_binop_all_equal
:
435 case ir_binop_nequal
:
436 case ir_binop_any_nequal
:
437 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
438 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
440 emit(CMP(this->result
, op
[0], op
[1],
441 brw_conditional_for_comparison(ir
->operation
)));
444 case ir_binop_logic_xor
:
445 emit(XOR(this->result
, op
[0], op
[1]));
448 case ir_binop_logic_or
:
449 emit(OR(this->result
, op
[0], op
[1]));
452 case ir_binop_logic_and
:
453 emit(AND(this->result
, op
[0], op
[1]));
458 assert(!"not reached: should be handled by brw_fs_channel_expressions");
462 assert(!"not reached: should be handled by lower_noise");
465 case ir_quadop_vector
:
466 assert(!"not reached: should be handled by lower_quadop_vector");
470 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
474 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
477 case ir_unop_bitcast_i2f
:
478 case ir_unop_bitcast_u2f
:
479 op
[0].type
= BRW_REGISTER_TYPE_F
;
480 this->result
= op
[0];
483 case ir_unop_bitcast_f2u
:
484 op
[0].type
= BRW_REGISTER_TYPE_UD
;
485 this->result
= op
[0];
488 case ir_unop_bitcast_f2i
:
489 op
[0].type
= BRW_REGISTER_TYPE_D
;
490 this->result
= op
[0];
496 emit(MOV(this->result
, op
[0]));
500 inst
= emit(AND(this->result
, op
[0], fs_reg(1)));
503 temp
= fs_reg(this, glsl_type::int_type
);
504 emit(AND(temp
, op
[0], fs_reg(1)));
505 emit(MOV(this->result
, temp
));
510 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
514 emit(RNDZ(this->result
, op
[0]));
517 op
[0].negate
= !op
[0].negate
;
518 inst
= emit(RNDD(this->result
, op
[0]));
519 this->result
.negate
= true;
522 inst
= emit(RNDD(this->result
, op
[0]));
525 inst
= emit(FRC(this->result
, op
[0]));
527 case ir_unop_round_even
:
528 emit(RNDE(this->result
, op
[0]));
533 resolve_ud_negate(&op
[0]);
534 resolve_ud_negate(&op
[1]);
535 emit_minmax(ir
->operation
== ir_binop_min
?
536 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
537 this->result
, op
[0], op
[1]);
541 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
544 case ir_unop_bit_not
:
545 inst
= emit(NOT(this->result
, op
[0]));
547 case ir_binop_bit_and
:
548 inst
= emit(AND(this->result
, op
[0], op
[1]));
550 case ir_binop_bit_xor
:
551 inst
= emit(XOR(this->result
, op
[0], op
[1]));
553 case ir_binop_bit_or
:
554 inst
= emit(OR(this->result
, op
[0], op
[1]));
557 case ir_binop_lshift
:
558 inst
= emit(SHL(this->result
, op
[0], op
[1]));
561 case ir_binop_rshift
:
562 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
563 inst
= emit(ASR(this->result
, op
[0], op
[1]));
565 inst
= emit(SHR(this->result
, op
[0], op
[1]));
568 case ir_binop_ubo_load
:
569 /* This IR node takes a constant uniform block and a constant or
570 * variable byte offset within the block and loads a vector from that.
572 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
573 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
574 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
576 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
577 packed_consts
.type
= result
.type
;
579 if (intel
->gen
>= 7) {
580 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] / 16);
581 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
582 struct brw_reg g0
= retype(brw_vec8_grf(0, 0),
583 BRW_REGISTER_TYPE_UD
);
584 fs_inst
*setup
= emit(MOV(payload
, fs_reg(g0
)));
585 setup
->force_writemask_all
= true;
586 /* We don't need the second half of this vgrf to be filled with g1
587 * in the 16-wide case, but if we use force_uncompressed then live
588 * variable analysis won't consider this a def!
591 emit(FS_OPCODE_SET_GLOBAL_OFFSET
, payload
,
592 payload
, const_offset_reg
);
593 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
, packed_consts
,
594 surf_index
, payload
);
596 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0]);
597 fs_inst
*pull
= emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
605 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
606 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
607 /* UBO bools are any nonzero value. We consider bools to be
608 * values with the low bit set to 1. Convert them using CMP.
610 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
611 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
613 emit(MOV(result
, packed_consts
));
616 packed_consts
.smear
++;
619 /* The std140 packing rules don't allow vectors to cross 16-byte
620 * boundaries, and a reg is 32 bytes.
622 assert(packed_consts
.smear
< 8);
625 /* Turn the byte offset into a dword offset. */
626 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
627 emit(SHR(base_offset
, op
[1], fs_reg(2)));
629 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
630 fs_reg offset
= fs_reg(this, glsl_type::int_type
);
631 emit(ADD(offset
, base_offset
, fs_reg(i
)));
632 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
, offset
));
634 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
635 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
641 result
.reg_offset
= 0;
647 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
648 const glsl_type
*type
, bool predicated
)
650 switch (type
->base_type
) {
651 case GLSL_TYPE_FLOAT
:
655 for (unsigned int i
= 0; i
< type
->components(); i
++) {
656 l
.type
= brw_type_for_base_type(type
);
657 r
.type
= brw_type_for_base_type(type
);
659 if (predicated
|| !l
.equals(r
)) {
660 fs_inst
*inst
= emit(MOV(l
, r
));
661 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
668 case GLSL_TYPE_ARRAY
:
669 for (unsigned int i
= 0; i
< type
->length
; i
++) {
670 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
674 case GLSL_TYPE_STRUCT
:
675 for (unsigned int i
= 0; i
< type
->length
; i
++) {
676 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
681 case GLSL_TYPE_SAMPLER
:
685 assert(!"not reached");
690 /* If the RHS processing resulted in an instruction generating a
691 * temporary value, and it would be easy to rewrite the instruction to
692 * generate its result right into the LHS instead, do so. This ends
693 * up reliably removing instructions where it can be tricky to do so
694 * later without real UD chain information.
697 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
700 fs_inst
*pre_rhs_inst
,
701 fs_inst
*last_rhs_inst
)
703 /* Only attempt if we're doing a direct assignment. */
705 !(ir
->lhs
->type
->is_scalar() ||
706 (ir
->lhs
->type
->is_vector() &&
707 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
710 /* Make sure the last instruction generated our source reg. */
711 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
717 /* If last_rhs_inst wrote a different number of components than our LHS,
718 * we can't safely rewrite it.
720 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written())
723 /* Success! Rewrite the instruction. */
730 fs_visitor::visit(ir_assignment
*ir
)
735 /* FINISHME: arrays on the lhs */
736 ir
->lhs
->accept(this);
739 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
741 ir
->rhs
->accept(this);
744 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
746 assert(l
.file
!= BAD_FILE
);
747 assert(r
.file
!= BAD_FILE
);
749 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
753 emit_bool_to_cond_code(ir
->condition
);
756 if (ir
->lhs
->type
->is_scalar() ||
757 ir
->lhs
->type
->is_vector()) {
758 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
759 if (ir
->write_mask
& (1 << i
)) {
760 inst
= emit(MOV(l
, r
));
762 inst
->predicate
= BRW_PREDICATE_NORMAL
;
768 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
773 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
774 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
784 if (ir
->shadow_comparitor
) {
785 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
786 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
787 coordinate
.reg_offset
++;
789 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
792 if (ir
->op
== ir_tex
) {
793 /* There's no plain shadow compare message, so we use shadow
794 * compare with a bias of 0.0.
796 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
798 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
799 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
802 assert(!"Should not get here.");
805 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
807 } else if (ir
->op
== ir_tex
) {
808 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
809 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
810 coordinate
.reg_offset
++;
812 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
814 } else if (ir
->op
== ir_txd
) {
817 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
818 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
819 coordinate
.reg_offset
++;
821 /* the slots for u and v are always present, but r is optional */
822 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
825 * dPdx = dudx, dvdx, drdx
826 * dPdy = dudy, dvdy, drdy
828 * 1-arg: Does not exist.
830 * 2-arg: dudx dvdx dudy dvdy
831 * dPdx.x dPdx.y dPdy.x dPdy.y
834 * 3-arg: dudx dvdx drdx dudy dvdy drdy
835 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
838 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
839 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
842 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
844 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
845 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
848 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
849 } else if (ir
->op
== ir_txs
) {
850 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
852 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
855 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
856 * instructions. We'll need to do SIMD16 here.
859 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
861 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
862 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
864 coordinate
.reg_offset
++;
867 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
868 * be necessary for TXF (ld), but seems wise to do for all messages.
870 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
871 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
874 /* lod/bias appears after u/v/r. */
877 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
880 /* The unused upper half. */
885 /* Now, since we're doing simd16, the return is 2 interleaved
886 * vec4s where the odd-indexed ones are junk. We'll need to move
887 * this weirdness around to the expected layout.
890 const glsl_type
*vec_type
=
891 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
892 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
893 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
894 : BRW_REGISTER_TYPE_F
;
897 fs_inst
*inst
= NULL
;
900 inst
= emit(SHADER_OPCODE_TEX
, dst
);
903 inst
= emit(FS_OPCODE_TXB
, dst
);
906 inst
= emit(SHADER_OPCODE_TXL
, dst
);
909 inst
= emit(SHADER_OPCODE_TXD
, dst
);
912 inst
= emit(SHADER_OPCODE_TXS
, dst
);
915 inst
= emit(SHADER_OPCODE_TXF
, dst
);
918 inst
->base_mrf
= base_mrf
;
920 inst
->header_present
= true;
923 for (int i
= 0; i
< 4; i
++) {
924 emit(MOV(orig_dst
, dst
));
925 orig_dst
.reg_offset
++;
933 /* gen5's sampler has slots for u, v, r, array index, then optional
934 * parameters like shadow comparitor or LOD bias. If optional
935 * parameters aren't present, those base slots are optional and don't
936 * need to be included in the message.
938 * We don't fill in the unnecessary slots regardless, which may look
939 * surprising in the disassembly.
942 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
943 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
947 int reg_width
= dispatch_width
/ 8;
948 bool header_present
= false;
949 const int vector_elements
=
950 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
952 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
953 /* It appears that the ld instruction used for txf does its
954 * address bounds check before adding in the offset. To work
955 * around this, just add the integer offset to the integer texel
956 * coordinate, and don't put the offset in the header.
958 ir_constant
*offset
= ir
->offset
->as_constant();
959 for (int i
= 0; i
< vector_elements
; i
++) {
960 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
962 offset
->value
.i
[i
]));
963 coordinate
.reg_offset
++;
967 /* The offsets set up by the ir_texture visitor are in the
968 * m1 header, so we can't go headerless.
970 header_present
= true;
975 for (int i
= 0; i
< vector_elements
; i
++) {
976 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
978 coordinate
.reg_offset
++;
981 mlen
+= vector_elements
* reg_width
;
983 if (ir
->shadow_comparitor
) {
984 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
986 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
990 fs_inst
*inst
= NULL
;
993 inst
= emit(SHADER_OPCODE_TEX
, dst
);
996 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
997 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1000 inst
= emit(FS_OPCODE_TXB
, dst
);
1003 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1004 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1007 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1010 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1014 * dPdx = dudx, dvdx, drdx
1015 * dPdy = dudy, dvdy, drdy
1017 * Load up these values:
1018 * - dudx dudy dvdx dvdy drdx drdy
1019 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1021 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1022 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1026 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1031 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1035 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1037 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1040 mlen
= header_present
+ 4 * reg_width
;
1042 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
1044 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1047 inst
->base_mrf
= base_mrf
;
1049 inst
->header_present
= header_present
;
1052 fail("Message length >11 disallowed by hardware\n");
1059 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1060 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
1064 int reg_width
= dispatch_width
/ 8;
1065 bool header_present
= false;
1068 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1069 /* The offsets set up by the ir_texture visitor are in the
1070 * m1 header, so we can't go headerless.
1072 header_present
= true;
1077 if (ir
->shadow_comparitor
) {
1078 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1082 /* Set up the LOD info */
1087 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1091 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1095 if (dispatch_width
== 16)
1096 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1098 /* Load dPdx and the coordinate together:
1099 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1101 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1102 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1103 coordinate
.reg_offset
++;
1106 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1107 * only derivatives for (u, v, r).
1109 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1110 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1114 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1122 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1126 /* It appears that the ld instruction used for txf does its
1127 * address bounds check before adding in the offset. To work
1128 * around this, just add the integer offset to the integer texel
1129 * coordinate, and don't put the offset in the header.
1132 ir_constant
*offset
= ir
->offset
->as_constant();
1133 offsets
[0] = offset
->value
.i
[0];
1134 offsets
[1] = offset
->value
.i
[1];
1135 offsets
[2] = offset
->value
.i
[2];
1137 memset(offsets
, 0, sizeof(offsets
));
1140 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1141 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1142 coordinate
, offsets
[0]));
1143 coordinate
.reg_offset
++;
1146 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1149 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1150 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1151 coordinate
, offsets
[i
]));
1152 coordinate
.reg_offset
++;
1158 /* Set up the coordinate (except for cases where it was done above) */
1159 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1160 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1161 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1162 coordinate
.reg_offset
++;
1167 /* Generate the SEND */
1168 fs_inst
*inst
= NULL
;
1170 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1171 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1172 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1173 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1174 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1175 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1177 inst
->base_mrf
= base_mrf
;
1179 inst
->header_present
= header_present
;
1182 fail("Message length >11 disallowed by hardware\n");
1189 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1190 bool is_rect
, int sampler
, int texunit
)
1192 fs_inst
*inst
= NULL
;
1193 bool needs_gl_clamp
= true;
1194 fs_reg scale_x
, scale_y
;
1196 /* The 965 requires the EU to do the normalization of GL rectangle
1197 * texture coordinates. We use the program parameter state
1198 * tracking to get the scaling factor.
1202 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1203 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1204 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1205 int tokens
[STATE_LENGTH
] = {
1207 STATE_TEXRECT_SCALE
,
1213 if (dispatch_width
== 16) {
1214 fail("rectangle scale uniform setup not supported on 16-wide\n");
1218 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1219 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1221 GLuint index
= _mesa_add_state_reference(params
,
1222 (gl_state_index
*)tokens
);
1223 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1224 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1225 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1226 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1229 /* The 965 requires the EU to do the normalization of GL rectangle
1230 * texture coordinates. We use the program parameter state
1231 * tracking to get the scaling factor.
1233 if (intel
->gen
< 6 && is_rect
) {
1234 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1235 fs_reg src
= coordinate
;
1238 emit(MUL(dst
, src
, scale_x
));
1241 emit(MUL(dst
, src
, scale_y
));
1242 } else if (is_rect
) {
1243 /* On gen6+, the sampler handles the rectangle coordinates
1244 * natively, without needing rescaling. But that means we have
1245 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1246 * not [0, 1] like the default case below.
1248 needs_gl_clamp
= false;
1250 for (int i
= 0; i
< 2; i
++) {
1251 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1252 fs_reg chan
= coordinate
;
1253 chan
.reg_offset
+= i
;
1255 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1256 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1258 /* Our parameter comes in as 1.0/width or 1.0/height,
1259 * because that's what people normally want for doing
1260 * texture rectangle handling. We need width or height
1261 * for clamping, but we don't care enough to make a new
1262 * parameter type, so just invert back.
1264 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1265 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1266 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1268 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1269 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1274 if (ir
->coordinate
&& needs_gl_clamp
) {
1275 for (unsigned int i
= 0;
1276 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1277 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1278 fs_reg chan
= coordinate
;
1279 chan
.reg_offset
+= i
;
1281 fs_inst
*inst
= emit(MOV(chan
, chan
));
1282 inst
->saturate
= true;
1290 fs_visitor::visit(ir_texture
*ir
)
1292 fs_inst
*inst
= NULL
;
1294 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1295 /* FINISHME: We're failing to recompile our programs when the sampler is
1296 * updated. This only matters for the texture rectangle scale parameters
1297 * (pre-gen6, or gen6+ with GL_CLAMP).
1299 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1301 /* Should be lowered by do_lower_texture_projection */
1302 assert(!ir
->projector
);
1304 /* Generate code to compute all the subexpression trees. This has to be
1305 * done before loading any values into MRFs for the sampler message since
1306 * generating these values may involve SEND messages that need the MRFs.
1309 if (ir
->coordinate
) {
1310 ir
->coordinate
->accept(this);
1312 coordinate
= rescale_texcoord(ir
, this->result
,
1313 ir
->sampler
->type
->sampler_dimensionality
==
1314 GLSL_SAMPLER_DIM_RECT
,
1318 fs_reg shadow_comparitor
;
1319 if (ir
->shadow_comparitor
) {
1320 ir
->shadow_comparitor
->accept(this);
1321 shadow_comparitor
= this->result
;
1329 ir
->lod_info
.bias
->accept(this);
1333 ir
->lod_info
.grad
.dPdx
->accept(this);
1336 ir
->lod_info
.grad
.dPdy
->accept(this);
1337 lod2
= this->result
;
1342 ir
->lod_info
.lod
->accept(this);
1347 /* Writemasking doesn't eliminate channels on SIMD8 texture
1348 * samples, so don't worry about them.
1350 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1352 if (intel
->gen
>= 7) {
1353 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1355 } else if (intel
->gen
>= 5) {
1356 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1359 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1363 /* The header is set up by generate_tex() when necessary. */
1364 inst
->src
[0] = reg_undef
;
1366 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1367 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1369 inst
->sampler
= sampler
;
1371 if (ir
->shadow_comparitor
)
1372 inst
->shadow_compare
= true;
1374 /* fixup #layers for cube map arrays */
1375 if (ir
->op
== ir_txs
) {
1376 glsl_type
const *type
= ir
->sampler
->type
;
1377 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1378 type
->sampler_array
) {
1380 depth
.reg_offset
= 2;
1381 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1385 swizzle_result(ir
, dst
, sampler
);
1389 * Swizzle the result of a texture result. This is necessary for
1390 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1393 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1395 this->result
= orig_val
;
1397 if (ir
->op
== ir_txs
)
1400 if (ir
->type
== glsl_type::float_type
) {
1401 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1402 assert(ir
->sampler
->type
->sampler_shadow
);
1403 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1404 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1406 for (int i
= 0; i
< 4; i
++) {
1407 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1408 fs_reg l
= swizzled_result
;
1411 if (swiz
== SWIZZLE_ZERO
) {
1412 emit(MOV(l
, fs_reg(0.0f
)));
1413 } else if (swiz
== SWIZZLE_ONE
) {
1414 emit(MOV(l
, fs_reg(1.0f
)));
1416 fs_reg r
= orig_val
;
1417 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1421 this->result
= swizzled_result
;
1426 fs_visitor::visit(ir_swizzle
*ir
)
1428 ir
->val
->accept(this);
1429 fs_reg val
= this->result
;
1431 if (ir
->type
->vector_elements
== 1) {
1432 this->result
.reg_offset
+= ir
->mask
.x
;
1436 fs_reg result
= fs_reg(this, ir
->type
);
1437 this->result
= result
;
1439 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1440 fs_reg channel
= val
;
1458 channel
.reg_offset
+= swiz
;
1459 emit(MOV(result
, channel
));
1460 result
.reg_offset
++;
1465 fs_visitor::visit(ir_discard
*ir
)
1467 assert(ir
->condition
== NULL
); /* FINISHME */
1469 /* We track our discarded pixels in f0.1. By predicating on it, we can
1470 * update just the flag bits that aren't yet discarded. By emitting a
1471 * CMP of g0 != g0, all our currently executing channels will get turned
1474 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1475 BRW_REGISTER_TYPE_UW
));
1476 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1477 BRW_CONDITIONAL_NZ
));
1478 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1479 cmp
->flag_subreg
= 1;
1481 if (intel
->gen
>= 6) {
1482 /* For performance, after a discard, jump to the end of the shader.
1483 * However, many people will do foliage by discarding based on a
1484 * texture's alpha mask, and then continue on to texture with the
1485 * remaining pixels. To avoid trashing the derivatives for those
1486 * texture samples, we'll only jump if all of the pixels in the subspan
1487 * have been discarded.
1489 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1490 discard_jump
->flag_subreg
= 1;
1491 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1492 discard_jump
->predicate_inverse
= true;
1497 fs_visitor::visit(ir_constant
*ir
)
1499 /* Set this->result to reg at the bottom of the function because some code
1500 * paths will cause this visitor to be applied to other fields. This will
1501 * cause the value stored in this->result to be modified.
1503 * Make reg constant so that it doesn't get accidentally modified along the
1504 * way. Yes, I actually had this problem. :(
1506 const fs_reg
reg(this, ir
->type
);
1507 fs_reg dst_reg
= reg
;
1509 if (ir
->type
->is_array()) {
1510 const unsigned size
= type_size(ir
->type
->fields
.array
);
1512 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1513 ir
->array_elements
[i
]->accept(this);
1514 fs_reg src_reg
= this->result
;
1516 dst_reg
.type
= src_reg
.type
;
1517 for (unsigned j
= 0; j
< size
; j
++) {
1518 emit(MOV(dst_reg
, src_reg
));
1519 src_reg
.reg_offset
++;
1520 dst_reg
.reg_offset
++;
1523 } else if (ir
->type
->is_record()) {
1524 foreach_list(node
, &ir
->components
) {
1525 ir_constant
*const field
= (ir_constant
*) node
;
1526 const unsigned size
= type_size(field
->type
);
1528 field
->accept(this);
1529 fs_reg src_reg
= this->result
;
1531 dst_reg
.type
= src_reg
.type
;
1532 for (unsigned j
= 0; j
< size
; j
++) {
1533 emit(MOV(dst_reg
, src_reg
));
1534 src_reg
.reg_offset
++;
1535 dst_reg
.reg_offset
++;
1539 const unsigned size
= type_size(ir
->type
);
1541 for (unsigned i
= 0; i
< size
; i
++) {
1542 switch (ir
->type
->base_type
) {
1543 case GLSL_TYPE_FLOAT
:
1544 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1546 case GLSL_TYPE_UINT
:
1547 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1550 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1552 case GLSL_TYPE_BOOL
:
1553 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1556 assert(!"Non-float/uint/int/bool constant");
1558 dst_reg
.reg_offset
++;
1566 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1568 ir_expression
*expr
= ir
->as_expression();
1574 assert(expr
->get_num_operands() <= 2);
1575 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1576 assert(expr
->operands
[i
]->type
->is_scalar());
1578 expr
->operands
[i
]->accept(this);
1579 op
[i
] = this->result
;
1581 resolve_ud_negate(&op
[i
]);
1584 switch (expr
->operation
) {
1585 case ir_unop_logic_not
:
1586 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1587 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1590 case ir_binop_logic_xor
:
1591 case ir_binop_logic_or
:
1592 case ir_binop_logic_and
:
1596 if (intel
->gen
>= 6) {
1597 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1599 inst
= emit(MOV(reg_null_f
, op
[0]));
1600 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1605 if (intel
->gen
>= 6) {
1606 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1608 inst
= emit(MOV(reg_null_d
, op
[0]));
1609 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1613 case ir_binop_greater
:
1614 case ir_binop_gequal
:
1616 case ir_binop_lequal
:
1617 case ir_binop_equal
:
1618 case ir_binop_all_equal
:
1619 case ir_binop_nequal
:
1620 case ir_binop_any_nequal
:
1621 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1622 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1624 emit(CMP(reg_null_d
, op
[0], op
[1],
1625 brw_conditional_for_comparison(expr
->operation
)));
1629 assert(!"not reached");
1630 fail("bad cond code\n");
1639 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1640 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1644 * Emit a gen6 IF statement with the comparison folded into the IF
1648 fs_visitor::emit_if_gen6(ir_if
*ir
)
1650 ir_expression
*expr
= ir
->condition
->as_expression();
1657 assert(expr
->get_num_operands() <= 2);
1658 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1659 assert(expr
->operands
[i
]->type
->is_scalar());
1661 expr
->operands
[i
]->accept(this);
1662 op
[i
] = this->result
;
1665 switch (expr
->operation
) {
1666 case ir_unop_logic_not
:
1667 case ir_binop_logic_xor
:
1668 case ir_binop_logic_or
:
1669 case ir_binop_logic_and
:
1670 /* For operations on bool arguments, only the low bit of the bool is
1671 * valid, and the others are undefined. Fall back to the condition
1677 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1678 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1682 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1685 case ir_binop_greater
:
1686 case ir_binop_gequal
:
1688 case ir_binop_lequal
:
1689 case ir_binop_equal
:
1690 case ir_binop_all_equal
:
1691 case ir_binop_nequal
:
1692 case ir_binop_any_nequal
:
1693 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1694 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1696 emit(IF(op
[0], op
[1],
1697 brw_conditional_for_comparison(expr
->operation
)));
1700 assert(!"not reached");
1701 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1702 fail("bad condition\n");
1707 emit_bool_to_cond_code(ir
->condition
);
1708 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1709 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1713 fs_visitor::visit(ir_if
*ir
)
1715 if (intel
->gen
< 6 && dispatch_width
== 16) {
1716 fail("Can't support (non-uniform) control flow on 16-wide\n");
1719 /* Don't point the annotation at the if statement, because then it plus
1720 * the then and else blocks get printed.
1722 this->base_ir
= ir
->condition
;
1724 if (intel
->gen
== 6) {
1727 emit_bool_to_cond_code(ir
->condition
);
1729 emit(IF(BRW_PREDICATE_NORMAL
));
1732 foreach_list(node
, &ir
->then_instructions
) {
1733 ir_instruction
*ir
= (ir_instruction
*)node
;
1739 if (!ir
->else_instructions
.is_empty()) {
1740 emit(BRW_OPCODE_ELSE
);
1742 foreach_list(node
, &ir
->else_instructions
) {
1743 ir_instruction
*ir
= (ir_instruction
*)node
;
1750 emit(BRW_OPCODE_ENDIF
);
1754 fs_visitor::visit(ir_loop
*ir
)
1756 fs_reg counter
= reg_undef
;
1758 if (intel
->gen
< 6 && dispatch_width
== 16) {
1759 fail("Can't support (non-uniform) control flow on 16-wide\n");
1763 this->base_ir
= ir
->counter
;
1764 ir
->counter
->accept(this);
1765 counter
= *(variable_storage(ir
->counter
));
1768 this->base_ir
= ir
->from
;
1769 ir
->from
->accept(this);
1771 emit(MOV(counter
, this->result
));
1775 this->base_ir
= NULL
;
1776 emit(BRW_OPCODE_DO
);
1779 this->base_ir
= ir
->to
;
1780 ir
->to
->accept(this);
1782 emit(CMP(reg_null_d
, counter
, this->result
,
1783 brw_conditional_for_comparison(ir
->cmp
)));
1785 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1786 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1789 foreach_list(node
, &ir
->body_instructions
) {
1790 ir_instruction
*ir
= (ir_instruction
*)node
;
1796 if (ir
->increment
) {
1797 this->base_ir
= ir
->increment
;
1798 ir
->increment
->accept(this);
1799 emit(ADD(counter
, counter
, this->result
));
1802 this->base_ir
= NULL
;
1803 emit(BRW_OPCODE_WHILE
);
1807 fs_visitor::visit(ir_loop_jump
*ir
)
1810 case ir_loop_jump::jump_break
:
1811 emit(BRW_OPCODE_BREAK
);
1813 case ir_loop_jump::jump_continue
:
1814 emit(BRW_OPCODE_CONTINUE
);
1820 fs_visitor::visit(ir_call
*ir
)
1822 assert(!"FINISHME");
1826 fs_visitor::visit(ir_return
*ir
)
1828 assert(!"FINISHME");
1832 fs_visitor::visit(ir_function
*ir
)
1834 /* Ignore function bodies other than main() -- we shouldn't see calls to
1835 * them since they should all be inlined before we get to ir_to_mesa.
1837 if (strcmp(ir
->name
, "main") == 0) {
1838 const ir_function_signature
*sig
;
1841 sig
= ir
->matching_signature(&empty
);
1845 foreach_list(node
, &sig
->body
) {
1846 ir_instruction
*ir
= (ir_instruction
*)node
;
1855 fs_visitor::visit(ir_function_signature
*ir
)
1857 assert(!"not reached");
1862 fs_visitor::emit(fs_inst inst
)
1864 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1871 fs_visitor::emit(fs_inst
*inst
)
1873 if (force_uncompressed_stack
> 0)
1874 inst
->force_uncompressed
= true;
1875 else if (force_sechalf_stack
> 0)
1876 inst
->force_sechalf
= true;
1878 inst
->annotation
= this->current_annotation
;
1879 inst
->ir
= this->base_ir
;
1881 this->instructions
.push_tail(inst
);
1887 fs_visitor::emit(exec_list list
)
1889 foreach_list_safe(node
, &list
) {
1890 fs_inst
*inst
= (fs_inst
*)node
;
1896 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1898 fs_visitor::emit_dummy_fs()
1900 int reg_width
= dispatch_width
/ 8;
1902 /* Everyone's favorite color. */
1903 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
1904 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
1905 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
1906 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
1909 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1910 write
->base_mrf
= 2;
1911 write
->mlen
= 4 * reg_width
;
1915 /* The register location here is relative to the start of the URB
1916 * data. It will get adjusted to be a real location before
1917 * generate_code() time.
1920 fs_visitor::interp_reg(int location
, int channel
)
1922 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1923 int stride
= (channel
& 1) * 4;
1925 assert(urb_setup
[location
] != -1);
1927 return brw_vec1_grf(regnr
, stride
);
1930 /** Emits the interpolation for the varying inputs. */
1932 fs_visitor::emit_interpolation_setup_gen4()
1934 this->current_annotation
= "compute pixel centers";
1935 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1936 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1937 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1938 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1940 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1941 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1943 this->current_annotation
= "compute pixel deltas from v0";
1945 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1946 fs_reg(this, glsl_type::vec2_type
);
1947 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1948 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1949 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1951 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1952 fs_reg(this, glsl_type::float_type
);
1953 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1954 fs_reg(this, glsl_type::float_type
);
1956 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1957 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
1958 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1959 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
1961 this->current_annotation
= "compute pos.w and 1/pos.w";
1962 /* Compute wpos.w. It's always in our setup, since it's needed to
1963 * interpolate the other attributes.
1965 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1966 emit(FS_OPCODE_LINTERP
, wpos_w
,
1967 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1968 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1969 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1970 /* Compute the pixel 1/W value from wpos.w. */
1971 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1972 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1973 this->current_annotation
= NULL
;
1976 /** Emits the interpolation for the varying inputs. */
1978 fs_visitor::emit_interpolation_setup_gen6()
1980 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1982 /* If the pixel centers end up used, the setup is the same as for gen4. */
1983 this->current_annotation
= "compute pixel centers";
1984 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1985 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1986 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1987 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1988 emit(ADD(int_pixel_x
,
1989 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1990 fs_reg(brw_imm_v(0x10101010))));
1991 emit(ADD(int_pixel_y
,
1992 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1993 fs_reg(brw_imm_v(0x11001100))));
1995 /* As of gen6, we can no longer mix float and int sources. We have
1996 * to turn the integer pixel centers into floats for their actual
1999 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2000 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2001 emit(MOV(this->pixel_x
, int_pixel_x
));
2002 emit(MOV(this->pixel_y
, int_pixel_y
));
2004 this->current_annotation
= "compute pos.w";
2005 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2006 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2007 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2009 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2010 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2011 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2012 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2015 this->current_annotation
= NULL
;
2019 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2021 int reg_width
= dispatch_width
/ 8;
2023 fs_reg color
= outputs
[target
];
2026 /* If there's no color data to be written, skip it. */
2027 if (color
.file
== BAD_FILE
)
2030 color
.reg_offset
+= index
;
2032 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2033 /* SIMD8 write looks like:
2039 * gen6 SIMD16 DP write looks like:
2049 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2052 inst
->saturate
= c
->key
.clamp_fragment_color
;
2054 /* pre-gen6 SIMD16 single source DP write looks like:
2064 if (brw
->has_compr4
) {
2065 /* By setting the high bit of the MRF register number, we
2066 * indicate that we want COMPR4 mode - instead of doing the
2067 * usual destination + 1 for the second half we get
2070 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2073 inst
->saturate
= c
->key
.clamp_fragment_color
;
2075 push_force_uncompressed();
2076 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2078 inst
->saturate
= c
->key
.clamp_fragment_color
;
2079 pop_force_uncompressed();
2081 push_force_sechalf();
2082 color
.sechalf
= true;
2083 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2085 inst
->saturate
= c
->key
.clamp_fragment_color
;
2086 pop_force_sechalf();
2087 color
.sechalf
= false;
2093 fs_visitor::emit_fb_writes()
2095 this->current_annotation
= "FB write header";
2096 bool header_present
= true;
2097 /* We can potentially have a message length of up to 15, so we have to set
2098 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2102 int reg_width
= dispatch_width
/ 8;
2103 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2104 bool src0_alpha_to_render_target
= false;
2106 if (dispatch_width
== 16 && do_dual_src
) {
2107 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2108 do_dual_src
= false;
2111 /* From the Sandy Bridge PRM, volume 4, page 198:
2113 * "Dispatched Pixel Enables. One bit per pixel indicating
2114 * which pixels were originally enabled when the thread was
2115 * dispatched. This field is only required for the end-of-
2116 * thread message and on all dual-source messages."
2118 if (intel
->gen
>= 6 &&
2119 !this->fp
->UsesKill
&&
2121 c
->key
.nr_color_regions
== 1) {
2122 header_present
= false;
2125 if (header_present
) {
2126 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2128 c
->key
.nr_color_regions
> 1 &&
2129 c
->key
.sample_alpha_to_coverage
;
2134 if (c
->aa_dest_stencil_reg
) {
2135 push_force_uncompressed();
2136 emit(MOV(fs_reg(MRF
, nr
++),
2137 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2138 pop_force_uncompressed();
2141 /* Reserve space for color. It'll be filled in per MRT below. */
2143 nr
+= 4 * reg_width
;
2146 if (src0_alpha_to_render_target
)
2149 if (c
->source_depth_to_render_target
) {
2150 if (intel
->gen
== 6 && dispatch_width
== 16) {
2151 /* For outputting oDepth on gen6, SIMD8 writes have to be
2152 * used. This would require 8-wide moves of each half to
2153 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2154 * Just bail on doing so for now.
2156 fail("Missing support for simd16 depth writes on gen6\n");
2159 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2160 /* Hand over gl_FragDepth. */
2161 assert(this->frag_depth
.file
!= BAD_FILE
);
2162 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2164 /* Pass through the payload depth. */
2165 emit(MOV(fs_reg(MRF
, nr
),
2166 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2171 if (c
->dest_depth_reg
) {
2172 emit(MOV(fs_reg(MRF
, nr
),
2173 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2178 fs_reg src0
= this->outputs
[0];
2179 fs_reg src1
= this->dual_src_output
;
2181 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2183 for (int i
= 0; i
< 4; i
++) {
2184 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2186 inst
->saturate
= c
->key
.clamp_fragment_color
;
2189 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2191 for (int i
= 0; i
< 4; i
++) {
2192 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2195 inst
->saturate
= c
->key
.clamp_fragment_color
;
2198 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2200 inst
->base_mrf
= base_mrf
;
2201 inst
->mlen
= nr
- base_mrf
;
2203 inst
->header_present
= header_present
;
2205 c
->prog_data
.dual_src_blend
= true;
2206 this->current_annotation
= NULL
;
2210 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2211 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2212 "FB write target %d",
2214 /* If src0_alpha_to_render_target is true, include source zero alpha
2215 * data in RenderTargetWrite message for targets > 0.
2217 int write_color_mrf
= color_mrf
;
2218 if (src0_alpha_to_render_target
&& target
!= 0) {
2220 fs_reg color
= outputs
[0];
2221 color
.reg_offset
+= 3;
2223 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2225 inst
->saturate
= c
->key
.clamp_fragment_color
;
2226 write_color_mrf
= color_mrf
+ reg_width
;
2229 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2230 emit_color_write(target
, i
, write_color_mrf
);
2232 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2233 inst
->target
= target
;
2234 inst
->base_mrf
= base_mrf
;
2235 if (src0_alpha_to_render_target
&& target
== 0)
2236 inst
->mlen
= nr
- base_mrf
- reg_width
;
2238 inst
->mlen
= nr
- base_mrf
;
2239 if (target
== c
->key
.nr_color_regions
- 1)
2241 inst
->header_present
= header_present
;
2244 if (c
->key
.nr_color_regions
== 0) {
2245 /* Even if there's no color buffers enabled, we still need to send
2246 * alpha out the pipeline to our null renderbuffer to support
2247 * alpha-testing, alpha-to-coverage, and so on.
2249 emit_color_write(0, 3, color_mrf
);
2251 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2252 inst
->base_mrf
= base_mrf
;
2253 inst
->mlen
= nr
- base_mrf
;
2255 inst
->header_present
= header_present
;
2258 this->current_annotation
= NULL
;
2262 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2264 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2268 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2269 emit(MOV(temp
, *reg
));
2274 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2276 if (rvalue
->type
!= glsl_type::bool_type
)
2279 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2280 emit(AND(temp
, *reg
, fs_reg(1)));
2284 fs_visitor::fs_visitor(struct brw_context
*brw
,
2285 struct brw_wm_compile
*c
,
2286 struct gl_shader_program
*prog
,
2287 struct gl_fragment_program
*fp
,
2288 unsigned dispatch_width
)
2289 : dispatch_width(dispatch_width
)
2295 this->intel
= &brw
->intel
;
2296 this->ctx
= &intel
->ctx
;
2297 this->mem_ctx
= ralloc_context(NULL
);
2299 shader
= (struct brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2302 this->failed
= false;
2303 this->variable_ht
= hash_table_ctor(0,
2304 hash_table_pointer_hash
,
2305 hash_table_pointer_compare
);
2307 memset(this->outputs
, 0, sizeof(this->outputs
));
2308 memset(this->output_components
, 0, sizeof(this->output_components
));
2309 this->first_non_payload_grf
= 0;
2310 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2312 this->current_annotation
= NULL
;
2313 this->base_ir
= NULL
;
2315 this->virtual_grf_sizes
= NULL
;
2316 this->virtual_grf_count
= 0;
2317 this->virtual_grf_array_size
= 0;
2318 this->virtual_grf_def
= NULL
;
2319 this->virtual_grf_use
= NULL
;
2320 this->live_intervals_valid
= false;
2322 this->force_uncompressed_stack
= 0;
2323 this->force_sechalf_stack
= 0;
2325 memset(&this->param_size
, 0, sizeof(this->param_size
));
2328 fs_visitor::~fs_visitor()
2330 ralloc_free(this->mem_ctx
);
2331 hash_table_dtor(this->variable_ht
);