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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
45 #include "main/uniforms.h"
46 #include "glsl/glsl_types.h"
47 #include "glsl/ir_optimization.h"
48 #include "program/sampler.h"
52 fs_visitor::emit_vs_system_value(int location
)
54 fs_reg
*reg
= new(this->mem_ctx
)
55 fs_reg(ATTR
, VERT_ATTRIB_MAX
, BRW_REGISTER_TYPE_D
);
56 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
59 case SYSTEM_VALUE_BASE_VERTEX
:
61 vs_prog_data
->uses_vertexid
= true;
63 case SYSTEM_VALUE_VERTEX_ID
:
64 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
66 vs_prog_data
->uses_vertexid
= true;
68 case SYSTEM_VALUE_INSTANCE_ID
:
70 vs_prog_data
->uses_instanceid
= true;
73 unreachable("not reached");
80 fs_visitor::visit(ir_variable
*ir
)
84 if (variable_storage(ir
))
87 if (ir
->data
.mode
== ir_var_shader_in
) {
88 assert(ir
->data
.location
!= -1);
89 if (stage
== MESA_SHADER_VERTEX
) {
90 reg
= new(this->mem_ctx
)
91 fs_reg(ATTR
, ir
->data
.location
,
92 brw_type_for_base_type(ir
->type
->get_scalar_type()));
93 } else if (ir
->data
.location
== VARYING_SLOT_POS
) {
94 reg
= emit_fragcoord_interpolation(ir
->data
.pixel_center_integer
,
95 ir
->data
.origin_upper_left
);
96 } else if (ir
->data
.location
== VARYING_SLOT_FACE
) {
97 reg
= emit_frontfacing_interpolation();
99 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
100 emit_general_interpolation(*reg
, ir
->name
, ir
->type
,
101 (glsl_interp_qualifier
) ir
->data
.interpolation
,
102 ir
->data
.location
, ir
->data
.centroid
,
106 hash_table_insert(this->variable_ht
, reg
, ir
);
108 } else if (ir
->data
.mode
== ir_var_shader_out
) {
109 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
111 if (stage
== MESA_SHADER_VERTEX
) {
112 int vector_elements
=
113 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
114 : ir
->type
->vector_elements
;
116 for (int i
= 0; i
< (type_size(ir
->type
) + 3) / 4; i
++) {
117 int output
= ir
->data
.location
+ i
;
118 this->outputs
[output
] = *reg
;
119 this->outputs
[output
].reg_offset
= i
* 4;
120 this->output_components
[output
] = vector_elements
;
123 } else if (ir
->data
.index
> 0) {
124 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
125 assert(ir
->data
.index
== 1);
126 this->dual_src_output
= *reg
;
127 this->do_dual_src
= true;
128 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
129 /* Writing gl_FragColor outputs to all color regions. */
130 assert(stage
== MESA_SHADER_FRAGMENT
);
131 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
132 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
133 this->outputs
[i
] = *reg
;
134 this->output_components
[i
] = 4;
136 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
137 this->frag_depth
= *reg
;
138 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
139 this->sample_mask
= *reg
;
141 /* gl_FragData or a user-defined FS output */
142 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
143 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
145 int vector_elements
=
146 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
147 : ir
->type
->vector_elements
;
149 /* General color output. */
150 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
151 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
152 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
153 this->output_components
[output
] = vector_elements
;
156 } else if (ir
->data
.mode
== ir_var_uniform
) {
157 int param_index
= uniforms
;
159 /* Thanks to the lower_ubo_reference pass, we will see only
160 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
161 * variables, so no need for them to be in variable_ht.
163 * Some uniforms, such as samplers and atomic counters, have no actual
164 * storage, so we should ignore them.
166 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
169 if (dispatch_width
== 16) {
170 if (!variable_storage(ir
)) {
171 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
176 param_size
[param_index
] = type_size(ir
->type
);
177 if (!strncmp(ir
->name
, "gl_", 3)) {
178 setup_builtin_uniform_values(ir
);
180 setup_uniform_values(ir
);
183 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
184 reg
->type
= brw_type_for_base_type(ir
->type
);
186 } else if (ir
->data
.mode
== ir_var_system_value
) {
187 switch (ir
->data
.location
) {
188 case SYSTEM_VALUE_BASE_VERTEX
:
189 case SYSTEM_VALUE_VERTEX_ID
:
190 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
191 case SYSTEM_VALUE_INSTANCE_ID
:
192 reg
= emit_vs_system_value(ir
->data
.location
);
194 case SYSTEM_VALUE_SAMPLE_POS
:
195 reg
= emit_samplepos_setup();
197 case SYSTEM_VALUE_SAMPLE_ID
:
198 reg
= emit_sampleid_setup();
200 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
201 assert(devinfo
->gen
>= 7);
203 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
204 BRW_REGISTER_TYPE_D
));
210 reg
= new(this->mem_ctx
) fs_reg(vgrf(ir
->type
));
212 hash_table_insert(this->variable_ht
, reg
, ir
);
216 fs_visitor::visit(ir_dereference_variable
*ir
)
218 fs_reg
*reg
= variable_storage(ir
->var
);
221 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
222 this->result
= fs_reg(reg_null_d
);
229 fs_visitor::visit(ir_dereference_record
*ir
)
231 const glsl_type
*struct_type
= ir
->record
->type
;
233 ir
->record
->accept(this);
235 unsigned int off
= 0;
236 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
237 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
239 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
241 this->result
= offset(this->result
, off
);
242 this->result
.type
= brw_type_for_base_type(ir
->type
);
246 fs_visitor::visit(ir_dereference_array
*ir
)
248 ir_constant
*constant_index
;
250 int element_size
= type_size(ir
->type
);
252 constant_index
= ir
->array_index
->as_constant();
254 ir
->array
->accept(this);
256 src
.type
= brw_type_for_base_type(ir
->type
);
258 if (constant_index
) {
259 if (src
.file
== ATTR
) {
260 /* Attribute arrays get loaded as one vec4 per element. In that case
261 * offset the source register.
263 src
.reg
+= constant_index
->value
.i
[0];
265 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
266 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
269 /* Variable index array dereference. We attach the variable index
270 * component to the reg as a pointer to a register containing the
271 * offset. Currently only uniform arrays are supported in this patch,
272 * and that reladdr pointer is resolved by
273 * move_uniform_array_access_to_pull_constants(). All other array types
274 * are lowered by lower_variable_index_to_cond_assign().
276 ir
->array_index
->accept(this);
279 index_reg
= vgrf(glsl_type::int_type
);
280 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
283 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
286 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
287 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
293 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
296 if (devinfo
->gen
< 6) {
297 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
298 fs_reg y_times_a
= vgrf(glsl_type::float_type
);
299 fs_reg one_minus_a
= vgrf(glsl_type::float_type
);
300 fs_reg x_times_one_minus_a
= vgrf(glsl_type::float_type
);
302 emit(MUL(y_times_a
, y
, a
));
304 fs_reg negative_a
= a
;
305 negative_a
.negate
= !a
.negate
;
306 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
307 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
309 return emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
311 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
312 * we need to reorder the operands.
314 return emit(LRP(dst
, a
, y
, x
));
319 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
320 const fs_reg
&src0
, const fs_reg
&src1
)
322 assert(conditionalmod
== BRW_CONDITIONAL_GE
||
323 conditionalmod
== BRW_CONDITIONAL_L
);
327 if (devinfo
->gen
>= 6) {
328 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
329 inst
->conditional_mod
= conditionalmod
;
331 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
333 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
334 inst
->predicate
= BRW_PREDICATE_NORMAL
;
339 fs_visitor::try_emit_saturate(ir_expression
*ir
)
341 if (ir
->operation
!= ir_unop_saturate
)
344 ir_rvalue
*sat_val
= ir
->operands
[0];
346 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
348 sat_val
->accept(this);
349 fs_reg src
= this->result
;
351 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
353 /* If the last instruction from our accept() generated our
354 * src, just set the saturate flag instead of emmitting a separate mov.
356 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
357 if (modify
&& modify
->regs_written
== modify
->dst
.width
/ 8 &&
358 modify
->can_do_saturate()) {
359 modify
->saturate
= true;
368 fs_visitor::try_emit_line(ir_expression
*ir
)
370 /* LINE's src0 must be of type float. */
371 if (ir
->type
!= glsl_type::float_type
)
374 ir_rvalue
*nonmul
= ir
->operands
[1];
375 ir_expression
*mul
= ir
->operands
[0]->as_expression();
377 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
378 nonmul
= ir
->operands
[0];
379 mul
= ir
->operands
[1]->as_expression();
381 if (!mul
|| mul
->operation
!= ir_binop_mul
)
385 ir_constant
*const_add
= nonmul
->as_constant();
389 int add_operand_vf
= brw_float_to_vf(const_add
->value
.f
[0]);
390 if (add_operand_vf
== -1)
393 ir_rvalue
*non_const_mul
= mul
->operands
[1];
394 ir_constant
*const_mul
= mul
->operands
[0]->as_constant();
396 const_mul
= mul
->operands
[1]->as_constant();
401 non_const_mul
= mul
->operands
[0];
404 int mul_operand_vf
= brw_float_to_vf(const_mul
->value
.f
[0]);
405 if (mul_operand_vf
== -1)
408 non_const_mul
->accept(this);
409 fs_reg src1
= this->result
;
411 fs_reg src0
= vgrf(ir
->type
);
412 emit(BRW_OPCODE_MOV
, src0
,
413 fs_reg((uint8_t)mul_operand_vf
, 0, 0, (uint8_t)add_operand_vf
));
415 this->result
= vgrf(ir
->type
);
416 emit(BRW_OPCODE_LINE
, this->result
, src0
, src1
);
421 fs_visitor::try_emit_mad(ir_expression
*ir
)
423 /* 3-src instructions were introduced in gen6. */
424 if (devinfo
->gen
< 6)
427 /* MAD can only handle floating-point data. */
428 if (ir
->type
!= glsl_type::float_type
)
433 bool mul_negate
, mul_abs
;
435 for (int i
= 0; i
< 2; i
++) {
439 mul
= ir
->operands
[i
]->as_expression();
440 nonmul
= ir
->operands
[1 - i
];
442 if (mul
&& mul
->operation
== ir_unop_abs
) {
443 mul
= mul
->operands
[0]->as_expression();
445 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
446 mul
= mul
->operands
[0]->as_expression();
450 if (mul
&& mul
->operation
== ir_binop_mul
)
454 if (!mul
|| mul
->operation
!= ir_binop_mul
)
457 nonmul
->accept(this);
458 fs_reg src0
= this->result
;
460 mul
->operands
[0]->accept(this);
461 fs_reg src1
= this->result
;
462 src1
.negate
^= mul_negate
;
467 mul
->operands
[1]->accept(this);
468 fs_reg src2
= this->result
;
473 this->result
= vgrf(ir
->type
);
474 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
480 fs_visitor::try_emit_b2f_of_comparison(ir_expression
*ir
)
482 /* On platforms that do not natively generate 0u and ~0u for Boolean
483 * results, b2f expressions that look like
485 * f = b2f(expr cmp 0)
487 * will generate better code by pretending the expression is
489 * f = ir_triop_csel(0.0, 1.0, expr cmp 0)
491 * This is because the last instruction of "expr" can generate the
492 * condition code for the "cmp 0". This avoids having to do the "-(b & 1)"
493 * trick to generate 0u or ~0u for the Boolean result. This means code like
496 * mul.ge.f0(16) null g6<8,8,1>F g14<8,8,1>F
497 * (+f0) sel(16) m6<1>F g16<8,8,1>F 0F
499 * will be generated instead of
501 * mul(16) g2<1>F g12<8,8,1>F g4<8,8,1>F
502 * cmp.ge.f0(16) g2<1>D g4<8,8,1>F 0F
503 * and(16) g4<1>D g2<8,8,1>D 1D
504 * and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD
506 * When the comparison is != 0.0 using the knowledge that the false case
507 * already results in zero would allow better code generation by possibly
508 * avoiding a load-immediate instruction.
510 ir_expression
*cmp
= ir
->operands
[0]->as_expression();
514 if (cmp
->operation
== ir_binop_nequal
) {
515 for (unsigned i
= 0; i
< 2; i
++) {
516 ir_constant
*c
= cmp
->operands
[i
]->as_constant();
517 if (c
== NULL
|| !c
->is_zero())
520 ir_expression
*expr
= cmp
->operands
[i
^ 1]->as_expression();
524 for (unsigned j
= 0; j
< 2; j
++) {
525 cmp
->operands
[j
]->accept(this);
526 op
[j
] = this->result
;
528 resolve_ud_negate(&op
[j
]);
531 emit_bool_to_cond_code_of_reg(cmp
, op
);
533 /* In this case we know when the condition is true, op[i ^ 1]
534 * contains zero. Invert the predicate, use op[i ^ 1] as src0,
535 * and immediate 1.0f as src1.
537 this->result
= vgrf(ir
->type
);
538 op
[i
^ 1].type
= BRW_REGISTER_TYPE_F
;
540 fs_inst
*inst
= emit(SEL(this->result
, op
[i
^ 1], fs_reg(1.0f
)));
541 inst
->predicate
= BRW_PREDICATE_NORMAL
;
542 inst
->predicate_inverse
= true;
548 emit_bool_to_cond_code(cmp
);
550 fs_reg temp
= vgrf(ir
->type
);
551 emit(MOV(temp
, fs_reg(1.0f
)));
553 this->result
= vgrf(ir
->type
);
554 fs_inst
*inst
= emit(SEL(this->result
, temp
, fs_reg(0.0f
)));
555 inst
->predicate
= BRW_PREDICATE_NORMAL
;
561 pack_pixel_offset(float x
)
563 /* Clamp upper end of the range to +7/16. See explanation in non-constant
564 * offset case below. */
565 int n
= MIN2((int)(x
* 16), 7);
570 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
572 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
573 * 8 channels at a time, same as the barycentric coords presented in
574 * the FS payload. this requires a bit of extra work to support.
576 no16("interpolate_at_* not yet supported in SIMD16 mode.");
578 assert(stage
== MESA_SHADER_FRAGMENT
);
579 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
581 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
582 ir_swizzle
* swiz
= NULL
;
584 /* the api does not allow a swizzle here, but the varying packing code
585 * may have pushed one into here.
587 swiz
= ir
->operands
[0]->as_swizzle();
589 deref
= swiz
->val
->as_dereference();
592 ir_variable
* var
= deref
->variable_referenced();
595 /* 1. collect interpolation factors */
597 fs_reg dst_xy
= vgrf(glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
599 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
600 * even when there is no payload. in the per-slot offset case, we'll replace this with
601 * the proper source data. */
602 fs_reg src
= vgrf(glsl_type::float_type
);
603 int mlen
= 1; /* one reg unless overriden */
604 int reg_width
= dispatch_width
/ 8;
607 switch (ir
->operation
) {
608 case ir_unop_interpolate_at_centroid
:
609 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_xy
, src
, fs_reg(0u));
612 case ir_binop_interpolate_at_sample
: {
613 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
614 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
616 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
617 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
, fs_reg(msg_data
));
621 case ir_binop_interpolate_at_offset
: {
622 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
624 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
625 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
626 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
629 /* pack the operands: hw wants offsets as 4 bit signed ints */
630 ir
->operands
[1]->accept(this);
631 src
= vgrf(glsl_type::ivec2_type
);
633 for (int i
= 0; i
< 2; i
++) {
634 fs_reg temp
= vgrf(glsl_type::float_type
);
635 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
636 emit(MOV(src2
, temp
)); /* float to int */
638 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
639 * that we support a maximum offset of +0.5, which isn't representable
640 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
641 * which is the opposite of what the shader author wanted.
643 * This is legal due to ARB_gpu_shader5's quantization rules:
645 * "Not all values of <offset> may be supported; x and y offsets may
646 * be rounded to fixed-point values with the number of fraction bits
647 * given by the implementation-dependent constant
648 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
651 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
652 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
654 src2
= offset(src2
, 1);
655 this->result
= offset(this->result
, 1);
658 mlen
= 2 * reg_width
;
659 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
666 unreachable("not reached");
670 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
671 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
672 INTERP_QUALIFIER_NOPERSPECTIVE
;
674 /* 2. emit linterp */
676 fs_reg res
= vgrf(ir
->type
);
679 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
680 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
681 emit(FS_OPCODE_LINTERP
, res
, dst_xy
,
682 fs_reg(interp_reg(var
->data
.location
, ch
)));
683 res
= offset(res
, 1);
688 fs_visitor::visit(ir_expression
*ir
)
690 unsigned int operand
;
693 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
695 assert(ir
->get_num_operands() <= 3);
697 if (try_emit_saturate(ir
))
700 /* Deal with the real oddball stuff first */
701 switch (ir
->operation
) {
703 if (devinfo
->gen
<= 5 && try_emit_line(ir
))
705 if (try_emit_mad(ir
))
710 ir
->operands
[1]->accept(this);
711 op
[1] = this->result
;
712 ir
->operands
[2]->accept(this);
713 op
[2] = this->result
;
715 emit_bool_to_cond_code(ir
->operands
[0]);
717 this->result
= vgrf(ir
->type
);
718 inst
= emit(SEL(this->result
, op
[1], op
[2]));
719 inst
->predicate
= BRW_PREDICATE_NORMAL
;
723 if (devinfo
->gen
<= 5 && try_emit_b2f_of_comparison(ir
))
727 case ir_unop_interpolate_at_centroid
:
728 case ir_binop_interpolate_at_offset
:
729 case ir_binop_interpolate_at_sample
:
730 emit_interpolate_expression(ir
);
737 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
738 ir
->operands
[operand
]->accept(this);
739 if (this->result
.file
== BAD_FILE
) {
740 fail("Failed to get tree for expression operand:\n");
741 ir
->operands
[operand
]->fprint(stderr
);
742 fprintf(stderr
, "\n");
744 assert(this->result
.file
== GRF
||
745 this->result
.file
== UNIFORM
|| this->result
.file
== ATTR
);
746 op
[operand
] = this->result
;
748 /* Matrix expression operands should have been broken down to vector
749 * operations already.
751 assert(!ir
->operands
[operand
]->type
->is_matrix());
752 /* And then those vector operands should have been broken down to scalar.
754 assert(!ir
->operands
[operand
]->type
->is_vector());
757 /* Storage for our result. If our result goes into an assignment, it will
758 * just get copy-propagated out, so no worries.
760 this->result
= vgrf(ir
->type
);
762 switch (ir
->operation
) {
763 case ir_unop_logic_not
:
764 emit(NOT(this->result
, op
[0]));
767 op
[0].negate
= !op
[0].negate
;
768 emit(MOV(this->result
, op
[0]));
772 op
[0].negate
= false;
773 emit(MOV(this->result
, op
[0]));
776 if (ir
->type
->is_float()) {
777 /* AND(val, 0x80000000) gives the sign bit.
779 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
782 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
784 op
[0].type
= BRW_REGISTER_TYPE_UD
;
785 this->result
.type
= BRW_REGISTER_TYPE_UD
;
786 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
788 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
789 inst
->predicate
= BRW_PREDICATE_NORMAL
;
791 this->result
.type
= BRW_REGISTER_TYPE_F
;
793 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
794 * -> non-negative val generates 0x00000000.
795 * Predicated OR sets 1 if val is positive.
797 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
799 emit(ASR(this->result
, op
[0], fs_reg(31)));
801 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
802 inst
->predicate
= BRW_PREDICATE_NORMAL
;
806 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
810 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
813 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
817 unreachable("not reached: should be handled by ir_explog_to_explog2");
819 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
822 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
826 /* Select one of the two opcodes based on the glHint value. */
827 if (fs_key
->high_quality_derivatives
)
828 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
830 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
833 case ir_unop_dFdx_coarse
:
834 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
837 case ir_unop_dFdx_fine
:
838 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
842 /* Select one of the two opcodes based on the glHint value. */
843 if (fs_key
->high_quality_derivatives
)
844 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
846 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
849 case ir_unop_dFdy_coarse
:
850 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
853 case ir_unop_dFdy_fine
:
854 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
858 emit(ADD(this->result
, op
[0], op
[1]));
861 unreachable("not reached: should be handled by ir_sub_to_add_neg");
864 if (devinfo
->gen
< 8 && ir
->type
->is_integer()) {
865 /* For integer multiplication, the MUL uses the low 16 bits
866 * of one of the operands (src0 on gen6, src1 on gen7). The
867 * MACH accumulates in the contribution of the upper 16 bits
870 if (ir
->operands
[0]->is_uint16_constant()) {
871 if (devinfo
->gen
< 7)
872 emit(MUL(this->result
, op
[0], op
[1]));
874 emit(MUL(this->result
, op
[1], op
[0]));
875 } else if (ir
->operands
[1]->is_uint16_constant()) {
876 if (devinfo
->gen
< 7)
877 emit(MUL(this->result
, op
[1], op
[0]));
879 emit(MUL(this->result
, op
[0], op
[1]));
881 if (devinfo
->gen
>= 7)
882 no16("SIMD16 explicit accumulator operands unsupported\n");
884 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
887 emit(MUL(acc
, op
[0], op
[1]));
888 emit(MACH(reg_null_d
, op
[0], op
[1]));
889 emit(MOV(this->result
, fs_reg(acc
)));
892 emit(MUL(this->result
, op
[0], op
[1]));
895 case ir_binop_imul_high
: {
896 if (devinfo
->gen
>= 7)
897 no16("SIMD16 explicit accumulator operands unsupported\n");
899 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
902 fs_inst
*mul
= emit(MUL(acc
, op
[0], op
[1]));
903 emit(MACH(this->result
, op
[0], op
[1]));
905 /* Until Gen8, integer multiplies read 32-bits from one source, and
906 * 16-bits from the other, and relying on the MACH instruction to
907 * generate the high bits of the result.
909 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
910 * but in order to do a 64x64-bit multiply we have to simulate the
911 * previous behavior and then use a MACH instruction.
913 * FINISHME: Don't use source modifiers on src1.
915 if (devinfo
->gen
>= 8) {
916 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
917 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
918 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
919 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
920 mul
->src
[1].stride
= 2;
922 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
923 mul
->src
[1].stride
= 2;
930 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
931 assert(ir
->type
->is_integer());
932 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
934 case ir_binop_carry
: {
935 if (devinfo
->gen
>= 7)
936 no16("SIMD16 explicit accumulator operands unsupported\n");
938 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
939 BRW_REGISTER_TYPE_UD
);
941 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
942 emit(MOV(this->result
, fs_reg(acc
)));
945 case ir_binop_borrow
: {
946 if (devinfo
->gen
>= 7)
947 no16("SIMD16 explicit accumulator operands unsupported\n");
949 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
950 BRW_REGISTER_TYPE_UD
);
952 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
953 emit(MOV(this->result
, fs_reg(acc
)));
957 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
958 assert(ir
->type
->is_integer());
959 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
963 case ir_binop_greater
:
964 case ir_binop_lequal
:
965 case ir_binop_gequal
:
967 case ir_binop_all_equal
:
968 case ir_binop_nequal
:
969 case ir_binop_any_nequal
:
970 if (devinfo
->gen
<= 5) {
971 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
972 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
975 emit(CMP(this->result
, op
[0], op
[1],
976 brw_conditional_for_comparison(ir
->operation
)));
979 case ir_binop_logic_xor
:
980 emit(XOR(this->result
, op
[0], op
[1]));
983 case ir_binop_logic_or
:
984 emit(OR(this->result
, op
[0], op
[1]));
987 case ir_binop_logic_and
:
988 emit(AND(this->result
, op
[0], op
[1]));
993 unreachable("not reached: should be handled by brw_fs_channel_expressions");
996 unreachable("not reached: should be handled by lower_noise");
998 case ir_quadop_vector
:
999 unreachable("not reached: should be handled by lower_quadop_vector");
1001 case ir_binop_vector_extract
:
1002 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
1004 case ir_triop_vector_insert
:
1005 unreachable("not reached: should be handled by lower_vector_insert()");
1007 case ir_binop_ldexp
:
1008 unreachable("not reached: should be handled by ldexp_to_arith()");
1011 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
1015 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
1018 case ir_unop_bitcast_i2f
:
1019 case ir_unop_bitcast_u2f
:
1020 op
[0].type
= BRW_REGISTER_TYPE_F
;
1021 this->result
= op
[0];
1024 case ir_unop_bitcast_f2u
:
1025 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1026 this->result
= op
[0];
1029 case ir_unop_bitcast_f2i
:
1030 op
[0].type
= BRW_REGISTER_TYPE_D
;
1031 this->result
= op
[0];
1037 emit(MOV(this->result
, op
[0]));
1041 emit(AND(this->result
, op
[0], fs_reg(1)));
1044 if (devinfo
->gen
<= 5) {
1045 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1047 op
[0].type
= BRW_REGISTER_TYPE_D
;
1048 this->result
.type
= BRW_REGISTER_TYPE_D
;
1049 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
1050 this->result
.type
= BRW_REGISTER_TYPE_F
;
1054 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1057 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1061 emit(RNDZ(this->result
, op
[0]));
1063 case ir_unop_ceil
: {
1064 fs_reg tmp
= vgrf(ir
->type
);
1065 op
[0].negate
= !op
[0].negate
;
1066 emit(RNDD(tmp
, op
[0]));
1068 emit(MOV(this->result
, tmp
));
1072 emit(RNDD(this->result
, op
[0]));
1075 emit(FRC(this->result
, op
[0]));
1077 case ir_unop_round_even
:
1078 emit(RNDE(this->result
, op
[0]));
1083 resolve_ud_negate(&op
[0]);
1084 resolve_ud_negate(&op
[1]);
1085 emit_minmax(ir
->operation
== ir_binop_min
?
1086 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
1087 this->result
, op
[0], op
[1]);
1089 case ir_unop_pack_snorm_2x16
:
1090 case ir_unop_pack_snorm_4x8
:
1091 case ir_unop_pack_unorm_2x16
:
1092 case ir_unop_pack_unorm_4x8
:
1093 case ir_unop_unpack_snorm_2x16
:
1094 case ir_unop_unpack_snorm_4x8
:
1095 case ir_unop_unpack_unorm_2x16
:
1096 case ir_unop_unpack_unorm_4x8
:
1097 case ir_unop_unpack_half_2x16
:
1098 case ir_unop_pack_half_2x16
:
1099 unreachable("not reached: should be handled by lower_packing_builtins");
1100 case ir_unop_unpack_half_2x16_split_x
:
1101 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
1103 case ir_unop_unpack_half_2x16_split_y
:
1104 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
1107 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
1110 case ir_unop_bitfield_reverse
:
1111 emit(BFREV(this->result
, op
[0]));
1113 case ir_unop_bit_count
:
1114 emit(CBIT(this->result
, op
[0]));
1116 case ir_unop_find_msb
:
1117 temp
= vgrf(glsl_type::uint_type
);
1118 emit(FBH(temp
, op
[0]));
1120 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1121 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1122 * subtract the result from 31 to convert the MSB count into an LSB count.
1125 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1126 emit(MOV(this->result
, temp
));
1127 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1130 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
1131 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1133 case ir_unop_find_lsb
:
1134 emit(FBL(this->result
, op
[0]));
1136 case ir_unop_saturate
:
1137 inst
= emit(MOV(this->result
, op
[0]));
1138 inst
->saturate
= true;
1140 case ir_triop_bitfield_extract
:
1141 /* Note that the instruction's argument order is reversed from GLSL
1144 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
1147 emit(BFI1(this->result
, op
[0], op
[1]));
1150 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
1152 case ir_quadop_bitfield_insert
:
1153 unreachable("not reached: should be handled by "
1154 "lower_instructions::bitfield_insert_to_bfm_bfi");
1156 case ir_unop_bit_not
:
1157 emit(NOT(this->result
, op
[0]));
1159 case ir_binop_bit_and
:
1160 emit(AND(this->result
, op
[0], op
[1]));
1162 case ir_binop_bit_xor
:
1163 emit(XOR(this->result
, op
[0], op
[1]));
1165 case ir_binop_bit_or
:
1166 emit(OR(this->result
, op
[0], op
[1]));
1169 case ir_binop_lshift
:
1170 emit(SHL(this->result
, op
[0], op
[1]));
1173 case ir_binop_rshift
:
1174 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1175 emit(ASR(this->result
, op
[0], op
[1]));
1177 emit(SHR(this->result
, op
[0], op
[1]));
1179 case ir_binop_pack_half_2x16_split
:
1180 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
1182 case ir_binop_ubo_load
: {
1183 /* This IR node takes a constant uniform block and a constant or
1184 * variable byte offset within the block and loads a vector from that.
1186 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1187 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
1190 if (const_uniform_block
) {
1191 /* The block index is a constant, so just emit the binding table entry
1194 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1195 const_uniform_block
->value
.u
[0]);
1197 /* The block index is not a constant. Evaluate the index expression
1198 * per-channel and add the base UBO index; the generator will select
1199 * a value from any live channel.
1201 surf_index
= vgrf(glsl_type::uint_type
);
1202 emit(ADD(surf_index
, op
[0],
1203 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1204 ->force_writemask_all
= true;
1206 /* Assume this may touch any UBO. It would be nice to provide
1207 * a tighter bound, but the array information is already lowered away.
1209 brw_mark_surface_used(prog_data
,
1210 stage_prog_data
->binding_table
.ubo_start
+
1211 shader_prog
->NumUniformBlocks
- 1);
1215 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1216 packed_consts
.type
= result
.type
;
1218 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
1219 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
1220 packed_consts
, surf_index
, const_offset_reg
));
1222 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1223 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
1225 /* The std140 packing rules don't allow vectors to cross 16-byte
1226 * boundaries, and a reg is 32 bytes.
1228 assert(packed_consts
.subreg_offset
< 32);
1230 /* UBO bools are any nonzero value. We consider bools to be
1231 * values with the low bit set to 1. Convert them using CMP.
1233 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1234 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
1236 emit(MOV(result
, packed_consts
));
1239 result
= offset(result
, 1);
1242 /* Turn the byte offset into a dword offset. */
1243 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1244 emit(SHR(base_offset
, op
[1], fs_reg(2)));
1246 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1247 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
1250 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
1251 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
1253 result
= offset(result
, 1);
1257 result
.reg_offset
= 0;
1262 /* Note that the instruction's argument order is reversed from GLSL
1265 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
1269 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1273 case ir_unop_interpolate_at_centroid
:
1274 case ir_binop_interpolate_at_offset
:
1275 case ir_binop_interpolate_at_sample
:
1276 unreachable("already handled above");
1286 case ir_unop_pack_double_2x32
:
1287 case ir_unop_unpack_double_2x32
:
1288 case ir_unop_frexp_sig
:
1289 case ir_unop_frexp_exp
:
1290 unreachable("fp64 todo");
1296 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1297 const glsl_type
*type
, bool predicated
)
1299 switch (type
->base_type
) {
1300 case GLSL_TYPE_FLOAT
:
1301 case GLSL_TYPE_UINT
:
1303 case GLSL_TYPE_BOOL
:
1304 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1305 l
.type
= brw_type_for_base_type(type
);
1306 r
.type
= brw_type_for_base_type(type
);
1308 if (predicated
|| !l
.equals(r
)) {
1309 fs_inst
*inst
= emit(MOV(l
, r
));
1310 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1317 case GLSL_TYPE_ARRAY
:
1318 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1319 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1323 case GLSL_TYPE_STRUCT
:
1324 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1325 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1330 case GLSL_TYPE_SAMPLER
:
1331 case GLSL_TYPE_IMAGE
:
1332 case GLSL_TYPE_ATOMIC_UINT
:
1335 case GLSL_TYPE_DOUBLE
:
1336 case GLSL_TYPE_VOID
:
1337 case GLSL_TYPE_ERROR
:
1338 case GLSL_TYPE_INTERFACE
:
1339 unreachable("not reached");
1343 /* If the RHS processing resulted in an instruction generating a
1344 * temporary value, and it would be easy to rewrite the instruction to
1345 * generate its result right into the LHS instead, do so. This ends
1346 * up reliably removing instructions where it can be tricky to do so
1347 * later without real UD chain information.
1350 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1353 fs_inst
*pre_rhs_inst
,
1354 fs_inst
*last_rhs_inst
)
1356 /* Only attempt if we're doing a direct assignment. */
1357 if (ir
->condition
||
1358 !(ir
->lhs
->type
->is_scalar() ||
1359 (ir
->lhs
->type
->is_vector() &&
1360 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1363 /* Make sure the last instruction generated our source reg. */
1364 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1370 /* If last_rhs_inst wrote a different number of components than our LHS,
1371 * we can't safely rewrite it.
1373 if (alloc
.sizes
[dst
.reg
] != modify
->regs_written
)
1376 /* Success! Rewrite the instruction. */
1383 fs_visitor::visit(ir_assignment
*ir
)
1388 /* FINISHME: arrays on the lhs */
1389 ir
->lhs
->accept(this);
1392 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1394 ir
->rhs
->accept(this);
1397 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1399 assert(l
.file
!= BAD_FILE
);
1400 assert(r
.file
!= BAD_FILE
);
1402 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1405 if (ir
->condition
) {
1406 emit_bool_to_cond_code(ir
->condition
);
1409 if (ir
->lhs
->type
->is_scalar() ||
1410 ir
->lhs
->type
->is_vector()) {
1411 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1412 if (ir
->write_mask
& (1 << i
)) {
1413 inst
= emit(MOV(l
, r
));
1415 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1421 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1426 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
1427 fs_reg coordinate
, int coord_components
,
1429 fs_reg lod
, fs_reg dPdy
, int grad_components
,
1434 bool simd16
= false;
1440 if (shadow_c
.file
!= BAD_FILE
) {
1441 for (int i
= 0; i
< coord_components
; i
++) {
1442 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1443 coordinate
= offset(coordinate
, 1);
1446 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1447 * the unused slots must be zeroed.
1449 for (int i
= coord_components
; i
< 3; i
++) {
1450 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1455 /* There's no plain shadow compare message, so we use shadow
1456 * compare with a bias of 0.0.
1458 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1460 } else if (op
== ir_txb
|| op
== ir_txl
) {
1461 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1464 unreachable("Should not get here.");
1467 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1469 } else if (op
== ir_tex
) {
1470 for (int i
= 0; i
< coord_components
; i
++) {
1471 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1472 coordinate
= offset(coordinate
, 1);
1474 /* zero the others. */
1475 for (int i
= coord_components
; i
<3; i
++) {
1476 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1478 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1480 } else if (op
== ir_txd
) {
1483 for (int i
= 0; i
< coord_components
; i
++) {
1484 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1485 coordinate
= offset(coordinate
, 1);
1487 /* the slots for u and v are always present, but r is optional */
1488 mlen
+= MAX2(coord_components
, 2);
1491 * dPdx = dudx, dvdx, drdx
1492 * dPdy = dudy, dvdy, drdy
1494 * 1-arg: Does not exist.
1496 * 2-arg: dudx dvdx dudy dvdy
1497 * dPdx.x dPdx.y dPdy.x dPdy.y
1500 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1501 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1502 * m5 m6 m7 m8 m9 m10
1504 for (int i
= 0; i
< grad_components
; i
++) {
1505 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1506 dPdx
= offset(dPdx
, 1);
1508 mlen
+= MAX2(grad_components
, 2);
1510 for (int i
= 0; i
< grad_components
; i
++) {
1511 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1512 dPdy
= offset(dPdy
, 1);
1514 mlen
+= MAX2(grad_components
, 2);
1515 } else if (op
== ir_txs
) {
1516 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1518 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1521 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1522 * instructions. We'll need to do SIMD16 here.
1525 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
1527 for (int i
= 0; i
< coord_components
; i
++) {
1528 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1530 coordinate
= offset(coordinate
, 1);
1533 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1534 * be necessary for TXF (ld), but seems wise to do for all messages.
1536 for (int i
= coord_components
; i
< 3; i
++) {
1537 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1540 /* lod/bias appears after u/v/r. */
1543 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1546 /* The unused upper half. */
1551 /* Now, since we're doing simd16, the return is 2 interleaved
1552 * vec4s where the odd-indexed ones are junk. We'll need to move
1553 * this weirdness around to the expected layout.
1556 dst
= fs_reg(GRF
, alloc
.allocate(8), orig_dst
.type
);
1561 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1562 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1563 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1564 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1565 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1566 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1568 unreachable("not reached");
1571 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1572 inst
->base_mrf
= base_mrf
;
1574 inst
->header_present
= true;
1575 inst
->regs_written
= simd16
? 8 : 4;
1578 for (int i
= 0; i
< 4; i
++) {
1579 emit(MOV(orig_dst
, dst
));
1580 orig_dst
= offset(orig_dst
, 1);
1581 dst
= offset(dst
, 2);
1589 fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op
, fs_reg dst
,
1590 fs_reg coordinate
, int vector_elements
,
1591 fs_reg shadow_c
, fs_reg lod
,
1594 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1595 bool has_lod
= op
== ir_txl
|| op
== ir_txb
|| op
== ir_txf
;
1597 if (has_lod
&& shadow_c
.file
!= BAD_FILE
)
1598 no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
1601 no16("textureGrad unsupported in SIMD16.");
1603 /* Copy the coordinates. */
1604 for (int i
= 0; i
< vector_elements
; i
++) {
1605 emit(MOV(retype(offset(message
, i
), coordinate
.type
), coordinate
));
1606 coordinate
= offset(coordinate
, 1);
1609 fs_reg msg_end
= offset(message
, vector_elements
);
1611 /* Messages other than sample and ld require all three components */
1612 if (has_lod
|| shadow_c
.file
!= BAD_FILE
) {
1613 for (int i
= vector_elements
; i
< 3; i
++) {
1614 emit(MOV(offset(message
, i
), fs_reg(0.0f
)));
1619 fs_reg msg_lod
= retype(offset(message
, 3), op
== ir_txf
?
1620 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
1621 emit(MOV(msg_lod
, lod
));
1622 msg_end
= offset(msg_lod
, 1);
1625 if (shadow_c
.file
!= BAD_FILE
) {
1626 fs_reg msg_ref
= offset(message
, 3 + has_lod
);
1627 emit(MOV(msg_ref
, shadow_c
));
1628 msg_end
= offset(msg_ref
, 1);
1633 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1634 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1635 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1636 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1637 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1638 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1639 default: unreachable("not reached");
1642 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1643 inst
->base_mrf
= message
.reg
- 1;
1644 inst
->mlen
= msg_end
.reg
- inst
->base_mrf
;
1645 inst
->header_present
= true;
1646 inst
->regs_written
= 8;
1651 /* gen5's sampler has slots for u, v, r, array index, then optional
1652 * parameters like shadow comparitor or LOD bias. If optional
1653 * parameters aren't present, those base slots are optional and don't
1654 * need to be included in the message.
1656 * We don't fill in the unnecessary slots regardless, which may look
1657 * surprising in the disassembly.
1660 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
1661 fs_reg coordinate
, int vector_elements
,
1663 fs_reg lod
, fs_reg lod2
, int grad_components
,
1664 fs_reg sample_index
, uint32_t sampler
,
1667 int reg_width
= dispatch_width
/ 8;
1668 bool header_present
= false;
1670 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1671 fs_reg msg_coords
= message
;
1674 /* The offsets set up by the ir_texture visitor are in the
1675 * m1 header, so we can't go headerless.
1677 header_present
= true;
1681 for (int i
= 0; i
< vector_elements
; i
++) {
1682 emit(MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
));
1683 coordinate
= offset(coordinate
, 1);
1685 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
1686 fs_reg msg_lod
= offset(msg_coords
, 4);
1688 if (shadow_c
.file
!= BAD_FILE
) {
1689 fs_reg msg_shadow
= msg_lod
;
1690 emit(MOV(msg_shadow
, shadow_c
));
1691 msg_lod
= offset(msg_shadow
, 1);
1698 opcode
= SHADER_OPCODE_TEX
;
1701 emit(MOV(msg_lod
, lod
));
1702 msg_end
= offset(msg_lod
, 1);
1704 opcode
= FS_OPCODE_TXB
;
1707 emit(MOV(msg_lod
, lod
));
1708 msg_end
= offset(msg_lod
, 1);
1710 opcode
= SHADER_OPCODE_TXL
;
1715 * dPdx = dudx, dvdx, drdx
1716 * dPdy = dudy, dvdy, drdy
1718 * Load up these values:
1719 * - dudx dudy dvdx dvdy drdx drdy
1720 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1723 for (int i
= 0; i
< grad_components
; i
++) {
1724 emit(MOV(msg_end
, lod
));
1725 lod
= offset(lod
, 1);
1726 msg_end
= offset(msg_end
, 1);
1728 emit(MOV(msg_end
, lod2
));
1729 lod2
= offset(lod2
, 1);
1730 msg_end
= offset(msg_end
, 1);
1733 opcode
= SHADER_OPCODE_TXD
;
1737 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
1738 emit(MOV(msg_lod
, lod
));
1739 msg_end
= offset(msg_lod
, 1);
1741 opcode
= SHADER_OPCODE_TXS
;
1743 case ir_query_levels
:
1745 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1746 msg_end
= offset(msg_lod
, 1);
1748 opcode
= SHADER_OPCODE_TXS
;
1751 msg_lod
= offset(msg_coords
, 3);
1752 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
));
1753 msg_end
= offset(msg_lod
, 1);
1755 opcode
= SHADER_OPCODE_TXF
;
1758 msg_lod
= offset(msg_coords
, 3);
1760 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1762 emit(MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
));
1763 msg_end
= offset(msg_lod
, 2);
1765 opcode
= SHADER_OPCODE_TXF_CMS
;
1768 opcode
= SHADER_OPCODE_LOD
;
1771 opcode
= SHADER_OPCODE_TG4
;
1774 unreachable("not reached");
1777 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1778 inst
->base_mrf
= message
.reg
;
1779 inst
->mlen
= msg_end
.reg
- message
.reg
;
1780 inst
->header_present
= header_present
;
1781 inst
->regs_written
= 4 * reg_width
;
1783 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1784 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1785 " disallowed by hardware\n");
1792 is_high_sampler(const struct brw_device_info
*devinfo
, fs_reg sampler
)
1794 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
1797 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1801 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
1802 fs_reg coordinate
, int coord_components
,
1804 fs_reg lod
, fs_reg lod2
, int grad_components
,
1805 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
1806 fs_reg offset_value
)
1808 int reg_width
= dispatch_width
/ 8;
1809 bool header_present
= false;
1811 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1812 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1813 sources
[i
] = vgrf(glsl_type::float_type
);
1817 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
1818 is_high_sampler(devinfo
, sampler
)) {
1819 /* For general texture offsets (no txf workaround), we need a header to
1820 * put them in. Note that for SIMD16 we're making space for two actual
1821 * hardware registers here, so the emit will have to fix up for this.
1823 * * ir4_tg4 needs to place its channel select in the header,
1824 * for interaction with ARB_texture_swizzle
1826 * The sampler index is only 4-bits, so for larger sampler numbers we
1827 * need to offset the Sampler State Pointer in the header.
1829 header_present
= true;
1830 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
1834 if (shadow_c
.file
!= BAD_FILE
) {
1835 emit(MOV(sources
[length
], shadow_c
));
1839 bool has_nonconstant_offset
=
1840 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
1841 bool coordinate_done
= false;
1843 /* The sampler can only meaningfully compute LOD for fragment shader
1844 * messages. For all other stages, we change the opcode to ir_txl and
1845 * hardcode the LOD to 0.
1847 if (stage
!= MESA_SHADER_FRAGMENT
&& op
== ir_tex
) {
1852 /* Set up the LOD info */
1858 emit(MOV(sources
[length
], lod
));
1862 emit(MOV(sources
[length
], lod
));
1866 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1868 /* Load dPdx and the coordinate together:
1869 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1871 for (int i
= 0; i
< coord_components
; i
++) {
1872 emit(MOV(sources
[length
], coordinate
));
1873 coordinate
= offset(coordinate
, 1);
1876 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1877 * only derivatives for (u, v, r).
1879 if (i
< grad_components
) {
1880 emit(MOV(sources
[length
], lod
));
1881 lod
= offset(lod
, 1);
1884 emit(MOV(sources
[length
], lod2
));
1885 lod2
= offset(lod2
, 1);
1890 coordinate_done
= true;
1894 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1897 case ir_query_levels
:
1898 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1902 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
1903 * On Gen9 they are u, v, lod, r
1906 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1907 coordinate
= offset(coordinate
, 1);
1910 if (devinfo
->gen
>= 9) {
1911 if (coord_components
>= 2) {
1912 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1913 coordinate
= offset(coordinate
, 1);
1918 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1921 for (int i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
1922 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1923 coordinate
= offset(coordinate
, 1);
1927 coordinate_done
= true;
1930 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1933 /* data from the multisample control surface */
1934 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1937 /* there is no offsetting for this message; just copy in the integer
1938 * texture coordinates
1940 for (int i
= 0; i
< coord_components
; i
++) {
1941 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1942 coordinate
= offset(coordinate
, 1);
1946 coordinate_done
= true;
1949 if (has_nonconstant_offset
) {
1950 if (shadow_c
.file
!= BAD_FILE
)
1951 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1953 /* More crazy intermixing */
1954 for (int i
= 0; i
< 2; i
++) { /* u, v */
1955 emit(MOV(sources
[length
], coordinate
));
1956 coordinate
= offset(coordinate
, 1);
1960 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1961 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1962 offset_value
= offset(offset_value
, 1);
1966 if (coord_components
== 3) { /* r if present */
1967 emit(MOV(sources
[length
], coordinate
));
1968 coordinate
= offset(coordinate
, 1);
1972 coordinate_done
= true;
1977 /* Set up the coordinate (except for cases where it was done above) */
1978 if (!coordinate_done
) {
1979 for (int i
= 0; i
< coord_components
; i
++) {
1980 emit(MOV(sources
[length
], coordinate
));
1981 coordinate
= offset(coordinate
, 1);
1988 mlen
= length
* reg_width
- header_present
;
1990 mlen
= length
* reg_width
;
1992 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1993 BRW_REGISTER_TYPE_F
);
1994 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1996 /* Generate the SEND */
1999 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
2000 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
2001 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2002 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2003 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2004 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2005 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2006 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2007 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
2009 if (has_nonconstant_offset
)
2010 opcode
= SHADER_OPCODE_TG4_OFFSET
;
2012 opcode
= SHADER_OPCODE_TG4
;
2015 unreachable("not reached");
2017 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
2018 inst
->base_mrf
= -1;
2020 inst
->header_present
= header_present
;
2021 inst
->regs_written
= 4 * reg_width
;
2023 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
2024 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
2025 " disallowed by hardware\n");
2032 fs_visitor::rescale_texcoord(fs_reg coordinate
, int coord_components
,
2033 bool is_rect
, uint32_t sampler
, int texunit
)
2035 fs_inst
*inst
= NULL
;
2036 bool needs_gl_clamp
= true;
2037 fs_reg scale_x
, scale_y
;
2039 /* The 965 requires the EU to do the normalization of GL rectangle
2040 * texture coordinates. We use the program parameter state
2041 * tracking to get the scaling factor.
2044 (devinfo
->gen
< 6 ||
2045 (devinfo
->gen
>= 6 && (key_tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
2046 key_tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
2047 struct gl_program_parameter_list
*params
= prog
->Parameters
;
2048 int tokens
[STATE_LENGTH
] = {
2050 STATE_TEXRECT_SCALE
,
2056 no16("rectangle scale uniform setup not supported on SIMD16\n");
2057 if (dispatch_width
== 16) {
2061 GLuint index
= _mesa_add_state_reference(params
,
2062 (gl_state_index
*)tokens
);
2063 /* Try to find existing copies of the texrect scale uniforms. */
2064 for (unsigned i
= 0; i
< uniforms
; i
++) {
2065 if (stage_prog_data
->param
[i
] ==
2066 &prog
->Parameters
->ParameterValues
[index
][0]) {
2067 scale_x
= fs_reg(UNIFORM
, i
);
2068 scale_y
= fs_reg(UNIFORM
, i
+ 1);
2073 /* If we didn't already set them up, do so now. */
2074 if (scale_x
.file
== BAD_FILE
) {
2075 scale_x
= fs_reg(UNIFORM
, uniforms
);
2076 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
2078 stage_prog_data
->param
[uniforms
++] =
2079 &prog
->Parameters
->ParameterValues
[index
][0];
2080 stage_prog_data
->param
[uniforms
++] =
2081 &prog
->Parameters
->ParameterValues
[index
][1];
2085 /* The 965 requires the EU to do the normalization of GL rectangle
2086 * texture coordinates. We use the program parameter state
2087 * tracking to get the scaling factor.
2089 if (devinfo
->gen
< 6 && is_rect
) {
2090 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(coord_components
));
2091 fs_reg src
= coordinate
;
2094 emit(MUL(dst
, src
, scale_x
));
2095 dst
= offset(dst
, 1);
2096 src
= offset(src
, 1);
2097 emit(MUL(dst
, src
, scale_y
));
2098 } else if (is_rect
) {
2099 /* On gen6+, the sampler handles the rectangle coordinates
2100 * natively, without needing rescaling. But that means we have
2101 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
2102 * not [0, 1] like the default case below.
2104 needs_gl_clamp
= false;
2106 for (int i
= 0; i
< 2; i
++) {
2107 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
2108 fs_reg chan
= coordinate
;
2109 chan
= offset(chan
, i
);
2111 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
2112 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
2114 /* Our parameter comes in as 1.0/width or 1.0/height,
2115 * because that's what people normally want for doing
2116 * texture rectangle handling. We need width or height
2117 * for clamping, but we don't care enough to make a new
2118 * parameter type, so just invert back.
2120 fs_reg limit
= vgrf(glsl_type::float_type
);
2121 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
2122 emit(SHADER_OPCODE_RCP
, limit
, limit
);
2124 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
2125 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
2130 if (coord_components
> 0 && needs_gl_clamp
) {
2131 for (int i
= 0; i
< MIN2(coord_components
, 3); i
++) {
2132 if (key_tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
2133 fs_reg chan
= coordinate
;
2134 chan
= offset(chan
, i
);
2136 fs_inst
*inst
= emit(MOV(chan
, chan
));
2137 inst
->saturate
= true;
2144 /* Sample from the MCS surface attached to this multisample texture. */
2146 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
2148 int reg_width
= dispatch_width
/ 8;
2149 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(components
* reg_width
),
2150 BRW_REGISTER_TYPE_F
);
2151 fs_reg dest
= vgrf(glsl_type::uvec4_type
);
2152 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
2154 /* parameters are: u, v, r; missing parameters are treated as zero */
2155 for (int i
= 0; i
< components
; i
++) {
2156 sources
[i
] = vgrf(glsl_type::float_type
);
2157 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
2158 coordinate
= offset(coordinate
, 1);
2161 emit(LOAD_PAYLOAD(payload
, sources
, components
));
2163 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
2164 inst
->base_mrf
= -1;
2165 inst
->mlen
= components
* reg_width
;
2166 inst
->header_present
= false;
2167 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
2168 * response, but the sampler always
2176 fs_visitor::emit_texture(ir_texture_opcode op
,
2177 const glsl_type
*dest_type
,
2178 fs_reg coordinate
, int coord_components
,
2180 fs_reg lod
, fs_reg lod2
, int grad_components
,
2181 fs_reg sample_index
,
2182 fs_reg offset_value
,
2184 int gather_component
,
2188 fs_reg sampler_reg
, int texunit
)
2190 fs_inst
*inst
= NULL
;
2193 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2194 * emitting anything other than setting up the constant result.
2196 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
2197 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2199 fs_reg res
= vgrf(glsl_type::vec4_type
);
2202 for (int i
=0; i
<4; i
++) {
2203 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
2204 res
= offset(res
, 1);
2210 if (coordinate
.file
!= BAD_FILE
) {
2211 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
2212 * samplers. This should only be a problem with GL_CLAMP on Gen7.
2214 coordinate
= rescale_texcoord(coordinate
, coord_components
, is_rect
,
2218 /* Writemasking doesn't eliminate channels on SIMD8 texture
2219 * samples, so don't worry about them.
2221 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
2223 if (devinfo
->gen
>= 7) {
2224 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
2225 shadow_c
, lod
, lod2
, grad_components
,
2226 sample_index
, mcs
, sampler_reg
,
2228 } else if (devinfo
->gen
>= 5) {
2229 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
2230 shadow_c
, lod
, lod2
, grad_components
,
2231 sample_index
, sampler
,
2232 offset_value
.file
!= BAD_FILE
);
2233 } else if (dispatch_width
== 16) {
2234 inst
= emit_texture_gen4_simd16(op
, dst
, coordinate
, coord_components
,
2235 shadow_c
, lod
, sampler
);
2237 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
2238 shadow_c
, lod
, lod2
, grad_components
,
2242 if (shadow_c
.file
!= BAD_FILE
)
2243 inst
->shadow_compare
= true;
2245 if (offset_value
.file
== IMM
)
2246 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
2250 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
2252 if (devinfo
->gen
== 6)
2253 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], dst
);
2256 /* fixup #layers for cube map arrays */
2257 if (op
== ir_txs
&& is_cube_array
) {
2258 fs_reg depth
= offset(dst
, 2);
2259 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
2260 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
2262 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
2263 int components
= inst
->regs_written
/ (dst
.width
/ 8);
2264 for (int i
= 0; i
< components
; i
++) {
2266 fixed_payload
[i
] = fixed_depth
;
2268 fixed_payload
[i
] = offset(dst
, i
);
2271 emit(LOAD_PAYLOAD(dst
, fixed_payload
, components
));
2274 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
2278 fs_visitor::visit(ir_texture
*ir
)
2281 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2283 ir_rvalue
*nonconst_sampler_index
=
2284 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2286 /* Handle non-constant sampler array indexing */
2288 if (nonconst_sampler_index
) {
2289 /* The highest sampler which may be used by this operation is
2290 * the last element of the array. Mark it here, because the generator
2291 * doesn't have enough information to determine the bound.
2293 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2294 ->array
->type
->array_size();
2296 uint32_t max_used
= sampler
+ array_size
- 1;
2297 if (ir
->op
== ir_tg4
&& devinfo
->gen
< 8) {
2298 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2300 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2303 brw_mark_surface_used(prog_data
, max_used
);
2305 /* Emit code to evaluate the actual indexing expression */
2306 nonconst_sampler_index
->accept(this);
2307 fs_reg temp
= vgrf(glsl_type::uint_type
);
2308 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
2309 ->force_writemask_all
= true;
2312 /* Single sampler, or constant array index; the indexing expression
2313 * is just an immediate.
2315 sampler_reg
= fs_reg(sampler
);
2318 /* FINISHME: We're failing to recompile our programs when the sampler is
2319 * updated. This only matters for the texture rectangle scale parameters
2320 * (pre-gen6, or gen6+ with GL_CLAMP).
2322 int texunit
= prog
->SamplerUnits
[sampler
];
2324 /* Should be lowered by do_lower_texture_projection */
2325 assert(!ir
->projector
);
2327 /* Should be lowered */
2328 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2330 /* Generate code to compute all the subexpression trees. This has to be
2331 * done before loading any values into MRFs for the sampler message since
2332 * generating these values may involve SEND messages that need the MRFs.
2335 int coord_components
= 0;
2336 if (ir
->coordinate
) {
2337 coord_components
= ir
->coordinate
->type
->vector_elements
;
2338 ir
->coordinate
->accept(this);
2339 coordinate
= this->result
;
2342 fs_reg shadow_comparitor
;
2343 if (ir
->shadow_comparitor
) {
2344 ir
->shadow_comparitor
->accept(this);
2345 shadow_comparitor
= this->result
;
2348 fs_reg offset_value
;
2350 ir_constant
*const_offset
= ir
->offset
->as_constant();
2352 /* Store the header bitfield in an IMM register. This allows us to
2353 * use offset_value.file to distinguish between no offset, a constant
2354 * offset, and a non-constant offset.
2357 fs_reg(brw_texture_offset(const_offset
->value
.i
,
2358 const_offset
->type
->vector_elements
));
2360 ir
->offset
->accept(this);
2361 offset_value
= this->result
;
2365 fs_reg lod
, lod2
, sample_index
, mcs
;
2366 int grad_components
= 0;
2371 case ir_query_levels
:
2374 ir
->lod_info
.bias
->accept(this);
2378 ir
->lod_info
.grad
.dPdx
->accept(this);
2381 ir
->lod_info
.grad
.dPdy
->accept(this);
2382 lod2
= this->result
;
2384 grad_components
= ir
->lod_info
.grad
.dPdx
->type
->vector_elements
;
2389 ir
->lod_info
.lod
->accept(this);
2393 ir
->lod_info
.sample_index
->accept(this);
2394 sample_index
= this->result
;
2396 if (devinfo
->gen
>= 7 &&
2397 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2398 mcs
= emit_mcs_fetch(coordinate
, ir
->coordinate
->type
->vector_elements
,
2405 unreachable("Unrecognized texture opcode");
2408 int gather_component
= 0;
2409 if (ir
->op
== ir_tg4
)
2410 gather_component
= ir
->lod_info
.component
->as_constant()->value
.i
[0];
2413 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
;
2415 bool is_cube_array
=
2416 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2417 ir
->sampler
->type
->sampler_array
;
2419 emit_texture(ir
->op
, ir
->type
, coordinate
, coord_components
,
2420 shadow_comparitor
, lod
, lod2
, grad_components
,
2421 sample_index
, offset_value
, mcs
,
2422 gather_component
, is_cube_array
, is_rect
, sampler
,
2423 sampler_reg
, texunit
);
2427 * Apply workarounds for Gen6 gather with UINT/SINT
2430 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2435 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2437 for (int i
= 0; i
< 4; i
++) {
2438 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2439 /* Convert from UNORM to UINT */
2440 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2441 emit(MOV(dst
, dst_f
));
2444 /* Reinterpret the UINT value as a signed INT value by
2445 * shifting the sign bit into place, then shifting back
2448 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2449 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2452 dst
= offset(dst
, 1);
2457 * Set up the gather channel based on the swizzle, for gather4.
2460 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
2462 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], orig_chan
);
2464 case SWIZZLE_X
: return 0;
2466 /* gather4 sampler is broken for green channel on RG32F --
2467 * we must ask for blue instead.
2469 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
2472 case SWIZZLE_Z
: return 2;
2473 case SWIZZLE_W
: return 3;
2475 unreachable("Not reached"); /* zero, one swizzles handled already */
2480 * Swizzle the result of a texture result. This is necessary for
2481 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2484 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
2485 fs_reg orig_val
, uint32_t sampler
)
2487 if (op
== ir_query_levels
) {
2488 /* # levels is in .w */
2489 this->result
= offset(orig_val
, 3);
2493 this->result
= orig_val
;
2495 /* txs,lod don't actually sample the texture, so swizzling the result
2498 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
2501 if (dest_components
== 1) {
2502 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2503 } else if (key_tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2504 fs_reg swizzled_result
= vgrf(glsl_type::vec4_type
);
2505 swizzled_result
.type
= orig_val
.type
;
2507 for (int i
= 0; i
< 4; i
++) {
2508 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], i
);
2509 fs_reg l
= swizzled_result
;
2512 if (swiz
== SWIZZLE_ZERO
) {
2513 emit(MOV(l
, fs_reg(0.0f
)));
2514 } else if (swiz
== SWIZZLE_ONE
) {
2515 emit(MOV(l
, fs_reg(1.0f
)));
2517 emit(MOV(l
, offset(orig_val
,
2518 GET_SWZ(key_tex
->swizzles
[sampler
], i
))));
2521 this->result
= swizzled_result
;
2526 fs_visitor::visit(ir_swizzle
*ir
)
2528 ir
->val
->accept(this);
2529 fs_reg val
= this->result
;
2531 if (ir
->type
->vector_elements
== 1) {
2532 this->result
= offset(this->result
, ir
->mask
.x
);
2536 fs_reg result
= vgrf(ir
->type
);
2537 this->result
= result
;
2539 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2540 fs_reg channel
= val
;
2558 emit(MOV(result
, offset(channel
, swiz
)));
2559 result
= offset(result
, 1);
2564 fs_visitor::visit(ir_discard
*ir
)
2566 /* We track our discarded pixels in f0.1. By predicating on it, we can
2567 * update just the flag bits that aren't yet discarded. If there's no
2568 * condition, we emit a CMP of g0 != g0, so all currently executing
2569 * channels will get turned off.
2572 if (ir
->condition
) {
2573 emit_bool_to_cond_code(ir
->condition
);
2574 cmp
= (fs_inst
*) this->instructions
.get_tail();
2575 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
2577 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2578 BRW_REGISTER_TYPE_UW
));
2579 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
2581 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2582 cmp
->flag_subreg
= 1;
2584 if (devinfo
->gen
>= 6) {
2585 emit_discard_jump();
2590 fs_visitor::visit(ir_constant
*ir
)
2592 /* Set this->result to reg at the bottom of the function because some code
2593 * paths will cause this visitor to be applied to other fields. This will
2594 * cause the value stored in this->result to be modified.
2596 * Make reg constant so that it doesn't get accidentally modified along the
2597 * way. Yes, I actually had this problem. :(
2599 const fs_reg reg
= vgrf(ir
->type
);
2600 fs_reg dst_reg
= reg
;
2602 if (ir
->type
->is_array()) {
2603 const unsigned size
= type_size(ir
->type
->fields
.array
);
2605 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2606 ir
->array_elements
[i
]->accept(this);
2607 fs_reg src_reg
= this->result
;
2609 dst_reg
.type
= src_reg
.type
;
2610 for (unsigned j
= 0; j
< size
; j
++) {
2611 emit(MOV(dst_reg
, src_reg
));
2612 src_reg
= offset(src_reg
, 1);
2613 dst_reg
= offset(dst_reg
, 1);
2616 } else if (ir
->type
->is_record()) {
2617 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2618 const unsigned size
= type_size(field
->type
);
2620 field
->accept(this);
2621 fs_reg src_reg
= this->result
;
2623 dst_reg
.type
= src_reg
.type
;
2624 for (unsigned j
= 0; j
< size
; j
++) {
2625 emit(MOV(dst_reg
, src_reg
));
2626 src_reg
= offset(src_reg
, 1);
2627 dst_reg
= offset(dst_reg
, 1);
2631 const unsigned size
= type_size(ir
->type
);
2633 for (unsigned i
= 0; i
< size
; i
++) {
2634 switch (ir
->type
->base_type
) {
2635 case GLSL_TYPE_FLOAT
:
2636 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2638 case GLSL_TYPE_UINT
:
2639 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2642 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2644 case GLSL_TYPE_BOOL
:
2645 emit(MOV(dst_reg
, fs_reg(ir
->value
.b
[i
] != 0 ? ~0 : 0)));
2648 unreachable("Non-float/uint/int/bool constant");
2650 dst_reg
= offset(dst_reg
, 1);
2658 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2660 ir_expression
*expr
= ir
->as_expression();
2662 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2665 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2666 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2672 assert(expr
->get_num_operands() <= 3);
2673 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2674 assert(expr
->operands
[i
]->type
->is_scalar());
2676 expr
->operands
[i
]->accept(this);
2677 op
[i
] = this->result
;
2679 resolve_ud_negate(&op
[i
]);
2682 emit_bool_to_cond_code_of_reg(expr
, op
);
2686 fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression
*expr
, fs_reg op
[3])
2690 switch (expr
->operation
) {
2691 case ir_unop_logic_not
:
2692 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2693 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2696 case ir_binop_logic_xor
:
2697 if (devinfo
->gen
<= 5) {
2698 fs_reg temp
= vgrf(expr
->type
);
2699 emit(XOR(temp
, op
[0], op
[1]));
2700 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2702 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2704 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2707 case ir_binop_logic_or
:
2708 if (devinfo
->gen
<= 5) {
2709 fs_reg temp
= vgrf(expr
->type
);
2710 emit(OR(temp
, op
[0], op
[1]));
2711 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2713 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2715 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2718 case ir_binop_logic_and
:
2719 if (devinfo
->gen
<= 5) {
2720 fs_reg temp
= vgrf(expr
->type
);
2721 emit(AND(temp
, op
[0], op
[1]));
2722 inst
= emit(AND(reg_null_d
, temp
, fs_reg(1)));
2724 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2726 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2730 if (devinfo
->gen
>= 6) {
2731 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2733 inst
= emit(MOV(reg_null_f
, op
[0]));
2734 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2739 if (devinfo
->gen
>= 6) {
2740 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2742 inst
= emit(MOV(reg_null_d
, op
[0]));
2743 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2747 case ir_binop_greater
:
2748 case ir_binop_gequal
:
2750 case ir_binop_lequal
:
2751 case ir_binop_equal
:
2752 case ir_binop_all_equal
:
2753 case ir_binop_nequal
:
2754 case ir_binop_any_nequal
:
2755 if (devinfo
->gen
<= 5) {
2756 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2757 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2760 emit(CMP(reg_null_d
, op
[0], op
[1],
2761 brw_conditional_for_comparison(expr
->operation
)));
2764 case ir_triop_csel
: {
2765 /* Expand the boolean condition into the flag register. */
2766 inst
= emit(MOV(reg_null_d
, op
[0]));
2767 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2769 /* Select which boolean to return. */
2770 fs_reg temp
= vgrf(expr
->operands
[1]->type
);
2771 inst
= emit(SEL(temp
, op
[1], op
[2]));
2772 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2774 /* Expand the result to a condition code. */
2775 inst
= emit(MOV(reg_null_d
, temp
));
2776 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2781 unreachable("not reached");
2786 * Emit a gen6 IF statement with the comparison folded into the IF
2790 fs_visitor::emit_if_gen6(ir_if
*ir
)
2792 ir_expression
*expr
= ir
->condition
->as_expression();
2794 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2799 assert(expr
->get_num_operands() <= 3);
2800 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2801 assert(expr
->operands
[i
]->type
->is_scalar());
2803 expr
->operands
[i
]->accept(this);
2804 op
[i
] = this->result
;
2807 switch (expr
->operation
) {
2808 case ir_unop_logic_not
:
2809 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2812 case ir_binop_logic_xor
:
2813 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2816 case ir_binop_logic_or
:
2817 temp
= vgrf(glsl_type::bool_type
);
2818 emit(OR(temp
, op
[0], op
[1]));
2819 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2822 case ir_binop_logic_and
:
2823 temp
= vgrf(glsl_type::bool_type
);
2824 emit(AND(temp
, op
[0], op
[1]));
2825 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2829 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2830 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2834 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2837 case ir_binop_greater
:
2838 case ir_binop_gequal
:
2840 case ir_binop_lequal
:
2841 case ir_binop_equal
:
2842 case ir_binop_all_equal
:
2843 case ir_binop_nequal
:
2844 case ir_binop_any_nequal
:
2845 if (devinfo
->gen
<= 5) {
2846 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2847 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2850 emit(IF(op
[0], op
[1],
2851 brw_conditional_for_comparison(expr
->operation
)));
2854 case ir_triop_csel
: {
2855 /* Expand the boolean condition into the flag register. */
2856 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2857 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2859 /* Select which boolean to use as the result. */
2860 fs_reg temp
= vgrf(expr
->operands
[1]->type
);
2861 inst
= emit(SEL(temp
, op
[1], op
[2]));
2862 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2864 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2869 unreachable("not reached");
2873 ir
->condition
->accept(this);
2874 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2878 fs_visitor::try_opt_frontfacing_ternary(ir_if
*ir
)
2880 ir_dereference_variable
*deref
= ir
->condition
->as_dereference_variable();
2881 if (!deref
|| strcmp(deref
->var
->name
, "gl_FrontFacing") != 0)
2884 if (ir
->then_instructions
.length() != 1 ||
2885 ir
->else_instructions
.length() != 1)
2888 ir_assignment
*then_assign
=
2889 ((ir_instruction
*)ir
->then_instructions
.head
)->as_assignment();
2890 ir_assignment
*else_assign
=
2891 ((ir_instruction
*)ir
->else_instructions
.head
)->as_assignment();
2893 if (!then_assign
|| then_assign
->condition
||
2894 !else_assign
|| else_assign
->condition
||
2895 then_assign
->write_mask
!= else_assign
->write_mask
||
2896 !then_assign
->lhs
->equals(else_assign
->lhs
))
2899 ir_constant
*then_rhs
= then_assign
->rhs
->as_constant();
2900 ir_constant
*else_rhs
= else_assign
->rhs
->as_constant();
2902 if (!then_rhs
|| !else_rhs
)
2905 if (then_rhs
->type
->base_type
!= GLSL_TYPE_FLOAT
)
2908 if ((then_rhs
->is_one() && else_rhs
->is_negative_one()) ||
2909 (else_rhs
->is_one() && then_rhs
->is_negative_one())) {
2910 then_assign
->lhs
->accept(this);
2911 fs_reg dst
= this->result
;
2912 dst
.type
= BRW_REGISTER_TYPE_D
;
2913 fs_reg tmp
= vgrf(glsl_type::int_type
);
2915 if (devinfo
->gen
>= 6) {
2916 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
2917 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
2919 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
2921 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
2922 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
2924 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
2927 if (then_rhs
->is_negative_one()) {
2928 assert(else_rhs
->is_one());
2932 tmp
.type
= BRW_REGISTER_TYPE_W
;
2933 tmp
.subreg_offset
= 2;
2936 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
2937 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
2939 tmp
.type
= BRW_REGISTER_TYPE_D
;
2940 tmp
.subreg_offset
= 0;
2943 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
2944 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
2946 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
2948 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
2949 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
2951 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
2954 if (then_rhs
->is_negative_one()) {
2955 assert(else_rhs
->is_one());
2959 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
2961 emit(AND(dst
, tmp
, fs_reg(0xbf800000)));
2969 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2971 * Many GLSL shaders contain the following pattern:
2973 * x = condition ? foo : bar
2975 * The compiler emits an ir_if tree for this, since each subexpression might be
2976 * a complex tree that could have side-effects or short-circuit logic.
2978 * However, the common case is to simply select one of two constants or
2979 * variable values---which is exactly what SEL is for. In this case, the
2980 * assembly looks like:
2988 * which can be easily translated into:
2990 * (+f0) SEL dst src0 src1
2992 * If src0 is an immediate value, we promote it to a temporary GRF.
2995 fs_visitor::try_replace_with_sel()
2997 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2998 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
3000 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
3002 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
3005 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
3006 for (int i
= 0; i
< 4; i
++) {
3007 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
3009 match
= (fs_inst
*) match
->prev
;
3012 /* The opcodes match; it looks like the right sequence of instructions. */
3013 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
3014 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
3015 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
3017 /* Check that the MOVs are the right form. */
3018 if (then_mov
->dst
.equals(else_mov
->dst
) &&
3019 !then_mov
->is_partial_write() &&
3020 !else_mov
->is_partial_write()) {
3022 /* Remove the matched instructions; we'll emit a SEL to replace them. */
3023 while (!if_inst
->next
->is_tail_sentinel())
3024 if_inst
->next
->exec_node::remove();
3025 if_inst
->exec_node::remove();
3027 /* Only the last source register can be a constant, so if the MOV in
3028 * the "then" clause uses a constant, we need to put it in a temporary.
3030 fs_reg
src0(then_mov
->src
[0]);
3031 if (src0
.file
== IMM
) {
3032 src0
= vgrf(glsl_type::float_type
);
3033 src0
.type
= then_mov
->src
[0].type
;
3034 emit(MOV(src0
, then_mov
->src
[0]));
3038 if (if_inst
->conditional_mod
) {
3039 /* Sandybridge-specific IF with embedded comparison */
3040 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
3041 if_inst
->conditional_mod
));
3042 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
3043 sel
->predicate
= BRW_PREDICATE_NORMAL
;
3045 /* Separate CMP and IF instructions */
3046 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
3047 sel
->predicate
= if_inst
->predicate
;
3048 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
3058 fs_visitor::visit(ir_if
*ir
)
3060 if (try_opt_frontfacing_ternary(ir
))
3063 /* Don't point the annotation at the if statement, because then it plus
3064 * the then and else blocks get printed.
3066 this->base_ir
= ir
->condition
;
3068 if (devinfo
->gen
== 6) {
3071 emit_bool_to_cond_code(ir
->condition
);
3073 emit(IF(BRW_PREDICATE_NORMAL
));
3076 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
3077 this->base_ir
= ir_
;
3081 if (!ir
->else_instructions
.is_empty()) {
3082 emit(BRW_OPCODE_ELSE
);
3084 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
3085 this->base_ir
= ir_
;
3090 emit(BRW_OPCODE_ENDIF
);
3092 if (!try_replace_with_sel() && devinfo
->gen
< 6) {
3093 no16("Can't support (non-uniform) control flow on SIMD16\n");
3098 fs_visitor::visit(ir_loop
*ir
)
3100 if (devinfo
->gen
< 6) {
3101 no16("Can't support (non-uniform) control flow on SIMD16\n");
3104 this->base_ir
= NULL
;
3105 emit(BRW_OPCODE_DO
);
3107 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
3108 this->base_ir
= ir_
;
3112 this->base_ir
= NULL
;
3113 emit(BRW_OPCODE_WHILE
);
3117 fs_visitor::visit(ir_loop_jump
*ir
)
3120 case ir_loop_jump::jump_break
:
3121 emit(BRW_OPCODE_BREAK
);
3123 case ir_loop_jump::jump_continue
:
3124 emit(BRW_OPCODE_CONTINUE
);
3130 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3132 ir_dereference
*deref
= static_cast<ir_dereference
*>(
3133 ir
->actual_parameters
.get_head());
3134 ir_variable
*location
= deref
->variable_referenced();
3135 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
3136 location
->data
.binding
);
3138 /* Calculate the surface offset */
3139 fs_reg offset
= vgrf(glsl_type::uint_type
);
3140 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
3143 deref_array
->array_index
->accept(this);
3145 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3146 emit(MUL(tmp
, this->result
, fs_reg(ATOMIC_COUNTER_SIZE
)));
3147 emit(ADD(offset
, tmp
, fs_reg(location
->data
.atomic
.offset
)));
3149 offset
= fs_reg(location
->data
.atomic
.offset
);
3152 /* Emit the appropriate machine instruction */
3153 const char *callee
= ir
->callee
->function_name();
3154 ir
->return_deref
->accept(this);
3155 fs_reg dst
= this->result
;
3157 if (!strcmp("__intrinsic_atomic_read", callee
)) {
3158 emit_untyped_surface_read(surf_index
, dst
, offset
);
3160 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
3161 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
3162 fs_reg(), fs_reg());
3164 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
3165 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
3166 fs_reg(), fs_reg());
3171 fs_visitor::visit(ir_call
*ir
)
3173 const char *callee
= ir
->callee
->function_name();
3175 if (!strcmp("__intrinsic_atomic_read", callee
) ||
3176 !strcmp("__intrinsic_atomic_increment", callee
) ||
3177 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
3178 visit_atomic_counter_intrinsic(ir
);
3180 unreachable("Unsupported intrinsic.");
3185 fs_visitor::visit(ir_return
*)
3187 unreachable("FINISHME");
3191 fs_visitor::visit(ir_function
*ir
)
3193 /* Ignore function bodies other than main() -- we shouldn't see calls to
3194 * them since they should all be inlined before we get to ir_to_mesa.
3196 if (strcmp(ir
->name
, "main") == 0) {
3197 const ir_function_signature
*sig
;
3200 sig
= ir
->matching_signature(NULL
, &empty
, false);
3204 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
3205 this->base_ir
= ir_
;
3212 fs_visitor::visit(ir_function_signature
*)
3214 unreachable("not reached");
3218 fs_visitor::visit(ir_emit_vertex
*)
3220 unreachable("not reached");
3224 fs_visitor::visit(ir_end_primitive
*)
3226 unreachable("not reached");
3230 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
3231 fs_reg dst
, fs_reg offset
, fs_reg src0
,
3234 int reg_width
= dispatch_width
/ 8;
3237 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
3239 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3240 /* Initialize the sample mask in the message header. */
3241 emit(MOV(sources
[0], fs_reg(0u)))
3242 ->force_writemask_all
= true;
3244 if (stage
== MESA_SHADER_FRAGMENT
) {
3245 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
3246 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
3247 ->force_writemask_all
= true;
3249 emit(MOV(component(sources
[0], 7),
3250 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
3251 ->force_writemask_all
= true;
3254 /* The execution mask is part of the side-band information sent together with
3255 * the message payload to the data port. It's implicitly ANDed with the sample
3256 * mask sent in the header to compute the actual set of channels that execute
3257 * the atomic operation.
3259 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
3260 emit(MOV(component(sources
[0], 7),
3261 fs_reg(0xffffu
)))->force_writemask_all
= true;
3265 /* Set the atomic operation offset. */
3266 sources
[1] = vgrf(glsl_type::uint_type
);
3267 emit(MOV(sources
[1], offset
));
3270 /* Set the atomic operation arguments. */
3271 if (src0
.file
!= BAD_FILE
) {
3272 sources
[length
] = vgrf(glsl_type::uint_type
);
3273 emit(MOV(sources
[length
], src0
));
3277 if (src1
.file
!= BAD_FILE
) {
3278 sources
[length
] = vgrf(glsl_type::uint_type
);
3279 emit(MOV(sources
[length
], src1
));
3283 int mlen
= 1 + (length
- 1) * reg_width
;
3284 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
3285 BRW_REGISTER_TYPE_UD
);
3286 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
3288 /* Emit the instruction. */
3289 fs_inst
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
3290 fs_reg(atomic_op
), fs_reg(surf_index
));
3295 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
3298 int reg_width
= dispatch_width
/ 8;
3300 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
3302 sources
[0] = fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
3303 /* Initialize the sample mask in the message header. */
3304 emit(MOV(sources
[0], fs_reg(0u)))
3305 ->force_writemask_all
= true;
3307 if (stage
== MESA_SHADER_FRAGMENT
) {
3308 if (((brw_wm_prog_data
*)this->prog_data
)->uses_kill
) {
3309 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
3310 ->force_writemask_all
= true;
3312 emit(MOV(component(sources
[0], 7),
3313 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
3314 ->force_writemask_all
= true;
3317 /* The execution mask is part of the side-band information sent together with
3318 * the message payload to the data port. It's implicitly ANDed with the sample
3319 * mask sent in the header to compute the actual set of channels that execute
3320 * the atomic operation.
3322 assert(stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_COMPUTE
);
3323 emit(MOV(component(sources
[0], 7),
3324 fs_reg(0xffffu
)))->force_writemask_all
= true;
3327 /* Set the surface read offset. */
3328 sources
[1] = vgrf(glsl_type::uint_type
);
3329 emit(MOV(sources
[1], offset
));
3331 int mlen
= 1 + reg_width
;
3332 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
3333 BRW_REGISTER_TYPE_UD
);
3334 fs_inst
*inst
= emit(LOAD_PAYLOAD(src_payload
, sources
, 2));
3336 /* Emit the instruction. */
3337 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
3338 fs_reg(surf_index
));
3343 fs_visitor::emit(fs_inst
*inst
)
3345 if (dispatch_width
== 16 && inst
->exec_size
== 8)
3346 inst
->force_uncompressed
= true;
3348 inst
->annotation
= this->current_annotation
;
3349 inst
->ir
= this->base_ir
;
3351 this->instructions
.push_tail(inst
);
3357 fs_visitor::emit(exec_list list
)
3359 foreach_in_list_safe(fs_inst
, inst
, &list
) {
3360 inst
->exec_node::remove();
3365 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
3367 fs_visitor::emit_dummy_fs()
3369 int reg_width
= dispatch_width
/ 8;
3371 /* Everyone's favorite color. */
3372 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
3373 for (int i
= 0; i
< 4; i
++) {
3374 emit(MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
,
3375 dispatch_width
), fs_reg(color
[i
])));
3379 write
= emit(FS_OPCODE_FB_WRITE
);
3381 if (devinfo
->gen
>= 6) {
3382 write
->base_mrf
= 2;
3383 write
->mlen
= 4 * reg_width
;
3385 write
->header_present
= true;
3386 write
->base_mrf
= 0;
3387 write
->mlen
= 2 + 4 * reg_width
;
3390 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
3391 * varying to avoid GPU hangs, so set that.
3393 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3394 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
3395 memset(wm_prog_data
->urb_setup
, -1,
3396 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
3398 /* We don't have any uniforms. */
3399 stage_prog_data
->nr_params
= 0;
3400 stage_prog_data
->nr_pull_params
= 0;
3401 stage_prog_data
->curb_read_length
= 0;
3402 stage_prog_data
->dispatch_grf_start_reg
= 2;
3403 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
3404 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
3409 /* The register location here is relative to the start of the URB
3410 * data. It will get adjusted to be a real location before
3411 * generate_code() time.
3414 fs_visitor::interp_reg(int location
, int channel
)
3416 assert(stage
== MESA_SHADER_FRAGMENT
);
3417 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3418 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
3419 int stride
= (channel
& 1) * 4;
3421 assert(prog_data
->urb_setup
[location
] != -1);
3423 return brw_vec1_grf(regnr
, stride
);
3426 /** Emits the interpolation for the varying inputs. */
3428 fs_visitor::emit_interpolation_setup_gen4()
3430 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
3432 this->current_annotation
= "compute pixel centers";
3433 this->pixel_x
= vgrf(glsl_type::uint_type
);
3434 this->pixel_y
= vgrf(glsl_type::uint_type
);
3435 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3436 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3437 emit(ADD(this->pixel_x
,
3438 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
3439 fs_reg(brw_imm_v(0x10101010))));
3440 emit(ADD(this->pixel_y
,
3441 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
3442 fs_reg(brw_imm_v(0x11001100))));
3444 this->current_annotation
= "compute pixel deltas from v0";
3446 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3447 vgrf(glsl_type::vec2_type
);
3448 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
3449 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
3450 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
3452 if (devinfo
->has_pln
&& dispatch_width
== 16) {
3453 emit(ADD(half(offset(delta_xy
, 0), 0), half(this->pixel_x
, 0), xstart
));
3454 emit(ADD(half(offset(delta_xy
, 0), 1), half(this->pixel_y
, 0), ystart
));
3455 emit(ADD(half(offset(delta_xy
, 1), 0), half(this->pixel_x
, 1), xstart
))
3456 ->force_sechalf
= true;
3457 emit(ADD(half(offset(delta_xy
, 1), 1), half(this->pixel_y
, 1), ystart
))
3458 ->force_sechalf
= true;
3460 emit(ADD(offset(delta_xy
, 0), this->pixel_x
, xstart
));
3461 emit(ADD(offset(delta_xy
, 1), this->pixel_y
, ystart
));
3464 this->current_annotation
= "compute pos.w and 1/pos.w";
3465 /* Compute wpos.w. It's always in our setup, since it's needed to
3466 * interpolate the other attributes.
3468 this->wpos_w
= vgrf(glsl_type::float_type
);
3469 emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
, interp_reg(VARYING_SLOT_POS
, 3));
3470 /* Compute the pixel 1/W value from wpos.w. */
3471 this->pixel_w
= vgrf(glsl_type::float_type
);
3472 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
3473 this->current_annotation
= NULL
;
3476 /** Emits the interpolation for the varying inputs. */
3478 fs_visitor::emit_interpolation_setup_gen6()
3480 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
3482 this->current_annotation
= "compute pixel centers";
3483 if (brw
->gen
>= 8 || dispatch_width
== 8) {
3484 /* The "Register Region Restrictions" page says for BDW (and newer,
3487 * "When destination spans two registers, the source may be one or
3488 * two registers. The destination elements must be evenly split
3489 * between the two registers."
3491 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
3492 * compute our pixel centers.
3494 fs_reg
int_pixel_xy(GRF
, alloc
.allocate(dispatch_width
/ 8),
3495 BRW_REGISTER_TYPE_UW
, dispatch_width
* 2);
3496 emit(ADD(int_pixel_xy
,
3497 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
3498 fs_reg(brw_imm_v(0x11001010))))
3499 ->force_writemask_all
= true;
3501 this->pixel_x
= vgrf(glsl_type::float_type
);
3502 this->pixel_y
= vgrf(glsl_type::float_type
);
3503 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
3504 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
3506 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
3508 * "When destination spans two registers, the source MUST span two
3511 * Since the GRF source of the ADD will only read a single register, we
3512 * must do two separate ADDs in SIMD16.
3514 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
3515 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
3516 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3517 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3518 emit(ADD(int_pixel_x
,
3519 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
3520 fs_reg(brw_imm_v(0x10101010))));
3521 emit(ADD(int_pixel_y
,
3522 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
3523 fs_reg(brw_imm_v(0x11001100))));
3525 /* As of gen6, we can no longer mix float and int sources. We have
3526 * to turn the integer pixel centers into floats for their actual
3529 this->pixel_x
= vgrf(glsl_type::float_type
);
3530 this->pixel_y
= vgrf(glsl_type::float_type
);
3531 emit(MOV(this->pixel_x
, int_pixel_x
));
3532 emit(MOV(this->pixel_y
, int_pixel_y
));
3535 this->current_annotation
= "compute pos.w";
3536 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
3537 this->wpos_w
= vgrf(glsl_type::float_type
);
3538 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
3540 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3541 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
3542 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
3545 this->current_annotation
= NULL
;
3549 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
,
3552 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3555 if (color
.file
== BAD_FILE
) {
3556 return 4 * (dispatch_width
/ 8);
3559 uint8_t colors_enabled
;
3560 if (components
== 0) {
3561 /* We want to write one component to the alpha channel */
3562 colors_enabled
= 0x8;
3564 /* Enable the first components-many channels */
3565 colors_enabled
= (1 << components
) - 1;
3568 if (dispatch_width
== 8 || (devinfo
->gen
>= 6 && !do_dual_src
)) {
3569 /* SIMD8 write looks like:
3575 * gen6 SIMD16 DP write looks like:
3586 for (unsigned i
= 0; i
< 4; ++i
) {
3587 if (colors_enabled
& (1 << i
)) {
3588 dst
[len
] = fs_reg(GRF
, alloc
.allocate(color
.width
/ 8),
3589 color
.type
, color
.width
);
3590 inst
= emit(MOV(dst
[len
], offset(color
, i
)));
3591 inst
->saturate
= key
->clamp_fragment_color
;
3592 } else if (color
.width
== 16) {
3593 /* We need two BAD_FILE slots for a 16-wide color */
3599 } else if (devinfo
->gen
>= 6 && do_dual_src
) {
3600 /* SIMD16 dual source blending for gen6+.
3602 * From the SNB PRM, volume 4, part 1, page 193:
3604 * "The dual source render target messages only have SIMD8 forms due to
3605 * maximum message length limitations. SIMD16 pixel shaders must send two
3606 * of these messages to cover all of the pixels. Each message contains
3607 * two colors (4 channels each) for each pixel in the message payload."
3609 * So in SIMD16 dual source blending we will send 2 SIMD8 messages,
3610 * each one will call this function twice (one for each color involved),
3611 * so in each pass we only write 4 registers. Notice that the second
3612 * SIMD8 message needs to read color data from the 2nd half of the color
3613 * registers, so it needs to call this with use_2nd_half = true.
3615 for (unsigned i
= 0; i
< 4; ++i
) {
3616 if (colors_enabled
& (1 << i
)) {
3617 dst
[i
] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3618 inst
= emit(MOV(dst
[i
], half(offset(color
, i
),
3619 use_2nd_half
? 1 : 0)));
3620 inst
->saturate
= key
->clamp_fragment_color
;
3622 inst
->force_sechalf
= true;
3627 /* pre-gen6 SIMD16 single source DP write looks like:
3637 for (unsigned i
= 0; i
< 4; ++i
) {
3638 if (colors_enabled
& (1 << i
)) {
3639 dst
[i
] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3640 inst
= emit(MOV(dst
[i
], half(offset(color
, i
), 0)));
3641 inst
->saturate
= key
->clamp_fragment_color
;
3643 dst
[i
+ 4] = fs_reg(GRF
, alloc
.allocate(1), color
.type
);
3644 inst
= emit(MOV(dst
[i
+ 4], half(offset(color
, i
), 1)));
3645 inst
->saturate
= key
->clamp_fragment_color
;
3646 inst
->force_sechalf
= true;
3653 static enum brw_conditional_mod
3654 cond_for_alpha_func(GLenum func
)
3658 return BRW_CONDITIONAL_G
;
3660 return BRW_CONDITIONAL_GE
;
3662 return BRW_CONDITIONAL_L
;
3664 return BRW_CONDITIONAL_LE
;
3666 return BRW_CONDITIONAL_EQ
;
3668 return BRW_CONDITIONAL_NEQ
;
3670 unreachable("Not reached");
3675 * Alpha test support for when we compile it into the shader instead
3676 * of using the normal fixed-function alpha test.
3679 fs_visitor::emit_alpha_test()
3681 assert(stage
== MESA_SHADER_FRAGMENT
);
3682 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3683 this->current_annotation
= "Alpha test";
3686 if (key
->alpha_test_func
== GL_ALWAYS
)
3689 if (key
->alpha_test_func
== GL_NEVER
) {
3691 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3692 BRW_REGISTER_TYPE_UW
));
3693 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3694 BRW_CONDITIONAL_NEQ
));
3697 fs_reg color
= offset(outputs
[0], 3);
3699 /* f0.1 &= func(color, ref) */
3700 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3701 cond_for_alpha_func(key
->alpha_test_func
)));
3703 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3704 cmp
->flag_subreg
= 1;
3708 fs_visitor::emit_single_fb_write(fs_reg color0
, fs_reg color1
,
3709 fs_reg src0_alpha
, unsigned components
,
3712 assert(stage
== MESA_SHADER_FRAGMENT
);
3713 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3714 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3716 this->current_annotation
= "FB write header";
3717 bool header_present
= true;
3718 int reg_size
= dispatch_width
/ 8;
3720 /* We can potentially have a message length of up to 15, so we have to set
3721 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3723 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
3726 /* From the Sandy Bridge PRM, volume 4, page 198:
3728 * "Dispatched Pixel Enables. One bit per pixel indicating
3729 * which pixels were originally enabled when the thread was
3730 * dispatched. This field is only required for the end-of-
3731 * thread message and on all dual-source messages."
3733 if (devinfo
->gen
>= 6 &&
3734 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3735 color1
.file
== BAD_FILE
&&
3736 key
->nr_color_regions
== 1) {
3737 header_present
= false;
3741 /* Allocate 2 registers for a header */
3744 if (payload
.aa_dest_stencil_reg
) {
3745 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1));
3746 emit(MOV(sources
[length
],
3747 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3751 prog_data
->uses_omask
=
3752 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3753 if (prog_data
->uses_omask
) {
3754 this->current_annotation
= "FB write oMask";
3755 assert(this->sample_mask
.file
!= BAD_FILE
);
3756 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
3757 * it's unsinged single words, one vgrf is always 16-wide.
3759 sources
[length
] = fs_reg(GRF
, alloc
.allocate(1),
3760 BRW_REGISTER_TYPE_UW
, 16);
3761 emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
3765 if (color0
.file
== BAD_FILE
) {
3766 /* Even if there's no color buffers enabled, we still need to send
3767 * alpha out the pipeline to our null renderbuffer to support
3768 * alpha-testing, alpha-to-coverage, and so on.
3770 length
+= setup_color_payload(sources
+ length
, this->outputs
[0], 0,
3772 } else if (color1
.file
== BAD_FILE
) {
3773 if (src0_alpha
.file
!= BAD_FILE
) {
3774 sources
[length
] = fs_reg(GRF
, alloc
.allocate(reg_size
),
3775 src0_alpha
.type
, src0_alpha
.width
);
3776 fs_inst
*inst
= emit(MOV(sources
[length
], src0_alpha
));
3777 inst
->saturate
= key
->clamp_fragment_color
;
3781 length
+= setup_color_payload(sources
+ length
, color0
, components
,
3784 length
+= setup_color_payload(sources
+ length
, color0
, components
,
3786 length
+= setup_color_payload(sources
+ length
, color1
, components
,
3790 if (source_depth_to_render_target
) {
3791 if (devinfo
->gen
== 6) {
3792 /* For outputting oDepth on gen6, SIMD8 writes have to be
3793 * used. This would require SIMD8 moves of each half to
3794 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3795 * Just bail on doing so for now.
3797 no16("Missing support for simd16 depth writes on gen6\n");
3800 sources
[length
] = vgrf(glsl_type::float_type
);
3801 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3802 /* Hand over gl_FragDepth. */
3803 assert(this->frag_depth
.file
!= BAD_FILE
);
3804 emit(MOV(sources
[length
], this->frag_depth
));
3806 /* Pass through the payload depth. */
3807 emit(MOV(sources
[length
],
3808 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3813 if (payload
.dest_depth_reg
) {
3814 sources
[length
] = vgrf(glsl_type::float_type
);
3815 emit(MOV(sources
[length
],
3816 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3822 if (devinfo
->gen
>= 7) {
3823 /* Send from the GRF */
3824 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3825 load
= emit(LOAD_PAYLOAD(payload
, sources
, length
));
3826 payload
.reg
= alloc
.allocate(load
->regs_written
);
3827 payload
.width
= dispatch_width
;
3828 load
->dst
= payload
;
3829 write
= emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
3830 write
->base_mrf
= -1;
3832 /* Send from the MRF */
3833 load
= emit(LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3835 write
= emit(FS_OPCODE_FB_WRITE
);
3836 write
->exec_size
= dispatch_width
;
3837 write
->base_mrf
= 1;
3840 write
->mlen
= load
->regs_written
;
3841 write
->header_present
= header_present
;
3842 if (prog_data
->uses_kill
) {
3843 write
->predicate
= BRW_PREDICATE_NORMAL
;
3844 write
->flag_subreg
= 1;
3850 fs_visitor::emit_fb_writes()
3852 assert(stage
== MESA_SHADER_FRAGMENT
);
3853 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3854 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3856 fs_inst
*inst
= NULL
;
3858 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3859 "FB dual-source write");
3860 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3864 /* SIMD16 dual source blending requires to send two SIMD8 dual source
3865 * messages, where each message contains color data for 8 pixels. Color
3866 * data for the first group of pixels is stored in the "lower" half of
3867 * the color registers, so in SIMD16, the previous message did:
3873 * Here goes the second message, which packs color data for the
3874 * remaining 8 pixels. Color data for these pixels is stored in the
3875 * "upper" half of the color registers, so we need to do:
3881 if (dispatch_width
== 16) {
3882 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3883 reg_undef
, 4, true);
3887 prog_data
->dual_src_blend
= true;
3889 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3890 /* Skip over outputs that weren't written. */
3891 if (this->outputs
[target
].file
== BAD_FILE
)
3894 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3895 "FB write target %d",
3898 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
3899 src0_alpha
= offset(outputs
[0], 3);
3901 inst
= emit_single_fb_write(this->outputs
[target
], reg_undef
,
3903 this->output_components
[target
]);
3904 inst
->target
= target
;
3909 /* Even if there's no color buffers enabled, we still need to send
3910 * alpha out the pipeline to our null renderbuffer to support
3911 * alpha-testing, alpha-to-coverage, and so on.
3913 inst
= emit_single_fb_write(reg_undef
, reg_undef
, reg_undef
, 0);
3918 this->current_annotation
= NULL
;
3922 fs_visitor::setup_uniform_clipplane_values()
3924 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
3925 const struct brw_vue_prog_key
*key
=
3926 (const struct brw_vue_prog_key
*) this->key
;
3928 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
3929 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
3930 for (int j
= 0; j
< 4; ++j
) {
3931 stage_prog_data
->param
[uniforms
+ j
] =
3932 (gl_constant_value
*) &clip_planes
[i
][j
];
3938 void fs_visitor::compute_clip_distance()
3940 struct brw_vue_prog_data
*vue_prog_data
=
3941 (struct brw_vue_prog_data
*) prog_data
;
3942 const struct brw_vue_prog_key
*key
=
3943 (const struct brw_vue_prog_key
*) this->key
;
3945 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3947 * "If a linked set of shaders forming the vertex stage contains no
3948 * static write to gl_ClipVertex or gl_ClipDistance, but the
3949 * application has requested clipping against user clip planes through
3950 * the API, then the coordinate written to gl_Position is used for
3951 * comparison against the user clip planes."
3953 * This function is only called if the shader didn't write to
3954 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3955 * if the user wrote to it; otherwise we use gl_Position.
3958 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3959 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
3960 clip_vertex
= VARYING_SLOT_POS
;
3962 /* If the clip vertex isn't written, skip this. Typically this means
3963 * the GS will set up clipping. */
3964 if (outputs
[clip_vertex
].file
== BAD_FILE
)
3967 setup_uniform_clipplane_values();
3969 current_annotation
= "user clip distances";
3971 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
3972 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
3974 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
3975 fs_reg u
= userplane
[i
];
3976 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
3977 output
.reg_offset
= i
& 3;
3979 emit(MUL(output
, outputs
[clip_vertex
], u
));
3980 for (int j
= 1; j
< 4; j
++) {
3981 u
.reg
= userplane
[i
].reg
+ j
;
3982 emit(MAD(output
, output
, offset(outputs
[clip_vertex
], j
), u
));
3988 fs_visitor::emit_urb_writes()
3990 int slot
, urb_offset
, length
;
3991 struct brw_vs_prog_data
*vs_prog_data
=
3992 (struct brw_vs_prog_data
*) prog_data
;
3993 const struct brw_vs_prog_key
*key
=
3994 (const struct brw_vs_prog_key
*) this->key
;
3995 const GLbitfield64 psiz_mask
=
3996 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
3997 const struct brw_vue_map
*vue_map
= &vs_prog_data
->base
.vue_map
;
4001 /* Lower legacy ff and ClipVertex clipping to clip distances */
4002 if (key
->base
.userclip_active
&& !prog
->UsesClipDistanceOut
)
4003 compute_clip_distance();
4005 /* If we don't have any valid slots to write, just do a minimal urb write
4006 * send to terminate the shader. */
4007 if (vue_map
->slots_valid
== 0) {
4009 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
4010 fs_inst
*inst
= emit(MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
4011 BRW_REGISTER_TYPE_UD
))));
4012 inst
->force_writemask_all
= true;
4014 inst
= emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
4024 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
4025 fs_reg reg
, src
, zero
;
4027 int varying
= vue_map
->slot_to_varying
[slot
];
4029 case VARYING_SLOT_PSIZ
:
4031 /* The point size varying slot is the vue header and is always in the
4032 * vue map. But often none of the special varyings that live there
4033 * are written and in that case we can skip writing to the vue
4034 * header, provided the corresponding state properly clamps the
4035 * values further down the pipeline. */
4036 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
4037 assert(length
== 0);
4042 zero
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
4043 emit(MOV(zero
, fs_reg(0u)));
4045 sources
[length
++] = zero
;
4046 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
4047 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
4049 sources
[length
++] = zero
;
4051 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
4052 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
4054 sources
[length
++] = zero
;
4056 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
4057 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
4059 sources
[length
++] = zero
;
4062 case BRW_VARYING_SLOT_NDC
:
4063 case VARYING_SLOT_EDGE
:
4064 unreachable("unexpected scalar vs output");
4067 case BRW_VARYING_SLOT_PAD
:
4071 /* gl_Position is always in the vue map, but isn't always written by
4072 * the shader. Other varyings (clip distances) get added to the vue
4073 * map but don't always get written. In those cases, the
4074 * corresponding this->output[] slot will be invalid we and can skip
4075 * the urb write for the varying. If we've already queued up a vue
4076 * slot for writing we flush a mlen 5 urb write, otherwise we just
4077 * advance the urb_offset.
4079 if (this->outputs
[varying
].file
== BAD_FILE
) {
4087 if ((varying
== VARYING_SLOT_COL0
||
4088 varying
== VARYING_SLOT_COL1
||
4089 varying
== VARYING_SLOT_BFC0
||
4090 varying
== VARYING_SLOT_BFC1
) &&
4091 key
->clamp_vertex_color
) {
4092 /* We need to clamp these guys, so do a saturating MOV into a
4093 * temp register and use that for the payload.
4095 for (int i
= 0; i
< 4; i
++) {
4096 reg
= fs_reg(GRF
, alloc
.allocate(1), outputs
[varying
].type
);
4097 src
= offset(this->outputs
[varying
], i
);
4098 fs_inst
*inst
= emit(MOV(reg
, src
));
4099 inst
->saturate
= true;
4100 sources
[length
++] = reg
;
4103 for (int i
= 0; i
< 4; i
++)
4104 sources
[length
++] = offset(this->outputs
[varying
], i
);
4109 current_annotation
= "URB write";
4111 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
4112 * the last slot or if we need to flush (see BAD_FILE varying case
4113 * above), emit a URB write send now to flush out the data.
4115 int last
= slot
== vue_map
->num_slots
- 1;
4116 if (length
== 8 || last
)
4119 fs_reg
*payload_sources
= ralloc_array(mem_ctx
, fs_reg
, length
+ 1);
4120 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(length
+ 1),
4121 BRW_REGISTER_TYPE_F
);
4123 /* We need WE_all on the MOV for the message header (the URB handles)
4124 * so do a MOV to a dummy register and set force_writemask_all on the
4125 * MOV. LOAD_PAYLOAD will preserve that.
4127 fs_reg dummy
= fs_reg(GRF
, alloc
.allocate(1),
4128 BRW_REGISTER_TYPE_UD
);
4129 fs_inst
*inst
= emit(MOV(dummy
, fs_reg(retype(brw_vec8_grf(1, 0),
4130 BRW_REGISTER_TYPE_UD
))));
4131 inst
->force_writemask_all
= true;
4132 payload_sources
[0] = dummy
;
4134 memcpy(&payload_sources
[1], sources
, length
* sizeof sources
[0]);
4135 emit(LOAD_PAYLOAD(payload
, payload_sources
, length
+ 1));
4137 inst
= emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
4139 inst
->mlen
= length
+ 1;
4140 inst
->offset
= urb_offset
;
4141 urb_offset
= slot
+ 1;
4149 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
4151 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
4155 fs_reg temp
= vgrf(glsl_type::uint_type
);
4156 emit(MOV(temp
, *reg
));
4161 fs_visitor::emit_cs_terminate()
4163 assert(brw
->gen
>= 7);
4165 /* We are getting the thread ID from the compute shader header */
4166 assert(stage
== MESA_SHADER_COMPUTE
);
4168 /* We can't directly send from g0, since sends with EOT have to use
4169 * g112-127. So, copy it to a virtual register, The register allocator will
4170 * make sure it uses the appropriate register range.
4172 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
4173 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
4174 fs_inst
*inst
= emit(MOV(payload
, g0
));
4175 inst
->force_writemask_all
= true;
4177 /* Send a message to the thread spawner to terminate the thread. */
4178 inst
= emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
4183 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
4185 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
4186 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
4189 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
4191 assert(devinfo
->gen
<= 5);
4193 if (rvalue
->type
!= glsl_type::bool_type
)
4196 fs_reg and_result
= vgrf(glsl_type::bool_type
);
4197 fs_reg neg_result
= vgrf(glsl_type::bool_type
);
4198 emit(AND(and_result
, *reg
, fs_reg(1)));
4199 emit(MOV(neg_result
, negate(and_result
)));
4203 fs_visitor::fs_visitor(struct brw_context
*brw
,
4205 const struct brw_wm_prog_key
*key
,
4206 struct brw_wm_prog_data
*prog_data
,
4207 struct gl_shader_program
*shader_prog
,
4208 struct gl_fragment_program
*fp
,
4209 unsigned dispatch_width
)
4210 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
4211 MESA_SHADER_FRAGMENT
),
4212 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
4213 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
4214 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
4215 key(key
), prog_data(&prog_data
->base
),
4216 dispatch_width(dispatch_width
), promoted_constants(0)
4218 this->mem_ctx
= mem_ctx
;
4222 fs_visitor::fs_visitor(struct brw_context
*brw
,
4224 const struct brw_vs_prog_key
*key
,
4225 struct brw_vs_prog_data
*prog_data
,
4226 struct gl_shader_program
*shader_prog
,
4227 struct gl_vertex_program
*cp
,
4228 unsigned dispatch_width
)
4229 : backend_visitor(brw
, shader_prog
, &cp
->Base
, &prog_data
->base
.base
,
4230 MESA_SHADER_VERTEX
),
4231 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
4232 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
4233 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
4234 key(key
), prog_data(&prog_data
->base
.base
),
4235 dispatch_width(dispatch_width
), promoted_constants(0)
4237 this->mem_ctx
= mem_ctx
;
4241 fs_visitor::fs_visitor(struct brw_context
*brw
,
4243 const struct brw_cs_prog_key
*key
,
4244 struct brw_cs_prog_data
*prog_data
,
4245 struct gl_shader_program
*shader_prog
,
4246 struct gl_compute_program
*cp
,
4247 unsigned dispatch_width
)
4248 : backend_visitor(brw
, shader_prog
, &cp
->Base
, &prog_data
->base
,
4249 MESA_SHADER_COMPUTE
),
4250 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
4251 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
4252 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
4253 key(key
), prog_data(&prog_data
->base
),
4254 dispatch_width(dispatch_width
)
4256 this->mem_ctx
= mem_ctx
;
4264 case MESA_SHADER_FRAGMENT
:
4265 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
4267 case MESA_SHADER_VERTEX
:
4268 case MESA_SHADER_GEOMETRY
:
4269 key_tex
= &((const brw_vue_prog_key
*) key
)->tex
;
4271 case MESA_SHADER_COMPUTE
:
4272 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
4275 unreachable("unhandled shader stage");
4278 this->failed
= false;
4279 this->simd16_unsupported
= false;
4280 this->no16_msg
= NULL
;
4281 this->variable_ht
= hash_table_ctor(0,
4282 hash_table_pointer_hash
,
4283 hash_table_pointer_compare
);
4285 this->nir_locals
= NULL
;
4286 this->nir_globals
= NULL
;
4288 memset(&this->payload
, 0, sizeof(this->payload
));
4289 memset(this->outputs
, 0, sizeof(this->outputs
));
4290 memset(this->output_components
, 0, sizeof(this->output_components
));
4291 this->source_depth_to_render_target
= false;
4292 this->runtime_check_aads_emit
= false;
4293 this->first_non_payload_grf
= 0;
4294 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
4296 this->current_annotation
= NULL
;
4297 this->base_ir
= NULL
;
4299 this->virtual_grf_start
= NULL
;
4300 this->virtual_grf_end
= NULL
;
4301 this->live_intervals
= NULL
;
4302 this->regs_live_at_ip
= NULL
;
4305 this->last_scratch
= 0;
4306 this->pull_constant_loc
= NULL
;
4307 this->push_constant_loc
= NULL
;
4309 this->spilled_any_registers
= false;
4310 this->do_dual_src
= false;
4312 if (dispatch_width
== 8)
4313 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
4316 fs_visitor::~fs_visitor()
4318 hash_table_dtor(this->variable_ht
);