2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_optimization.h"
51 #include "../glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
62 this->frag_color
= ir
;
63 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
65 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
66 this->frag_depth
= ir
;
69 if (ir
->mode
== ir_var_in
) {
70 if (!strcmp(ir
->name
, "gl_FragCoord")) {
71 reg
= emit_fragcoord_interpolation(ir
);
72 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
73 reg
= emit_frontfacing_interpolation(ir
);
75 reg
= emit_general_interpolation(ir
);
78 hash_table_insert(this->variable_ht
, reg
, ir
);
82 if (ir
->mode
== ir_var_uniform
) {
83 int param_index
= c
->prog_data
.nr_params
;
85 if (c
->dispatch_width
== 16) {
86 if (!variable_storage(ir
)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
92 if (!strncmp(ir
->name
, "gl_", 3)) {
93 setup_builtin_uniform_values(ir
);
95 setup_uniform_values(ir
->location
, ir
->type
);
98 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
99 reg
->type
= brw_type_for_base_type(ir
->type
);
103 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
105 hash_table_insert(this->variable_ht
, reg
, ir
);
109 fs_visitor::visit(ir_dereference_variable
*ir
)
111 fs_reg
*reg
= variable_storage(ir
->var
);
116 fs_visitor::visit(ir_dereference_record
*ir
)
118 const glsl_type
*struct_type
= ir
->record
->type
;
120 ir
->record
->accept(this);
122 unsigned int offset
= 0;
123 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
124 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
126 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
128 this->result
.reg_offset
+= offset
;
129 this->result
.type
= brw_type_for_base_type(ir
->type
);
133 fs_visitor::visit(ir_dereference_array
*ir
)
138 ir
->array
->accept(this);
139 index
= ir
->array_index
->as_constant();
141 element_size
= type_size(ir
->type
);
142 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 assert(this->result
.file
== UNIFORM
||
146 (this->result
.file
== GRF
&&
147 this->result
.reg
!= 0));
148 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
150 assert(!"FINISHME: non-constant array element");
154 /* Instruction selection: Produce a MOV.sat instead of
155 * MIN(MAX(val, 0), 1) when possible.
158 fs_visitor::try_emit_saturate(ir_expression
*ir
)
160 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
165 this->result
= reg_undef
;
166 sat_val
->accept(this);
167 fs_reg src
= this->result
;
169 this->result
= fs_reg(this, ir
->type
);
170 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
171 inst
->saturate
= true;
177 fs_visitor::visit(ir_expression
*ir
)
179 unsigned int operand
;
183 assert(ir
->get_num_operands() <= 2);
185 if (try_emit_saturate(ir
))
188 /* This is where our caller would like us to put the result, if possible. */
189 fs_reg saved_result_storage
= this->result
;
191 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
192 this->result
= reg_undef
;
193 ir
->operands
[operand
]->accept(this);
194 if (this->result
.file
== BAD_FILE
) {
196 fail("Failed to get tree for expression operand:\n");
197 ir
->operands
[operand
]->accept(&v
);
199 op
[operand
] = this->result
;
201 /* Matrix expression operands should have been broken down to vector
202 * operations already.
204 assert(!ir
->operands
[operand
]->type
->is_matrix());
205 /* And then those vector operands should have been broken down to scalar.
207 assert(!ir
->operands
[operand
]->type
->is_vector());
210 /* Inherit storage from our parent if possible, and otherwise we
213 if (saved_result_storage
.file
== BAD_FILE
) {
214 this->result
= fs_reg(this, ir
->type
);
216 this->result
= saved_result_storage
;
219 switch (ir
->operation
) {
220 case ir_unop_logic_not
:
221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
222 * ones complement of the whole register, not just bit 0.
224 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
227 op
[0].negate
= !op
[0].negate
;
228 this->result
= op
[0];
232 op
[0].negate
= false;
233 this->result
= op
[0];
236 temp
= fs_reg(this, ir
->type
);
238 /* Unalias the destination. (imagine a = sign(a)) */
239 this->result
= fs_reg(this, ir
->type
);
241 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
243 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
244 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
245 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
246 inst
->predicated
= true;
248 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
249 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
250 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
251 inst
->predicated
= true;
255 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
259 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
262 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
266 assert(!"not reached: should be handled by ir_explog_to_explog2");
269 case ir_unop_sin_reduced
:
270 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
273 case ir_unop_cos_reduced
:
274 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
278 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
281 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
285 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
288 assert(!"not reached: should be handled by ir_sub_to_add_neg");
292 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
295 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
302 case ir_binop_greater
:
303 case ir_binop_lequal
:
304 case ir_binop_gequal
:
306 case ir_binop_all_equal
:
307 case ir_binop_nequal
:
308 case ir_binop_any_nequal
:
310 /* original gen4 does implicit conversion before comparison. */
312 temp
.type
= op
[0].type
;
314 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
315 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
316 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
319 case ir_binop_logic_xor
:
320 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
323 case ir_binop_logic_or
:
324 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
327 case ir_binop_logic_and
:
328 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
333 assert(!"not reached: should be handled by brw_fs_channel_expressions");
337 assert(!"not reached: should be handled by lower_noise");
340 case ir_quadop_vector
:
341 assert(!"not reached: should be handled by lower_quadop_vector");
345 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
349 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
356 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
361 /* original gen4 does implicit conversion before comparison. */
363 temp
.type
= op
[0].type
;
365 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
366 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
367 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
371 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
374 op
[0].negate
= !op
[0].negate
;
375 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
376 this->result
.negate
= true;
379 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
382 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
384 case ir_unop_round_even
:
385 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
389 /* Unalias the destination */
390 this->result
= fs_reg(this, ir
->type
);
392 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
393 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
395 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
396 inst
->predicated
= true;
399 /* Unalias the destination */
400 this->result
= fs_reg(this, ir
->type
);
402 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
403 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
405 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
406 inst
->predicated
= true;
410 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
413 case ir_unop_bit_not
:
414 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
416 case ir_binop_bit_and
:
417 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
419 case ir_binop_bit_xor
:
420 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
422 case ir_binop_bit_or
:
423 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
427 case ir_binop_lshift
:
428 case ir_binop_rshift
:
429 assert(!"GLSL 1.30 features unsupported");
435 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
436 const glsl_type
*type
, bool predicated
)
438 switch (type
->base_type
) {
439 case GLSL_TYPE_FLOAT
:
443 for (unsigned int i
= 0; i
< type
->components(); i
++) {
444 l
.type
= brw_type_for_base_type(type
);
445 r
.type
= brw_type_for_base_type(type
);
447 if (predicated
|| !l
.equals(&r
)) {
448 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
449 inst
->predicated
= predicated
;
456 case GLSL_TYPE_ARRAY
:
457 for (unsigned int i
= 0; i
< type
->length
; i
++) {
458 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
462 case GLSL_TYPE_STRUCT
:
463 for (unsigned int i
= 0; i
< type
->length
; i
++) {
464 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
469 case GLSL_TYPE_SAMPLER
:
473 assert(!"not reached");
479 fs_visitor::visit(ir_assignment
*ir
)
484 /* FINISHME: arrays on the lhs */
485 this->result
= reg_undef
;
486 ir
->lhs
->accept(this);
489 /* If we're doing a direct assignment, an RHS expression could
490 * drop its result right into our destination. Otherwise, tell it
494 !(ir
->lhs
->type
->is_scalar() ||
495 (ir
->lhs
->type
->is_vector() &&
496 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1))) {
497 this->result
= reg_undef
;
500 ir
->rhs
->accept(this);
503 assert(l
.file
!= BAD_FILE
);
504 assert(r
.file
!= BAD_FILE
);
507 emit_bool_to_cond_code(ir
->condition
);
510 if (ir
->lhs
->type
->is_scalar() ||
511 ir
->lhs
->type
->is_vector()) {
512 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
513 if (ir
->write_mask
& (1 << i
)) {
515 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
516 inst
->predicated
= true;
517 } else if (!l
.equals(&r
)) {
518 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
526 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
531 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
542 if (ir
->shadow_comparitor
) {
543 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
544 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
545 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
546 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
547 inst
->saturate
= true;
549 coordinate
.reg_offset
++;
551 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
554 if (ir
->op
== ir_tex
) {
555 /* There's no plain shadow compare message, so we use shadow
556 * compare with a bias of 0.0.
558 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
560 } else if (ir
->op
== ir_txb
) {
561 this->result
= reg_undef
;
562 ir
->lod_info
.bias
->accept(this);
563 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
566 assert(ir
->op
== ir_txl
);
567 this->result
= reg_undef
;
568 ir
->lod_info
.lod
->accept(this);
569 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
573 this->result
= reg_undef
;
574 ir
->shadow_comparitor
->accept(this);
575 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
577 } else if (ir
->op
== ir_tex
) {
578 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
579 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
581 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
582 inst
->saturate
= true;
583 coordinate
.reg_offset
++;
585 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
587 } else if (ir
->op
== ir_txd
) {
588 assert(!"TXD isn't supported on gen4 yet.");
590 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
591 * instructions. We'll need to do SIMD16 here.
593 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
595 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
596 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
597 base_mrf
+ mlen
+ i
* 2),
599 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
600 inst
->saturate
= true;
601 coordinate
.reg_offset
++;
604 /* lod/bias appears after u/v/r. */
607 if (ir
->op
== ir_txb
) {
608 this->result
= reg_undef
;
609 ir
->lod_info
.bias
->accept(this);
610 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
613 this->result
= reg_undef
;
614 ir
->lod_info
.lod
->accept(this);
615 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
619 /* The unused upper half. */
622 /* Now, since we're doing simd16, the return is 2 interleaved
623 * vec4s where the odd-indexed ones are junk. We'll need to move
624 * this weirdness around to the expected layout.
628 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
630 dst
.type
= BRW_REGISTER_TYPE_F
;
633 fs_inst
*inst
= NULL
;
636 inst
= emit(FS_OPCODE_TEX
, dst
);
639 inst
= emit(FS_OPCODE_TXB
, dst
);
642 inst
= emit(FS_OPCODE_TXL
, dst
);
645 inst
= emit(FS_OPCODE_TXD
, dst
);
648 assert(!"GLSL 1.30 features unsupported");
651 inst
->base_mrf
= base_mrf
;
653 inst
->header_present
= true;
656 for (int i
= 0; i
< 4; i
++) {
657 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
658 orig_dst
.reg_offset
++;
666 /* gen5's sampler has slots for u, v, r, array index, then optional
667 * parameters like shadow comparitor or LOD bias. If optional
668 * parameters aren't present, those base slots are optional and don't
669 * need to be included in the message.
671 * We don't fill in the unnecessary slots regardless, which may look
672 * surprising in the disassembly.
675 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
680 int reg_width
= c
->dispatch_width
/ 8;
681 bool header_present
= false;
684 /* The offsets set up by the ir_texture visitor are in the
685 * m1 header, so we can't go headerless.
687 header_present
= true;
692 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
693 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
694 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
),
696 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
697 inst
->saturate
= true;
698 coordinate
.reg_offset
++;
700 mlen
+= ir
->coordinate
->type
->vector_elements
* reg_width
;
702 if (ir
->shadow_comparitor
) {
703 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
705 this->result
= reg_undef
;
706 ir
->shadow_comparitor
->accept(this);
707 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
711 fs_inst
*inst
= NULL
;
714 inst
= emit(FS_OPCODE_TEX
, dst
);
717 this->result
= reg_undef
;
718 ir
->lod_info
.bias
->accept(this);
719 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
720 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
723 inst
= emit(FS_OPCODE_TXB
, dst
);
727 this->result
= reg_undef
;
728 ir
->lod_info
.lod
->accept(this);
729 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
730 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
733 inst
= emit(FS_OPCODE_TXL
, dst
);
737 assert(!"GLSL 1.30 features unsupported");
740 inst
->base_mrf
= base_mrf
;
742 inst
->header_present
= header_present
;
745 fail("Message length >11 disallowed by hardware\n");
752 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
757 int reg_width
= c
->dispatch_width
/ 8;
758 bool header_present
= false;
761 /* The offsets set up by the ir_texture visitor are in the
762 * m1 header, so we can't go headerless.
764 header_present
= true;
769 if (ir
->shadow_comparitor
) {
770 ir
->shadow_comparitor
->accept(this);
771 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
775 /* Set up the LOD info */
780 ir
->lod_info
.bias
->accept(this);
781 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
785 ir
->lod_info
.lod
->accept(this);
786 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
791 assert(!"GLSL 1.30 features unsupported");
795 /* Set up the coordinate */
796 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
797 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
799 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
800 inst
->saturate
= true;
801 coordinate
.reg_offset
++;
805 /* Generate the SEND */
806 fs_inst
*inst
= NULL
;
808 case ir_tex
: inst
= emit(FS_OPCODE_TEX
, dst
); break;
809 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
810 case ir_txl
: inst
= emit(FS_OPCODE_TXL
, dst
); break;
811 case ir_txd
: inst
= emit(FS_OPCODE_TXD
, dst
); break;
812 case ir_txf
: assert(!"TXF unsupported.");
814 inst
->base_mrf
= base_mrf
;
816 inst
->header_present
= header_present
;
819 fail("Message length >11 disallowed by hardware\n");
826 fs_visitor::visit(ir_texture
*ir
)
829 fs_inst
*inst
= NULL
;
831 this->result
= reg_undef
;
832 ir
->coordinate
->accept(this);
833 fs_reg coordinate
= this->result
;
835 if (ir
->offset
!= NULL
) {
836 ir_constant
*offset
= ir
->offset
->as_constant();
837 assert(offset
!= NULL
);
839 signed char offsets
[3];
840 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
841 offsets
[i
] = (signed char) offset
->value
.i
[i
];
843 /* Combine all three offsets into a single unsigned dword:
845 * bits 11:8 - U Offset (X component)
846 * bits 7:4 - V Offset (Y component)
847 * bits 3:0 - R Offset (Z component)
849 unsigned offset_bits
= 0;
850 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
851 const unsigned shift
= 4 * (2 - i
);
852 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
855 /* Explicitly set up the message header by copying g0 to msg reg m1. */
856 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
857 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
859 /* Then set the offset bits in DWord 2 of the message header. */
861 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
862 BRW_REGISTER_TYPE_UD
)),
863 fs_reg(brw_imm_uw(offset_bits
)));
866 /* Should be lowered by do_lower_texture_projection */
867 assert(!ir
->projector
);
869 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
870 ctx
->Shader
.CurrentFragmentProgram
,
871 &brw
->fragment_program
->Base
);
872 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
874 /* The 965 requires the EU to do the normalization of GL rectangle
875 * texture coordinates. We use the program parameter state
876 * tracking to get the scaling factor.
878 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
879 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
880 int tokens
[STATE_LENGTH
] = {
888 if (c
->dispatch_width
== 16) {
889 fail("rectangle scale uniform setup not supported on 16-wide\n");
890 this->result
= fs_reg(this, ir
->type
);
894 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
896 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
899 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
900 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
901 GLuint index
= _mesa_add_state_reference(params
,
902 (gl_state_index
*)tokens
);
904 this->param_index
[c
->prog_data
.nr_params
] = index
;
905 this->param_offset
[c
->prog_data
.nr_params
] = 0;
906 c
->prog_data
.nr_params
++;
907 this->param_index
[c
->prog_data
.nr_params
] = index
;
908 this->param_offset
[c
->prog_data
.nr_params
] = 1;
909 c
->prog_data
.nr_params
++;
911 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
912 fs_reg src
= coordinate
;
915 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
918 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
921 /* Writemasking doesn't eliminate channels on SIMD8 texture
922 * samples, so don't worry about them.
924 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
926 if (intel
->gen
>= 7) {
927 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
928 } else if (intel
->gen
>= 5) {
929 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
931 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
934 /* If there's an offset, we already set up m1. To avoid the implied move,
935 * use the null register. Otherwise, we want an implied move from g0.
937 if (ir
->offset
!= NULL
|| !inst
->header_present
)
938 inst
->src
[0] = reg_undef
;
940 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
942 inst
->sampler
= sampler
;
946 if (ir
->shadow_comparitor
)
947 inst
->shadow_compare
= true;
949 if (ir
->type
== glsl_type::float_type
) {
950 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
951 assert(ir
->sampler
->type
->sampler_shadow
);
952 } else if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
953 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
955 for (int i
= 0; i
< 4; i
++) {
956 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
957 fs_reg l
= swizzle_dst
;
960 if (swiz
== SWIZZLE_ZERO
) {
961 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
962 } else if (swiz
== SWIZZLE_ONE
) {
963 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
966 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
967 emit(BRW_OPCODE_MOV
, l
, r
);
970 this->result
= swizzle_dst
;
975 fs_visitor::visit(ir_swizzle
*ir
)
977 this->result
= reg_undef
;
978 ir
->val
->accept(this);
979 fs_reg val
= this->result
;
981 if (ir
->type
->vector_elements
== 1) {
982 this->result
.reg_offset
+= ir
->mask
.x
;
986 fs_reg result
= fs_reg(this, ir
->type
);
987 this->result
= result
;
989 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
990 fs_reg channel
= val
;
1008 channel
.reg_offset
+= swiz
;
1009 emit(BRW_OPCODE_MOV
, result
, channel
);
1010 result
.reg_offset
++;
1015 fs_visitor::visit(ir_discard
*ir
)
1017 assert(ir
->condition
== NULL
); /* FINISHME */
1019 emit(FS_OPCODE_DISCARD
);
1020 kill_emitted
= true;
1024 fs_visitor::visit(ir_constant
*ir
)
1026 /* Set this->result to reg at the bottom of the function because some code
1027 * paths will cause this visitor to be applied to other fields. This will
1028 * cause the value stored in this->result to be modified.
1030 * Make reg constant so that it doesn't get accidentally modified along the
1031 * way. Yes, I actually had this problem. :(
1033 const fs_reg
reg(this, ir
->type
);
1034 fs_reg dst_reg
= reg
;
1036 if (ir
->type
->is_array()) {
1037 const unsigned size
= type_size(ir
->type
->fields
.array
);
1039 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1040 this->result
= reg_undef
;
1041 ir
->array_elements
[i
]->accept(this);
1042 fs_reg src_reg
= this->result
;
1044 dst_reg
.type
= src_reg
.type
;
1045 for (unsigned j
= 0; j
< size
; j
++) {
1046 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1047 src_reg
.reg_offset
++;
1048 dst_reg
.reg_offset
++;
1051 } else if (ir
->type
->is_record()) {
1052 foreach_list(node
, &ir
->components
) {
1053 ir_instruction
*const field
= (ir_instruction
*) node
;
1054 const unsigned size
= type_size(field
->type
);
1056 this->result
= reg_undef
;
1057 field
->accept(this);
1058 fs_reg src_reg
= this->result
;
1060 dst_reg
.type
= src_reg
.type
;
1061 for (unsigned j
= 0; j
< size
; j
++) {
1062 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1063 src_reg
.reg_offset
++;
1064 dst_reg
.reg_offset
++;
1068 const unsigned size
= type_size(ir
->type
);
1070 for (unsigned i
= 0; i
< size
; i
++) {
1071 switch (ir
->type
->base_type
) {
1072 case GLSL_TYPE_FLOAT
:
1073 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1075 case GLSL_TYPE_UINT
:
1076 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1079 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1081 case GLSL_TYPE_BOOL
:
1082 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1085 assert(!"Non-float/uint/int/bool constant");
1087 dst_reg
.reg_offset
++;
1095 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1097 ir_expression
*expr
= ir
->as_expression();
1103 assert(expr
->get_num_operands() <= 2);
1104 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1105 assert(expr
->operands
[i
]->type
->is_scalar());
1107 this->result
= reg_undef
;
1108 expr
->operands
[i
]->accept(this);
1109 op
[i
] = this->result
;
1112 switch (expr
->operation
) {
1113 case ir_unop_logic_not
:
1114 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1115 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1118 case ir_binop_logic_xor
:
1119 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1120 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1123 case ir_binop_logic_or
:
1124 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1125 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1128 case ir_binop_logic_and
:
1129 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1130 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1134 if (intel
->gen
>= 6) {
1135 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1137 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1139 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1143 if (intel
->gen
>= 6) {
1144 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1146 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1148 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1151 case ir_binop_greater
:
1152 case ir_binop_gequal
:
1154 case ir_binop_lequal
:
1155 case ir_binop_equal
:
1156 case ir_binop_all_equal
:
1157 case ir_binop_nequal
:
1158 case ir_binop_any_nequal
:
1159 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1160 inst
->conditional_mod
=
1161 brw_conditional_for_comparison(expr
->operation
);
1165 assert(!"not reached");
1166 fail("bad cond code\n");
1172 this->result
= reg_undef
;
1175 if (intel
->gen
>= 6) {
1176 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1177 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1179 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1180 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1185 * Emit a gen6 IF statement with the comparison folded into the IF
1189 fs_visitor::emit_if_gen6(ir_if
*ir
)
1191 ir_expression
*expr
= ir
->condition
->as_expression();
1198 assert(expr
->get_num_operands() <= 2);
1199 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1200 assert(expr
->operands
[i
]->type
->is_scalar());
1202 this->result
= reg_undef
;
1203 expr
->operands
[i
]->accept(this);
1204 op
[i
] = this->result
;
1207 switch (expr
->operation
) {
1208 case ir_unop_logic_not
:
1209 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1210 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1213 case ir_binop_logic_xor
:
1214 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1215 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1218 case ir_binop_logic_or
:
1219 temp
= fs_reg(this, glsl_type::bool_type
);
1220 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1221 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1222 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1225 case ir_binop_logic_and
:
1226 temp
= fs_reg(this, glsl_type::bool_type
);
1227 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1228 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1229 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1233 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1234 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1238 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1239 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1242 case ir_binop_greater
:
1243 case ir_binop_gequal
:
1245 case ir_binop_lequal
:
1246 case ir_binop_equal
:
1247 case ir_binop_all_equal
:
1248 case ir_binop_nequal
:
1249 case ir_binop_any_nequal
:
1250 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1251 inst
->conditional_mod
=
1252 brw_conditional_for_comparison(expr
->operation
);
1255 assert(!"not reached");
1256 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1257 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1258 fail("bad condition\n");
1264 this->result
= reg_undef
;
1265 ir
->condition
->accept(this);
1267 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1268 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1272 fs_visitor::visit(ir_if
*ir
)
1276 if (intel
->gen
!= 6 && c
->dispatch_width
== 16) {
1277 fail("Can't support (non-uniform) control flow on 16-wide\n");
1280 /* Don't point the annotation at the if statement, because then it plus
1281 * the then and else blocks get printed.
1283 this->base_ir
= ir
->condition
;
1285 if (intel
->gen
== 6) {
1288 emit_bool_to_cond_code(ir
->condition
);
1290 inst
= emit(BRW_OPCODE_IF
);
1291 inst
->predicated
= true;
1294 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1295 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1297 this->result
= reg_undef
;
1301 if (!ir
->else_instructions
.is_empty()) {
1302 emit(BRW_OPCODE_ELSE
);
1304 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1305 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1307 this->result
= reg_undef
;
1312 emit(BRW_OPCODE_ENDIF
);
1316 fs_visitor::visit(ir_loop
*ir
)
1318 fs_reg counter
= reg_undef
;
1320 if (c
->dispatch_width
== 16) {
1321 fail("Can't support (non-uniform) control flow on 16-wide\n");
1325 this->base_ir
= ir
->counter
;
1326 ir
->counter
->accept(this);
1327 counter
= *(variable_storage(ir
->counter
));
1330 this->result
= counter
;
1332 this->base_ir
= ir
->from
;
1333 this->result
= counter
;
1334 ir
->from
->accept(this);
1336 if (!this->result
.equals(&counter
))
1337 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1341 emit(BRW_OPCODE_DO
);
1344 this->base_ir
= ir
->to
;
1345 this->result
= reg_undef
;
1346 ir
->to
->accept(this);
1348 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1349 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1351 inst
= emit(BRW_OPCODE_BREAK
);
1352 inst
->predicated
= true;
1355 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1356 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1359 this->result
= reg_undef
;
1363 if (ir
->increment
) {
1364 this->base_ir
= ir
->increment
;
1365 this->result
= reg_undef
;
1366 ir
->increment
->accept(this);
1367 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1370 emit(BRW_OPCODE_WHILE
);
1374 fs_visitor::visit(ir_loop_jump
*ir
)
1377 case ir_loop_jump::jump_break
:
1378 emit(BRW_OPCODE_BREAK
);
1380 case ir_loop_jump::jump_continue
:
1381 emit(BRW_OPCODE_CONTINUE
);
1387 fs_visitor::visit(ir_call
*ir
)
1389 assert(!"FINISHME");
1393 fs_visitor::visit(ir_return
*ir
)
1395 assert(!"FINISHME");
1399 fs_visitor::visit(ir_function
*ir
)
1401 /* Ignore function bodies other than main() -- we shouldn't see calls to
1402 * them since they should all be inlined before we get to ir_to_mesa.
1404 if (strcmp(ir
->name
, "main") == 0) {
1405 const ir_function_signature
*sig
;
1408 sig
= ir
->matching_signature(&empty
);
1412 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1413 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1415 this->result
= reg_undef
;
1422 fs_visitor::visit(ir_function_signature
*ir
)
1424 assert(!"not reached");
1429 fs_visitor::emit(fs_inst inst
)
1431 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1434 if (force_uncompressed_stack
> 0)
1435 list_inst
->force_uncompressed
= true;
1436 else if (force_sechalf_stack
> 0)
1437 list_inst
->force_sechalf
= true;
1439 list_inst
->annotation
= this->current_annotation
;
1440 list_inst
->ir
= this->base_ir
;
1442 this->instructions
.push_tail(list_inst
);
1447 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1449 fs_visitor::emit_dummy_fs()
1451 /* Everyone's favorite color. */
1452 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1453 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1454 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1455 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1458 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1459 write
->base_mrf
= 0;
1462 /* The register location here is relative to the start of the URB
1463 * data. It will get adjusted to be a real location before
1464 * generate_code() time.
1467 fs_visitor::interp_reg(int location
, int channel
)
1469 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1470 int stride
= (channel
& 1) * 4;
1472 assert(urb_setup
[location
] != -1);
1474 return brw_vec1_grf(regnr
, stride
);
1477 /** Emits the interpolation for the varying inputs. */
1479 fs_visitor::emit_interpolation_setup_gen4()
1481 this->current_annotation
= "compute pixel centers";
1482 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1483 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1484 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1485 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1487 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1488 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1490 this->current_annotation
= "compute pixel deltas from v0";
1492 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1493 this->delta_y
= this->delta_x
;
1494 this->delta_y
.reg_offset
++;
1496 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1497 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1499 emit(BRW_OPCODE_ADD
, this->delta_x
,
1500 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1501 emit(BRW_OPCODE_ADD
, this->delta_y
,
1502 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1504 this->current_annotation
= "compute pos.w and 1/pos.w";
1505 /* Compute wpos.w. It's always in our setup, since it's needed to
1506 * interpolate the other attributes.
1508 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1509 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1510 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1511 /* Compute the pixel 1/W value from wpos.w. */
1512 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1513 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1514 this->current_annotation
= NULL
;
1517 /** Emits the interpolation for the varying inputs. */
1519 fs_visitor::emit_interpolation_setup_gen6()
1521 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1523 /* If the pixel centers end up used, the setup is the same as for gen4. */
1524 this->current_annotation
= "compute pixel centers";
1525 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1526 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1527 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1528 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1529 emit(BRW_OPCODE_ADD
,
1531 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1532 fs_reg(brw_imm_v(0x10101010)));
1533 emit(BRW_OPCODE_ADD
,
1535 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1536 fs_reg(brw_imm_v(0x11001100)));
1538 /* As of gen6, we can no longer mix float and int sources. We have
1539 * to turn the integer pixel centers into floats for their actual
1542 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1543 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1544 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1545 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1547 this->current_annotation
= "compute pos.w";
1548 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1549 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1550 emit_math(FS_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1552 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1553 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1555 this->current_annotation
= NULL
;
1559 fs_visitor::emit_color_write(int index
, int first_color_mrf
, fs_reg color
)
1561 int reg_width
= c
->dispatch_width
/ 8;
1563 if (c
->dispatch_width
== 8 || intel
->gen
== 6) {
1564 /* SIMD8 write looks like:
1570 * gen6 SIMD16 DP write looks like:
1580 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
* reg_width
),
1583 /* pre-gen6 SIMD16 single source DP write looks like:
1593 if (brw
->has_compr4
) {
1594 /* By setting the high bit of the MRF register number, we
1595 * indicate that we want COMPR4 mode - instead of doing the
1596 * usual destination + 1 for the second half we get
1599 emit(BRW_OPCODE_MOV
,
1600 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
), color
);
1602 push_force_uncompressed();
1603 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
), color
);
1604 pop_force_uncompressed();
1606 push_force_sechalf();
1607 color
.sechalf
= true;
1608 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4), color
);
1609 pop_force_sechalf();
1610 color
.sechalf
= false;
1616 fs_visitor::emit_fb_writes()
1618 this->current_annotation
= "FB write header";
1619 GLboolean header_present
= GL_TRUE
;
1621 int reg_width
= c
->dispatch_width
/ 8;
1623 if (intel
->gen
>= 6 &&
1624 !this->kill_emitted
&&
1625 c
->key
.nr_color_regions
== 1) {
1626 header_present
= false;
1629 if (header_present
) {
1634 if (c
->aa_dest_stencil_reg
) {
1635 push_force_uncompressed();
1636 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1637 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1638 pop_force_uncompressed();
1641 /* Reserve space for color. It'll be filled in per MRT below. */
1643 nr
+= 4 * reg_width
;
1645 if (c
->source_depth_to_render_target
) {
1646 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1647 /* For outputting oDepth on gen6, SIMD8 writes have to be
1648 * used. This would require 8-wide moves of each half to
1649 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1650 * Just bail on doing so for now.
1652 fail("Missing support for simd16 depth writes on gen6\n");
1655 if (c
->computes_depth
) {
1656 /* Hand over gl_FragDepth. */
1657 assert(this->frag_depth
);
1658 fs_reg depth
= *(variable_storage(this->frag_depth
));
1660 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1662 /* Pass through the payload depth. */
1663 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1664 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1669 if (c
->dest_depth_reg
) {
1670 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1671 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1675 fs_reg color
= reg_undef
;
1676 if (this->frag_color
)
1677 color
= *(variable_storage(this->frag_color
));
1678 else if (this->frag_data
) {
1679 color
= *(variable_storage(this->frag_data
));
1680 color
.type
= BRW_REGISTER_TYPE_F
;
1683 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1684 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1685 "FB write target %d",
1687 if (this->frag_color
|| this->frag_data
) {
1688 for (int i
= 0; i
< 4; i
++) {
1689 emit_color_write(i
, color_mrf
, color
);
1694 if (this->frag_color
)
1695 color
.reg_offset
-= 4;
1697 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1698 inst
->target
= target
;
1701 if (target
== c
->key
.nr_color_regions
- 1)
1703 inst
->header_present
= header_present
;
1706 if (c
->key
.nr_color_regions
== 0) {
1707 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
1708 /* If the alpha test is enabled but there's no color buffer,
1709 * we still need to send alpha out the pipeline to our null
1712 color
.reg_offset
+= 3;
1713 emit_color_write(3, color_mrf
, color
);
1716 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1720 inst
->header_present
= header_present
;
1723 this->current_annotation
= NULL
;