2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_shader_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_shader_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->is_in_uniform_block())
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
)
204 if (intel
->gen
< 6 || x
.file
!= GRF
|| y
.file
!= GRF
|| a
.file
!= GRF
) {
205 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
206 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
207 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
208 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
210 emit(MUL(y_times_a
, y
, a
));
212 a
.negate
= !a
.negate
;
213 emit(ADD(one_minus_a
, a
, fs_reg(1.0f
)));
214 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
216 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
218 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
219 * we need to reorder the operands.
221 emit(LRP(dst
, a
, y
, x
));
226 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
227 fs_reg src0
, fs_reg src1
)
231 if (intel
->gen
>= 6) {
232 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
233 inst
->conditional_mod
= conditionalmod
;
235 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
237 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
238 inst
->predicate
= BRW_PREDICATE_NORMAL
;
242 /* Instruction selection: Produce a MOV.sat instead of
243 * MIN(MAX(val, 0), 1) when possible.
246 fs_visitor::try_emit_saturate(ir_expression
*ir
)
248 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
253 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
255 sat_val
->accept(this);
256 fs_reg src
= this->result
;
258 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
260 /* If the last instruction from our accept() didn't generate our
261 * src, generate a saturated MOV
263 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
264 if (!modify
|| modify
->regs_written() != 1) {
265 this->result
= fs_reg(this, ir
->type
);
266 fs_inst
*inst
= emit(MOV(this->result
, src
));
267 inst
->saturate
= true;
269 modify
->saturate
= true;
278 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
280 /* 3-src instructions were introduced in gen6. */
284 /* MAD can only handle floating-point data. */
285 if (ir
->type
!= glsl_type::float_type
)
288 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
289 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
291 if (!mul
|| mul
->operation
!= ir_binop_mul
)
294 if (nonmul
->as_constant() ||
295 mul
->operands
[0]->as_constant() ||
296 mul
->operands
[1]->as_constant())
299 nonmul
->accept(this);
300 fs_reg src0
= this->result
;
302 mul
->operands
[0]->accept(this);
303 fs_reg src1
= this->result
;
305 mul
->operands
[1]->accept(this);
306 fs_reg src2
= this->result
;
308 this->result
= fs_reg(this, ir
->type
);
309 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
315 fs_visitor::visit(ir_expression
*ir
)
317 unsigned int operand
;
321 assert(ir
->get_num_operands() <= 3);
323 if (try_emit_saturate(ir
))
325 if (ir
->operation
== ir_binop_add
) {
326 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
330 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
331 ir
->operands
[operand
]->accept(this);
332 if (this->result
.file
== BAD_FILE
) {
334 fail("Failed to get tree for expression operand:\n");
335 ir
->operands
[operand
]->accept(&v
);
337 op
[operand
] = this->result
;
339 /* Matrix expression operands should have been broken down to vector
340 * operations already.
342 assert(!ir
->operands
[operand
]->type
->is_matrix());
343 /* And then those vector operands should have been broken down to scalar.
345 assert(!ir
->operands
[operand
]->type
->is_vector());
348 /* Storage for our result. If our result goes into an assignment, it will
349 * just get copy-propagated out, so no worries.
351 this->result
= fs_reg(this, ir
->type
);
353 switch (ir
->operation
) {
354 case ir_unop_logic_not
:
355 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
356 * ones complement of the whole register, not just bit 0.
358 emit(XOR(this->result
, op
[0], fs_reg(1)));
361 op
[0].negate
= !op
[0].negate
;
362 this->result
= op
[0];
366 op
[0].negate
= false;
367 this->result
= op
[0];
370 temp
= fs_reg(this, ir
->type
);
372 emit(MOV(this->result
, fs_reg(0.0f
)));
374 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
375 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
376 inst
->predicate
= BRW_PREDICATE_NORMAL
;
378 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
379 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
380 inst
->predicate
= BRW_PREDICATE_NORMAL
;
384 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
388 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
391 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
395 assert(!"not reached: should be handled by ir_explog_to_explog2");
398 case ir_unop_sin_reduced
:
399 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
402 case ir_unop_cos_reduced
:
403 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
407 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
410 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
414 emit(ADD(this->result
, op
[0], op
[1]));
417 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 if (ir
->type
->is_integer()) {
422 /* For integer multiplication, the MUL uses the low 16 bits
423 * of one of the operands (src0 on gen6, src1 on gen7). The
424 * MACH accumulates in the contribution of the upper 16 bits
427 * FINISHME: Emit just the MUL if we know an operand is small
430 if (intel
->gen
>= 7 && dispatch_width
== 16)
431 fail("16-wide explicit accumulator operands unsupported\n");
433 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
435 emit(MUL(acc
, op
[0], op
[1]));
436 emit(MACH(reg_null_d
, op
[0], op
[1]));
437 emit(MOV(this->result
, fs_reg(acc
)));
439 emit(MUL(this->result
, op
[0], op
[1]));
443 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
444 assert(ir
->type
->is_integer());
445 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
448 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
449 assert(ir
->type
->is_integer());
450 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
454 case ir_binop_greater
:
455 case ir_binop_lequal
:
456 case ir_binop_gequal
:
458 case ir_binop_all_equal
:
459 case ir_binop_nequal
:
460 case ir_binop_any_nequal
:
461 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
462 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
464 emit(CMP(this->result
, op
[0], op
[1],
465 brw_conditional_for_comparison(ir
->operation
)));
468 case ir_binop_logic_xor
:
469 emit(XOR(this->result
, op
[0], op
[1]));
472 case ir_binop_logic_or
:
473 emit(OR(this->result
, op
[0], op
[1]));
476 case ir_binop_logic_and
:
477 emit(AND(this->result
, op
[0], op
[1]));
482 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 assert(!"not reached: should be handled by lower_noise");
489 case ir_quadop_vector
:
490 assert(!"not reached: should be handled by lower_quadop_vector");
494 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
498 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
501 case ir_unop_bitcast_i2f
:
502 case ir_unop_bitcast_u2f
:
503 op
[0].type
= BRW_REGISTER_TYPE_F
;
504 this->result
= op
[0];
507 case ir_unop_bitcast_f2u
:
508 op
[0].type
= BRW_REGISTER_TYPE_UD
;
509 this->result
= op
[0];
512 case ir_unop_bitcast_f2i
:
513 op
[0].type
= BRW_REGISTER_TYPE_D
;
514 this->result
= op
[0];
520 emit(MOV(this->result
, op
[0]));
524 inst
= emit(AND(this->result
, op
[0], fs_reg(1)));
527 temp
= fs_reg(this, glsl_type::int_type
);
528 emit(AND(temp
, op
[0], fs_reg(1)));
529 emit(MOV(this->result
, temp
));
533 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
536 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
540 emit(RNDZ(this->result
, op
[0]));
543 op
[0].negate
= !op
[0].negate
;
544 inst
= emit(RNDD(this->result
, op
[0]));
545 this->result
.negate
= true;
548 inst
= emit(RNDD(this->result
, op
[0]));
551 inst
= emit(FRC(this->result
, op
[0]));
553 case ir_unop_round_even
:
554 emit(RNDE(this->result
, op
[0]));
559 resolve_ud_negate(&op
[0]);
560 resolve_ud_negate(&op
[1]);
561 emit_minmax(ir
->operation
== ir_binop_min
?
562 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
563 this->result
, op
[0], op
[1]);
565 case ir_unop_pack_snorm_2x16
:
566 case ir_unop_pack_snorm_4x8
:
567 case ir_unop_pack_unorm_2x16
:
568 case ir_unop_pack_unorm_4x8
:
569 case ir_unop_unpack_snorm_2x16
:
570 case ir_unop_unpack_snorm_4x8
:
571 case ir_unop_unpack_unorm_2x16
:
572 case ir_unop_unpack_unorm_4x8
:
573 case ir_unop_unpack_half_2x16
:
574 case ir_unop_pack_half_2x16
:
575 assert(!"not reached: should be handled by lower_packing_builtins");
577 case ir_unop_unpack_half_2x16_split_x
:
578 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
580 case ir_unop_unpack_half_2x16_split_y
:
581 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
584 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
587 case ir_unop_bit_not
:
588 inst
= emit(NOT(this->result
, op
[0]));
590 case ir_binop_bit_and
:
591 inst
= emit(AND(this->result
, op
[0], op
[1]));
593 case ir_binop_bit_xor
:
594 inst
= emit(XOR(this->result
, op
[0], op
[1]));
596 case ir_binop_bit_or
:
597 inst
= emit(OR(this->result
, op
[0], op
[1]));
600 case ir_binop_lshift
:
601 inst
= emit(SHL(this->result
, op
[0], op
[1]));
604 case ir_binop_rshift
:
605 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
606 inst
= emit(ASR(this->result
, op
[0], op
[1]));
608 inst
= emit(SHR(this->result
, op
[0], op
[1]));
610 case ir_binop_pack_half_2x16_split
:
611 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
613 case ir_binop_ubo_load
: {
614 /* This IR node takes a constant uniform block and a constant or
615 * variable byte offset within the block and loads a vector from that.
617 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
618 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
619 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
621 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
622 packed_consts
.type
= result
.type
;
624 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
625 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
626 packed_consts
, surf_index
, const_offset_reg
));
628 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
629 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
630 /* UBO bools are any nonzero value. We consider bools to be
631 * values with the low bit set to 1. Convert them using CMP.
633 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
634 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
636 emit(MOV(result
, packed_consts
));
639 packed_consts
.smear
++;
642 /* The std140 packing rules don't allow vectors to cross 16-byte
643 * boundaries, and a reg is 32 bytes.
645 assert(packed_consts
.smear
< 8);
648 /* Turn the byte offset into a dword offset. */
649 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
650 emit(SHR(base_offset
, op
[1], fs_reg(2)));
652 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
653 fs_reg offset
= fs_reg(this, glsl_type::int_type
);
654 emit(ADD(offset
, base_offset
, fs_reg(i
)));
655 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
, offset
));
657 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
658 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
664 result
.reg_offset
= 0;
669 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
675 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
676 const glsl_type
*type
, bool predicated
)
678 switch (type
->base_type
) {
679 case GLSL_TYPE_FLOAT
:
683 for (unsigned int i
= 0; i
< type
->components(); i
++) {
684 l
.type
= brw_type_for_base_type(type
);
685 r
.type
= brw_type_for_base_type(type
);
687 if (predicated
|| !l
.equals(r
)) {
688 fs_inst
*inst
= emit(MOV(l
, r
));
689 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
696 case GLSL_TYPE_ARRAY
:
697 for (unsigned int i
= 0; i
< type
->length
; i
++) {
698 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
702 case GLSL_TYPE_STRUCT
:
703 for (unsigned int i
= 0; i
< type
->length
; i
++) {
704 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
709 case GLSL_TYPE_SAMPLER
:
713 case GLSL_TYPE_ERROR
:
714 case GLSL_TYPE_INTERFACE
:
715 assert(!"not reached");
720 /* If the RHS processing resulted in an instruction generating a
721 * temporary value, and it would be easy to rewrite the instruction to
722 * generate its result right into the LHS instead, do so. This ends
723 * up reliably removing instructions where it can be tricky to do so
724 * later without real UD chain information.
727 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
730 fs_inst
*pre_rhs_inst
,
731 fs_inst
*last_rhs_inst
)
733 /* Only attempt if we're doing a direct assignment. */
735 !(ir
->lhs
->type
->is_scalar() ||
736 (ir
->lhs
->type
->is_vector() &&
737 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
740 /* Make sure the last instruction generated our source reg. */
741 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
747 /* If last_rhs_inst wrote a different number of components than our LHS,
748 * we can't safely rewrite it.
750 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written())
753 /* Success! Rewrite the instruction. */
760 fs_visitor::visit(ir_assignment
*ir
)
765 /* FINISHME: arrays on the lhs */
766 ir
->lhs
->accept(this);
769 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
771 ir
->rhs
->accept(this);
774 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
776 assert(l
.file
!= BAD_FILE
);
777 assert(r
.file
!= BAD_FILE
);
779 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
783 emit_bool_to_cond_code(ir
->condition
);
786 if (ir
->lhs
->type
->is_scalar() ||
787 ir
->lhs
->type
->is_vector()) {
788 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
789 if (ir
->write_mask
& (1 << i
)) {
790 inst
= emit(MOV(l
, r
));
792 inst
->predicate
= BRW_PREDICATE_NORMAL
;
798 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
803 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
804 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
814 if (ir
->shadow_comparitor
) {
815 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
816 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
817 coordinate
.reg_offset
++;
819 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
822 if (ir
->op
== ir_tex
) {
823 /* There's no plain shadow compare message, so we use shadow
824 * compare with a bias of 0.0.
826 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
828 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
829 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
832 assert(!"Should not get here.");
835 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
837 } else if (ir
->op
== ir_tex
) {
838 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
839 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
840 coordinate
.reg_offset
++;
842 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
844 } else if (ir
->op
== ir_txd
) {
847 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
848 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
849 coordinate
.reg_offset
++;
851 /* the slots for u and v are always present, but r is optional */
852 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
855 * dPdx = dudx, dvdx, drdx
856 * dPdy = dudy, dvdy, drdy
858 * 1-arg: Does not exist.
860 * 2-arg: dudx dvdx dudy dvdy
861 * dPdx.x dPdx.y dPdy.x dPdy.y
864 * 3-arg: dudx dvdx drdx dudy dvdy drdy
865 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
868 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
869 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
872 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
874 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
875 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
878 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
879 } else if (ir
->op
== ir_txs
) {
880 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
882 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
885 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
886 * instructions. We'll need to do SIMD16 here.
889 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
891 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
892 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
894 coordinate
.reg_offset
++;
897 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
898 * be necessary for TXF (ld), but seems wise to do for all messages.
900 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
901 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
904 /* lod/bias appears after u/v/r. */
907 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
910 /* The unused upper half. */
915 /* Now, since we're doing simd16, the return is 2 interleaved
916 * vec4s where the odd-indexed ones are junk. We'll need to move
917 * this weirdness around to the expected layout.
920 const glsl_type
*vec_type
=
921 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
922 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
923 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
924 : BRW_REGISTER_TYPE_F
;
927 fs_inst
*inst
= NULL
;
930 inst
= emit(SHADER_OPCODE_TEX
, dst
);
933 inst
= emit(FS_OPCODE_TXB
, dst
);
936 inst
= emit(SHADER_OPCODE_TXL
, dst
);
939 inst
= emit(SHADER_OPCODE_TXD
, dst
);
942 inst
= emit(SHADER_OPCODE_TXS
, dst
);
945 inst
= emit(SHADER_OPCODE_TXF
, dst
);
948 fail("unrecognized texture opcode");
950 inst
->base_mrf
= base_mrf
;
952 inst
->header_present
= true;
955 for (int i
= 0; i
< 4; i
++) {
956 emit(MOV(orig_dst
, dst
));
957 orig_dst
.reg_offset
++;
965 /* gen5's sampler has slots for u, v, r, array index, then optional
966 * parameters like shadow comparitor or LOD bias. If optional
967 * parameters aren't present, those base slots are optional and don't
968 * need to be included in the message.
970 * We don't fill in the unnecessary slots regardless, which may look
971 * surprising in the disassembly.
974 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
975 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
980 int reg_width
= dispatch_width
/ 8;
981 bool header_present
= false;
982 const int vector_elements
=
983 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
985 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
986 /* It appears that the ld instruction used for txf does its
987 * address bounds check before adding in the offset. To work
988 * around this, just add the integer offset to the integer texel
989 * coordinate, and don't put the offset in the header.
991 ir_constant
*offset
= ir
->offset
->as_constant();
992 for (int i
= 0; i
< vector_elements
; i
++) {
993 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
995 offset
->value
.i
[i
]));
996 coordinate
.reg_offset
++;
1000 /* The offsets set up by the ir_texture visitor are in the
1001 * m1 header, so we can't go headerless.
1003 header_present
= true;
1008 for (int i
= 0; i
< vector_elements
; i
++) {
1009 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
1011 coordinate
.reg_offset
++;
1014 mlen
+= vector_elements
* reg_width
;
1016 if (ir
->shadow_comparitor
) {
1017 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1019 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1023 fs_inst
*inst
= NULL
;
1026 inst
= emit(SHADER_OPCODE_TEX
, dst
);
1029 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1030 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1033 inst
= emit(FS_OPCODE_TXB
, dst
);
1036 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1037 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1040 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1043 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1047 * dPdx = dudx, dvdx, drdx
1048 * dPdy = dudy, dvdy, drdy
1050 * Load up these values:
1051 * - dudx dudy dvdx dvdy drdx drdy
1052 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1054 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1055 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1059 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1064 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1068 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1070 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1073 mlen
= header_present
+ 4 * reg_width
;
1074 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), lod
));
1075 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1078 mlen
= header_present
+ 4 * reg_width
;
1081 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
), fs_reg(0)));
1083 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1085 inst
= emit(SHADER_OPCODE_TXF_MS
, dst
);
1088 inst
->base_mrf
= base_mrf
;
1090 inst
->header_present
= header_present
;
1093 fail("Message length >11 disallowed by hardware\n");
1100 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1101 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
,
1102 fs_reg sample_index
)
1106 int reg_width
= dispatch_width
/ 8;
1107 bool header_present
= false;
1110 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1111 /* The offsets set up by the ir_texture visitor are in the
1112 * m1 header, so we can't go headerless.
1114 header_present
= true;
1119 if (ir
->shadow_comparitor
) {
1120 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1124 /* Set up the LOD info */
1129 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1133 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1137 if (dispatch_width
== 16)
1138 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1140 /* Load dPdx and the coordinate together:
1141 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1143 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1144 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1145 coordinate
.reg_offset
++;
1148 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1149 * only derivatives for (u, v, r).
1151 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1152 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1156 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1164 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1168 /* It appears that the ld instruction used for txf does its
1169 * address bounds check before adding in the offset. To work
1170 * around this, just add the integer offset to the integer texel
1171 * coordinate, and don't put the offset in the header.
1174 ir_constant
*offset
= ir
->offset
->as_constant();
1175 offsets
[0] = offset
->value
.i
[0];
1176 offsets
[1] = offset
->value
.i
[1];
1177 offsets
[2] = offset
->value
.i
[2];
1179 memset(offsets
, 0, sizeof(offsets
));
1182 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1183 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1184 coordinate
, offsets
[0]));
1185 coordinate
.reg_offset
++;
1188 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1191 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1192 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1193 coordinate
, offsets
[i
]));
1194 coordinate
.reg_offset
++;
1199 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), sample_index
));
1202 /* constant zero MCS; we arrange to never actually have a compressed
1203 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1204 * if we ever support texturing from compressed multisample surfaces
1206 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1209 /* there is no offsetting for this message; just copy in the integer
1210 * texture coordinates
1212 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1213 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1215 coordinate
.reg_offset
++;
1221 /* Set up the coordinate (except for cases where it was done above) */
1222 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
&& ir
->op
!= ir_txf_ms
) {
1223 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1224 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1225 coordinate
.reg_offset
++;
1230 /* Generate the SEND */
1231 fs_inst
*inst
= NULL
;
1233 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1234 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1235 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1236 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1237 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1238 case ir_txf_ms
: inst
= emit(SHADER_OPCODE_TXF_MS
, dst
); break;
1239 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1241 inst
->base_mrf
= base_mrf
;
1243 inst
->header_present
= header_present
;
1246 fail("Message length >11 disallowed by hardware\n");
1253 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1254 bool is_rect
, int sampler
, int texunit
)
1256 fs_inst
*inst
= NULL
;
1257 bool needs_gl_clamp
= true;
1258 fs_reg scale_x
, scale_y
;
1260 /* The 965 requires the EU to do the normalization of GL rectangle
1261 * texture coordinates. We use the program parameter state
1262 * tracking to get the scaling factor.
1266 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1267 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1268 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1269 int tokens
[STATE_LENGTH
] = {
1271 STATE_TEXRECT_SCALE
,
1277 if (dispatch_width
== 16) {
1278 fail("rectangle scale uniform setup not supported on 16-wide\n");
1282 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1283 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1285 GLuint index
= _mesa_add_state_reference(params
,
1286 (gl_state_index
*)tokens
);
1287 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1288 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1289 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1290 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1293 /* The 965 requires the EU to do the normalization of GL rectangle
1294 * texture coordinates. We use the program parameter state
1295 * tracking to get the scaling factor.
1297 if (intel
->gen
< 6 && is_rect
) {
1298 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1299 fs_reg src
= coordinate
;
1302 emit(MUL(dst
, src
, scale_x
));
1305 emit(MUL(dst
, src
, scale_y
));
1306 } else if (is_rect
) {
1307 /* On gen6+, the sampler handles the rectangle coordinates
1308 * natively, without needing rescaling. But that means we have
1309 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1310 * not [0, 1] like the default case below.
1312 needs_gl_clamp
= false;
1314 for (int i
= 0; i
< 2; i
++) {
1315 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1316 fs_reg chan
= coordinate
;
1317 chan
.reg_offset
+= i
;
1319 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1320 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1322 /* Our parameter comes in as 1.0/width or 1.0/height,
1323 * because that's what people normally want for doing
1324 * texture rectangle handling. We need width or height
1325 * for clamping, but we don't care enough to make a new
1326 * parameter type, so just invert back.
1328 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1329 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1330 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1332 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1333 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1338 if (ir
->coordinate
&& needs_gl_clamp
) {
1339 for (unsigned int i
= 0;
1340 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1341 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1342 fs_reg chan
= coordinate
;
1343 chan
.reg_offset
+= i
;
1345 fs_inst
*inst
= emit(MOV(chan
, chan
));
1346 inst
->saturate
= true;
1354 fs_visitor::visit(ir_texture
*ir
)
1356 fs_inst
*inst
= NULL
;
1358 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1359 /* FINISHME: We're failing to recompile our programs when the sampler is
1360 * updated. This only matters for the texture rectangle scale parameters
1361 * (pre-gen6, or gen6+ with GL_CLAMP).
1363 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1365 /* Should be lowered by do_lower_texture_projection */
1366 assert(!ir
->projector
);
1368 /* Generate code to compute all the subexpression trees. This has to be
1369 * done before loading any values into MRFs for the sampler message since
1370 * generating these values may involve SEND messages that need the MRFs.
1373 if (ir
->coordinate
) {
1374 ir
->coordinate
->accept(this);
1376 coordinate
= rescale_texcoord(ir
, this->result
,
1377 ir
->sampler
->type
->sampler_dimensionality
==
1378 GLSL_SAMPLER_DIM_RECT
,
1382 fs_reg shadow_comparitor
;
1383 if (ir
->shadow_comparitor
) {
1384 ir
->shadow_comparitor
->accept(this);
1385 shadow_comparitor
= this->result
;
1388 fs_reg lod
, lod2
, sample_index
;
1393 ir
->lod_info
.bias
->accept(this);
1397 ir
->lod_info
.grad
.dPdx
->accept(this);
1400 ir
->lod_info
.grad
.dPdy
->accept(this);
1401 lod2
= this->result
;
1406 ir
->lod_info
.lod
->accept(this);
1410 ir
->lod_info
.sample_index
->accept(this);
1411 sample_index
= this->result
;
1415 /* Writemasking doesn't eliminate channels on SIMD8 texture
1416 * samples, so don't worry about them.
1418 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1420 if (intel
->gen
>= 7) {
1421 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1422 lod
, lod2
, sample_index
);
1423 } else if (intel
->gen
>= 5) {
1424 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1425 lod
, lod2
, sample_index
);
1427 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1431 /* The header is set up by generate_tex() when necessary. */
1432 inst
->src
[0] = reg_undef
;
1434 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1435 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1437 inst
->sampler
= sampler
;
1439 if (ir
->shadow_comparitor
)
1440 inst
->shadow_compare
= true;
1442 /* fixup #layers for cube map arrays */
1443 if (ir
->op
== ir_txs
) {
1444 glsl_type
const *type
= ir
->sampler
->type
;
1445 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1446 type
->sampler_array
) {
1448 depth
.reg_offset
= 2;
1449 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1453 swizzle_result(ir
, dst
, sampler
);
1457 * Swizzle the result of a texture result. This is necessary for
1458 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1461 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1463 this->result
= orig_val
;
1465 if (ir
->op
== ir_txs
)
1468 if (ir
->type
== glsl_type::float_type
) {
1469 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1470 assert(ir
->sampler
->type
->sampler_shadow
);
1471 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1472 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1474 for (int i
= 0; i
< 4; i
++) {
1475 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1476 fs_reg l
= swizzled_result
;
1479 if (swiz
== SWIZZLE_ZERO
) {
1480 emit(MOV(l
, fs_reg(0.0f
)));
1481 } else if (swiz
== SWIZZLE_ONE
) {
1482 emit(MOV(l
, fs_reg(1.0f
)));
1484 fs_reg r
= orig_val
;
1485 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1489 this->result
= swizzled_result
;
1494 fs_visitor::visit(ir_swizzle
*ir
)
1496 ir
->val
->accept(this);
1497 fs_reg val
= this->result
;
1499 if (ir
->type
->vector_elements
== 1) {
1500 this->result
.reg_offset
+= ir
->mask
.x
;
1504 fs_reg result
= fs_reg(this, ir
->type
);
1505 this->result
= result
;
1507 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1508 fs_reg channel
= val
;
1526 channel
.reg_offset
+= swiz
;
1527 emit(MOV(result
, channel
));
1528 result
.reg_offset
++;
1533 fs_visitor::visit(ir_discard
*ir
)
1535 assert(ir
->condition
== NULL
); /* FINISHME */
1537 /* We track our discarded pixels in f0.1. By predicating on it, we can
1538 * update just the flag bits that aren't yet discarded. By emitting a
1539 * CMP of g0 != g0, all our currently executing channels will get turned
1542 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1543 BRW_REGISTER_TYPE_UW
));
1544 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1545 BRW_CONDITIONAL_NZ
));
1546 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1547 cmp
->flag_subreg
= 1;
1549 if (intel
->gen
>= 6) {
1550 /* For performance, after a discard, jump to the end of the shader.
1551 * However, many people will do foliage by discarding based on a
1552 * texture's alpha mask, and then continue on to texture with the
1553 * remaining pixels. To avoid trashing the derivatives for those
1554 * texture samples, we'll only jump if all of the pixels in the subspan
1555 * have been discarded.
1557 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1558 discard_jump
->flag_subreg
= 1;
1559 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1560 discard_jump
->predicate_inverse
= true;
1565 fs_visitor::visit(ir_constant
*ir
)
1567 /* Set this->result to reg at the bottom of the function because some code
1568 * paths will cause this visitor to be applied to other fields. This will
1569 * cause the value stored in this->result to be modified.
1571 * Make reg constant so that it doesn't get accidentally modified along the
1572 * way. Yes, I actually had this problem. :(
1574 const fs_reg
reg(this, ir
->type
);
1575 fs_reg dst_reg
= reg
;
1577 if (ir
->type
->is_array()) {
1578 const unsigned size
= type_size(ir
->type
->fields
.array
);
1580 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1581 ir
->array_elements
[i
]->accept(this);
1582 fs_reg src_reg
= this->result
;
1584 dst_reg
.type
= src_reg
.type
;
1585 for (unsigned j
= 0; j
< size
; j
++) {
1586 emit(MOV(dst_reg
, src_reg
));
1587 src_reg
.reg_offset
++;
1588 dst_reg
.reg_offset
++;
1591 } else if (ir
->type
->is_record()) {
1592 foreach_list(node
, &ir
->components
) {
1593 ir_constant
*const field
= (ir_constant
*) node
;
1594 const unsigned size
= type_size(field
->type
);
1596 field
->accept(this);
1597 fs_reg src_reg
= this->result
;
1599 dst_reg
.type
= src_reg
.type
;
1600 for (unsigned j
= 0; j
< size
; j
++) {
1601 emit(MOV(dst_reg
, src_reg
));
1602 src_reg
.reg_offset
++;
1603 dst_reg
.reg_offset
++;
1607 const unsigned size
= type_size(ir
->type
);
1609 for (unsigned i
= 0; i
< size
; i
++) {
1610 switch (ir
->type
->base_type
) {
1611 case GLSL_TYPE_FLOAT
:
1612 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1614 case GLSL_TYPE_UINT
:
1615 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1618 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1620 case GLSL_TYPE_BOOL
:
1621 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1624 assert(!"Non-float/uint/int/bool constant");
1626 dst_reg
.reg_offset
++;
1634 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1636 ir_expression
*expr
= ir
->as_expression();
1642 assert(expr
->get_num_operands() <= 2);
1643 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1644 assert(expr
->operands
[i
]->type
->is_scalar());
1646 expr
->operands
[i
]->accept(this);
1647 op
[i
] = this->result
;
1649 resolve_ud_negate(&op
[i
]);
1652 switch (expr
->operation
) {
1653 case ir_unop_logic_not
:
1654 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1655 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1658 case ir_binop_logic_xor
:
1659 case ir_binop_logic_or
:
1660 case ir_binop_logic_and
:
1664 if (intel
->gen
>= 6) {
1665 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1667 inst
= emit(MOV(reg_null_f
, op
[0]));
1668 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1673 if (intel
->gen
>= 6) {
1674 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1676 inst
= emit(MOV(reg_null_d
, op
[0]));
1677 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1681 case ir_binop_greater
:
1682 case ir_binop_gequal
:
1684 case ir_binop_lequal
:
1685 case ir_binop_equal
:
1686 case ir_binop_all_equal
:
1687 case ir_binop_nequal
:
1688 case ir_binop_any_nequal
:
1689 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1690 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1692 emit(CMP(reg_null_d
, op
[0], op
[1],
1693 brw_conditional_for_comparison(expr
->operation
)));
1697 assert(!"not reached");
1698 fail("bad cond code\n");
1707 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1708 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1712 * Emit a gen6 IF statement with the comparison folded into the IF
1716 fs_visitor::emit_if_gen6(ir_if
*ir
)
1718 ir_expression
*expr
= ir
->condition
->as_expression();
1725 assert(expr
->get_num_operands() <= 2);
1726 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1727 assert(expr
->operands
[i
]->type
->is_scalar());
1729 expr
->operands
[i
]->accept(this);
1730 op
[i
] = this->result
;
1733 switch (expr
->operation
) {
1734 case ir_unop_logic_not
:
1735 case ir_binop_logic_xor
:
1736 case ir_binop_logic_or
:
1737 case ir_binop_logic_and
:
1738 /* For operations on bool arguments, only the low bit of the bool is
1739 * valid, and the others are undefined. Fall back to the condition
1745 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1746 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1750 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1753 case ir_binop_greater
:
1754 case ir_binop_gequal
:
1756 case ir_binop_lequal
:
1757 case ir_binop_equal
:
1758 case ir_binop_all_equal
:
1759 case ir_binop_nequal
:
1760 case ir_binop_any_nequal
:
1761 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1762 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1764 emit(IF(op
[0], op
[1],
1765 brw_conditional_for_comparison(expr
->operation
)));
1768 assert(!"not reached");
1769 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1770 fail("bad condition\n");
1775 emit_bool_to_cond_code(ir
->condition
);
1776 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1777 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1781 fs_visitor::visit(ir_if
*ir
)
1783 if (intel
->gen
< 6 && dispatch_width
== 16) {
1784 fail("Can't support (non-uniform) control flow on 16-wide\n");
1787 /* Don't point the annotation at the if statement, because then it plus
1788 * the then and else blocks get printed.
1790 this->base_ir
= ir
->condition
;
1792 if (intel
->gen
== 6) {
1795 emit_bool_to_cond_code(ir
->condition
);
1797 emit(IF(BRW_PREDICATE_NORMAL
));
1800 foreach_list(node
, &ir
->then_instructions
) {
1801 ir_instruction
*ir
= (ir_instruction
*)node
;
1807 if (!ir
->else_instructions
.is_empty()) {
1808 emit(BRW_OPCODE_ELSE
);
1810 foreach_list(node
, &ir
->else_instructions
) {
1811 ir_instruction
*ir
= (ir_instruction
*)node
;
1818 emit(BRW_OPCODE_ENDIF
);
1822 fs_visitor::visit(ir_loop
*ir
)
1824 fs_reg counter
= reg_undef
;
1826 if (intel
->gen
< 6 && dispatch_width
== 16) {
1827 fail("Can't support (non-uniform) control flow on 16-wide\n");
1831 this->base_ir
= ir
->counter
;
1832 ir
->counter
->accept(this);
1833 counter
= *(variable_storage(ir
->counter
));
1836 this->base_ir
= ir
->from
;
1837 ir
->from
->accept(this);
1839 emit(MOV(counter
, this->result
));
1843 this->base_ir
= NULL
;
1844 emit(BRW_OPCODE_DO
);
1847 this->base_ir
= ir
->to
;
1848 ir
->to
->accept(this);
1850 emit(CMP(reg_null_d
, counter
, this->result
,
1851 brw_conditional_for_comparison(ir
->cmp
)));
1853 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1854 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1857 foreach_list(node
, &ir
->body_instructions
) {
1858 ir_instruction
*ir
= (ir_instruction
*)node
;
1864 if (ir
->increment
) {
1865 this->base_ir
= ir
->increment
;
1866 ir
->increment
->accept(this);
1867 emit(ADD(counter
, counter
, this->result
));
1870 this->base_ir
= NULL
;
1871 emit(BRW_OPCODE_WHILE
);
1875 fs_visitor::visit(ir_loop_jump
*ir
)
1878 case ir_loop_jump::jump_break
:
1879 emit(BRW_OPCODE_BREAK
);
1881 case ir_loop_jump::jump_continue
:
1882 emit(BRW_OPCODE_CONTINUE
);
1888 fs_visitor::visit(ir_call
*ir
)
1890 assert(!"FINISHME");
1894 fs_visitor::visit(ir_return
*ir
)
1896 assert(!"FINISHME");
1900 fs_visitor::visit(ir_function
*ir
)
1902 /* Ignore function bodies other than main() -- we shouldn't see calls to
1903 * them since they should all be inlined before we get to ir_to_mesa.
1905 if (strcmp(ir
->name
, "main") == 0) {
1906 const ir_function_signature
*sig
;
1909 sig
= ir
->matching_signature(&empty
);
1913 foreach_list(node
, &sig
->body
) {
1914 ir_instruction
*ir
= (ir_instruction
*)node
;
1923 fs_visitor::visit(ir_function_signature
*ir
)
1925 assert(!"not reached");
1930 fs_visitor::emit(fs_inst inst
)
1932 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1939 fs_visitor::emit(fs_inst
*inst
)
1941 if (force_uncompressed_stack
> 0)
1942 inst
->force_uncompressed
= true;
1943 else if (force_sechalf_stack
> 0)
1944 inst
->force_sechalf
= true;
1946 inst
->annotation
= this->current_annotation
;
1947 inst
->ir
= this->base_ir
;
1949 this->instructions
.push_tail(inst
);
1955 fs_visitor::emit(exec_list list
)
1957 foreach_list_safe(node
, &list
) {
1958 fs_inst
*inst
= (fs_inst
*)node
;
1964 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1966 fs_visitor::emit_dummy_fs()
1968 int reg_width
= dispatch_width
/ 8;
1970 /* Everyone's favorite color. */
1971 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
1972 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
1973 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
1974 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
1977 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1978 write
->base_mrf
= 2;
1979 write
->mlen
= 4 * reg_width
;
1983 /* The register location here is relative to the start of the URB
1984 * data. It will get adjusted to be a real location before
1985 * generate_code() time.
1988 fs_visitor::interp_reg(int location
, int channel
)
1990 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1991 int stride
= (channel
& 1) * 4;
1993 assert(urb_setup
[location
] != -1);
1995 return brw_vec1_grf(regnr
, stride
);
1998 /** Emits the interpolation for the varying inputs. */
2000 fs_visitor::emit_interpolation_setup_gen4()
2002 this->current_annotation
= "compute pixel centers";
2003 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2004 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2005 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2006 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2008 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
2009 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
2011 this->current_annotation
= "compute pixel deltas from v0";
2013 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2014 fs_reg(this, glsl_type::vec2_type
);
2015 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2016 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
2017 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
2019 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2020 fs_reg(this, glsl_type::float_type
);
2021 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
2022 fs_reg(this, glsl_type::float_type
);
2024 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2025 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
2026 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2027 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
2029 this->current_annotation
= "compute pos.w and 1/pos.w";
2030 /* Compute wpos.w. It's always in our setup, since it's needed to
2031 * interpolate the other attributes.
2033 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2034 emit(FS_OPCODE_LINTERP
, wpos_w
,
2035 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2036 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
2037 interp_reg(VARYING_SLOT_POS
, 3));
2038 /* Compute the pixel 1/W value from wpos.w. */
2039 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2040 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2041 this->current_annotation
= NULL
;
2044 /** Emits the interpolation for the varying inputs. */
2046 fs_visitor::emit_interpolation_setup_gen6()
2048 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2050 /* If the pixel centers end up used, the setup is the same as for gen4. */
2051 this->current_annotation
= "compute pixel centers";
2052 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2053 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2054 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2055 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2056 emit(ADD(int_pixel_x
,
2057 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2058 fs_reg(brw_imm_v(0x10101010))));
2059 emit(ADD(int_pixel_y
,
2060 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2061 fs_reg(brw_imm_v(0x11001100))));
2063 /* As of gen6, we can no longer mix float and int sources. We have
2064 * to turn the integer pixel centers into floats for their actual
2067 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2068 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2069 emit(MOV(this->pixel_x
, int_pixel_x
));
2070 emit(MOV(this->pixel_y
, int_pixel_y
));
2072 this->current_annotation
= "compute pos.w";
2073 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2074 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2075 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2077 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2078 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2079 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2080 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2083 this->current_annotation
= NULL
;
2087 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2089 int reg_width
= dispatch_width
/ 8;
2091 fs_reg color
= outputs
[target
];
2094 /* If there's no color data to be written, skip it. */
2095 if (color
.file
== BAD_FILE
)
2098 color
.reg_offset
+= index
;
2100 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2101 /* SIMD8 write looks like:
2107 * gen6 SIMD16 DP write looks like:
2117 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2120 inst
->saturate
= c
->key
.clamp_fragment_color
;
2122 /* pre-gen6 SIMD16 single source DP write looks like:
2132 if (brw
->has_compr4
) {
2133 /* By setting the high bit of the MRF register number, we
2134 * indicate that we want COMPR4 mode - instead of doing the
2135 * usual destination + 1 for the second half we get
2138 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2141 inst
->saturate
= c
->key
.clamp_fragment_color
;
2143 push_force_uncompressed();
2144 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2146 inst
->saturate
= c
->key
.clamp_fragment_color
;
2147 pop_force_uncompressed();
2149 push_force_sechalf();
2150 color
.sechalf
= true;
2151 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2153 inst
->saturate
= c
->key
.clamp_fragment_color
;
2154 pop_force_sechalf();
2155 color
.sechalf
= false;
2161 fs_visitor::emit_fb_writes()
2163 this->current_annotation
= "FB write header";
2164 bool header_present
= true;
2165 /* We can potentially have a message length of up to 15, so we have to set
2166 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2170 int reg_width
= dispatch_width
/ 8;
2171 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2172 bool src0_alpha_to_render_target
= false;
2174 if (dispatch_width
== 16 && do_dual_src
) {
2175 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2176 do_dual_src
= false;
2179 /* From the Sandy Bridge PRM, volume 4, page 198:
2181 * "Dispatched Pixel Enables. One bit per pixel indicating
2182 * which pixels were originally enabled when the thread was
2183 * dispatched. This field is only required for the end-of-
2184 * thread message and on all dual-source messages."
2186 if (intel
->gen
>= 6 &&
2187 !this->fp
->UsesKill
&&
2189 c
->key
.nr_color_regions
== 1) {
2190 header_present
= false;
2193 if (header_present
) {
2194 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2196 c
->key
.nr_color_regions
> 1 &&
2197 c
->key
.sample_alpha_to_coverage
;
2202 if (c
->aa_dest_stencil_reg
) {
2203 push_force_uncompressed();
2204 emit(MOV(fs_reg(MRF
, nr
++),
2205 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2206 pop_force_uncompressed();
2209 /* Reserve space for color. It'll be filled in per MRT below. */
2211 nr
+= 4 * reg_width
;
2214 if (src0_alpha_to_render_target
)
2217 if (c
->source_depth_to_render_target
) {
2218 if (intel
->gen
== 6 && dispatch_width
== 16) {
2219 /* For outputting oDepth on gen6, SIMD8 writes have to be
2220 * used. This would require 8-wide moves of each half to
2221 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2222 * Just bail on doing so for now.
2224 fail("Missing support for simd16 depth writes on gen6\n");
2227 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2228 /* Hand over gl_FragDepth. */
2229 assert(this->frag_depth
.file
!= BAD_FILE
);
2230 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2232 /* Pass through the payload depth. */
2233 emit(MOV(fs_reg(MRF
, nr
),
2234 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2239 if (c
->dest_depth_reg
) {
2240 emit(MOV(fs_reg(MRF
, nr
),
2241 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2246 fs_reg src0
= this->outputs
[0];
2247 fs_reg src1
= this->dual_src_output
;
2249 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2251 for (int i
= 0; i
< 4; i
++) {
2252 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2254 inst
->saturate
= c
->key
.clamp_fragment_color
;
2257 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2259 for (int i
= 0; i
< 4; i
++) {
2260 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2263 inst
->saturate
= c
->key
.clamp_fragment_color
;
2266 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2268 inst
->base_mrf
= base_mrf
;
2269 inst
->mlen
= nr
- base_mrf
;
2271 inst
->header_present
= header_present
;
2273 c
->prog_data
.dual_src_blend
= true;
2274 this->current_annotation
= NULL
;
2278 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2279 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2280 "FB write target %d",
2282 /* If src0_alpha_to_render_target is true, include source zero alpha
2283 * data in RenderTargetWrite message for targets > 0.
2285 int write_color_mrf
= color_mrf
;
2286 if (src0_alpha_to_render_target
&& target
!= 0) {
2288 fs_reg color
= outputs
[0];
2289 color
.reg_offset
+= 3;
2291 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2293 inst
->saturate
= c
->key
.clamp_fragment_color
;
2294 write_color_mrf
= color_mrf
+ reg_width
;
2297 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2298 emit_color_write(target
, i
, write_color_mrf
);
2300 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2301 inst
->target
= target
;
2302 inst
->base_mrf
= base_mrf
;
2303 if (src0_alpha_to_render_target
&& target
== 0)
2304 inst
->mlen
= nr
- base_mrf
- reg_width
;
2306 inst
->mlen
= nr
- base_mrf
;
2307 if (target
== c
->key
.nr_color_regions
- 1)
2309 inst
->header_present
= header_present
;
2312 if (c
->key
.nr_color_regions
== 0) {
2313 /* Even if there's no color buffers enabled, we still need to send
2314 * alpha out the pipeline to our null renderbuffer to support
2315 * alpha-testing, alpha-to-coverage, and so on.
2317 emit_color_write(0, 3, color_mrf
);
2319 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2320 inst
->base_mrf
= base_mrf
;
2321 inst
->mlen
= nr
- base_mrf
;
2323 inst
->header_present
= header_present
;
2326 this->current_annotation
= NULL
;
2330 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2332 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2336 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2337 emit(MOV(temp
, *reg
));
2342 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2344 if (rvalue
->type
!= glsl_type::bool_type
)
2347 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2348 emit(AND(temp
, *reg
, fs_reg(1)));
2352 fs_visitor::fs_visitor(struct brw_context
*brw
,
2353 struct brw_wm_compile
*c
,
2354 struct gl_shader_program
*prog
,
2355 struct gl_fragment_program
*fp
,
2356 unsigned dispatch_width
)
2357 : dispatch_width(dispatch_width
)
2363 this->intel
= &brw
->intel
;
2364 this->ctx
= &intel
->ctx
;
2365 this->mem_ctx
= ralloc_context(NULL
);
2367 shader
= (struct brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2370 this->failed
= false;
2371 this->variable_ht
= hash_table_ctor(0,
2372 hash_table_pointer_hash
,
2373 hash_table_pointer_compare
);
2375 memset(this->outputs
, 0, sizeof(this->outputs
));
2376 memset(this->output_components
, 0, sizeof(this->output_components
));
2377 this->first_non_payload_grf
= 0;
2378 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2380 this->current_annotation
= NULL
;
2381 this->base_ir
= NULL
;
2383 this->virtual_grf_sizes
= NULL
;
2384 this->virtual_grf_count
= 0;
2385 this->virtual_grf_array_size
= 0;
2386 this->virtual_grf_def
= NULL
;
2387 this->virtual_grf_use
= NULL
;
2388 this->live_intervals_valid
= false;
2390 this->force_uncompressed_stack
= 0;
2391 this->force_sechalf_stack
= 0;
2393 memset(&this->param_size
, 0, sizeof(this->param_size
));
2396 fs_visitor::~fs_visitor()
2398 ralloc_free(this->mem_ctx
);
2399 hash_table_dtor(this->variable_ht
);