2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50 #include "glsl/ir_print_visitor.h"
53 fs_visitor::visit(ir_variable
*ir
)
57 if (variable_storage(ir
))
60 if (ir
->mode
== ir_var_in
) {
61 if (!strcmp(ir
->name
, "gl_FragCoord")) {
62 reg
= emit_fragcoord_interpolation(ir
);
63 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
64 reg
= emit_frontfacing_interpolation(ir
);
66 reg
= emit_general_interpolation(ir
);
69 hash_table_insert(this->variable_ht
, reg
, ir
);
71 } else if (ir
->mode
== ir_var_out
) {
72 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
75 assert(ir
->location
== FRAG_RESULT_DATA0
);
76 assert(ir
->index
== 1);
77 this->dual_src_output
= *reg
;
78 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
81 this->outputs
[i
] = *reg
;
82 this->output_components
[i
] = 4;
84 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
85 this->frag_depth
= *reg
;
87 /* gl_FragData or a user-defined FS output */
88 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
89 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
92 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
93 : ir
->type
->vector_elements
;
95 /* General color output. */
96 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
97 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
98 this->outputs
[output
] = *reg
;
99 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
100 this->output_components
[output
] = vector_elements
;
103 } else if (ir
->mode
== ir_var_uniform
) {
104 int param_index
= c
->prog_data
.nr_params
;
106 /* Thanks to the lower_ubo_reference pass, we will see only
107 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
108 * variables, so no need for them to be in variable_ht.
110 if (ir
->uniform_block
!= -1)
113 if (dispatch_width
== 16) {
114 if (!variable_storage(ir
)) {
115 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
120 param_size
[param_index
] = type_size(ir
->type
);
121 if (!strncmp(ir
->name
, "gl_", 3)) {
122 setup_builtin_uniform_values(ir
);
124 setup_uniform_values(ir
);
127 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
128 reg
->type
= brw_type_for_base_type(ir
->type
);
132 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
134 hash_table_insert(this->variable_ht
, reg
, ir
);
138 fs_visitor::visit(ir_dereference_variable
*ir
)
140 fs_reg
*reg
= variable_storage(ir
->var
);
145 fs_visitor::visit(ir_dereference_record
*ir
)
147 const glsl_type
*struct_type
= ir
->record
->type
;
149 ir
->record
->accept(this);
151 unsigned int offset
= 0;
152 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
153 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
155 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
157 this->result
.reg_offset
+= offset
;
158 this->result
.type
= brw_type_for_base_type(ir
->type
);
162 fs_visitor::visit(ir_dereference_array
*ir
)
164 ir_constant
*constant_index
;
166 int element_size
= type_size(ir
->type
);
168 constant_index
= ir
->array_index
->as_constant();
170 ir
->array
->accept(this);
172 src
.type
= brw_type_for_base_type(ir
->type
);
174 if (constant_index
) {
175 assert(src
.file
== UNIFORM
|| src
.file
== GRF
);
176 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
178 /* Variable index array dereference. We attach the variable index
179 * component to the reg as a pointer to a register containing the
180 * offset. Currently only uniform arrays are supported in this patch,
181 * and that reladdr pointer is resolved by
182 * move_uniform_array_access_to_pull_constants(). All other array types
183 * are lowered by lower_variable_index_to_cond_assign().
185 ir
->array_index
->accept(this);
188 index_reg
= fs_reg(this, glsl_type::int_type
);
189 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
192 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
195 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
196 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
202 fs_visitor::emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
203 fs_reg src0
, fs_reg src1
)
207 if (intel
->gen
>= 6) {
208 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
209 inst
->conditional_mod
= conditionalmod
;
211 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
213 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
218 /* Instruction selection: Produce a MOV.sat instead of
219 * MIN(MAX(val, 0), 1) when possible.
222 fs_visitor::try_emit_saturate(ir_expression
*ir
)
224 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
229 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
231 sat_val
->accept(this);
232 fs_reg src
= this->result
;
234 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
236 /* If the last instruction from our accept() didn't generate our
237 * src, generate a saturated MOV
239 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
240 if (!modify
|| modify
->regs_written() != 1) {
241 this->result
= fs_reg(this, ir
->type
);
242 fs_inst
*inst
= emit(MOV(this->result
, src
));
243 inst
->saturate
= true;
245 modify
->saturate
= true;
254 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
256 /* 3-src instructions were introduced in gen6. */
260 /* MAD can only handle floating-point data. */
261 if (ir
->type
!= glsl_type::float_type
)
264 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
265 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
267 if (!mul
|| mul
->operation
!= ir_binop_mul
)
270 if (nonmul
->as_constant() ||
271 mul
->operands
[0]->as_constant() ||
272 mul
->operands
[1]->as_constant())
275 nonmul
->accept(this);
276 fs_reg src0
= this->result
;
278 mul
->operands
[0]->accept(this);
279 fs_reg src1
= this->result
;
281 mul
->operands
[1]->accept(this);
282 fs_reg src2
= this->result
;
284 this->result
= fs_reg(this, ir
->type
);
285 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
291 fs_visitor::visit(ir_expression
*ir
)
293 unsigned int operand
;
297 assert(ir
->get_num_operands() <= 2);
299 if (try_emit_saturate(ir
))
301 if (ir
->operation
== ir_binop_add
) {
302 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
306 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
307 ir
->operands
[operand
]->accept(this);
308 if (this->result
.file
== BAD_FILE
) {
310 fail("Failed to get tree for expression operand:\n");
311 ir
->operands
[operand
]->accept(&v
);
313 op
[operand
] = this->result
;
315 /* Matrix expression operands should have been broken down to vector
316 * operations already.
318 assert(!ir
->operands
[operand
]->type
->is_matrix());
319 /* And then those vector operands should have been broken down to scalar.
321 assert(!ir
->operands
[operand
]->type
->is_vector());
324 /* Storage for our result. If our result goes into an assignment, it will
325 * just get copy-propagated out, so no worries.
327 this->result
= fs_reg(this, ir
->type
);
329 switch (ir
->operation
) {
330 case ir_unop_logic_not
:
331 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
332 * ones complement of the whole register, not just bit 0.
334 emit(XOR(this->result
, op
[0], fs_reg(1)));
337 op
[0].negate
= !op
[0].negate
;
338 this->result
= op
[0];
342 op
[0].negate
= false;
343 this->result
= op
[0];
346 temp
= fs_reg(this, ir
->type
);
348 emit(MOV(this->result
, fs_reg(0.0f
)));
350 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_G
));
351 inst
= emit(MOV(this->result
, fs_reg(1.0f
)));
352 inst
->predicate
= BRW_PREDICATE_NORMAL
;
354 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_L
));
355 inst
= emit(MOV(this->result
, fs_reg(-1.0f
)));
356 inst
->predicate
= BRW_PREDICATE_NORMAL
;
360 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
364 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
367 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
371 assert(!"not reached: should be handled by ir_explog_to_explog2");
374 case ir_unop_sin_reduced
:
375 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
378 case ir_unop_cos_reduced
:
379 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
383 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
386 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
390 emit(ADD(this->result
, op
[0], op
[1]));
393 assert(!"not reached: should be handled by ir_sub_to_add_neg");
397 if (ir
->type
->is_integer()) {
398 /* For integer multiplication, the MUL uses the low 16 bits
399 * of one of the operands (src0 on gen6, src1 on gen7). The
400 * MACH accumulates in the contribution of the upper 16 bits
403 * FINISHME: Emit just the MUL if we know an operand is small
406 if (intel
->gen
>= 7 && dispatch_width
== 16)
407 fail("16-wide explicit accumulator operands unsupported\n");
409 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
411 emit(MUL(acc
, op
[0], op
[1]));
412 emit(MACH(reg_null_d
, op
[0], op
[1]));
413 emit(MOV(this->result
, fs_reg(acc
)));
415 emit(MUL(this->result
, op
[0], op
[1]));
419 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
420 assert(ir
->type
->is_integer());
421 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
424 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
425 assert(ir
->type
->is_integer());
426 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
430 case ir_binop_greater
:
431 case ir_binop_lequal
:
432 case ir_binop_gequal
:
434 case ir_binop_all_equal
:
435 case ir_binop_nequal
:
436 case ir_binop_any_nequal
:
437 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
438 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
440 emit(CMP(this->result
, op
[0], op
[1],
441 brw_conditional_for_comparison(ir
->operation
)));
444 case ir_binop_logic_xor
:
445 emit(XOR(this->result
, op
[0], op
[1]));
448 case ir_binop_logic_or
:
449 emit(OR(this->result
, op
[0], op
[1]));
452 case ir_binop_logic_and
:
453 emit(AND(this->result
, op
[0], op
[1]));
458 assert(!"not reached: should be handled by brw_fs_channel_expressions");
462 assert(!"not reached: should be handled by lower_noise");
465 case ir_quadop_vector
:
466 assert(!"not reached: should be handled by lower_quadop_vector");
470 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
474 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
477 case ir_unop_bitcast_i2f
:
478 case ir_unop_bitcast_u2f
:
479 op
[0].type
= BRW_REGISTER_TYPE_F
;
480 this->result
= op
[0];
483 case ir_unop_bitcast_f2u
:
484 op
[0].type
= BRW_REGISTER_TYPE_UD
;
485 this->result
= op
[0];
488 case ir_unop_bitcast_f2i
:
489 op
[0].type
= BRW_REGISTER_TYPE_D
;
490 this->result
= op
[0];
496 emit(MOV(this->result
, op
[0]));
500 inst
= emit(AND(this->result
, op
[0], fs_reg(1)));
503 temp
= fs_reg(this, glsl_type::int_type
);
504 emit(AND(temp
, op
[0], fs_reg(1)));
505 emit(MOV(this->result
, temp
));
509 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
512 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
516 emit(RNDZ(this->result
, op
[0]));
519 op
[0].negate
= !op
[0].negate
;
520 inst
= emit(RNDD(this->result
, op
[0]));
521 this->result
.negate
= true;
524 inst
= emit(RNDD(this->result
, op
[0]));
527 inst
= emit(FRC(this->result
, op
[0]));
529 case ir_unop_round_even
:
530 emit(RNDE(this->result
, op
[0]));
535 resolve_ud_negate(&op
[0]);
536 resolve_ud_negate(&op
[1]);
537 emit_minmax(ir
->operation
== ir_binop_min
?
538 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
539 this->result
, op
[0], op
[1]);
543 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
546 case ir_unop_bit_not
:
547 inst
= emit(NOT(this->result
, op
[0]));
549 case ir_binop_bit_and
:
550 inst
= emit(AND(this->result
, op
[0], op
[1]));
552 case ir_binop_bit_xor
:
553 inst
= emit(XOR(this->result
, op
[0], op
[1]));
555 case ir_binop_bit_or
:
556 inst
= emit(OR(this->result
, op
[0], op
[1]));
559 case ir_binop_lshift
:
560 inst
= emit(SHL(this->result
, op
[0], op
[1]));
563 case ir_binop_rshift
:
564 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
565 inst
= emit(ASR(this->result
, op
[0], op
[1]));
567 inst
= emit(SHR(this->result
, op
[0], op
[1]));
570 case ir_binop_ubo_load
:
571 /* This IR node takes a constant uniform block and a constant or
572 * variable byte offset within the block and loads a vector from that.
574 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
575 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
576 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block
->value
.u
[0]));
578 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
579 packed_consts
.type
= result
.type
;
581 if (intel
->gen
>= 7) {
582 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] / 16);
583 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
584 struct brw_reg g0
= retype(brw_vec8_grf(0, 0),
585 BRW_REGISTER_TYPE_UD
);
586 fs_inst
*setup
= emit(MOV(payload
, fs_reg(g0
)));
587 setup
->force_writemask_all
= true;
588 /* We don't need the second half of this vgrf to be filled with g1
589 * in the 16-wide case, but if we use force_uncompressed then live
590 * variable analysis won't consider this a def!
593 emit(FS_OPCODE_SET_GLOBAL_OFFSET
, payload
,
594 payload
, const_offset_reg
);
595 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
, packed_consts
,
596 surf_index
, payload
);
598 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0]);
599 fs_inst
*pull
= emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
607 packed_consts
.smear
= const_offset
->value
.u
[0] % 16 / 4;
608 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
609 /* UBO bools are any nonzero value. We consider bools to be
610 * values with the low bit set to 1. Convert them using CMP.
612 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
613 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
615 emit(MOV(result
, packed_consts
));
618 packed_consts
.smear
++;
621 /* The std140 packing rules don't allow vectors to cross 16-byte
622 * boundaries, and a reg is 32 bytes.
624 assert(packed_consts
.smear
< 8);
627 /* Turn the byte offset into a dword offset. */
628 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
629 emit(SHR(base_offset
, op
[1], fs_reg(2)));
631 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
632 fs_reg offset
= fs_reg(this, glsl_type::int_type
);
633 emit(ADD(offset
, base_offset
, fs_reg(i
)));
634 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
, offset
));
636 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
637 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
643 result
.reg_offset
= 0;
649 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
650 const glsl_type
*type
, bool predicated
)
652 switch (type
->base_type
) {
653 case GLSL_TYPE_FLOAT
:
657 for (unsigned int i
= 0; i
< type
->components(); i
++) {
658 l
.type
= brw_type_for_base_type(type
);
659 r
.type
= brw_type_for_base_type(type
);
661 if (predicated
|| !l
.equals(r
)) {
662 fs_inst
*inst
= emit(MOV(l
, r
));
663 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
670 case GLSL_TYPE_ARRAY
:
671 for (unsigned int i
= 0; i
< type
->length
; i
++) {
672 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
676 case GLSL_TYPE_STRUCT
:
677 for (unsigned int i
= 0; i
< type
->length
; i
++) {
678 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
683 case GLSL_TYPE_SAMPLER
:
687 assert(!"not reached");
692 /* If the RHS processing resulted in an instruction generating a
693 * temporary value, and it would be easy to rewrite the instruction to
694 * generate its result right into the LHS instead, do so. This ends
695 * up reliably removing instructions where it can be tricky to do so
696 * later without real UD chain information.
699 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
702 fs_inst
*pre_rhs_inst
,
703 fs_inst
*last_rhs_inst
)
705 /* Only attempt if we're doing a direct assignment. */
707 !(ir
->lhs
->type
->is_scalar() ||
708 (ir
->lhs
->type
->is_vector() &&
709 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
712 /* Make sure the last instruction generated our source reg. */
713 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
719 /* If last_rhs_inst wrote a different number of components than our LHS,
720 * we can't safely rewrite it.
722 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written())
725 /* Success! Rewrite the instruction. */
732 fs_visitor::visit(ir_assignment
*ir
)
737 /* FINISHME: arrays on the lhs */
738 ir
->lhs
->accept(this);
741 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
743 ir
->rhs
->accept(this);
746 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
748 assert(l
.file
!= BAD_FILE
);
749 assert(r
.file
!= BAD_FILE
);
751 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
755 emit_bool_to_cond_code(ir
->condition
);
758 if (ir
->lhs
->type
->is_scalar() ||
759 ir
->lhs
->type
->is_vector()) {
760 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
761 if (ir
->write_mask
& (1 << i
)) {
762 inst
= emit(MOV(l
, r
));
764 inst
->predicate
= BRW_PREDICATE_NORMAL
;
770 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
775 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
776 fs_reg shadow_c
, fs_reg lod
, fs_reg dPdy
)
786 if (ir
->shadow_comparitor
) {
787 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
788 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
789 coordinate
.reg_offset
++;
791 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
794 if (ir
->op
== ir_tex
) {
795 /* There's no plain shadow compare message, so we use shadow
796 * compare with a bias of 0.0.
798 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
800 } else if (ir
->op
== ir_txb
|| ir
->op
== ir_txl
) {
801 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
804 assert(!"Should not get here.");
807 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
809 } else if (ir
->op
== ir_tex
) {
810 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
811 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
812 coordinate
.reg_offset
++;
814 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
816 } else if (ir
->op
== ir_txd
) {
819 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
820 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
821 coordinate
.reg_offset
++;
823 /* the slots for u and v are always present, but r is optional */
824 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
827 * dPdx = dudx, dvdx, drdx
828 * dPdy = dudy, dvdy, drdy
830 * 1-arg: Does not exist.
832 * 2-arg: dudx dvdx dudy dvdy
833 * dPdx.x dPdx.y dPdy.x dPdy.y
836 * 3-arg: dudx dvdx drdx dudy dvdy drdy
837 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
840 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
841 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
844 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
846 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
847 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
850 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
851 } else if (ir
->op
== ir_txs
) {
852 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
854 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
857 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
858 * instructions. We'll need to do SIMD16 here.
861 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
863 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
864 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
866 coordinate
.reg_offset
++;
869 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
870 * be necessary for TXF (ld), but seems wise to do for all messages.
872 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
873 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
876 /* lod/bias appears after u/v/r. */
879 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
882 /* The unused upper half. */
887 /* Now, since we're doing simd16, the return is 2 interleaved
888 * vec4s where the odd-indexed ones are junk. We'll need to move
889 * this weirdness around to the expected layout.
892 const glsl_type
*vec_type
=
893 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
894 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
895 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
896 : BRW_REGISTER_TYPE_F
;
899 fs_inst
*inst
= NULL
;
902 inst
= emit(SHADER_OPCODE_TEX
, dst
);
905 inst
= emit(FS_OPCODE_TXB
, dst
);
908 inst
= emit(SHADER_OPCODE_TXL
, dst
);
911 inst
= emit(SHADER_OPCODE_TXD
, dst
);
914 inst
= emit(SHADER_OPCODE_TXS
, dst
);
917 inst
= emit(SHADER_OPCODE_TXF
, dst
);
920 inst
->base_mrf
= base_mrf
;
922 inst
->header_present
= true;
925 for (int i
= 0; i
< 4; i
++) {
926 emit(MOV(orig_dst
, dst
));
927 orig_dst
.reg_offset
++;
935 /* gen5's sampler has slots for u, v, r, array index, then optional
936 * parameters like shadow comparitor or LOD bias. If optional
937 * parameters aren't present, those base slots are optional and don't
938 * need to be included in the message.
940 * We don't fill in the unnecessary slots regardless, which may look
941 * surprising in the disassembly.
944 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
945 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
949 int reg_width
= dispatch_width
/ 8;
950 bool header_present
= false;
951 const int vector_elements
=
952 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
954 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
955 /* It appears that the ld instruction used for txf does its
956 * address bounds check before adding in the offset. To work
957 * around this, just add the integer offset to the integer texel
958 * coordinate, and don't put the offset in the header.
960 ir_constant
*offset
= ir
->offset
->as_constant();
961 for (int i
= 0; i
< vector_elements
; i
++) {
962 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
964 offset
->value
.i
[i
]));
965 coordinate
.reg_offset
++;
969 /* The offsets set up by the ir_texture visitor are in the
970 * m1 header, so we can't go headerless.
972 header_present
= true;
977 for (int i
= 0; i
< vector_elements
; i
++) {
978 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
980 coordinate
.reg_offset
++;
983 mlen
+= vector_elements
* reg_width
;
985 if (ir
->shadow_comparitor
) {
986 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
988 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
992 fs_inst
*inst
= NULL
;
995 inst
= emit(SHADER_OPCODE_TEX
, dst
);
998 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
999 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1002 inst
= emit(FS_OPCODE_TXB
, dst
);
1005 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
1006 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1009 inst
= emit(SHADER_OPCODE_TXL
, dst
);
1012 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
1016 * dPdx = dudx, dvdx, drdx
1017 * dPdy = dudy, dvdy, drdy
1019 * Load up these values:
1020 * - dudx dudy dvdx dvdy drdx drdy
1021 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1023 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
1024 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1028 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1033 inst
= emit(SHADER_OPCODE_TXD
, dst
);
1037 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1039 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1042 mlen
= header_present
+ 4 * reg_width
;
1044 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
1046 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1049 inst
->base_mrf
= base_mrf
;
1051 inst
->header_present
= header_present
;
1054 fail("Message length >11 disallowed by hardware\n");
1061 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1062 fs_reg shadow_c
, fs_reg lod
, fs_reg lod2
)
1066 int reg_width
= dispatch_width
/ 8;
1067 bool header_present
= false;
1070 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1071 /* The offsets set up by the ir_texture visitor are in the
1072 * m1 header, so we can't go headerless.
1074 header_present
= true;
1079 if (ir
->shadow_comparitor
) {
1080 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1084 /* Set up the LOD info */
1089 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1093 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1097 if (dispatch_width
== 16)
1098 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1100 /* Load dPdx and the coordinate together:
1101 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1103 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1104 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1105 coordinate
.reg_offset
++;
1108 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1109 * only derivatives for (u, v, r).
1111 if (i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
) {
1112 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1116 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod2
));
1124 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1128 /* It appears that the ld instruction used for txf does its
1129 * address bounds check before adding in the offset. To work
1130 * around this, just add the integer offset to the integer texel
1131 * coordinate, and don't put the offset in the header.
1134 ir_constant
*offset
= ir
->offset
->as_constant();
1135 offsets
[0] = offset
->value
.i
[0];
1136 offsets
[1] = offset
->value
.i
[1];
1137 offsets
[2] = offset
->value
.i
[2];
1139 memset(offsets
, 0, sizeof(offsets
));
1142 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1143 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1144 coordinate
, offsets
[0]));
1145 coordinate
.reg_offset
++;
1148 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), lod
));
1151 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1152 emit(ADD(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
),
1153 coordinate
, offsets
[i
]));
1154 coordinate
.reg_offset
++;
1160 /* Set up the coordinate (except for cases where it was done above) */
1161 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1162 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1163 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1164 coordinate
.reg_offset
++;
1169 /* Generate the SEND */
1170 fs_inst
*inst
= NULL
;
1172 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1173 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1174 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1175 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1176 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1177 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1179 inst
->base_mrf
= base_mrf
;
1181 inst
->header_present
= header_present
;
1184 fail("Message length >11 disallowed by hardware\n");
1191 fs_visitor::rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
1192 bool is_rect
, int sampler
, int texunit
)
1194 fs_inst
*inst
= NULL
;
1195 bool needs_gl_clamp
= true;
1196 fs_reg scale_x
, scale_y
;
1198 /* The 965 requires the EU to do the normalization of GL rectangle
1199 * texture coordinates. We use the program parameter state
1200 * tracking to get the scaling factor.
1204 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1205 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1206 struct gl_program_parameter_list
*params
= fp
->Base
.Parameters
;
1207 int tokens
[STATE_LENGTH
] = {
1209 STATE_TEXRECT_SCALE
,
1215 if (dispatch_width
== 16) {
1216 fail("rectangle scale uniform setup not supported on 16-wide\n");
1220 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1221 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1223 GLuint index
= _mesa_add_state_reference(params
,
1224 (gl_state_index
*)tokens
);
1225 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1226 &fp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
1227 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
1228 &fp
->Base
.Parameters
->ParameterValues
[index
][1].f
;
1231 /* The 965 requires the EU to do the normalization of GL rectangle
1232 * texture coordinates. We use the program parameter state
1233 * tracking to get the scaling factor.
1235 if (intel
->gen
< 6 && is_rect
) {
1236 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1237 fs_reg src
= coordinate
;
1240 emit(MUL(dst
, src
, scale_x
));
1243 emit(MUL(dst
, src
, scale_y
));
1244 } else if (is_rect
) {
1245 /* On gen6+, the sampler handles the rectangle coordinates
1246 * natively, without needing rescaling. But that means we have
1247 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1248 * not [0, 1] like the default case below.
1250 needs_gl_clamp
= false;
1252 for (int i
= 0; i
< 2; i
++) {
1253 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1254 fs_reg chan
= coordinate
;
1255 chan
.reg_offset
+= i
;
1257 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1258 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1260 /* Our parameter comes in as 1.0/width or 1.0/height,
1261 * because that's what people normally want for doing
1262 * texture rectangle handling. We need width or height
1263 * for clamping, but we don't care enough to make a new
1264 * parameter type, so just invert back.
1266 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1267 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1268 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1270 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1271 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1276 if (ir
->coordinate
&& needs_gl_clamp
) {
1277 for (unsigned int i
= 0;
1278 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1279 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1280 fs_reg chan
= coordinate
;
1281 chan
.reg_offset
+= i
;
1283 fs_inst
*inst
= emit(MOV(chan
, chan
));
1284 inst
->saturate
= true;
1292 fs_visitor::visit(ir_texture
*ir
)
1294 fs_inst
*inst
= NULL
;
1296 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1297 /* FINISHME: We're failing to recompile our programs when the sampler is
1298 * updated. This only matters for the texture rectangle scale parameters
1299 * (pre-gen6, or gen6+ with GL_CLAMP).
1301 int texunit
= fp
->Base
.SamplerUnits
[sampler
];
1303 /* Should be lowered by do_lower_texture_projection */
1304 assert(!ir
->projector
);
1306 /* Generate code to compute all the subexpression trees. This has to be
1307 * done before loading any values into MRFs for the sampler message since
1308 * generating these values may involve SEND messages that need the MRFs.
1311 if (ir
->coordinate
) {
1312 ir
->coordinate
->accept(this);
1314 coordinate
= rescale_texcoord(ir
, this->result
,
1315 ir
->sampler
->type
->sampler_dimensionality
==
1316 GLSL_SAMPLER_DIM_RECT
,
1320 fs_reg shadow_comparitor
;
1321 if (ir
->shadow_comparitor
) {
1322 ir
->shadow_comparitor
->accept(this);
1323 shadow_comparitor
= this->result
;
1331 ir
->lod_info
.bias
->accept(this);
1335 ir
->lod_info
.grad
.dPdx
->accept(this);
1338 ir
->lod_info
.grad
.dPdy
->accept(this);
1339 lod2
= this->result
;
1344 ir
->lod_info
.lod
->accept(this);
1349 /* Writemasking doesn't eliminate channels on SIMD8 texture
1350 * samples, so don't worry about them.
1352 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1354 if (intel
->gen
>= 7) {
1355 inst
= emit_texture_gen7(ir
, dst
, coordinate
, shadow_comparitor
,
1357 } else if (intel
->gen
>= 5) {
1358 inst
= emit_texture_gen5(ir
, dst
, coordinate
, shadow_comparitor
,
1361 inst
= emit_texture_gen4(ir
, dst
, coordinate
, shadow_comparitor
,
1365 /* The header is set up by generate_tex() when necessary. */
1366 inst
->src
[0] = reg_undef
;
1368 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1369 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1371 inst
->sampler
= sampler
;
1373 if (ir
->shadow_comparitor
)
1374 inst
->shadow_compare
= true;
1376 /* fixup #layers for cube map arrays */
1377 if (ir
->op
== ir_txs
) {
1378 glsl_type
const *type
= ir
->sampler
->type
;
1379 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1380 type
->sampler_array
) {
1382 depth
.reg_offset
= 2;
1383 emit_math(SHADER_OPCODE_INT_QUOTIENT
, depth
, depth
, fs_reg(6));
1387 swizzle_result(ir
, dst
, sampler
);
1391 * Swizzle the result of a texture result. This is necessary for
1392 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1395 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1397 this->result
= orig_val
;
1399 if (ir
->op
== ir_txs
)
1402 if (ir
->type
== glsl_type::float_type
) {
1403 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1404 assert(ir
->sampler
->type
->sampler_shadow
);
1405 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1406 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1408 for (int i
= 0; i
< 4; i
++) {
1409 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1410 fs_reg l
= swizzled_result
;
1413 if (swiz
== SWIZZLE_ZERO
) {
1414 emit(MOV(l
, fs_reg(0.0f
)));
1415 } else if (swiz
== SWIZZLE_ONE
) {
1416 emit(MOV(l
, fs_reg(1.0f
)));
1418 fs_reg r
= orig_val
;
1419 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1423 this->result
= swizzled_result
;
1428 fs_visitor::visit(ir_swizzle
*ir
)
1430 ir
->val
->accept(this);
1431 fs_reg val
= this->result
;
1433 if (ir
->type
->vector_elements
== 1) {
1434 this->result
.reg_offset
+= ir
->mask
.x
;
1438 fs_reg result
= fs_reg(this, ir
->type
);
1439 this->result
= result
;
1441 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1442 fs_reg channel
= val
;
1460 channel
.reg_offset
+= swiz
;
1461 emit(MOV(result
, channel
));
1462 result
.reg_offset
++;
1467 fs_visitor::visit(ir_discard
*ir
)
1469 assert(ir
->condition
== NULL
); /* FINISHME */
1471 /* We track our discarded pixels in f0.1. By predicating on it, we can
1472 * update just the flag bits that aren't yet discarded. By emitting a
1473 * CMP of g0 != g0, all our currently executing channels will get turned
1476 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1477 BRW_REGISTER_TYPE_UW
));
1478 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1479 BRW_CONDITIONAL_NZ
));
1480 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1481 cmp
->flag_subreg
= 1;
1483 if (intel
->gen
>= 6) {
1484 /* For performance, after a discard, jump to the end of the shader.
1485 * However, many people will do foliage by discarding based on a
1486 * texture's alpha mask, and then continue on to texture with the
1487 * remaining pixels. To avoid trashing the derivatives for those
1488 * texture samples, we'll only jump if all of the pixels in the subspan
1489 * have been discarded.
1491 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1492 discard_jump
->flag_subreg
= 1;
1493 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1494 discard_jump
->predicate_inverse
= true;
1499 fs_visitor::visit(ir_constant
*ir
)
1501 /* Set this->result to reg at the bottom of the function because some code
1502 * paths will cause this visitor to be applied to other fields. This will
1503 * cause the value stored in this->result to be modified.
1505 * Make reg constant so that it doesn't get accidentally modified along the
1506 * way. Yes, I actually had this problem. :(
1508 const fs_reg
reg(this, ir
->type
);
1509 fs_reg dst_reg
= reg
;
1511 if (ir
->type
->is_array()) {
1512 const unsigned size
= type_size(ir
->type
->fields
.array
);
1514 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1515 ir
->array_elements
[i
]->accept(this);
1516 fs_reg src_reg
= this->result
;
1518 dst_reg
.type
= src_reg
.type
;
1519 for (unsigned j
= 0; j
< size
; j
++) {
1520 emit(MOV(dst_reg
, src_reg
));
1521 src_reg
.reg_offset
++;
1522 dst_reg
.reg_offset
++;
1525 } else if (ir
->type
->is_record()) {
1526 foreach_list(node
, &ir
->components
) {
1527 ir_constant
*const field
= (ir_constant
*) node
;
1528 const unsigned size
= type_size(field
->type
);
1530 field
->accept(this);
1531 fs_reg src_reg
= this->result
;
1533 dst_reg
.type
= src_reg
.type
;
1534 for (unsigned j
= 0; j
< size
; j
++) {
1535 emit(MOV(dst_reg
, src_reg
));
1536 src_reg
.reg_offset
++;
1537 dst_reg
.reg_offset
++;
1541 const unsigned size
= type_size(ir
->type
);
1543 for (unsigned i
= 0; i
< size
; i
++) {
1544 switch (ir
->type
->base_type
) {
1545 case GLSL_TYPE_FLOAT
:
1546 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
1548 case GLSL_TYPE_UINT
:
1549 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
1552 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
1554 case GLSL_TYPE_BOOL
:
1555 emit(MOV(dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1558 assert(!"Non-float/uint/int/bool constant");
1560 dst_reg
.reg_offset
++;
1568 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1570 ir_expression
*expr
= ir
->as_expression();
1576 assert(expr
->get_num_operands() <= 2);
1577 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1578 assert(expr
->operands
[i
]->type
->is_scalar());
1580 expr
->operands
[i
]->accept(this);
1581 op
[i
] = this->result
;
1583 resolve_ud_negate(&op
[i
]);
1586 switch (expr
->operation
) {
1587 case ir_unop_logic_not
:
1588 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
1589 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1592 case ir_binop_logic_xor
:
1593 case ir_binop_logic_or
:
1594 case ir_binop_logic_and
:
1598 if (intel
->gen
>= 6) {
1599 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1601 inst
= emit(MOV(reg_null_f
, op
[0]));
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1607 if (intel
->gen
>= 6) {
1608 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1610 inst
= emit(MOV(reg_null_d
, op
[0]));
1611 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1615 case ir_binop_greater
:
1616 case ir_binop_gequal
:
1618 case ir_binop_lequal
:
1619 case ir_binop_equal
:
1620 case ir_binop_all_equal
:
1621 case ir_binop_nequal
:
1622 case ir_binop_any_nequal
:
1623 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1624 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1626 emit(CMP(reg_null_d
, op
[0], op
[1],
1627 brw_conditional_for_comparison(expr
->operation
)));
1631 assert(!"not reached");
1632 fail("bad cond code\n");
1641 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
1642 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1646 * Emit a gen6 IF statement with the comparison folded into the IF
1650 fs_visitor::emit_if_gen6(ir_if
*ir
)
1652 ir_expression
*expr
= ir
->condition
->as_expression();
1659 assert(expr
->get_num_operands() <= 2);
1660 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1661 assert(expr
->operands
[i
]->type
->is_scalar());
1663 expr
->operands
[i
]->accept(this);
1664 op
[i
] = this->result
;
1667 switch (expr
->operation
) {
1668 case ir_unop_logic_not
:
1669 case ir_binop_logic_xor
:
1670 case ir_binop_logic_or
:
1671 case ir_binop_logic_and
:
1672 /* For operations on bool arguments, only the low bit of the bool is
1673 * valid, and the others are undefined. Fall back to the condition
1679 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1680 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1684 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1687 case ir_binop_greater
:
1688 case ir_binop_gequal
:
1690 case ir_binop_lequal
:
1691 case ir_binop_equal
:
1692 case ir_binop_all_equal
:
1693 case ir_binop_nequal
:
1694 case ir_binop_any_nequal
:
1695 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1696 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1698 emit(IF(op
[0], op
[1],
1699 brw_conditional_for_comparison(expr
->operation
)));
1702 assert(!"not reached");
1703 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1704 fail("bad condition\n");
1709 emit_bool_to_cond_code(ir
->condition
);
1710 fs_inst
*inst
= emit(BRW_OPCODE_IF
);
1711 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1715 fs_visitor::visit(ir_if
*ir
)
1717 if (intel
->gen
< 6 && dispatch_width
== 16) {
1718 fail("Can't support (non-uniform) control flow on 16-wide\n");
1721 /* Don't point the annotation at the if statement, because then it plus
1722 * the then and else blocks get printed.
1724 this->base_ir
= ir
->condition
;
1726 if (intel
->gen
== 6) {
1729 emit_bool_to_cond_code(ir
->condition
);
1731 emit(IF(BRW_PREDICATE_NORMAL
));
1734 foreach_list(node
, &ir
->then_instructions
) {
1735 ir_instruction
*ir
= (ir_instruction
*)node
;
1741 if (!ir
->else_instructions
.is_empty()) {
1742 emit(BRW_OPCODE_ELSE
);
1744 foreach_list(node
, &ir
->else_instructions
) {
1745 ir_instruction
*ir
= (ir_instruction
*)node
;
1752 emit(BRW_OPCODE_ENDIF
);
1756 fs_visitor::visit(ir_loop
*ir
)
1758 fs_reg counter
= reg_undef
;
1760 if (intel
->gen
< 6 && dispatch_width
== 16) {
1761 fail("Can't support (non-uniform) control flow on 16-wide\n");
1765 this->base_ir
= ir
->counter
;
1766 ir
->counter
->accept(this);
1767 counter
= *(variable_storage(ir
->counter
));
1770 this->base_ir
= ir
->from
;
1771 ir
->from
->accept(this);
1773 emit(MOV(counter
, this->result
));
1777 this->base_ir
= NULL
;
1778 emit(BRW_OPCODE_DO
);
1781 this->base_ir
= ir
->to
;
1782 ir
->to
->accept(this);
1784 emit(CMP(reg_null_d
, counter
, this->result
,
1785 brw_conditional_for_comparison(ir
->cmp
)));
1787 fs_inst
*inst
= emit(BRW_OPCODE_BREAK
);
1788 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1791 foreach_list(node
, &ir
->body_instructions
) {
1792 ir_instruction
*ir
= (ir_instruction
*)node
;
1798 if (ir
->increment
) {
1799 this->base_ir
= ir
->increment
;
1800 ir
->increment
->accept(this);
1801 emit(ADD(counter
, counter
, this->result
));
1804 this->base_ir
= NULL
;
1805 emit(BRW_OPCODE_WHILE
);
1809 fs_visitor::visit(ir_loop_jump
*ir
)
1812 case ir_loop_jump::jump_break
:
1813 emit(BRW_OPCODE_BREAK
);
1815 case ir_loop_jump::jump_continue
:
1816 emit(BRW_OPCODE_CONTINUE
);
1822 fs_visitor::visit(ir_call
*ir
)
1824 assert(!"FINISHME");
1828 fs_visitor::visit(ir_return
*ir
)
1830 assert(!"FINISHME");
1834 fs_visitor::visit(ir_function
*ir
)
1836 /* Ignore function bodies other than main() -- we shouldn't see calls to
1837 * them since they should all be inlined before we get to ir_to_mesa.
1839 if (strcmp(ir
->name
, "main") == 0) {
1840 const ir_function_signature
*sig
;
1843 sig
= ir
->matching_signature(&empty
);
1847 foreach_list(node
, &sig
->body
) {
1848 ir_instruction
*ir
= (ir_instruction
*)node
;
1857 fs_visitor::visit(ir_function_signature
*ir
)
1859 assert(!"not reached");
1864 fs_visitor::emit(fs_inst inst
)
1866 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1873 fs_visitor::emit(fs_inst
*inst
)
1875 if (force_uncompressed_stack
> 0)
1876 inst
->force_uncompressed
= true;
1877 else if (force_sechalf_stack
> 0)
1878 inst
->force_sechalf
= true;
1880 inst
->annotation
= this->current_annotation
;
1881 inst
->ir
= this->base_ir
;
1883 this->instructions
.push_tail(inst
);
1889 fs_visitor::emit(exec_list list
)
1891 foreach_list_safe(node
, &list
) {
1892 fs_inst
*inst
= (fs_inst
*)node
;
1898 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1900 fs_visitor::emit_dummy_fs()
1902 int reg_width
= dispatch_width
/ 8;
1904 /* Everyone's favorite color. */
1905 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
1906 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
1907 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
1908 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
1911 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1912 write
->base_mrf
= 2;
1913 write
->mlen
= 4 * reg_width
;
1917 /* The register location here is relative to the start of the URB
1918 * data. It will get adjusted to be a real location before
1919 * generate_code() time.
1922 fs_visitor::interp_reg(int location
, int channel
)
1924 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1925 int stride
= (channel
& 1) * 4;
1927 assert(urb_setup
[location
] != -1);
1929 return brw_vec1_grf(regnr
, stride
);
1932 /** Emits the interpolation for the varying inputs. */
1934 fs_visitor::emit_interpolation_setup_gen4()
1936 this->current_annotation
= "compute pixel centers";
1937 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1938 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1939 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1940 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1942 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1943 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1945 this->current_annotation
= "compute pixel deltas from v0";
1947 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1948 fs_reg(this, glsl_type::vec2_type
);
1949 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1950 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1951 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1953 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1954 fs_reg(this, glsl_type::float_type
);
1955 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1956 fs_reg(this, glsl_type::float_type
);
1958 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1959 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
1960 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1961 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
1963 this->current_annotation
= "compute pos.w and 1/pos.w";
1964 /* Compute wpos.w. It's always in our setup, since it's needed to
1965 * interpolate the other attributes.
1967 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1968 emit(FS_OPCODE_LINTERP
, wpos_w
,
1969 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1970 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1971 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1972 /* Compute the pixel 1/W value from wpos.w. */
1973 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1974 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1975 this->current_annotation
= NULL
;
1978 /** Emits the interpolation for the varying inputs. */
1980 fs_visitor::emit_interpolation_setup_gen6()
1982 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1984 /* If the pixel centers end up used, the setup is the same as for gen4. */
1985 this->current_annotation
= "compute pixel centers";
1986 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1987 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1988 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1989 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1990 emit(ADD(int_pixel_x
,
1991 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1992 fs_reg(brw_imm_v(0x10101010))));
1993 emit(ADD(int_pixel_y
,
1994 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1995 fs_reg(brw_imm_v(0x11001100))));
1997 /* As of gen6, we can no longer mix float and int sources. We have
1998 * to turn the integer pixel centers into floats for their actual
2001 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2002 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2003 emit(MOV(this->pixel_x
, int_pixel_x
));
2004 emit(MOV(this->pixel_y
, int_pixel_y
));
2006 this->current_annotation
= "compute pos.w";
2007 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2008 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2009 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2011 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2012 uint8_t reg
= c
->barycentric_coord_reg
[i
];
2013 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
2014 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
2017 this->current_annotation
= NULL
;
2021 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
2023 int reg_width
= dispatch_width
/ 8;
2025 fs_reg color
= outputs
[target
];
2028 /* If there's no color data to be written, skip it. */
2029 if (color
.file
== BAD_FILE
)
2032 color
.reg_offset
+= index
;
2034 if (dispatch_width
== 8 || intel
->gen
>= 6) {
2035 /* SIMD8 write looks like:
2041 * gen6 SIMD16 DP write looks like:
2051 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
* reg_width
,
2054 inst
->saturate
= c
->key
.clamp_fragment_color
;
2056 /* pre-gen6 SIMD16 single source DP write looks like:
2066 if (brw
->has_compr4
) {
2067 /* By setting the high bit of the MRF register number, we
2068 * indicate that we want COMPR4 mode - instead of doing the
2069 * usual destination + 1 for the second half we get
2072 inst
= emit(MOV(fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
2075 inst
->saturate
= c
->key
.clamp_fragment_color
;
2077 push_force_uncompressed();
2078 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
, color
.type
),
2080 inst
->saturate
= c
->key
.clamp_fragment_color
;
2081 pop_force_uncompressed();
2083 push_force_sechalf();
2084 color
.sechalf
= true;
2085 inst
= emit(MOV(fs_reg(MRF
, first_color_mrf
+ index
+ 4, color
.type
),
2087 inst
->saturate
= c
->key
.clamp_fragment_color
;
2088 pop_force_sechalf();
2089 color
.sechalf
= false;
2095 fs_visitor::emit_fb_writes()
2097 this->current_annotation
= "FB write header";
2098 bool header_present
= true;
2099 /* We can potentially have a message length of up to 15, so we have to set
2100 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2104 int reg_width
= dispatch_width
/ 8;
2105 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2106 bool src0_alpha_to_render_target
= false;
2108 if (dispatch_width
== 16 && do_dual_src
) {
2109 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2110 do_dual_src
= false;
2113 /* From the Sandy Bridge PRM, volume 4, page 198:
2115 * "Dispatched Pixel Enables. One bit per pixel indicating
2116 * which pixels were originally enabled when the thread was
2117 * dispatched. This field is only required for the end-of-
2118 * thread message and on all dual-source messages."
2120 if (intel
->gen
>= 6 &&
2121 !this->fp
->UsesKill
&&
2123 c
->key
.nr_color_regions
== 1) {
2124 header_present
= false;
2127 if (header_present
) {
2128 src0_alpha_to_render_target
= intel
->gen
>= 6 &&
2130 c
->key
.nr_color_regions
> 1 &&
2131 c
->key
.sample_alpha_to_coverage
;
2136 if (c
->aa_dest_stencil_reg
) {
2137 push_force_uncompressed();
2138 emit(MOV(fs_reg(MRF
, nr
++),
2139 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2140 pop_force_uncompressed();
2143 /* Reserve space for color. It'll be filled in per MRT below. */
2145 nr
+= 4 * reg_width
;
2148 if (src0_alpha_to_render_target
)
2151 if (c
->source_depth_to_render_target
) {
2152 if (intel
->gen
== 6 && dispatch_width
== 16) {
2153 /* For outputting oDepth on gen6, SIMD8 writes have to be
2154 * used. This would require 8-wide moves of each half to
2155 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2156 * Just bail on doing so for now.
2158 fail("Missing support for simd16 depth writes on gen6\n");
2161 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2162 /* Hand over gl_FragDepth. */
2163 assert(this->frag_depth
.file
!= BAD_FILE
);
2164 emit(MOV(fs_reg(MRF
, nr
), this->frag_depth
));
2166 /* Pass through the payload depth. */
2167 emit(MOV(fs_reg(MRF
, nr
),
2168 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2173 if (c
->dest_depth_reg
) {
2174 emit(MOV(fs_reg(MRF
, nr
),
2175 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2180 fs_reg src0
= this->outputs
[0];
2181 fs_reg src1
= this->dual_src_output
;
2183 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2185 for (int i
= 0; i
< 4; i
++) {
2186 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ i
, src0
.type
), src0
));
2188 inst
->saturate
= c
->key
.clamp_fragment_color
;
2191 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2193 for (int i
= 0; i
< 4; i
++) {
2194 fs_inst
*inst
= emit(MOV(fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2197 inst
->saturate
= c
->key
.clamp_fragment_color
;
2200 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2202 inst
->base_mrf
= base_mrf
;
2203 inst
->mlen
= nr
- base_mrf
;
2205 inst
->header_present
= header_present
;
2207 c
->prog_data
.dual_src_blend
= true;
2208 this->current_annotation
= NULL
;
2212 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2213 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2214 "FB write target %d",
2216 /* If src0_alpha_to_render_target is true, include source zero alpha
2217 * data in RenderTargetWrite message for targets > 0.
2219 int write_color_mrf
= color_mrf
;
2220 if (src0_alpha_to_render_target
&& target
!= 0) {
2222 fs_reg color
= outputs
[0];
2223 color
.reg_offset
+= 3;
2225 inst
= emit(MOV(fs_reg(MRF
, write_color_mrf
, color
.type
),
2227 inst
->saturate
= c
->key
.clamp_fragment_color
;
2228 write_color_mrf
= color_mrf
+ reg_width
;
2231 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2232 emit_color_write(target
, i
, write_color_mrf
);
2234 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2235 inst
->target
= target
;
2236 inst
->base_mrf
= base_mrf
;
2237 if (src0_alpha_to_render_target
&& target
== 0)
2238 inst
->mlen
= nr
- base_mrf
- reg_width
;
2240 inst
->mlen
= nr
- base_mrf
;
2241 if (target
== c
->key
.nr_color_regions
- 1)
2243 inst
->header_present
= header_present
;
2246 if (c
->key
.nr_color_regions
== 0) {
2247 /* Even if there's no color buffers enabled, we still need to send
2248 * alpha out the pipeline to our null renderbuffer to support
2249 * alpha-testing, alpha-to-coverage, and so on.
2251 emit_color_write(0, 3, color_mrf
);
2253 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2254 inst
->base_mrf
= base_mrf
;
2255 inst
->mlen
= nr
- base_mrf
;
2257 inst
->header_present
= header_present
;
2260 this->current_annotation
= NULL
;
2264 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2266 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2270 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2271 emit(MOV(temp
, *reg
));
2276 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2278 if (rvalue
->type
!= glsl_type::bool_type
)
2281 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2282 emit(AND(temp
, *reg
, fs_reg(1)));
2286 fs_visitor::fs_visitor(struct brw_context
*brw
,
2287 struct brw_wm_compile
*c
,
2288 struct gl_shader_program
*prog
,
2289 struct gl_fragment_program
*fp
,
2290 unsigned dispatch_width
)
2291 : dispatch_width(dispatch_width
)
2297 this->intel
= &brw
->intel
;
2298 this->ctx
= &intel
->ctx
;
2299 this->mem_ctx
= ralloc_context(NULL
);
2301 shader
= (struct brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2304 this->failed
= false;
2305 this->variable_ht
= hash_table_ctor(0,
2306 hash_table_pointer_hash
,
2307 hash_table_pointer_compare
);
2309 memset(this->outputs
, 0, sizeof(this->outputs
));
2310 memset(this->output_components
, 0, sizeof(this->output_components
));
2311 this->first_non_payload_grf
= 0;
2312 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2314 this->current_annotation
= NULL
;
2315 this->base_ir
= NULL
;
2317 this->virtual_grf_sizes
= NULL
;
2318 this->virtual_grf_count
= 0;
2319 this->virtual_grf_array_size
= 0;
2320 this->virtual_grf_def
= NULL
;
2321 this->virtual_grf_use
= NULL
;
2322 this->live_intervals_valid
= false;
2324 this->force_uncompressed_stack
= 0;
2325 this->force_sechalf_stack
= 0;
2327 memset(&this->param_size
, 0, sizeof(this->param_size
));
2330 fs_visitor::~fs_visitor()
2332 ralloc_free(this->mem_ctx
);
2333 hash_table_dtor(this->variable_ht
);