i965: Use state streaming on programs, and state base address on gen5+.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "main/glheader.h"
33 #include "main/macros.h"
34 #include "main/enums.h"
35
36 #include "intel_batchbuffer.h"
37
38 #include "brw_defines.h"
39 #include "brw_context.h"
40 #include "brw_eu.h"
41 #include "brw_util.h"
42 #include "brw_state.h"
43 #include "brw_gs.h"
44
45 #include "../glsl/ralloc.h"
46
47 static void compile_gs_prog( struct brw_context *brw,
48 struct brw_gs_prog_key *key )
49 {
50 struct intel_context *intel = &brw->intel;
51 struct brw_gs_compile c;
52 const GLuint *program;
53 void *mem_ctx;
54 GLuint program_size;
55
56 /* Gen6: VF has already converted into polygon, and LINELOOP is
57 * converted to LINESTRIP at the beginning of the 3D pipeline.
58 */
59 if (intel->gen >= 6)
60 return;
61
62 memset(&c, 0, sizeof(c));
63
64 c.key = *key;
65 /* Need to locate the two positions present in vertex + header.
66 * These are currently hardcoded:
67 */
68 c.nr_attrs = brw_count_bits(c.key.attrs);
69
70 if (intel->gen >= 5)
71 c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
72 else
73 c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */
74
75 c.nr_bytes = c.nr_regs * REG_SIZE;
76
77 mem_ctx = NULL;
78
79 /* Begin the compilation:
80 */
81 brw_init_compile(brw, &c.func, mem_ctx);
82
83 c.func.single_program_flow = 1;
84
85 /* For some reason the thread is spawned with only 4 channels
86 * unmasked.
87 */
88 brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
89
90
91 /* Note that primitives which don't require a GS program have
92 * already been weeded out by this stage:
93 */
94
95 switch (key->primitive) {
96 case GL_QUADS:
97 brw_gs_quads( &c, key );
98 break;
99 case GL_QUAD_STRIP:
100 brw_gs_quad_strip( &c, key );
101 break;
102 case GL_LINE_LOOP:
103 brw_gs_lines( &c );
104 break;
105 default:
106 ralloc_free(mem_ctx);
107 return;
108 }
109
110 /* get the program
111 */
112 program = brw_get_program(&c.func, &program_size);
113
114 if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
115 int i;
116
117 printf("gs:\n");
118 for (i = 0; i < program_size / sizeof(struct brw_instruction); i++)
119 brw_disasm(stdout, &((struct brw_instruction *)program)[i],
120 intel->gen);
121 printf("\n");
122 }
123
124 brw_upload_cache(&brw->cache, BRW_GS_PROG,
125 &c.key, sizeof(c.key),
126 program, program_size,
127 &c.prog_data, sizeof(c.prog_data),
128 &brw->gs.prog_offset, &brw->gs.prog_data);
129 ralloc_free(mem_ctx);
130 }
131
132 static const GLenum gs_prim[GL_POLYGON+1] = {
133 GL_POINTS,
134 GL_LINES,
135 GL_LINE_LOOP,
136 GL_LINES,
137 GL_TRIANGLES,
138 GL_TRIANGLES,
139 GL_TRIANGLES,
140 GL_QUADS,
141 GL_QUAD_STRIP,
142 GL_TRIANGLES
143 };
144
145 static void populate_key( struct brw_context *brw,
146 struct brw_gs_prog_key *key )
147 {
148 struct gl_context *ctx = &brw->intel.ctx;
149 struct intel_context *intel = &brw->intel;
150
151 memset(key, 0, sizeof(*key));
152
153 /* CACHE_NEW_VS_PROG */
154 key->attrs = brw->vs.prog_data->outputs_written;
155
156 /* BRW_NEW_PRIMITIVE */
157 key->primitive = gs_prim[brw->primitive];
158
159 /* _NEW_LIGHT */
160 key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
161 if (key->primitive == GL_QUADS && ctx->Light.ShadeModel != GL_FLAT) {
162 /* Provide consistent primitive order with brw_set_prim's
163 * optimization of single quads to trifans.
164 */
165 key->pv_first = GL_TRUE;
166 }
167
168 key->need_gs_prog = (intel->gen >= 6)
169 ? 0
170 : (brw->primitive == GL_QUADS ||
171 brw->primitive == GL_QUAD_STRIP ||
172 brw->primitive == GL_LINE_LOOP);
173 }
174
175 /* Calculate interpolants for triangle and line rasterization.
176 */
177 static void prepare_gs_prog(struct brw_context *brw)
178 {
179 struct brw_gs_prog_key key;
180 /* Populate the key:
181 */
182 populate_key(brw, &key);
183
184 if (brw->gs.prog_active != key.need_gs_prog) {
185 brw->state.dirty.cache |= CACHE_NEW_GS_PROG;
186 brw->gs.prog_active = key.need_gs_prog;
187 }
188
189 if (brw->gs.prog_active) {
190 if (!brw_search_cache(&brw->cache, BRW_GS_PROG,
191 &key, sizeof(key),
192 &brw->gs.prog_offset, &brw->gs.prog_data)) {
193 compile_gs_prog( brw, &key );
194 }
195 }
196 }
197
198
199 const struct brw_tracked_state brw_gs_prog = {
200 .dirty = {
201 .mesa = _NEW_LIGHT,
202 .brw = BRW_NEW_PRIMITIVE,
203 .cache = CACHE_NEW_VS_PROG
204 },
205 .prepare = prepare_gs_prog
206 };