i965/gs: Use NIR info for setting up prog_data
[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * \file brw_vec4_gs.c
26 *
27 * State atom for client-programmable geometry shaders, and support code.
28 */
29
30 #include "brw_gs.h"
31 #include "brw_context.h"
32 #include "brw_vec4_gs_visitor.h"
33 #include "brw_state.h"
34 #include "brw_ff_gs.h"
35 #include "brw_nir.h"
36
37 static void
38 assign_gs_binding_table_offsets(const struct brw_device_info *devinfo,
39 const struct gl_shader_program *shader_prog,
40 const struct gl_program *prog,
41 struct brw_gs_prog_data *prog_data)
42 {
43 /* In gen6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform
44 * feedback surfaces.
45 */
46 uint32_t reserved = devinfo->gen == 6 ? BRW_MAX_SOL_BINDINGS : 0;
47
48 brw_assign_common_binding_table_offsets(MESA_SHADER_GEOMETRY, devinfo,
49 shader_prog, prog,
50 &prog_data->base.base,
51 reserved);
52 }
53
54 bool
55 brw_codegen_gs_prog(struct brw_context *brw,
56 struct gl_shader_program *prog,
57 struct brw_geometry_program *gp,
58 struct brw_gs_prog_key *key)
59 {
60 struct gl_shader *shader = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
61 nir_shader *nir = gp->program.Base.nir;
62 struct brw_stage_state *stage_state = &brw->gs.base;
63 struct brw_gs_prog_data prog_data;
64 struct brw_gs_compile c;
65 memset(&prog_data, 0, sizeof(prog_data));
66 memset(&c, 0, sizeof(c));
67 c.key = *key;
68
69 prog_data.include_primitive_id =
70 (nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;
71
72 prog_data.invocations = nir->info.gs.invocations;
73
74 assign_gs_binding_table_offsets(brw->intelScreen->devinfo, prog,
75 &gp->program.Base, &prog_data);
76
77 /* Allocate the references to the uniforms that will end up in the
78 * prog_data associated with the compiled program, and which will be freed
79 * by the state cache.
80 *
81 * Note: param_count needs to be num_uniform_components * 4, since we add
82 * padding around uniform values below vec4 size, so the worst case is that
83 * every uniform is a float which gets padded to the size of a vec4.
84 */
85 struct gl_shader *gs = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
86 int param_count = gp->program.Base.nir->num_uniforms * 4;
87
88 prog_data.base.base.param =
89 rzalloc_array(NULL, const gl_constant_value *, param_count);
90 prog_data.base.base.pull_param =
91 rzalloc_array(NULL, const gl_constant_value *, param_count);
92 prog_data.base.base.image_param =
93 rzalloc_array(NULL, struct brw_image_param, gs->NumImages);
94 prog_data.base.base.nr_params = param_count;
95 prog_data.base.base.nr_image_params = gs->NumImages;
96
97 brw_nir_setup_glsl_uniforms(gp->program.Base.nir, prog, &gp->program.Base,
98 &prog_data.base.base, false);
99
100 if (brw->gen >= 8) {
101 prog_data.static_vertex_count =
102 nir_gs_count_vertices(gp->program.Base.nir);
103 }
104
105 if (brw->gen >= 7) {
106 if (nir->info.gs.output_primitive == GL_POINTS) {
107 /* When the output type is points, the geometry shader may output data
108 * to multiple streams, and EndPrimitive() has no effect. So we
109 * configure the hardware to interpret the control data as stream ID.
110 */
111 prog_data.control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID;
112
113 /* We only have to emit control bits if we are using streams */
114 if (nir->info.gs.uses_streams)
115 c.control_data_bits_per_vertex = 2;
116 else
117 c.control_data_bits_per_vertex = 0;
118 } else {
119 /* When the output type is triangle_strip or line_strip, EndPrimitive()
120 * may be used to terminate the current strip and start a new one
121 * (similar to primitive restart), and outputting data to multiple
122 * streams is not supported. So we configure the hardware to interpret
123 * the control data as EndPrimitive information (a.k.a. "cut bits").
124 */
125 prog_data.control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT;
126
127 /* We only need to output control data if the shader actually calls
128 * EndPrimitive().
129 */
130 c.control_data_bits_per_vertex =
131 nir->info.gs.uses_end_primitive ? 1 : 0;
132 }
133 } else {
134 /* There are no control data bits in gen6. */
135 c.control_data_bits_per_vertex = 0;
136
137 /* If it is using transform feedback, enable it */
138 if (nir->info.has_transform_feedback_varyings)
139 prog_data.gen6_xfb_enabled = true;
140 else
141 prog_data.gen6_xfb_enabled = false;
142 }
143 c.control_data_header_size_bits =
144 nir->info.gs.vertices_out * c.control_data_bits_per_vertex;
145
146 /* 1 HWORD = 32 bytes = 256 bits */
147 prog_data.control_data_header_size_hwords =
148 ALIGN(c.control_data_header_size_bits, 256) / 256;
149
150 GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
151
152 brw_compute_vue_map(brw->intelScreen->devinfo,
153 &prog_data.base.vue_map, outputs_written,
154 prog ? prog->SeparateShader : false);
155
156 /* Compute the output vertex size.
157 *
158 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 STATE_GS - Output Vertex
159 * Size (p168):
160 *
161 * [0,62] indicating [1,63] 16B units
162 *
163 * Specifies the size of each vertex stored in the GS output entry
164 * (following any Control Header data) as a number of 128-bit units
165 * (minus one).
166 *
167 * Programming Restrictions: The vertex size must be programmed as a
168 * multiple of 32B units with the following exception: Rendering is
169 * disabled (as per SOL stage state) and the vertex size output by the
170 * GS thread is 16B.
171 *
172 * If rendering is enabled (as per SOL state) the vertex size must be
173 * programmed as a multiple of 32B units. In other words, the only time
174 * software can program a vertex size with an odd number of 16B units
175 * is when rendering is disabled.
176 *
177 * Note: B=bytes in the above text.
178 *
179 * It doesn't seem worth the extra trouble to optimize the case where the
180 * vertex size is 16B (especially since this would require special-casing
181 * the GEN assembly that writes to the URB). So we just set the vertex
182 * size to a multiple of 32B (2 vec4's) in all cases.
183 *
184 * The maximum output vertex size is 62*16 = 992 bytes (31 hwords). We
185 * budget that as follows:
186 *
187 * 512 bytes for varyings (a varying component is 4 bytes and
188 * gl_MaxGeometryOutputComponents = 128)
189 * 16 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
190 * bytes)
191 * 16 bytes overhead for gl_Position (we allocate it a slot in the VUE
192 * even if it's not used)
193 * 32 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
194 * whenever clip planes are enabled, even if the shader doesn't
195 * write to gl_ClipDistance)
196 * 16 bytes overhead since the VUE size must be a multiple of 32 bytes
197 * (see below)--this causes up to 1 VUE slot to be wasted
198 * 400 bytes available for varying packing overhead
199 *
200 * Worst-case varying packing overhead is 3/4 of a varying slot (12 bytes)
201 * per interpolation type, so this is plenty.
202 *
203 */
204 unsigned output_vertex_size_bytes = prog_data.base.vue_map.num_slots * 16;
205 assert(brw->gen == 6 ||
206 output_vertex_size_bytes <= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES);
207 prog_data.output_vertex_size_hwords =
208 ALIGN(output_vertex_size_bytes, 32) / 32;
209
210 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
211 * That divides up as follows:
212 *
213 * 64 bytes for the control data header (cut indices or StreamID bits)
214 * 4096 bytes for varyings (a varying component is 4 bytes and
215 * gl_MaxGeometryTotalOutputComponents = 1024)
216 * 4096 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
217 * bytes/vertex and gl_MaxGeometryOutputVertices is 256)
218 * 4096 bytes overhead for gl_Position (we allocate it a slot in the VUE
219 * even if it's not used)
220 * 8192 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
221 * whenever clip planes are enabled, even if the shader doesn't
222 * write to gl_ClipDistance)
223 * 4096 bytes overhead since the VUE size must be a multiple of 32
224 * bytes (see above)--this causes up to 1 VUE slot to be wasted
225 * 8128 bytes available for varying packing overhead
226 *
227 * Worst-case varying packing overhead is 3/4 of a varying slot per
228 * interpolation type, which works out to 3072 bytes, so this would allow
229 * us to accommodate 2 interpolation types without any danger of running
230 * out of URB space.
231 *
232 * In practice, the risk of running out of URB space is very small, since
233 * the above figures are all worst-case, and most of them scale with the
234 * number of output vertices. So we'll just calculate the amount of space
235 * we need, and if it's too large, fail to compile.
236 *
237 * The above is for gen7+ where we have a single URB entry that will hold
238 * all the output. In gen6, we will have to allocate URB entries for every
239 * vertex we emit, so our URB entries only need to be large enough to hold
240 * a single vertex. Also, gen6 does not have a control data header.
241 */
242 unsigned output_size_bytes;
243 if (brw->gen >= 7) {
244 output_size_bytes =
245 prog_data.output_vertex_size_hwords * 32 * nir->info.gs.vertices_out;
246 output_size_bytes += 32 * prog_data.control_data_header_size_hwords;
247 } else {
248 output_size_bytes = prog_data.output_vertex_size_hwords * 32;
249 }
250
251 /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output,
252 * which comes before the control header.
253 */
254 if (brw->gen >= 8)
255 output_size_bytes += 32;
256
257 assert(output_size_bytes >= 1);
258 int max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES;
259 if (brw->gen == 6)
260 max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
261 if (output_size_bytes > max_output_size_bytes)
262 return false;
263
264
265 /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and
266 * a multiple of 128 bytes in gen6.
267 */
268 if (brw->gen >= 7)
269 prog_data.base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
270 else
271 prog_data.base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128;
272
273 prog_data.output_topology =
274 get_hw_prim_for_gl_prim(nir->info.gs.output_primitive);
275
276 /* The GLSL linker will have already matched up GS inputs and the outputs
277 * of prior stages. The driver does extend VS outputs in some cases, but
278 * only for legacy OpenGL or Gen4-5 hardware, neither of which offer
279 * geometry shader support. So we can safely ignore that.
280 *
281 * For SSO pipelines, we use a fixed VUE map layout based on variable
282 * locations, so we can rely on rendezvous-by-location making this work.
283 *
284 * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not
285 * written by previous stages and shows up via payload magic.
286 */
287 GLbitfield64 inputs_read =
288 nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID;
289 brw_compute_vue_map(brw->intelScreen->devinfo,
290 &c.input_vue_map, inputs_read,
291 nir->info.separate_shader);
292
293 /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
294 * need to program a URB read length of ceiling(num_slots / 2).
295 */
296 prog_data.base.urb_read_length = (c.input_vue_map.num_slots + 1) / 2;
297
298 if (unlikely(INTEL_DEBUG & DEBUG_GS))
299 brw_dump_ir("geometry", prog, gs, NULL);
300
301 int st_index = -1;
302 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
303 st_index = brw_get_shader_time_index(brw, prog, NULL, ST_GS);
304
305 void *mem_ctx = ralloc_context(NULL);
306 unsigned program_size;
307 char *error_str;
308 const unsigned *program =
309 brw_compile_gs(brw->intelScreen->compiler, brw, mem_ctx, &c,
310 &prog_data, shader->Program->nir, prog,
311 st_index, &program_size, &error_str);
312 if (program == NULL) {
313 ralloc_free(mem_ctx);
314 return false;
315 }
316
317 /* Scratch space is used for register spilling */
318 if (prog_data.base.base.total_scratch) {
319 brw_get_scratch_bo(brw, &stage_state->scratch_bo,
320 prog_data.base.base.total_scratch *
321 brw->max_gs_threads);
322 }
323
324 brw_upload_cache(&brw->cache, BRW_CACHE_GS_PROG,
325 &c.key, sizeof(c.key),
326 program, program_size,
327 &prog_data, sizeof(prog_data),
328 &stage_state->prog_offset, &brw->gs.prog_data);
329 ralloc_free(mem_ctx);
330
331 return true;
332 }
333
334 static bool
335 brw_gs_state_dirty(struct brw_context *brw)
336 {
337 return brw_state_dirty(brw,
338 _NEW_TEXTURE,
339 BRW_NEW_GEOMETRY_PROGRAM |
340 BRW_NEW_TRANSFORM_FEEDBACK);
341 }
342
343 static void
344 brw_gs_populate_key(struct brw_context *brw,
345 struct brw_gs_prog_key *key)
346 {
347 struct gl_context *ctx = &brw->ctx;
348 struct brw_stage_state *stage_state = &brw->gs.base;
349 struct brw_geometry_program *gp =
350 (struct brw_geometry_program *) brw->geometry_program;
351 struct gl_program *prog = &gp->program.Base;
352
353 memset(key, 0, sizeof(*key));
354
355 key->program_string_id = gp->id;
356
357 /* _NEW_TEXTURE */
358 brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count,
359 &key->tex);
360 }
361
362 void
363 brw_upload_gs_prog(struct brw_context *brw)
364 {
365 struct gl_context *ctx = &brw->ctx;
366 struct gl_shader_program **current = ctx->_Shader->CurrentProgram;
367 struct brw_stage_state *stage_state = &brw->gs.base;
368 struct brw_gs_prog_key key;
369 /* BRW_NEW_GEOMETRY_PROGRAM */
370 struct brw_geometry_program *gp =
371 (struct brw_geometry_program *) brw->geometry_program;
372
373 if (!brw_gs_state_dirty(brw))
374 return;
375
376 if (gp == NULL) {
377 /* No geometry shader. Vertex data just passes straight through. */
378 if (brw->gen == 6 &&
379 (brw->ctx.NewDriverState & BRW_NEW_TRANSFORM_FEEDBACK)) {
380 gen6_brw_upload_ff_gs_prog(brw);
381 return;
382 }
383
384 /* Other state atoms had better not try to access prog_data, since
385 * there's no GS program.
386 */
387 brw->gs.prog_data = NULL;
388 brw->gs.base.prog_data = NULL;
389
390 return;
391 }
392
393 brw_gs_populate_key(brw, &key);
394
395 if (!brw_search_cache(&brw->cache, BRW_CACHE_GS_PROG,
396 &key, sizeof(key),
397 &stage_state->prog_offset, &brw->gs.prog_data)) {
398 bool success = brw_codegen_gs_prog(brw, current[MESA_SHADER_GEOMETRY],
399 gp, &key);
400 assert(success);
401 (void)success;
402 }
403 brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
404 }
405
406 bool
407 brw_gs_precompile(struct gl_context *ctx,
408 struct gl_shader_program *shader_prog,
409 struct gl_program *prog)
410 {
411 struct brw_context *brw = brw_context(ctx);
412 struct brw_gs_prog_key key;
413 uint32_t old_prog_offset = brw->gs.base.prog_offset;
414 struct brw_gs_prog_data *old_prog_data = brw->gs.prog_data;
415 bool success;
416
417 struct gl_geometry_program *gp = (struct gl_geometry_program *) prog;
418 struct brw_geometry_program *bgp = brw_geometry_program(gp);
419
420 memset(&key, 0, sizeof(key));
421
422 brw_setup_tex_for_precompile(brw, &key.tex, prog);
423 key.program_string_id = bgp->id;
424
425 success = brw_codegen_gs_prog(brw, shader_prog, bgp, &key);
426
427 brw->gs.base.prog_offset = old_prog_offset;
428 brw->gs.prog_data = old_prog_data;
429
430 return success;
431 }