src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 static void brw_gs_alloc_regs( struct brw_gs_compile *c,
  46                                GLuint nr_verts )
  47 {
  48    GLuint i = 0,j;
  49
  50    /* Register usage is static, precompute here:
  51     */
  52    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  53
  54    /* Payload vertices plus space for more generated vertices:
  55     */
  56    for (j = 0; j < nr_verts; j++) {
  57       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  58       i += c->nr_regs;
  59    }
  60
  61    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  62    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  63
  64    c->prog_data.urb_read_length = c->nr_regs;
  65    c->prog_data.total_grf = i;
  66 }
  67
  68
  69 /**
  70  * Set up the initial value of c->reg.header register based on c->reg.R0.
  71  *
  72  * The following information is passed to the GS thread in R0, and needs to be
  73  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  74  *
  75  * - DWORD 0 [31:0] handle info (Gen4 only)
  76  * - DWORD 5 [7:0] FFTID
  77  * - DWORD 6 [31:0] Debug info
  78  * - DWORD 7 [31:0] Debug info
  79  *
  80  * This function sets up the above data by copying by copying the contents of
  81  * R0 to the header register.
  82  */
  83 static void brw_gs_initialize_header(struct brw_gs_compile *c)
  84 {
  85    struct brw_compile *p = &c->func;
  86    brw_MOV(p, c->reg.header, c->reg.R0);
  87 }
  88
  89 /**
  90  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
  91  *
  92  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
  93  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
  94  * need to be able to update on a per-vertex basis.
  95  */
  96 static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c,
  97                                         unsigned dw2)
  98 {
  99    struct brw_compile *p = &c->func;
 100    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 101 }
 102
 103 /**
 104  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 105  *
 106  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 107  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 108  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 109  * appropriately, and stores it in c->reg.header.
 110  */
 111 static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c)
 112 {
 113    struct brw_compile *p = &c->func;
 114    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 115            brw_imm_ud(0x1f));
 116    brw_SHL(p, get_element_ud(c->reg.header, 2),
 117            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 118 }
 119
 120 /**
 121  * Apply an additive offset to DWORD 2 of c->reg.header.
 122  *
 123  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 124  * for each vertex.
 125  */
 126 static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset)
 127 {
 128    struct brw_compile *p = &c->func;
 129    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 130            brw_imm_d(offset));
 131 }
 132
 133
 134 /**
 135  * Emit a vertex using the URB_WRITE message.  Use the contents of
 136  * c->reg.header for the message header, and the registers starting at \c vert
 137  * for the vertex data.
 138  *
 139  * If \c last is true, then this is the last vertex, so no further URB space
 140  * should be allocated, and this message should end the thread.
 141  *
 142  * If \c last is false, then a new URB entry will be allocated, and its handle
 143  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 144  * message.
 145  */
 146 static void brw_gs_emit_vue(struct brw_gs_compile *c,
 147                             struct brw_reg vert,
 148                             bool last)
 149 {
 150    struct brw_compile *p = &c->func;
 151    bool allocate = !last;
 152
 153    /* Copy the vertex from vertn into m1..mN+1:
 154     */
 155    brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
 156
 157    /* Send each vertex as a seperate write to the urb.  This is
 158     * different to the concept in brw_sf_emit.c, where subsequent
 159     * writes are used to build up a single urb entry.  Each of these
 160     * writes instantiates a seperate urb entry, and a new one must be
 161     * allocated each time.
 162     */
 163    brw_urb_WRITE(p,
 164                  allocate ? c->reg.temp
 165                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 166                  0,
 167                  c->reg.header,
 168                  allocate,
 169                  1,             /* used */
 170                  c->nr_regs + 1, /* msg length */
 171                  allocate ? 1 : 0, /* response length */
 172                  allocate ? 0 : 1, /* eot */
 173                  1,             /* writes_complete */
 174                  0,             /* urb offset */
 175                  BRW_URB_SWIZZLE_NONE);
 176
 177    if (allocate) {
 178       brw_MOV(p, get_element_ud(c->reg.header, 0),
 179               get_element_ud(c->reg.temp, 0));
 180    }
 181 }
 182
 183 /**
 184  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 185  * have finished sending primitives down the pipeline, and to allocate a URB
 186  * entry for the first output vertex.  Only needed when intel->needs_ff_sync
 187  * is true.
 188  *
 189  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 190  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 191  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 192  * follows).
 193  */
 194 static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
 195 {
 196    struct brw_compile *p = &c->func;
 197
 198    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 199    brw_ff_sync(p,
 200                c->reg.temp,
 201                0,
 202                c->reg.header,
 203                1, /* allocate */
 204                1, /* response length */
 205                0 /* eot */);
 206    brw_MOV(p, get_element_ud(c->reg.header, 0),
 207            get_element_ud(c->reg.temp, 0));
 208 }
 209
 210
 211 void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 212 {
 213    struct intel_context *intel = &c->func.brw->intel;
 214
 215    brw_gs_alloc_regs(c, 4);
 216    brw_gs_initialize_header(c);
 217    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 218     * is the PV for quads, but vertex 0 for polygons:
 219     */
 220    if (intel->needs_ff_sync)
 221       brw_gs_ff_sync(c, 1);
 222    brw_gs_overwrite_header_dw2(
 223       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 224           | URB_WRITE_PRIM_START));
 225    if (key->pv_first) {
 226       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 227       brw_gs_overwrite_header_dw2(
 228          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 229       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 230       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 231       brw_gs_overwrite_header_dw2(
 232          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 233              | URB_WRITE_PRIM_END));
 234       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 235    }
 236    else {
 237       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 238       brw_gs_overwrite_header_dw2(
 239          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 240       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 241       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 242       brw_gs_overwrite_header_dw2(
 243          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 244              | URB_WRITE_PRIM_END));
 245       brw_gs_emit_vue(c, c->reg.vertex[2], 1);
 246    }
 247 }
 248
 249 void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 250 {
 251    struct intel_context *intel = &c->func.brw->intel;
 252
 253    brw_gs_alloc_regs(c, 4);
 254    brw_gs_initialize_header(c);
 255
 256    if (intel->needs_ff_sync)
 257       brw_gs_ff_sync(c, 1);
 258    brw_gs_overwrite_header_dw2(
 259       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 260           | URB_WRITE_PRIM_START));
 261    if (key->pv_first) {
 262       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 263       brw_gs_overwrite_header_dw2(
 264          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 265       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 266       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 267       brw_gs_overwrite_header_dw2(
 268          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 269              | URB_WRITE_PRIM_END));
 270       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 271    }
 272    else {
 273       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 274       brw_gs_overwrite_header_dw2(
 275          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 276       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 277       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 278       brw_gs_overwrite_header_dw2(
 279          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 280              | URB_WRITE_PRIM_END));
 281       brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 282    }
 283 }
 284
 285 void brw_gs_lines( struct brw_gs_compile *c )
 286 {
 287    struct intel_context *intel = &c->func.brw->intel;
 288
 289    brw_gs_alloc_regs(c, 2);
 290    brw_gs_initialize_header(c);
 291
 292    if (intel->needs_ff_sync)
 293       brw_gs_ff_sync(c, 1);
 294    brw_gs_overwrite_header_dw2(
 295       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 296           | URB_WRITE_PRIM_START));
 297    brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 298    brw_gs_overwrite_header_dw2(
 299       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 300           | URB_WRITE_PRIM_END));
 301    brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 302 }
 303
 304 /**
 305  * Generate the geometry shader program used on Gen6 to perform stream output
 306  * (transform feedback).
 307  */
 308 void
 309 gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key,
 310                  unsigned num_verts, bool check_edge_flags)
 311 {
 312    struct brw_compile *p = &c->func;
 313
 314    brw_gs_alloc_regs(c, num_verts);
 315    brw_gs_initialize_header(c);
 316
 317    brw_gs_ff_sync(c, 1);
 318
 319    brw_gs_overwrite_header_dw2_from_r0(c);
 320    switch (num_verts) {
 321    case 1:
 322       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 323       brw_gs_emit_vue(c, c->reg.vertex[0], true);
 324       break;
 325    case 2:
 326       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 327       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 328       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 329       brw_gs_emit_vue(c, c->reg.vertex[1], true);
 330       break;
 331    case 3:
 332       if (check_edge_flags) {
 333          /* Only emit vertices 0 and 1 if this is the first triangle of the
 334           * polygon.  Otherwise they are redundant.
 335           */
 336          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 337          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 338                  get_element_ud(c->reg.R0, 2),
 339                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 340          brw_IF(p, BRW_EXECUTE_1);
 341       }
 342       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 343       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 344       brw_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 345       brw_gs_emit_vue(c, c->reg.vertex[1], false);
 346       if (check_edge_flags) {
 347          brw_ENDIF(p);
 348          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 349           * of the polygon.  Otherwise leave the primitive incomplete because
 350           * there are more polygon vertices coming.
 351           */
 352          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 353          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 354                  get_element_ud(c->reg.R0, 2),
 355                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 356          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 357       }
 358       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 359       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 360       brw_gs_emit_vue(c, c->reg.vertex[2], true);
 361       break;
 362    }
 363 }