src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 /**
  46  * Allocate registers for GS.
  47  *
  48  * If sol_program is true, then:
  49  *
  50  * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
  51  *   1 needs to be set aside to hold the streamed vertex buffer indices.
  52  *
  53  * - The thread will need to use the destination_indices register.
  54  */
  55 static void brw_gs_alloc_regs( struct brw_gs_compile *c,
  56                                GLuint nr_verts,
  57                                bool sol_program )
  58 {
  59    GLuint i = 0,j;
  60
  61    /* Register usage is static, precompute here:
  62     */
  63    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  64
  65    /* Streamed vertex buffer indices */
  66    if (sol_program)
  67       c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  68
  69    /* Payload vertices plus space for more generated vertices:
  70     */
  71    for (j = 0; j < nr_verts; j++) {
  72       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  73       i += c->nr_regs;
  74    }
  75
  76    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  77    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  78
  79    if (sol_program) {
  80       c->reg.destination_indices =
  81          retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  82    }
  83
  84    c->prog_data.urb_read_length = c->nr_regs;
  85    c->prog_data.total_grf = i;
  86 }
  87
  88
  89 /**
  90  * Set up the initial value of c->reg.header register based on c->reg.R0.
  91  *
  92  * The following information is passed to the GS thread in R0, and needs to be
  93  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  94  *
  95  * - DWORD 0 [31:0] handle info (Gen4 only)
  96  * - DWORD 5 [7:0] FFTID
  97  * - DWORD 6 [31:0] Debug info
  98  * - DWORD 7 [31:0] Debug info
  99  *
 100  * This function sets up the above data by copying by copying the contents of
 101  * R0 to the header register.
 102  */
 103 static void brw_gs_initialize_header(struct brw_gs_compile *c)
 104 {
 105    struct brw_compile *p = &c->func;
 106    brw_MOV(p, c->reg.header, c->reg.R0);
 107 }
 108
 109 /**
 110  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
 111  *
 112  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
 113  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
 114  * need to be able to update on a per-vertex basis.
 115  */
 116 static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c,
 117                                         unsigned dw2)
 118 {
 119    struct brw_compile *p = &c->func;
 120    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 121 }
 122
 123 /**
 124  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 125  *
 126  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 127  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 128  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 129  * appropriately, and stores it in c->reg.header.
 130  */
 131 static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c)
 132 {
 133    struct brw_compile *p = &c->func;
 134    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 135            brw_imm_ud(0x1f));
 136    brw_SHL(p, get_element_ud(c->reg.header, 2),
 137            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 138 }
 139
 140 /**
 141  * Apply an additive offset to DWORD 2 of c->reg.header.
 142  *
 143  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 144  * for each vertex.
 145  */
 146 static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset)
 147 {
 148    struct brw_compile *p = &c->func;
 149    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 150            brw_imm_d(offset));
 151 }
 152
 153
 154 /**
 155  * Emit a vertex using the URB_WRITE message.  Use the contents of
 156  * c->reg.header for the message header, and the registers starting at \c vert
 157  * for the vertex data.
 158  *
 159  * If \c last is true, then this is the last vertex, so no further URB space
 160  * should be allocated, and this message should end the thread.
 161  *
 162  * If \c last is false, then a new URB entry will be allocated, and its handle
 163  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 164  * message.
 165  */
 166 static void brw_gs_emit_vue(struct brw_gs_compile *c,
 167                             struct brw_reg vert,
 168                             bool last)
 169 {
 170    struct brw_compile *p = &c->func;
 171    bool allocate = !last;
 172
 173    /* Copy the vertex from vertn into m1..mN+1:
 174     */
 175    brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
 176
 177    /* Send each vertex as a seperate write to the urb.  This is
 178     * different to the concept in brw_sf_emit.c, where subsequent
 179     * writes are used to build up a single urb entry.  Each of these
 180     * writes instantiates a seperate urb entry, and a new one must be
 181     * allocated each time.
 182     */
 183    brw_urb_WRITE(p,
 184                  allocate ? c->reg.temp
 185                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 186                  0,
 187                  c->reg.header,
 188                  allocate,
 189                  1,             /* used */
 190                  c->nr_regs + 1, /* msg length */
 191                  allocate ? 1 : 0, /* response length */
 192                  allocate ? 0 : 1, /* eot */
 193                  1,             /* writes_complete */
 194                  0,             /* urb offset */
 195                  BRW_URB_SWIZZLE_NONE);
 196
 197    if (allocate) {
 198       brw_MOV(p, get_element_ud(c->reg.header, 0),
 199               get_element_ud(c->reg.temp, 0));
 200    }
 201 }
 202
 203 /**
 204  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 205  * have finished sending primitives down the pipeline, and to allocate a URB
 206  * entry for the first output vertex.  Only needed when intel->needs_ff_sync
 207  * is true.
 208  *
 209  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 210  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 211  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 212  * follows).
 213  */
 214 static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
 215 {
 216    struct brw_compile *p = &c->func;
 217
 218    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 219    brw_ff_sync(p,
 220                c->reg.temp,
 221                0,
 222                c->reg.header,
 223                1, /* allocate */
 224                1, /* response length */
 225                0 /* eot */);
 226    brw_MOV(p, get_element_ud(c->reg.header, 0),
 227            get_element_ud(c->reg.temp, 0));
 228 }
 229
 230
 231 void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 232 {
 233    struct intel_context *intel = &c->func.brw->intel;
 234
 235    brw_gs_alloc_regs(c, 4, false);
 236    brw_gs_initialize_header(c);
 237    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 238     * is the PV for quads, but vertex 0 for polygons:
 239     */
 240    if (intel->needs_ff_sync)
 241       brw_gs_ff_sync(c, 1);
 242    brw_gs_overwrite_header_dw2(
 243       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 244           | URB_WRITE_PRIM_START));
 245    if (key->pv_first) {
 246       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 247       brw_gs_overwrite_header_dw2(
 248          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 249       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 250       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 251       brw_gs_overwrite_header_dw2(
 252          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 253              | URB_WRITE_PRIM_END));
 254       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 255    }
 256    else {
 257       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 258       brw_gs_overwrite_header_dw2(
 259          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 260       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 261       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 262       brw_gs_overwrite_header_dw2(
 263          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 264              | URB_WRITE_PRIM_END));
 265       brw_gs_emit_vue(c, c->reg.vertex[2], 1);
 266    }
 267 }
 268
 269 void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 270 {
 271    struct intel_context *intel = &c->func.brw->intel;
 272
 273    brw_gs_alloc_regs(c, 4, false);
 274    brw_gs_initialize_header(c);
 275
 276    if (intel->needs_ff_sync)
 277       brw_gs_ff_sync(c, 1);
 278    brw_gs_overwrite_header_dw2(
 279       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 280           | URB_WRITE_PRIM_START));
 281    if (key->pv_first) {
 282       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 283       brw_gs_overwrite_header_dw2(
 284          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 285       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 286       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 287       brw_gs_overwrite_header_dw2(
 288          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 289              | URB_WRITE_PRIM_END));
 290       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 291    }
 292    else {
 293       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 294       brw_gs_overwrite_header_dw2(
 295          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 296       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 297       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 298       brw_gs_overwrite_header_dw2(
 299          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 300              | URB_WRITE_PRIM_END));
 301       brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 302    }
 303 }
 304
 305 void brw_gs_lines( struct brw_gs_compile *c )
 306 {
 307    struct intel_context *intel = &c->func.brw->intel;
 308
 309    brw_gs_alloc_regs(c, 2, false);
 310    brw_gs_initialize_header(c);
 311
 312    if (intel->needs_ff_sync)
 313       brw_gs_ff_sync(c, 1);
 314    brw_gs_overwrite_header_dw2(
 315       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 316           | URB_WRITE_PRIM_START));
 317    brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 318    brw_gs_overwrite_header_dw2(
 319       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 320           | URB_WRITE_PRIM_END));
 321    brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 322 }
 323
 324 /**
 325  * Generate the geometry shader program used on Gen6 to perform stream output
 326  * (transform feedback).
 327  */
 328 void
 329 gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key,
 330                  unsigned num_verts, bool check_edge_flags)
 331 {
 332    struct brw_compile *p = &c->func;
 333    c->prog_data.svbi_postincrement_value = num_verts;
 334
 335    brw_gs_alloc_regs(c, num_verts, true);
 336    brw_gs_initialize_header(c);
 337
 338    if (key->num_transform_feedback_bindings > 0) {
 339       unsigned vertex, binding;
 340       struct brw_reg destination_indices_uw =
 341          vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
 342
 343       /* Note: since we use the binding table to keep track of buffer offsets
 344        * and stride, the GS doesn't need to keep track of a separate pointer
 345        * into each buffer; it uses a single pointer which increments by 1 for
 346        * each vertex.  So we use SVBI0 for this pointer, regardless of whether
 347        * transform feedback is in interleaved or separate attribs mode.
 348        *
 349        * Make sure that the buffers have enough room for all the vertices.
 350        */
 351       brw_ADD(p, get_element_ud(c->reg.temp, 0),
 352                  get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
 353       brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
 354                  get_element_ud(c->reg.temp, 0),
 355                  get_element_ud(c->reg.SVBI, 4));
 356       brw_IF(p, BRW_EXECUTE_1);
 357
 358       /* Compute the destination indices to write to.  Usually we use SVBI[0]
 359        * + (0, 1, 2).  However, for odd-numbered triangles in tristrips, the
 360        * vertices come down the pipeline in reversed winding order, so we need
 361        * to flip the order when writing to the transform feedback buffer.  To
 362        * ensure that flatshading accuracy is preserved, we need to write them
 363        * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
 364        * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
 365        * the last provoking vertex convention.
 366        *
 367        * Note: since brw_imm_v can only be used in instructions in
 368        * packed-word execution mode, and SVBI is a double-word, we need to
 369        * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
 370        * or (1, 0, 2)) to the destination_indices register, and then add SVBI
 371        * using a separate instruction.  Also, since the immediate constant is
 372        * expressed as packed words, and we need to load double-words into
 373        * destination_indices, we need to intersperse zeros to fill the upper
 374        * halves of each double-word.
 375        */
 376       brw_MOV(p, destination_indices_uw,
 377               brw_imm_v(0x00020100)); /* (0, 1, 2) */
 378       if (num_verts == 3) {
 379          /* Get primitive type into temp register. */
 380          brw_AND(p, get_element_ud(c->reg.temp, 0),
 381                  get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
 382
 383          /* Test if primitive type is TRISTRIP_REVERSE.  We need to do this as
 384           * an 8-wide comparison so that the conditional MOV that follows
 385           * moves all 8 words correctly.
 386           */
 387          brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
 388                  get_element_ud(c->reg.temp, 0),
 389                  brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
 390
 391          /* If so, then overwrite destination_indices_uw with the appropriate
 392           * reordering.
 393           */
 394          brw_MOV(p, destination_indices_uw,
 395                  brw_imm_v(key->pv_first ? 0x00010200    /* (0, 2, 1) */
 396                                          : 0x00020001)); /* (1, 0, 2) */
 397          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 398       }
 399       brw_ADD(p, c->reg.destination_indices,
 400               c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
 401
 402       /* For each vertex, generate code to output each varying using the
 403        * appropriate binding table entry.
 404        */
 405       for (vertex = 0; vertex < num_verts; ++vertex) {
 406          /* Set up the correct destination index for this vertex */
 407          brw_MOV(p, get_element_ud(c->reg.header, 5),
 408                  get_element_ud(c->reg.destination_indices, vertex));
 409
 410          for (binding = 0; binding < key->num_transform_feedback_bindings;
 411               ++binding) {
 412             unsigned char varying =
 413                key->transform_feedback_bindings[binding];
 414             unsigned char slot = c->vue_map.varying_to_slot[varying];
 415             /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
 416              *
 417              *   "Prior to End of Thread with a URB_WRITE, the kernel must
 418              *   ensure that all writes are complete by sending the final
 419              *   write as a committed write."
 420              */
 421             bool final_write =
 422                binding == key->num_transform_feedback_bindings - 1 &&
 423                vertex == num_verts - 1;
 424             struct brw_reg vertex_slot = c->reg.vertex[vertex];
 425             vertex_slot.nr += slot / 2;
 426             vertex_slot.subnr = (slot % 2) * 16;
 427             /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 428             vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
 429                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
 430             brw_set_access_mode(p, BRW_ALIGN_16);
 431             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
 432                     retype(vertex_slot, BRW_REGISTER_TYPE_UD));
 433             brw_set_access_mode(p, BRW_ALIGN_1);
 434             brw_svb_write(p,
 435                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
 436                           1, /* msg_reg_nr */
 437                           c->reg.header, /* src0 */
 438                           SURF_INDEX_SOL_BINDING(binding), /* binding_table_index */
 439                           final_write); /* send_commit_msg */
 440          }
 441       }
 442       brw_ENDIF(p);
 443
 444       /* Now, reinitialize the header register from R0 to restore the parts of
 445        * the register that we overwrote while streaming out transform feedback
 446        * data.
 447        */
 448       brw_gs_initialize_header(c);
 449
 450       /* Finally, wait for the write commit to occur so that we can proceed to
 451        * other things safely.
 452        *
 453        * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
 454        *
 455        *   The write commit does not modify the destination register, but
 456        *   merely clears the dependency associated with the destination
 457        *   register. Thus, a simple “mov” instruction using the register as a
 458        *   source is sufficient to wait for the write commit to occur.
 459        */
 460       brw_MOV(p, c->reg.temp, c->reg.temp);
 461    }
 462
 463    brw_gs_ff_sync(c, 1);
 464
 465    brw_gs_overwrite_header_dw2_from_r0(c);
 466    switch (num_verts) {
 467    case 1:
 468       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 469       brw_gs_emit_vue(c, c->reg.vertex[0], true);
 470       break;
 471    case 2:
 472       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 473       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 474       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 475       brw_gs_emit_vue(c, c->reg.vertex[1], true);
 476       break;
 477    case 3:
 478       if (check_edge_flags) {
 479          /* Only emit vertices 0 and 1 if this is the first triangle of the
 480           * polygon.  Otherwise they are redundant.
 481           */
 482          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 483          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 484                  get_element_ud(c->reg.R0, 2),
 485                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 486          brw_IF(p, BRW_EXECUTE_1);
 487       }
 488       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 489       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 490       brw_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 491       brw_gs_emit_vue(c, c->reg.vertex[1], false);
 492       if (check_edge_flags) {
 493          brw_ENDIF(p);
 494          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 495           * of the polygon.  Otherwise leave the primitive incomplete because
 496           * there are more polygon vertices coming.
 497           */
 498          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 499          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 500                  get_element_ud(c->reg.R0, 2),
 501                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 502          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 503       }
 504       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 505       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 506       brw_gs_emit_vue(c, c->reg.vertex[2], true);
 507       break;
 508    }
 509 }