src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 /**
  46  * Allocate registers for GS.
  47  *
  48  * If sol_program is true, then:
  49  *
  50  * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
  51  *   1 needs to be set aside to hold the streamed vertex buffer indices.
  52  *
  53  * - The thread will need to use the destination_indices register.
  54  */
  55 static void brw_gs_alloc_regs( struct brw_gs_compile *c,
  56                                GLuint nr_verts,
  57                                bool sol_program )
  58 {
  59    GLuint i = 0,j;
  60
  61    /* Register usage is static, precompute here:
  62     */
  63    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  64
  65    /* Streamed vertex buffer indices */
  66    if (sol_program)
  67       c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  68
  69    /* Payload vertices plus space for more generated vertices:
  70     */
  71    for (j = 0; j < nr_verts; j++) {
  72       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  73       i += c->nr_regs;
  74    }
  75
  76    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  77    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  78
  79    if (sol_program) {
  80       c->reg.destination_indices =
  81          retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  82    }
  83
  84    c->prog_data.urb_read_length = c->nr_regs;
  85    c->prog_data.total_grf = i;
  86 }
  87
  88
  89 /**
  90  * Set up the initial value of c->reg.header register based on c->reg.R0.
  91  *
  92  * The following information is passed to the GS thread in R0, and needs to be
  93  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  94  *
  95  * - DWORD 0 [31:0] handle info (Gen4 only)
  96  * - DWORD 5 [7:0] FFTID
  97  * - DWORD 6 [31:0] Debug info
  98  * - DWORD 7 [31:0] Debug info
  99  *
 100  * This function sets up the above data by copying by copying the contents of
 101  * R0 to the header register.
 102  */
 103 static void brw_gs_initialize_header(struct brw_gs_compile *c)
 104 {
 105    struct brw_compile *p = &c->func;
 106    brw_MOV(p, c->reg.header, c->reg.R0);
 107 }
 108
 109 /**
 110  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
 111  *
 112  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
 113  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
 114  * need to be able to update on a per-vertex basis.
 115  */
 116 static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c,
 117                                         unsigned dw2)
 118 {
 119    struct brw_compile *p = &c->func;
 120    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 121 }
 122
 123 /**
 124  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 125  *
 126  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 127  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 128  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 129  * appropriately, and stores it in c->reg.header.
 130  */
 131 static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c)
 132 {
 133    struct brw_compile *p = &c->func;
 134    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 135            brw_imm_ud(0x1f));
 136    brw_SHL(p, get_element_ud(c->reg.header, 2),
 137            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 138 }
 139
 140 /**
 141  * Apply an additive offset to DWORD 2 of c->reg.header.
 142  *
 143  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 144  * for each vertex.
 145  */
 146 static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset)
 147 {
 148    struct brw_compile *p = &c->func;
 149    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 150            brw_imm_d(offset));
 151 }
 152
 153
 154 /**
 155  * Emit a vertex using the URB_WRITE message.  Use the contents of
 156  * c->reg.header for the message header, and the registers starting at \c vert
 157  * for the vertex data.
 158  *
 159  * If \c last is true, then this is the last vertex, so no further URB space
 160  * should be allocated, and this message should end the thread.
 161  *
 162  * If \c last is false, then a new URB entry will be allocated, and its handle
 163  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 164  * message.
 165  */
 166 static void brw_gs_emit_vue(struct brw_gs_compile *c,
 167                             struct brw_reg vert,
 168                             bool last)
 169 {
 170    struct brw_compile *p = &c->func;
 171    bool allocate = !last;
 172
 173    /* Copy the vertex from vertn into m1..mN+1:
 174     */
 175    brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
 176
 177    /* Send each vertex as a seperate write to the urb.  This is
 178     * different to the concept in brw_sf_emit.c, where subsequent
 179     * writes are used to build up a single urb entry.  Each of these
 180     * writes instantiates a seperate urb entry, and a new one must be
 181     * allocated each time.
 182     */
 183    brw_urb_WRITE(p,
 184                  allocate ? c->reg.temp
 185                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 186                  0,
 187                  c->reg.header,
 188                  allocate ? BRW_URB_WRITE_ALLOCATE_COMPLETE
 189                           : BRW_URB_WRITE_EOT_COMPLETE,
 190                  c->nr_regs + 1, /* msg length */
 191                  allocate ? 1 : 0, /* response length */
 192                  0,             /* urb offset */
 193                  BRW_URB_SWIZZLE_NONE);
 194
 195    if (allocate) {
 196       brw_MOV(p, get_element_ud(c->reg.header, 0),
 197               get_element_ud(c->reg.temp, 0));
 198    }
 199 }
 200
 201 /**
 202  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 203  * have finished sending primitives down the pipeline, and to allocate a URB
 204  * entry for the first output vertex.  Only needed on Ironlake+.
 205  *
 206  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 207  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 208  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 209  * follows).
 210  */
 211 static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
 212 {
 213    struct brw_compile *p = &c->func;
 214
 215    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 216    brw_ff_sync(p,
 217                c->reg.temp,
 218                0,
 219                c->reg.header,
 220                1, /* allocate */
 221                1, /* response length */
 222                0 /* eot */);
 223    brw_MOV(p, get_element_ud(c->reg.header, 0),
 224            get_element_ud(c->reg.temp, 0));
 225 }
 226
 227
 228 void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 229 {
 230    struct brw_context *brw = c->func.brw;
 231
 232    brw_gs_alloc_regs(c, 4, false);
 233    brw_gs_initialize_header(c);
 234    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 235     * is the PV for quads, but vertex 0 for polygons:
 236     */
 237    if (brw->gen == 5)
 238       brw_gs_ff_sync(c, 1);
 239    brw_gs_overwrite_header_dw2(
 240       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 241           | URB_WRITE_PRIM_START));
 242    if (key->pv_first) {
 243       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 244       brw_gs_overwrite_header_dw2(
 245          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 246       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 247       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 248       brw_gs_overwrite_header_dw2(
 249          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 250              | URB_WRITE_PRIM_END));
 251       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 252    }
 253    else {
 254       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 255       brw_gs_overwrite_header_dw2(
 256          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 257       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 258       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 259       brw_gs_overwrite_header_dw2(
 260          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 261              | URB_WRITE_PRIM_END));
 262       brw_gs_emit_vue(c, c->reg.vertex[2], 1);
 263    }
 264 }
 265
 266 void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 267 {
 268    struct brw_context *brw = c->func.brw;
 269
 270    brw_gs_alloc_regs(c, 4, false);
 271    brw_gs_initialize_header(c);
 272
 273    if (brw->gen == 5)
 274       brw_gs_ff_sync(c, 1);
 275    brw_gs_overwrite_header_dw2(
 276       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 277           | URB_WRITE_PRIM_START));
 278    if (key->pv_first) {
 279       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 280       brw_gs_overwrite_header_dw2(
 281          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 282       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 283       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 284       brw_gs_overwrite_header_dw2(
 285          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 286              | URB_WRITE_PRIM_END));
 287       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 288    }
 289    else {
 290       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 291       brw_gs_overwrite_header_dw2(
 292          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 293       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 294       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 295       brw_gs_overwrite_header_dw2(
 296          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 297              | URB_WRITE_PRIM_END));
 298       brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 299    }
 300 }
 301
 302 void brw_gs_lines( struct brw_gs_compile *c )
 303 {
 304    struct brw_context *brw = c->func.brw;
 305
 306    brw_gs_alloc_regs(c, 2, false);
 307    brw_gs_initialize_header(c);
 308
 309    if (brw->gen == 5)
 310       brw_gs_ff_sync(c, 1);
 311    brw_gs_overwrite_header_dw2(
 312       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 313           | URB_WRITE_PRIM_START));
 314    brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 315    brw_gs_overwrite_header_dw2(
 316       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 317           | URB_WRITE_PRIM_END));
 318    brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 319 }
 320
 321 /**
 322  * Generate the geometry shader program used on Gen6 to perform stream output
 323  * (transform feedback).
 324  */
 325 void
 326 gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key,
 327                  unsigned num_verts, bool check_edge_flags)
 328 {
 329    struct brw_compile *p = &c->func;
 330    c->prog_data.svbi_postincrement_value = num_verts;
 331
 332    brw_gs_alloc_regs(c, num_verts, true);
 333    brw_gs_initialize_header(c);
 334
 335    if (key->num_transform_feedback_bindings > 0) {
 336       unsigned vertex, binding;
 337       struct brw_reg destination_indices_uw =
 338          vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
 339
 340       /* Note: since we use the binding table to keep track of buffer offsets
 341        * and stride, the GS doesn't need to keep track of a separate pointer
 342        * into each buffer; it uses a single pointer which increments by 1 for
 343        * each vertex.  So we use SVBI0 for this pointer, regardless of whether
 344        * transform feedback is in interleaved or separate attribs mode.
 345        *
 346        * Make sure that the buffers have enough room for all the vertices.
 347        */
 348       brw_ADD(p, get_element_ud(c->reg.temp, 0),
 349                  get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
 350       brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
 351                  get_element_ud(c->reg.temp, 0),
 352                  get_element_ud(c->reg.SVBI, 4));
 353       brw_IF(p, BRW_EXECUTE_1);
 354
 355       /* Compute the destination indices to write to.  Usually we use SVBI[0]
 356        * + (0, 1, 2).  However, for odd-numbered triangles in tristrips, the
 357        * vertices come down the pipeline in reversed winding order, so we need
 358        * to flip the order when writing to the transform feedback buffer.  To
 359        * ensure that flatshading accuracy is preserved, we need to write them
 360        * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
 361        * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
 362        * the last provoking vertex convention.
 363        *
 364        * Note: since brw_imm_v can only be used in instructions in
 365        * packed-word execution mode, and SVBI is a double-word, we need to
 366        * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
 367        * or (1, 0, 2)) to the destination_indices register, and then add SVBI
 368        * using a separate instruction.  Also, since the immediate constant is
 369        * expressed as packed words, and we need to load double-words into
 370        * destination_indices, we need to intersperse zeros to fill the upper
 371        * halves of each double-word.
 372        */
 373       brw_MOV(p, destination_indices_uw,
 374               brw_imm_v(0x00020100)); /* (0, 1, 2) */
 375       if (num_verts == 3) {
 376          /* Get primitive type into temp register. */
 377          brw_AND(p, get_element_ud(c->reg.temp, 0),
 378                  get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
 379
 380          /* Test if primitive type is TRISTRIP_REVERSE.  We need to do this as
 381           * an 8-wide comparison so that the conditional MOV that follows
 382           * moves all 8 words correctly.
 383           */
 384          brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
 385                  get_element_ud(c->reg.temp, 0),
 386                  brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
 387
 388          /* If so, then overwrite destination_indices_uw with the appropriate
 389           * reordering.
 390           */
 391          brw_MOV(p, destination_indices_uw,
 392                  brw_imm_v(key->pv_first ? 0x00010200    /* (0, 2, 1) */
 393                                          : 0x00020001)); /* (1, 0, 2) */
 394          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 395       }
 396       brw_ADD(p, c->reg.destination_indices,
 397               c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
 398
 399       /* For each vertex, generate code to output each varying using the
 400        * appropriate binding table entry.
 401        */
 402       for (vertex = 0; vertex < num_verts; ++vertex) {
 403          /* Set up the correct destination index for this vertex */
 404          brw_MOV(p, get_element_ud(c->reg.header, 5),
 405                  get_element_ud(c->reg.destination_indices, vertex));
 406
 407          for (binding = 0; binding < key->num_transform_feedback_bindings;
 408               ++binding) {
 409             unsigned char varying =
 410                key->transform_feedback_bindings[binding];
 411             unsigned char slot = c->vue_map.varying_to_slot[varying];
 412             /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
 413              *
 414              *   "Prior to End of Thread with a URB_WRITE, the kernel must
 415              *   ensure that all writes are complete by sending the final
 416              *   write as a committed write."
 417              */
 418             bool final_write =
 419                binding == key->num_transform_feedback_bindings - 1 &&
 420                vertex == num_verts - 1;
 421             struct brw_reg vertex_slot = c->reg.vertex[vertex];
 422             vertex_slot.nr += slot / 2;
 423             vertex_slot.subnr = (slot % 2) * 16;
 424             /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 425             vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
 426                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
 427             brw_set_access_mode(p, BRW_ALIGN_16);
 428             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
 429                     retype(vertex_slot, BRW_REGISTER_TYPE_UD));
 430             brw_set_access_mode(p, BRW_ALIGN_1);
 431             brw_svb_write(p,
 432                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
 433                           1, /* msg_reg_nr */
 434                           c->reg.header, /* src0 */
 435                           SURF_INDEX_SOL_BINDING(binding), /* binding_table_index */
 436                           final_write); /* send_commit_msg */
 437          }
 438       }
 439       brw_ENDIF(p);
 440
 441       /* Now, reinitialize the header register from R0 to restore the parts of
 442        * the register that we overwrote while streaming out transform feedback
 443        * data.
 444        */
 445       brw_gs_initialize_header(c);
 446
 447       /* Finally, wait for the write commit to occur so that we can proceed to
 448        * other things safely.
 449        *
 450        * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
 451        *
 452        *   The write commit does not modify the destination register, but
 453        *   merely clears the dependency associated with the destination
 454        *   register. Thus, a simple “mov” instruction using the register as a
 455        *   source is sufficient to wait for the write commit to occur.
 456        */
 457       brw_MOV(p, c->reg.temp, c->reg.temp);
 458    }
 459
 460    brw_gs_ff_sync(c, 1);
 461
 462    brw_gs_overwrite_header_dw2_from_r0(c);
 463    switch (num_verts) {
 464    case 1:
 465       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 466       brw_gs_emit_vue(c, c->reg.vertex[0], true);
 467       break;
 468    case 2:
 469       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 470       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 471       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 472       brw_gs_emit_vue(c, c->reg.vertex[1], true);
 473       break;
 474    case 3:
 475       if (check_edge_flags) {
 476          /* Only emit vertices 0 and 1 if this is the first triangle of the
 477           * polygon.  Otherwise they are redundant.
 478           */
 479          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 480          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 481                  get_element_ud(c->reg.R0, 2),
 482                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 483          brw_IF(p, BRW_EXECUTE_1);
 484       }
 485       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 486       brw_gs_emit_vue(c, c->reg.vertex[0], false);
 487       brw_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 488       brw_gs_emit_vue(c, c->reg.vertex[1], false);
 489       if (check_edge_flags) {
 490          brw_ENDIF(p);
 491          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 492           * of the polygon.  Otherwise leave the primitive incomplete because
 493           * there are more polygon vertices coming.
 494           */
 495          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 496          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 497                  get_element_ud(c->reg.R0, 2),
 498                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 499          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 500       }
 501       brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 502       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 503       brw_gs_emit_vue(c, c->reg.vertex[2], true);
 504       break;
 505    }
 506 }