src/mesa/drivers/dri/i965/brw_inst.h

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_inst.h
  26  *
  27  * A representation of i965 EU assembly instructions, with helper methods to
  28  * get and set various fields.  This is the actual hardware format.
  29  */
  30
  31 #ifndef BRW_INST_H
  32 #define BRW_INST_H
  33
  34 #include <stdint.h>
  35
  36 #include "brw_context.h"
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 struct brw_instruction;
  43
  44 typedef struct {
  45    uint64_t data[2];
  46 } brw_inst;
  47
  48 static inline uint64_t brw_inst_bits(struct brw_instruction *inst,
  49                                      unsigned high, unsigned low);
  50 static inline void brw_inst_set_bits(struct brw_instruction *inst,
  51                                      unsigned high, unsigned low,
  52                                      uint64_t value);
  53
  54 #define FC(name, high, low, assertions)                       \
  55 static inline void                                            \
  56 brw_inst_set_##name(const struct brw_context *brw,            \
  57                     struct brw_instruction *inst, uint64_t v) \
  58 {                                                             \
  59    assert(assertions);                                        \
  60    brw_inst_set_bits(inst, high, low, v);                     \
  61 }                                                             \
  62 static inline uint64_t                                        \
  63 brw_inst_##name(const struct brw_context *brw,                \
  64                 struct brw_instruction *inst)                 \
  65 {                                                             \
  66    assert(assertions);                                        \
  67    return brw_inst_bits(inst, high, low);                     \
  68 }
  69
  70 /* A simple macro for fields which stay in the same place on all generations. */
  71 #define F(name, high, low) FC(name, high, low, true)
  72
  73 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
  74    unsigned high, low;                                                       \
  75    if (brw->gen >= 8) {                                                      \
  76       high = hi8;  low = lo8;                                                \
  77    } else if (brw->gen >= 7) {                                               \
  78       high = hi7;  low = lo7;                                                \
  79    } else if (brw->gen >= 6) {                                               \
  80       high = hi6;  low = lo6;                                                \
  81    } else if (brw->gen >= 5) {                                               \
  82       high = hi5;  low = lo5;                                                \
  83    } else if (brw->is_g4x) {                                                 \
  84       high = hi45; low = lo45;                                               \
  85    } else {                                                                  \
  86       high = hi4;  low = lo4;                                                \
  87    }                                                                         \
  88    assert(((int) high) != -1 && ((int) low) != -1);                          \
  89
  90 /* A general macro for cases where the field has moved to several different
  91  * bit locations across generations.  GCC appears to combine cases where the
  92  * bits are identical, removing some of the inefficiency.
  93  */
  94 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
  95 static inline void                                                            \
  96 brw_inst_set_##name(const struct brw_context *brw,                            \
  97                     struct brw_instruction *inst, uint64_t value)             \
  98 {                                                                             \
  99    BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)       \
 100    brw_inst_set_bits(inst, high, low, value);                                 \
 101 }                                                                             \
 102 static inline uint64_t                                                        \
 103 brw_inst_##name(const struct brw_context *brw, struct brw_instruction *inst)  \
 104 {                                                                             \
 105    BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)       \
 106    return brw_inst_bits(inst, high, low);                                     \
 107 }
 108
 109 /* A macro for fields which moved as of Gen8+. */
 110 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
 111 FF(name,                                                   \
 112    /* 4:   */ gen4_high, gen4_low,                         \
 113    /* 4.5: */ gen4_high, gen4_low,                         \
 114    /* 5:   */ gen4_high, gen4_low,                         \
 115    /* 6:   */ gen4_high, gen4_low,                         \
 116    /* 7:   */ gen4_high, gen4_low,                         \
 117    /* 8:   */ gen8_high, gen8_low);
 118
 119 F(src1_vstride,        120, 117)
 120 F(src1_width,          116, 114)
 121 F(src1_da16_swiz_w,    115, 114)
 122 F(src1_da16_swiz_z,    113, 112)
 123 F(src1_hstride,        113, 112)
 124 F(src1_address_mode,   111, 111)
 125 /** Src1.SrcMod @{ */
 126 F(src1_negate,         110, 110)
 127 F(src1_abs,            109, 109)
 128 /** @} */
 129 F8(src1_ia_subreg_nr,  /* 4+ */ 108, 106, /* 8+ */ 108, 105)
 130 F(src1_da_reg_nr,      108, 101)
 131 F(src1_da16_subreg_nr, 100, 100)
 132 F(src1_da1_subreg_nr,  100,  96)
 133 F(src1_da16_swiz_y,     99,  98)
 134 F(src1_da16_swiz_x,     97,  96)
 135 F8(src1_reg_type,      /* 4+ */  46,  44, /* 8+ */  94,  91)
 136 F8(src1_reg_file,      /* 4+ */  43,  42, /* 8+ */  90,  89)
 137 F(src0_vstride,         88,  85)
 138 F(src0_width,           84,  82)
 139 F(src0_da16_swiz_w,     83,  82)
 140 F(src0_da16_swiz_z,     81,  80)
 141 F(src0_hstride,         81,  80)
 142 F(src0_address_mode,    79,  79)
 143 /** Src0.SrcMod @{ */
 144 F(src0_negate,          78,  78)
 145 F(src0_abs,             77,  77)
 146 /** @} */
 147 F8(src0_ia_subreg_nr,  /* 4+ */  76,  74, /* 8+ */  76,  73)
 148 F(src0_da_reg_nr,       76,  69)
 149 F(src0_da16_subreg_nr,  68,  68)
 150 F(src0_da1_subreg_nr,   68,  64)
 151 F(src0_da16_swiz_y,     67,  66)
 152 F(src0_da16_swiz_x,     65,  64)
 153 F(dst_address_mode,     63,  63)
 154 F(dst_hstride,          62,  61)
 155 F8(dst_ia_subreg_nr,   /* 4+ */  60,  58, /* 8+ */  60,  57)
 156 F(dst_da_reg_nr,        60,  53)
 157 F(dst_da16_subreg_nr,   52,  52)
 158 F(dst_da1_subreg_nr,    52,  48)
 159 F(da16_writemask,       51,  48) /* Dst.ChanEn */
 160 F8(src0_reg_type,      /* 4+ */  41,  39, /* 8+ */  46,  43)
 161 F8(src0_reg_file,      /* 4+ */  38,  37, /* 8+ */  42,  41)
 162 F8(dst_reg_type,       /* 4+ */  36,  34, /* 8+ */  40,  37)
 163 F8(dst_reg_file,       /* 4+ */  33,  32, /* 8+ */  36,  35)
 164 F8(mask_control,       /* 4+ */   9,   9, /* 8+ */  34,  34)
 165 FF(flag_reg_nr,
 166    /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
 167    /* 7: */ 90, 90,
 168    /* 8: */ 33, 33)
 169 F8(flag_subreg_nr,     /* 4+ */  89, 89, /* 8+ */ 32, 32)
 170 F(saturate,             31,  31)
 171 FC(branch_control,      30,  30, brw->gen >= 8)
 172 F(debug_control,        30,  30)
 173 F(cmpt_control,         29,  29)
 174 F(acc_wr_control,       28,  28)
 175 F(cond_modifier,        27,  24)
 176 FC(math_function,       27,  24, brw->gen >= 6)
 177 F(exec_size,            23,  21)
 178 F(pred_inv,             20,  20)
 179 F(pred_control,         19,  16)
 180 F(thread_control,       15,  14)
 181 F(qtr_control,          13,  12)
 182 FF(nib_control,
 183    /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
 184    /* 7: */ 47, 47,
 185    /* 8: */ 11, 11)
 186 F8(no_dd_check,        /* 4+ */  11, 11, /* 8+ */  10,  10)
 187 F8(no_dd_clear,        /* 4+ */  10, 10, /* 8+ */   9,   9)
 188 F(access_mode,           8,   8)
 189 /* Bit 7 is Reserved (for future Opcode expansion) */
 190 F(opcode,                6,   0)
 191
 192 /**
 193  * Three-source instructions:
 194  *  @{
 195  */
 196 F(3src_src2_reg_nr,    125, 118)
 197 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
 198 F(3src_src2_swizzle,   114, 107)
 199 F(3src_src2_rep_ctrl,  106, 106)
 200 F(3src_src1_reg_nr,    104,  97)
 201 F(3src_src1_subreg_nr,  96,  94) /* Extra discontiguous bit on CHV? */
 202 F(3src_src1_swizzle,    93,  86)
 203 F(3src_src1_rep_ctrl,   85,  85)
 204 F(3src_src0_reg_nr,     83,  76)
 205 F(3src_src0_subreg_nr,  75,  73) /* Extra discontiguous bit on CHV? */
 206 F(3src_src0_swizzle,    72,  65)
 207 F(3src_src0_rep_ctrl,   64,  64)
 208 F(3src_dst_reg_nr,      63,  56)
 209 F(3src_dst_subreg_nr,   55,  53)
 210 F(3src_dst_writemask,   52,  49)
 211 F8(3src_nib_ctrl,       47, 47, 11, 11) /* only exists on IVB+ */
 212 F8(3src_dst_type,       45, 44, 48, 46) /* only exists on IVB+ */
 213 F8(3src_src_type,       43, 42, 45, 43)
 214 F8(3src_src2_negate,    41, 41, 42, 42)
 215 F8(3src_src2_abs,       40, 40, 41, 41)
 216 F8(3src_src1_negate,    39, 39, 40, 40)
 217 F8(3src_src1_abs,       38, 38, 39, 39)
 218 F8(3src_src0_negate,    37, 37, 38, 38)
 219 F8(3src_src0_abs,       36, 36, 37, 37)
 220 F8(3src_flag_reg_nr,    34, 34, 33, 33)
 221 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
 222 FF(3src_dst_reg_file,
 223    /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
 224    /* 6: */ 32, 32,
 225    /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
 226 F(3src_saturate,        31, 31)
 227 F(3src_debug_control,   30, 30)
 228 F(3src_cmpt_control,    29, 29)
 229 F(3src_acc_wr_control,  28, 28)
 230 F(3src_cond_modifier,   27, 24)
 231 F(3src_exec_size,       23, 21)
 232 F(3src_pred_inv,        20, 20)
 233 F(3src_pred_control,    19, 16)
 234 F(3src_thread_control,  15, 14)
 235 F(3src_qtr_control,     13, 12)
 236 F8(3src_no_dd_check,    11, 11, 10, 10)
 237 F8(3src_no_dd_clear,    10, 10,  9,  9)
 238 F8(3src_mask_control,    9,  9, 34, 34)
 239 F(3src_access_mode,      8,  8)
 240 /* Bit 7 is Reserved (for future Opcode expansion) */
 241 F(3src_opcode,           6,  0)
 242 /** @} */
 243
 244 /**
 245  * Flow control instruction bits:
 246  *  @{
 247  */
 248 static inline void
 249 brw_inst_set_uip(const struct brw_context *brw,
 250                  struct brw_instruction *inst, int32_t value)
 251 {
 252    assert(brw->gen >= 6);
 253
 254    if (brw->gen >= 8) {
 255       brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
 256    } else {
 257       assert(value <= (1 << 16) - 1);
 258       assert(value > -(1 << 16));
 259       brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
 260    }
 261 }
 262
 263 static inline int32_t
 264 brw_inst_uip(const struct brw_context *brw, struct brw_instruction *inst)
 265 {
 266    assert(brw->gen >= 6);
 267
 268    if (brw->gen >= 8) {
 269       return brw_inst_bits(inst, 95, 64);
 270    } else {
 271       return (int16_t)brw_inst_bits(inst, 127, 112);
 272    }
 273 }
 274
 275 static inline void
 276 brw_inst_set_jip(const struct brw_context *brw,
 277                  struct brw_instruction *inst, int32_t value)
 278 {
 279    assert(brw->gen >= 6);
 280
 281    if (brw->gen >= 8) {
 282       brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
 283    } else {
 284       assert(value <= (1 << 16) - 1);
 285       assert(value > -(1 << 16));
 286       brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
 287    }
 288 }
 289
 290 static inline int32_t
 291 brw_inst_jip(const struct brw_context *brw, struct brw_instruction *inst)
 292 {
 293    assert(brw->gen >= 6);
 294
 295    if (brw->gen >= 8) {
 296       return brw_inst_bits(inst, 127, 96);
 297    } else {
 298       return (int16_t)brw_inst_bits(inst, 111, 96);
 299    }
 300 }
 301
 302 /** Like FC, but using int16_t to handle negative jump targets. */
 303 #define FJ(name, high, low, assertions)                                       \
 304 static inline void                                                            \
 305 brw_inst_set_##name(const struct brw_context *brw, brw_inst *inst, int16_t v) \
 306 {                                                                             \
 307    assert(assertions);                                                        \
 308    assert(v <= (1 << 16) - 1);                                                \
 309    assert(v > -(1 << 16));                                                    \
 310    brw_inst_set_bits(inst, high, low, (uint16_t) v);                          \
 311 }                                                                             \
 312 static inline int16_t                                                         \
 313 brw_inst_##name(const struct brw_context *brw, brw_inst *inst)                \
 314 {                                                                             \
 315    assert(assertions);                                                        \
 316    return brw_inst_bits(inst, high, low);                                     \
 317 }
 318
 319 FJ(gen6_jump_count,  63,  48, brw->gen == 6)
 320 FJ(gen4_jump_count, 111,  96, brw->gen < 6)
 321 FC(gen4_pop_count,  115, 112, brw->gen < 6)
 322 /** @} */
 323
 324 /**
 325  * Fields for SEND messages:
 326  *  @{
 327  */
 328 F(eot,                 127, 127)
 329 FF(mlen,
 330    /* 4:   */ 119, 116,
 331    /* 4.5: */ 119, 116,
 332    /* 5:   */ 124, 121,
 333    /* 6:   */ 124, 121,
 334    /* 7:   */ 124, 121,
 335    /* 8:   */ 124, 121);
 336 FF(rlen,
 337    /* 4:   */ 115, 112,
 338    /* 4.5: */ 115, 112,
 339    /* 5:   */ 120, 116,
 340    /* 6:   */ 120, 116,
 341    /* 7:   */ 120, 116,
 342    /* 8:   */ 120, 116);
 343 FF(header_present,
 344    /* 4: doesn't exist */ -1, -1, -1, -1,
 345    /* 5:   */ 115, 115,
 346    /* 6:   */ 115, 115,
 347    /* 7:   */ 115, 115,
 348    /* 8:   */ 115, 115)
 349 FF(function_control,
 350    /* 4:   */ 111,  96,
 351    /* 4.5: */ 111,  96,
 352    /* 5:   */ 114,  96,
 353    /* 6:   */ 114,  96,
 354    /* 7:   */ 114,  96,
 355    /* 8:   */ 114,  96)
 356 FF(sfid,
 357    /* 4:   */ 123, 120, /* called msg_target */
 358    /* 4.5  */ 123, 120,
 359    /* 5:   */  95,  92,
 360    /* 6:   */  27,  24,
 361    /* 7:   */  27,  24,
 362    /* 8:   */  27,  24)
 363 FC(base_mrf,   27,  24, brw->gen < 6);
 364 /** @} */
 365
 366 /* Message descriptor bits */
 367 #define MD(x) (x + 96)
 368
 369 /**
 370  * URB message function control bits:
 371  *  @{
 372  */
 373 FF(urb_per_slot_offset,
 374    /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
 375    /* 7:   */ MD(16), MD(16),
 376    /* 8:   */ MD(17), MD(17))
 377 FC(urb_complete, MD(15), MD(15), brw->gen < 8)
 378 FC(urb_used, MD(14), MD(14), brw->gen < 7)
 379 FC(urb_allocate, MD(13), MD(13), brw->gen < 7)
 380 FF(urb_swizzle_control,
 381    /* 4:   */ MD(11), MD(10),
 382    /* 4.5: */ MD(11), MD(10),
 383    /* 5:   */ MD(11), MD(10),
 384    /* 6:   */ MD(11), MD(10),
 385    /* 7:   */ MD(14), MD(14),
 386    /* 8:   */ MD(15), MD(15))
 387 FF(urb_global_offset,
 388    /* 4:   */ MD( 9), MD(4),
 389    /* 4.5: */ MD( 9), MD(4),
 390    /* 5:   */ MD( 9), MD(4),
 391    /* 6:   */ MD( 9), MD(4),
 392    /* 7:   */ MD(13), MD(3),
 393    /* 8:   */ MD(14), MD(4))
 394 FF(urb_opcode,
 395    /* 4:   */ MD( 3), MD(0),
 396    /* 4.5: */ MD( 3), MD(0),
 397    /* 5:   */ MD( 3), MD(0),
 398    /* 6:   */ MD( 3), MD(0),
 399    /* 7:   */ MD( 2), MD(0),
 400    /* 8:   */ MD( 3), MD(0))
 401 /** @} */
 402
 403 /**
 404  * Gen4-5 math messages:
 405  *  @{
 406  */
 407 FC(math_msg_data_type,  MD(7), MD(7), brw->gen < 6)
 408 FC(math_msg_saturate,   MD(6), MD(6), brw->gen < 6)
 409 FC(math_msg_precision,  MD(5), MD(5), brw->gen < 6)
 410 FC(math_msg_signed_int, MD(4), MD(4), brw->gen < 6)
 411 FC(math_msg_function,   MD(3), MD(0), brw->gen < 6)
 412 /** @} */
 413
 414 /**
 415  * Sampler message function control bits:
 416  *  @{
 417  */
 418 FF(sampler_simd_mode,
 419    /* 4: doesn't exist */ -1, -1, -1, -1,
 420    /* 5:   */ MD(17), MD(16),
 421    /* 6:   */ MD(17), MD(16),
 422    /* 7:   */ MD(18), MD(17),
 423    /* 8:   */ MD(18), MD(17))
 424 FF(sampler_msg_type,
 425    /* 4:   */ MD(15), MD(14),
 426    /* 4.5: */ MD(15), MD(12),
 427    /* 5:   */ MD(15), MD(12),
 428    /* 6:   */ MD(15), MD(12),
 429    /* 7:   */ MD(16), MD(12),
 430    /* 8:   */ MD(16), MD(12))
 431 FC(sampler_return_format, MD(13), MD(12), brw->gen == 4 && !brw->is_g4x)
 432 F(sampler,                MD(11), MD(8))
 433 F(binding_table_index,    MD( 7), MD(0)) /* also used by other messages */
 434 /** @} */
 435
 436 /**
 437  * Data port message function control bits:
 438  *  @{
 439  */
 440 FC(dp_category,         MD(18), MD(18), brw->gen >= 7)
 441
 442 /* Gen4-5 store fields in different bits for read/write messages. */
 443 FF(dp_read_msg_type,
 444    /* 4:   */ MD(13), MD(12),
 445    /* 4.5: */ MD(13), MD(11),
 446    /* 5:   */ MD(13), MD(11),
 447    /* 6:   */ MD(16), MD(13),
 448    /* 7:   */ MD(17), MD(14),
 449    /* 8:   */ MD(17), MD(14))
 450 FF(dp_write_msg_type,
 451    /* 4:   */ MD(14), MD(12),
 452    /* 4.5: */ MD(14), MD(12),
 453    /* 5:   */ MD(14), MD(12),
 454    /* 6:   */ MD(16), MD(13),
 455    /* 7:   */ MD(17), MD(14),
 456    /* 8:   */ MD(17), MD(14))
 457 FF(dp_read_msg_control,
 458    /* 4:   */ MD(11), MD( 8),
 459    /* 4.5: */ MD(10), MD( 8),
 460    /* 5:   */ MD(10), MD( 8),
 461    /* 6:   */ MD(12), MD( 8),
 462    /* 7:   */ MD(13), MD( 8),
 463    /* 8:   */ MD(13), MD( 8))
 464 FF(dp_write_msg_control,
 465    /* 4:   */ MD(11), MD( 8),
 466    /* 4.5: */ MD(11), MD( 8),
 467    /* 5:   */ MD(11), MD( 8),
 468    /* 6:   */ MD(12), MD( 8),
 469    /* 7:   */ MD(13), MD( 8),
 470    /* 8:   */ MD(13), MD( 8))
 471 FC(dp_read_target_cache, MD(15), MD(14), brw->gen < 6);
 472
 473 FF(dp_write_commit,
 474    /* 4:   */ MD(15),  MD(15),
 475    /* 4.5: */ MD(15),  MD(15),
 476    /* 5:   */ MD(15),  MD(15),
 477    /* 6:   */ MD(17),  MD(17),
 478    /* 7+: does not exist */ -1, -1, -1, -1)
 479
 480 /* Gen6+ use the same bit locations for everything. */
 481 FF(dp_msg_type,
 482    /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
 483    -1, -1, -1, -1, -1, -1,
 484    /* 6:   */ MD(16), MD(13),
 485    /* 7:   */ MD(17), MD(14),
 486    /* 8:   */ MD(17), MD(14))
 487 FF(dp_msg_control,
 488    /* 4:   */ MD(11), MD( 8),
 489    /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
 490    /* 6:   */ MD(12), MD( 8),
 491    /* 7:   */ MD(13), MD( 8),
 492    /* 8:   */ MD(13), MD( 8))
 493 /** @} */
 494
 495 /**
 496  * Scratch message bits (Gen7+):
 497  *  @{
 498  */
 499 FC(scratch_read_write, MD(17), MD(17), brw->gen >= 7) /* 0 = read,  1 = write */
 500 FC(scratch_type,       MD(16), MD(16), brw->gen >= 7) /* 0 = OWord, 1 = DWord */
 501 FC(scratch_invalidate_after_read, MD(15), MD(15), brw->gen >= 7)
 502 FC(scratch_block_size,  MD(13),  MD(12), brw->gen >= 7)
 503 FC(scratch_addr_offset, MD(11),  MD( 0), brw->gen >= 7)
 504 /** @} */
 505
 506 /**
 507  * Render Target message function control bits:
 508  *  @{
 509  */
 510 FF(rt_last,
 511    /* 4:   */ MD(11), MD(11),
 512    /* 4.5: */ MD(11), MD(11),
 513    /* 5:   */ MD(11), MD(11),
 514    /* 6:   */ MD(12), MD(12),
 515    /* 7:   */ MD(12), MD(12),
 516    /* 8:   */ MD(12), MD(12))
 517 FC(rt_slot_group,      MD(11),  MD(11), brw->gen >= 6)
 518 F(rt_message_type,     MD(10),  MD( 8))
 519 /** @} */
 520
 521 /**
 522  * Thread Spawn message function control bits:
 523  *  @{
 524  */
 525 F(ts_resource_select,  MD( 4),  MD( 4))
 526 F(ts_request_type,     MD( 1),  MD( 1))
 527 F(ts_opcode,           MD( 0),  MD( 0))
 528 /** @} */
 529
 530 /**
 531  * Immediates:
 532  *  @{
 533  */
 534 static inline int
 535 brw_inst_imm_d(const struct brw_context *brw, struct brw_instruction *insn)
 536 {
 537    return brw_inst_bits(insn, 127, 96);
 538 }
 539
 540 static inline unsigned
 541 brw_inst_imm_ud(const struct brw_context *brw, struct brw_instruction *insn)
 542 {
 543    return brw_inst_bits(insn, 127, 96);
 544 }
 545
 546 static inline float
 547 brw_inst_imm_f(const struct brw_context *brw, struct brw_instruction *insn)
 548 {
 549    fi_type ft;
 550    ft.u = brw_inst_bits(insn, 127, 96);
 551    return ft.f;
 552 }
 553
 554 static inline void
 555 brw_inst_set_imm_d(const struct brw_context *brw,
 556                    struct brw_instruction *insn, int value)
 557 {
 558    return brw_inst_set_bits(insn, 127, 96, value);
 559 }
 560
 561 static inline void
 562 brw_inst_set_imm_ud(const struct brw_context *brw,
 563                     struct brw_instruction *insn, unsigned value)
 564 {
 565    return brw_inst_set_bits(insn, 127, 96, value);
 566 }
 567
 568 static inline void
 569 brw_inst_set_imm_f(const struct brw_context *brw,
 570                    struct brw_instruction *insn, float value)
 571 {
 572    fi_type ft;
 573    ft.f = value;
 574    brw_inst_set_bits(insn, 127, 96, ft.u);
 575 }
 576
 577 /** @} */
 578
 579 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
 580 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
 581 static inline void                                                       \
 582 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw,         \
 583                                   struct brw_instruction *inst,          \
 584                                   unsigned value)                        \
 585 {                                                                        \
 586    assert((value & ~0x3ff) == 0);                                        \
 587    if (brw->gen >= 8) {                                                  \
 588       brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff);           \
 589       brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9);             \
 590    } else {                                                              \
 591       brw_inst_set_bits(inst, g4_high, g4_low, value);                   \
 592    }                                                                     \
 593 }                                                                        \
 594 static inline unsigned                                                   \
 595 brw_inst_##reg##_ia1_addr_imm(const struct brw_context *brw,             \
 596                               struct brw_instruction *inst)              \
 597 {                                                                        \
 598    if (brw->gen >= 8) {                                                  \
 599       return brw_inst_bits(inst, g8_high, g8_low) |                      \
 600              (brw_inst_bits(inst, g8_nine, g8_nine) << 9);               \
 601    } else {                                                              \
 602       return brw_inst_bits(inst, g4_high, g4_low);                       \
 603    }                                                                     \
 604 }
 605
 606 /* AddrImm[9:0] for Align1 Indirect Addressing */
 607 /*                     -Gen 4-  ----Gen8---- */
 608 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
 609 BRW_IA1_ADDR_IMM(src0,  73, 64,  95,  72, 64)
 610 BRW_IA1_ADDR_IMM(dst,   57, 48,  47,  56, 48)
 611
 612 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
 613 static inline void                                                        \
 614 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw,         \
 615                                    struct brw_instruction *inst,          \
 616                                    unsigned value)                        \
 617 {                                                                         \
 618    assert((value & ~0x3ff) == 0);                                         \
 619    if (brw->gen >= 8) {                                                   \
 620       brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff);            \
 621       brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9);              \
 622    } else {                                                               \
 623       brw_inst_set_bits(inst, g4_high, g4_low, value >> 9);               \
 624    }                                                                      \
 625 }                                                                         \
 626 static inline unsigned                                                    \
 627 brw_inst_##reg##_ia16_addr_imm(const struct brw_context *brw,             \
 628                                struct brw_instruction *inst)              \
 629 {                                                                         \
 630    if (brw->gen >= 8) {                                                   \
 631       return brw_inst_bits(inst, g8_high, g8_low) |                       \
 632              (brw_inst_bits(inst, g8_nine, g8_nine) << 9);                \
 633    } else {                                                               \
 634       return brw_inst_bits(inst, g4_high, g4_low);                        \
 635    }                                                                      \
 636 }
 637
 638 /* AddrImm[9:0] for Align16 Indirect Addressing:
 639  * Compared to Align1, these are missing the low 4 bits.
 640  *                     -Gen 4-  ----Gen8----
 641  */
 642 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
 643 BRW_IA16_ADDR_IMM(src0,  73, 64,  95,  72,  68)
 644 BRW_IA16_ADDR_IMM(dst,   57, 52,  47,  56,  52)
 645
 646 /**
 647  * Fetch a set of contiguous bits from the instruction.
 648  *
 649  * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
 650  */
 651 static inline uint64_t
 652 brw_inst_bits(struct brw_instruction *insn, unsigned high, unsigned low)
 653 {
 654    brw_inst *inst = (brw_inst *) insn;
 655
 656    /* We assume the field doesn't cross 64-bit boundaries. */
 657    const unsigned word = high / 64;
 658    assert(word == low / 64);
 659
 660    high %= 64;
 661    low %= 64;
 662
 663    const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
 664
 665    return (inst->data[word] & mask) >> low;
 666 }
 667
 668 /**
 669  * Set bits in the instruction, with proper shifting and masking.
 670  *
 671  * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
 672  */
 673 static inline void
 674 brw_inst_set_bits(struct brw_instruction *insn,
 675                   unsigned high, unsigned low,
 676                   uint64_t value)
 677 {
 678    brw_inst *inst = (brw_inst *) insn;
 679
 680    const unsigned word = high / 64;
 681    assert(word == low / 64);
 682
 683    high %= 64;
 684    low %= 64;
 685
 686    const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
 687
 688    /* Make sure the supplied value actually fits in the given bitfield. */
 689    assert((value & (mask >> low)) == value);
 690
 691    inst->data[word] = (inst->data[word] & ~mask) | ((value << low) & mask);
 692 }
 693
 694 #undef BRW_IA16_ADDR_IMM
 695 #undef BRW_IA1_ADDR_IMM
 696 #undef MD
 697 #undef F8
 698 #undef FF
 699 #undef BOUNDS
 700 #undef F
 701 #undef FC
 702
 703 #ifdef __cplusplus
 704 }
 705 #endif
 706
 707 #endif