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[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /** Maximum SEND message length */
43 #define BRW_MAX_MSG_LENGTH 15
44
45 /** First MRF register used by pull loads */
46 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
47
48 /** First MRF register used by spills */
49 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
50
51 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
52 typedef struct brw_inst {
53 uint64_t data[2];
54 } brw_inst;
55
56 static inline uint64_t brw_inst_bits(const brw_inst *inst,
57 unsigned high, unsigned low);
58 static inline void brw_inst_set_bits(brw_inst *inst,
59 unsigned high, unsigned low,
60 uint64_t value);
61
62 #define FC(name, high, low, assertions) \
63 static inline void \
64 brw_inst_set_##name(const struct brw_device_info *devinfo, \
65 brw_inst *inst, uint64_t v) \
66 { \
67 assert(assertions); \
68 (void) devinfo; \
69 brw_inst_set_bits(inst, high, low, v); \
70 } \
71 static inline uint64_t \
72 brw_inst_##name(const struct brw_device_info *devinfo, \
73 const brw_inst *inst) \
74 { \
75 assert(assertions); \
76 (void) devinfo; \
77 return brw_inst_bits(inst, high, low); \
78 }
79
80 /* A simple macro for fields which stay in the same place on all generations. */
81 #define F(name, high, low) FC(name, high, low, true)
82
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
84 unsigned high, low; \
85 if (devinfo->gen >= 8) { \
86 high = hi8; low = lo8; \
87 } else if (devinfo->gen >= 7) { \
88 high = hi7; low = lo7; \
89 } else if (devinfo->gen >= 6) { \
90 high = hi6; low = lo6; \
91 } else if (devinfo->gen >= 5) { \
92 high = hi5; low = lo5; \
93 } else if (devinfo->is_g4x) { \
94 high = hi45; low = lo45; \
95 } else { \
96 high = hi4; low = lo4; \
97 } \
98 assert(((int) high) != -1 && ((int) low) != -1); \
99
100 /* A general macro for cases where the field has moved to several different
101 * bit locations across generations. GCC appears to combine cases where the
102 * bits are identical, removing some of the inefficiency.
103 */
104 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
105 static inline void \
106 brw_inst_set_##name(const struct brw_device_info *devinfo, \
107 brw_inst *inst, uint64_t value) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 brw_inst_set_bits(inst, high, low, value); \
111 } \
112 static inline uint64_t \
113 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
114 { \
115 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
116 return brw_inst_bits(inst, high, low); \
117 }
118
119 /* A macro for fields which moved as of Gen8+. */
120 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
121 FF(name, \
122 /* 4: */ gen4_high, gen4_low, \
123 /* 4.5: */ gen4_high, gen4_low, \
124 /* 5: */ gen4_high, gen4_low, \
125 /* 6: */ gen4_high, gen4_low, \
126 /* 7: */ gen4_high, gen4_low, \
127 /* 8: */ gen8_high, gen8_low);
128
129 F(src1_vstride, 120, 117)
130 F(src1_width, 116, 114)
131 F(src1_da16_swiz_w, 115, 114)
132 F(src1_da16_swiz_z, 113, 112)
133 F(src1_hstride, 113, 112)
134 F(src1_address_mode, 111, 111)
135 /** Src1.SrcMod @{ */
136 F(src1_negate, 110, 110)
137 F(src1_abs, 109, 109)
138 /** @} */
139 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
140 F(src1_da_reg_nr, 108, 101)
141 F(src1_da16_subreg_nr, 100, 100)
142 F(src1_da1_subreg_nr, 100, 96)
143 F(src1_da16_swiz_y, 99, 98)
144 F(src1_da16_swiz_x, 97, 96)
145 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
146 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
147 F(src0_vstride, 88, 85)
148 F(src0_width, 84, 82)
149 F(src0_da16_swiz_w, 83, 82)
150 F(src0_da16_swiz_z, 81, 80)
151 F(src0_hstride, 81, 80)
152 F(src0_address_mode, 79, 79)
153 /** Src0.SrcMod @{ */
154 F(src0_negate, 78, 78)
155 F(src0_abs, 77, 77)
156 /** @} */
157 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
158 F(src0_da_reg_nr, 76, 69)
159 F(src0_da16_subreg_nr, 68, 68)
160 F(src0_da1_subreg_nr, 68, 64)
161 F(src0_da16_swiz_y, 67, 66)
162 F(src0_da16_swiz_x, 65, 64)
163 F(dst_address_mode, 63, 63)
164 F(dst_hstride, 62, 61)
165 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
166 F(dst_da_reg_nr, 60, 53)
167 F(dst_da16_subreg_nr, 52, 52)
168 F(dst_da1_subreg_nr, 52, 48)
169 F(da16_writemask, 51, 48) /* Dst.ChanEn */
170 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
171 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
172 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
173 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
174 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
175 FF(flag_reg_nr,
176 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
177 /* 7: */ 90, 90,
178 /* 8: */ 33, 33)
179 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
180 F(saturate, 31, 31)
181 F(debug_control, 30, 30)
182 F(cmpt_control, 29, 29)
183 FC(branch_control, 28, 28, devinfo->gen >= 8)
184 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
185 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
186 F(cond_modifier, 27, 24)
187 FC(math_function, 27, 24, devinfo->gen >= 6)
188 F(exec_size, 23, 21)
189 F(pred_inv, 20, 20)
190 F(pred_control, 19, 16)
191 F(thread_control, 15, 14)
192 F(qtr_control, 13, 12)
193 FF(nib_control,
194 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
195 /* 7: */ 47, 47,
196 /* 8: */ 11, 11)
197 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
198 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
199 F(access_mode, 8, 8)
200 /* Bit 7 is Reserved (for future Opcode expansion) */
201 F(opcode, 6, 0)
202
203 /**
204 * Three-source instructions:
205 * @{
206 */
207 F(3src_src2_reg_nr, 125, 118)
208 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
209 F(3src_src2_swizzle, 114, 107)
210 F(3src_src2_rep_ctrl, 106, 106)
211 F(3src_src1_reg_nr, 104, 97)
212 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
213 F(3src_src1_swizzle, 93, 86)
214 F(3src_src1_rep_ctrl, 85, 85)
215 F(3src_src0_reg_nr, 83, 76)
216 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
217 F(3src_src0_swizzle, 72, 65)
218 F(3src_src0_rep_ctrl, 64, 64)
219 F(3src_dst_reg_nr, 63, 56)
220 F(3src_dst_subreg_nr, 55, 53)
221 F(3src_dst_writemask, 52, 49)
222 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
223 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
224 F8(3src_src_type, 43, 42, 45, 43)
225 F8(3src_src2_negate, 41, 41, 42, 42)
226 F8(3src_src2_abs, 40, 40, 41, 41)
227 F8(3src_src1_negate, 39, 39, 40, 40)
228 F8(3src_src1_abs, 38, 38, 39, 39)
229 F8(3src_src0_negate, 37, 37, 38, 38)
230 F8(3src_src0_abs, 36, 36, 37, 37)
231 F8(3src_flag_reg_nr, 34, 34, 33, 33)
232 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
233 FF(3src_dst_reg_file,
234 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
235 /* 6: */ 32, 32,
236 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
237 F(3src_saturate, 31, 31)
238 F(3src_debug_control, 30, 30)
239 F(3src_cmpt_control, 29, 29)
240 F(3src_acc_wr_control, 28, 28)
241 F(3src_cond_modifier, 27, 24)
242 F(3src_exec_size, 23, 21)
243 F(3src_pred_inv, 20, 20)
244 F(3src_pred_control, 19, 16)
245 F(3src_thread_control, 15, 14)
246 F(3src_qtr_control, 13, 12)
247 F8(3src_no_dd_check, 11, 11, 10, 10)
248 F8(3src_no_dd_clear, 10, 10, 9, 9)
249 F8(3src_mask_control, 9, 9, 34, 34)
250 F(3src_access_mode, 8, 8)
251 /* Bit 7 is Reserved (for future Opcode expansion) */
252 F(3src_opcode, 6, 0)
253 /** @} */
254
255 /**
256 * Flow control instruction bits:
257 * @{
258 */
259 static inline void
260 brw_inst_set_uip(const struct brw_device_info *devinfo,
261 brw_inst *inst, int32_t value)
262 {
263 assert(devinfo->gen >= 6);
264
265 if (devinfo->gen >= 8) {
266 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
267 } else {
268 assert(value <= (1 << 16) - 1);
269 assert(value > -(1 << 16));
270 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
271 }
272 }
273
274 static inline int32_t
275 brw_inst_uip(const struct brw_device_info *devinfo, const brw_inst *inst)
276 {
277 assert(devinfo->gen >= 6);
278
279 if (devinfo->gen >= 8) {
280 return brw_inst_bits(inst, 95, 64);
281 } else {
282 return (int16_t)brw_inst_bits(inst, 127, 112);
283 }
284 }
285
286 static inline void
287 brw_inst_set_jip(const struct brw_device_info *devinfo,
288 brw_inst *inst, int32_t value)
289 {
290 assert(devinfo->gen >= 6);
291
292 if (devinfo->gen >= 8) {
293 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
294 } else {
295 assert(value <= (1 << 16) - 1);
296 assert(value > -(1 << 16));
297 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
298 }
299 }
300
301 static inline int32_t
302 brw_inst_jip(const struct brw_device_info *devinfo, const brw_inst *inst)
303 {
304 assert(devinfo->gen >= 6);
305
306 if (devinfo->gen >= 8) {
307 return brw_inst_bits(inst, 127, 96);
308 } else {
309 return (int16_t)brw_inst_bits(inst, 111, 96);
310 }
311 }
312
313 /** Like FC, but using int16_t to handle negative jump targets. */
314 #define FJ(name, high, low, assertions) \
315 static inline void \
316 brw_inst_set_##name(const struct brw_device_info *devinfo, brw_inst *inst, int16_t v) \
317 { \
318 assert(assertions); \
319 (void) devinfo; \
320 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
321 } \
322 static inline int16_t \
323 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
324 { \
325 assert(assertions); \
326 (void) devinfo; \
327 return brw_inst_bits(inst, high, low); \
328 }
329
330 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
331 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
332 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
333 /** @} */
334
335 /* Message descriptor bits */
336 #define MD(x) ((x) + 96)
337
338 /**
339 * Fields for SEND messages:
340 * @{
341 */
342 F(eot, 127, 127)
343 FF(mlen,
344 /* 4: */ 119, 116,
345 /* 4.5: */ 119, 116,
346 /* 5: */ 124, 121,
347 /* 6: */ 124, 121,
348 /* 7: */ 124, 121,
349 /* 8: */ 124, 121);
350 FF(rlen,
351 /* 4: */ 115, 112,
352 /* 4.5: */ 115, 112,
353 /* 5: */ 120, 116,
354 /* 6: */ 120, 116,
355 /* 7: */ 120, 116,
356 /* 8: */ 120, 116);
357 FF(header_present,
358 /* 4: doesn't exist */ -1, -1, -1, -1,
359 /* 5: */ 115, 115,
360 /* 6: */ 115, 115,
361 /* 7: */ 115, 115,
362 /* 8: */ 115, 115)
363 F(gateway_notify, MD(16), MD(15))
364 FF(function_control,
365 /* 4: */ 111, 96,
366 /* 4.5: */ 111, 96,
367 /* 5: */ 114, 96,
368 /* 6: */ 114, 96,
369 /* 7: */ 114, 96,
370 /* 8: */ 114, 96)
371 FF(gateway_subfuncid,
372 /* 4: */ MD(1), MD(0),
373 /* 4.5: */ MD(1), MD(0),
374 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
375 /* 6: */ MD(2), MD(0),
376 /* 7: */ MD(2), MD(0),
377 /* 8: */ MD(2), MD(0))
378 FF(sfid,
379 /* 4: */ 123, 120, /* called msg_target */
380 /* 4.5 */ 123, 120,
381 /* 5: */ 95, 92,
382 /* 6: */ 27, 24,
383 /* 7: */ 27, 24,
384 /* 8: */ 27, 24)
385 FC(base_mrf, 27, 24, devinfo->gen < 6);
386 /** @} */
387
388 /**
389 * URB message function control bits:
390 * @{
391 */
392 FF(urb_per_slot_offset,
393 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
394 /* 7: */ MD(16), MD(16),
395 /* 8: */ MD(17), MD(17))
396 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
397 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
398 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
399 FF(urb_swizzle_control,
400 /* 4: */ MD(11), MD(10),
401 /* 4.5: */ MD(11), MD(10),
402 /* 5: */ MD(11), MD(10),
403 /* 6: */ MD(11), MD(10),
404 /* 7: */ MD(14), MD(14),
405 /* 8: */ MD(15), MD(15))
406 FF(urb_global_offset,
407 /* 4: */ MD( 9), MD(4),
408 /* 4.5: */ MD( 9), MD(4),
409 /* 5: */ MD( 9), MD(4),
410 /* 6: */ MD( 9), MD(4),
411 /* 7: */ MD(13), MD(3),
412 /* 8: */ MD(14), MD(4))
413 FF(urb_opcode,
414 /* 4: */ MD( 3), MD(0),
415 /* 4.5: */ MD( 3), MD(0),
416 /* 5: */ MD( 3), MD(0),
417 /* 6: */ MD( 3), MD(0),
418 /* 7: */ MD( 2), MD(0),
419 /* 8: */ MD( 3), MD(0))
420 /** @} */
421
422 /**
423 * Gen4-5 math messages:
424 * @{
425 */
426 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
427 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
428 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
429 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
430 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
431 /** @} */
432
433 /**
434 * Sampler message function control bits:
435 * @{
436 */
437 FF(sampler_simd_mode,
438 /* 4: doesn't exist */ -1, -1, -1, -1,
439 /* 5: */ MD(17), MD(16),
440 /* 6: */ MD(17), MD(16),
441 /* 7: */ MD(18), MD(17),
442 /* 8: */ MD(18), MD(17))
443 FF(sampler_msg_type,
444 /* 4: */ MD(15), MD(14),
445 /* 4.5: */ MD(15), MD(12),
446 /* 5: */ MD(15), MD(12),
447 /* 6: */ MD(15), MD(12),
448 /* 7: */ MD(16), MD(12),
449 /* 8: */ MD(16), MD(12))
450 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
451 F(sampler, MD(11), MD(8))
452 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
453 /** @} */
454
455 /**
456 * Data port message function control bits:
457 * @{
458 */
459 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
460
461 /* Gen4-5 store fields in different bits for read/write messages. */
462 FF(dp_read_msg_type,
463 /* 4: */ MD(13), MD(12),
464 /* 4.5: */ MD(13), MD(11),
465 /* 5: */ MD(13), MD(11),
466 /* 6: */ MD(16), MD(13),
467 /* 7: */ MD(17), MD(14),
468 /* 8: */ MD(17), MD(14))
469 FF(dp_write_msg_type,
470 /* 4: */ MD(14), MD(12),
471 /* 4.5: */ MD(14), MD(12),
472 /* 5: */ MD(14), MD(12),
473 /* 6: */ MD(16), MD(13),
474 /* 7: */ MD(17), MD(14),
475 /* 8: */ MD(17), MD(14))
476 FF(dp_read_msg_control,
477 /* 4: */ MD(11), MD( 8),
478 /* 4.5: */ MD(10), MD( 8),
479 /* 5: */ MD(10), MD( 8),
480 /* 6: */ MD(12), MD( 8),
481 /* 7: */ MD(13), MD( 8),
482 /* 8: */ MD(13), MD( 8))
483 FF(dp_write_msg_control,
484 /* 4: */ MD(11), MD( 8),
485 /* 4.5: */ MD(11), MD( 8),
486 /* 5: */ MD(11), MD( 8),
487 /* 6: */ MD(12), MD( 8),
488 /* 7: */ MD(13), MD( 8),
489 /* 8: */ MD(13), MD( 8))
490 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
491
492 FF(dp_write_commit,
493 /* 4: */ MD(15), MD(15),
494 /* 4.5: */ MD(15), MD(15),
495 /* 5: */ MD(15), MD(15),
496 /* 6: */ MD(17), MD(17),
497 /* 7+: does not exist */ -1, -1, -1, -1)
498
499 /* Gen6+ use the same bit locations for everything. */
500 FF(dp_msg_type,
501 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
502 -1, -1, -1, -1, -1, -1,
503 /* 6: */ MD(16), MD(13),
504 /* 7: */ MD(17), MD(14),
505 /* 8: */ MD(17), MD(14))
506 FF(dp_msg_control,
507 /* 4: */ MD(11), MD( 8),
508 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
509 /* 6: */ MD(12), MD( 8),
510 /* 7: */ MD(13), MD( 8),
511 /* 8: */ MD(13), MD( 8))
512 /** @} */
513
514 /**
515 * Scratch message bits (Gen7+):
516 * @{
517 */
518 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
519 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
520 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
521 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
522 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
523 /** @} */
524
525 /**
526 * Render Target message function control bits:
527 * @{
528 */
529 FF(rt_last,
530 /* 4: */ MD(11), MD(11),
531 /* 4.5: */ MD(11), MD(11),
532 /* 5: */ MD(11), MD(11),
533 /* 6: */ MD(12), MD(12),
534 /* 7: */ MD(12), MD(12),
535 /* 8: */ MD(12), MD(12))
536 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
537 F(rt_message_type, MD(10), MD( 8))
538 /** @} */
539
540 /**
541 * Thread Spawn message function control bits:
542 * @{
543 */
544 F(ts_resource_select, MD( 4), MD( 4))
545 F(ts_request_type, MD( 1), MD( 1))
546 F(ts_opcode, MD( 0), MD( 0))
547 /** @} */
548
549 /**
550 * Pixel Interpolator message function control bits:
551 * @{
552 */
553 F(pi_simd_mode, MD(16), MD(16))
554 F(pi_nopersp, MD(14), MD(14))
555 F(pi_message_type, MD(13), MD(12))
556 F(pi_slot_group, MD(11), MD(11))
557 F(pi_message_data, MD(7), MD(0))
558 /** @} */
559
560 /**
561 * Immediates:
562 * @{
563 */
564 static inline int
565 brw_inst_imm_d(const struct brw_device_info *devinfo, const brw_inst *insn)
566 {
567 (void) devinfo;
568 return brw_inst_bits(insn, 127, 96);
569 }
570
571 static inline unsigned
572 brw_inst_imm_ud(const struct brw_device_info *devinfo, const brw_inst *insn)
573 {
574 (void) devinfo;
575 return brw_inst_bits(insn, 127, 96);
576 }
577
578 static inline float
579 brw_inst_imm_f(const struct brw_device_info *devinfo, const brw_inst *insn)
580 {
581 fi_type ft;
582 (void) devinfo;
583 ft.u = brw_inst_bits(insn, 127, 96);
584 return ft.f;
585 }
586
587 static inline void
588 brw_inst_set_imm_d(const struct brw_device_info *devinfo,
589 brw_inst *insn, int value)
590 {
591 (void) devinfo;
592 return brw_inst_set_bits(insn, 127, 96, value);
593 }
594
595 static inline void
596 brw_inst_set_imm_ud(const struct brw_device_info *devinfo,
597 brw_inst *insn, unsigned value)
598 {
599 (void) devinfo;
600 return brw_inst_set_bits(insn, 127, 96, value);
601 }
602
603 static inline void
604 brw_inst_set_imm_f(const struct brw_device_info *devinfo,
605 brw_inst *insn, float value)
606 {
607 fi_type ft;
608 (void) devinfo;
609 ft.f = value;
610 brw_inst_set_bits(insn, 127, 96, ft.u);
611 }
612
613 /** @} */
614
615 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
616 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
617 static inline void \
618 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
619 brw_inst *inst, \
620 unsigned value) \
621 { \
622 assert((value & ~0x3ff) == 0); \
623 if (devinfo->gen >= 8) { \
624 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
625 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
626 } else { \
627 brw_inst_set_bits(inst, g4_high, g4_low, value); \
628 } \
629 } \
630 static inline unsigned \
631 brw_inst_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
632 const brw_inst *inst) \
633 { \
634 if (devinfo->gen >= 8) { \
635 return brw_inst_bits(inst, g8_high, g8_low) | \
636 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
637 } else { \
638 return brw_inst_bits(inst, g4_high, g4_low); \
639 } \
640 }
641
642 /* AddrImm[9:0] for Align1 Indirect Addressing */
643 /* -Gen 4- ----Gen8---- */
644 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
645 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
646 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
647
648 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
649 static inline void \
650 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
651 brw_inst *inst, unsigned value) \
652 { \
653 assert((value & ~0x3ff) == 0); \
654 if (devinfo->gen >= 8) { \
655 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
656 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
657 } else { \
658 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
659 } \
660 } \
661 static inline unsigned \
662 brw_inst_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
663 const brw_inst *inst) \
664 { \
665 if (devinfo->gen >= 8) { \
666 return brw_inst_bits(inst, g8_high, g8_low) | \
667 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
668 } else { \
669 return brw_inst_bits(inst, g4_high, g4_low); \
670 } \
671 }
672
673 /* AddrImm[9:0] for Align16 Indirect Addressing:
674 * Compared to Align1, these are missing the low 4 bits.
675 * -Gen 4- ----Gen8----
676 */
677 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
678 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
679 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
680
681 /**
682 * Fetch a set of contiguous bits from the instruction.
683 *
684 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
685 */
686 static inline uint64_t
687 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
688 {
689 /* We assume the field doesn't cross 64-bit boundaries. */
690 const unsigned word = high / 64;
691 assert(word == low / 64);
692
693 high %= 64;
694 low %= 64;
695
696 const uint64_t mask = (1ull << (high - low + 1)) - 1;
697
698 return (inst->data[word] >> low) & mask;
699 }
700
701 /**
702 * Set bits in the instruction, with proper shifting and masking.
703 *
704 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
705 */
706 static inline void
707 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
708 {
709 const unsigned word = high / 64;
710 assert(word == low / 64);
711
712 high %= 64;
713 low %= 64;
714
715 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
716
717 /* Make sure the supplied value actually fits in the given bitfield. */
718 assert((value & (mask >> low)) == value);
719
720 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
721 }
722
723 #undef BRW_IA16_ADDR_IMM
724 #undef BRW_IA1_ADDR_IMM
725 #undef MD
726 #undef F8
727 #undef FF
728 #undef BOUNDS
729 #undef F
730 #undef FC
731
732 typedef struct {
733 uint64_t data;
734 } brw_compact_inst;
735
736 /**
737 * Fetch a set of contiguous bits from the compacted instruction.
738 *
739 * Bits indices range from 0..63.
740 */
741 static inline unsigned
742 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
743 {
744 const uint64_t mask = (1ull << (high - low + 1)) - 1;
745
746 return (inst->data >> low) & mask;
747 }
748
749 /**
750 * Set bits in the compacted instruction.
751 *
752 * Bits indices range from 0..63.
753 */
754 static inline void
755 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
756 uint64_t value)
757 {
758 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
759
760 /* Make sure the supplied value actually fits in the given bitfield. */
761 assert((value & (mask >> low)) == value);
762
763 inst->data = (inst->data & ~mask) | (value << low);
764 }
765
766 #define FC(name, high, low, assertions) \
767 static inline void \
768 brw_compact_inst_set_##name(const struct brw_device_info *devinfo, \
769 brw_compact_inst *inst, unsigned v) \
770 { \
771 assert(assertions); \
772 (void) devinfo; \
773 brw_compact_inst_set_bits(inst, high, low, v); \
774 } \
775 static inline unsigned \
776 brw_compact_inst_##name(const struct brw_device_info *devinfo, \
777 const brw_compact_inst *inst) \
778 { \
779 assert(assertions); \
780 (void) devinfo; \
781 return brw_compact_inst_bits(inst, high, low); \
782 }
783
784 /* A simple macro for fields which stay in the same place on all generations. */
785 #define F(name, high, low) FC(name, high, low, true)
786
787 F(src1_reg_nr, 63, 56)
788 F(src0_reg_nr, 55, 48)
789 F(dst_reg_nr, 47, 40)
790 F(src1_index, 39, 35)
791 F(src0_index, 34, 30)
792 F(cmpt_control, 29, 29) /* Same location as brw_inst */
793 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
794 F(cond_modifier, 27, 24) /* Same location as brw_inst */
795 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
796 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
797 F(subreg_index, 22, 18)
798 F(datatype_index, 17, 13)
799 F(control_index, 12, 8)
800 F(debug_control, 7, 7)
801 F(opcode, 6, 0) /* Same location as brw_inst */
802
803 /**
804 * (Gen8+) Compacted three-source instructions:
805 * @{
806 */
807 F(3src_src2_reg_nr, 63, 57)
808 F(3src_src1_reg_nr, 56, 50)
809 F(3src_src0_reg_nr, 49, 43)
810 F(3src_src2_subreg_nr, 42, 40)
811 F(3src_src1_subreg_nr, 39, 37)
812 F(3src_src0_subreg_nr, 36, 34)
813 F(3src_src2_rep_ctrl, 33, 33)
814 F(3src_src1_rep_ctrl, 32, 32)
815 F(3src_saturate, 31, 31)
816 F(3src_debug_control, 30, 30)
817 F(3src_cmpt_control, 29, 29)
818 F(3src_src0_rep_ctrl, 28, 28)
819 /* Reserved */
820 F(3src_dst_reg_nr, 18, 12)
821 F(3src_source_index, 11, 10)
822 F(3src_control_index, 9, 8)
823 /* Bit 7 is Reserved (for future Opcode expansion) */
824 F(3src_opcode, 6, 0)
825 /** @} */
826
827 #undef F
828
829 #ifdef __cplusplus
830 }
831 #endif
832
833 #endif