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i965: Silence many unused parameter warnings
[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
43 typedef struct brw_inst {
44 uint64_t data[2];
45 } brw_inst;
46
47 static inline uint64_t brw_inst_bits(brw_inst *inst,
48 unsigned high, unsigned low);
49 static inline void brw_inst_set_bits(brw_inst *inst,
50 unsigned high, unsigned low,
51 uint64_t value);
52
53 #define FC(name, high, low, assertions) \
54 static inline void \
55 brw_inst_set_##name(const struct brw_context *brw, \
56 brw_inst *inst, uint64_t v) \
57 { \
58 assert(assertions); \
59 (void) brw; \
60 brw_inst_set_bits(inst, high, low, v); \
61 } \
62 static inline uint64_t \
63 brw_inst_##name(const struct brw_context *brw, \
64 brw_inst *inst) \
65 { \
66 assert(assertions); \
67 (void) brw; \
68 return brw_inst_bits(inst, high, low); \
69 }
70
71 /* A simple macro for fields which stay in the same place on all generations. */
72 #define F(name, high, low) FC(name, high, low, true)
73
74 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
75 unsigned high, low; \
76 if (brw->gen >= 8) { \
77 high = hi8; low = lo8; \
78 } else if (brw->gen >= 7) { \
79 high = hi7; low = lo7; \
80 } else if (brw->gen >= 6) { \
81 high = hi6; low = lo6; \
82 } else if (brw->gen >= 5) { \
83 high = hi5; low = lo5; \
84 } else if (brw->is_g4x) { \
85 high = hi45; low = lo45; \
86 } else { \
87 high = hi4; low = lo4; \
88 } \
89 assert(((int) high) != -1 && ((int) low) != -1); \
90
91 /* A general macro for cases where the field has moved to several different
92 * bit locations across generations. GCC appears to combine cases where the
93 * bits are identical, removing some of the inefficiency.
94 */
95 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
96 static inline void \
97 brw_inst_set_##name(const struct brw_context *brw, \
98 brw_inst *inst, uint64_t value) \
99 { \
100 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
101 brw_inst_set_bits(inst, high, low, value); \
102 } \
103 static inline uint64_t \
104 brw_inst_##name(const struct brw_context *brw, brw_inst *inst) \
105 { \
106 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
107 return brw_inst_bits(inst, high, low); \
108 }
109
110 /* A macro for fields which moved as of Gen8+. */
111 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
112 FF(name, \
113 /* 4: */ gen4_high, gen4_low, \
114 /* 4.5: */ gen4_high, gen4_low, \
115 /* 5: */ gen4_high, gen4_low, \
116 /* 6: */ gen4_high, gen4_low, \
117 /* 7: */ gen4_high, gen4_low, \
118 /* 8: */ gen8_high, gen8_low);
119
120 F(src1_vstride, 120, 117)
121 F(src1_width, 116, 114)
122 F(src1_da16_swiz_w, 115, 114)
123 F(src1_da16_swiz_z, 113, 112)
124 F(src1_hstride, 113, 112)
125 F(src1_address_mode, 111, 111)
126 /** Src1.SrcMod @{ */
127 F(src1_negate, 110, 110)
128 F(src1_abs, 109, 109)
129 /** @} */
130 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
131 F(src1_da_reg_nr, 108, 101)
132 F(src1_da16_subreg_nr, 100, 100)
133 F(src1_da1_subreg_nr, 100, 96)
134 F(src1_da16_swiz_y, 99, 98)
135 F(src1_da16_swiz_x, 97, 96)
136 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
137 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
138 F(src0_vstride, 88, 85)
139 F(src0_width, 84, 82)
140 F(src0_da16_swiz_w, 83, 82)
141 F(src0_da16_swiz_z, 81, 80)
142 F(src0_hstride, 81, 80)
143 F(src0_address_mode, 79, 79)
144 /** Src0.SrcMod @{ */
145 F(src0_negate, 78, 78)
146 F(src0_abs, 77, 77)
147 /** @} */
148 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
149 F(src0_da_reg_nr, 76, 69)
150 F(src0_da16_subreg_nr, 68, 68)
151 F(src0_da1_subreg_nr, 68, 64)
152 F(src0_da16_swiz_y, 67, 66)
153 F(src0_da16_swiz_x, 65, 64)
154 F(dst_address_mode, 63, 63)
155 F(dst_hstride, 62, 61)
156 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
157 F(dst_da_reg_nr, 60, 53)
158 F(dst_da16_subreg_nr, 52, 52)
159 F(dst_da1_subreg_nr, 52, 48)
160 F(da16_writemask, 51, 48) /* Dst.ChanEn */
161 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
162 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
163 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
164 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
165 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
166 FF(flag_reg_nr,
167 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
168 /* 7: */ 90, 90,
169 /* 8: */ 33, 33)
170 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
171 F(saturate, 31, 31)
172 FC(branch_control, 30, 30, brw->gen >= 8)
173 F(debug_control, 30, 30)
174 F(cmpt_control, 29, 29)
175 F(acc_wr_control, 28, 28)
176 F(cond_modifier, 27, 24)
177 FC(math_function, 27, 24, brw->gen >= 6)
178 F(exec_size, 23, 21)
179 F(pred_inv, 20, 20)
180 F(pred_control, 19, 16)
181 F(thread_control, 15, 14)
182 F(qtr_control, 13, 12)
183 FF(nib_control,
184 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
185 /* 7: */ 47, 47,
186 /* 8: */ 11, 11)
187 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
188 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
189 F(access_mode, 8, 8)
190 /* Bit 7 is Reserved (for future Opcode expansion) */
191 F(opcode, 6, 0)
192
193 /**
194 * Three-source instructions:
195 * @{
196 */
197 F(3src_src2_reg_nr, 125, 118)
198 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
199 F(3src_src2_swizzle, 114, 107)
200 F(3src_src2_rep_ctrl, 106, 106)
201 F(3src_src1_reg_nr, 104, 97)
202 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
203 F(3src_src1_swizzle, 93, 86)
204 F(3src_src1_rep_ctrl, 85, 85)
205 F(3src_src0_reg_nr, 83, 76)
206 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
207 F(3src_src0_swizzle, 72, 65)
208 F(3src_src0_rep_ctrl, 64, 64)
209 F(3src_dst_reg_nr, 63, 56)
210 F(3src_dst_subreg_nr, 55, 53)
211 F(3src_dst_writemask, 52, 49)
212 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
213 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
214 F8(3src_src_type, 43, 42, 45, 43)
215 F8(3src_src2_negate, 41, 41, 42, 42)
216 F8(3src_src2_abs, 40, 40, 41, 41)
217 F8(3src_src1_negate, 39, 39, 40, 40)
218 F8(3src_src1_abs, 38, 38, 39, 39)
219 F8(3src_src0_negate, 37, 37, 38, 38)
220 F8(3src_src0_abs, 36, 36, 37, 37)
221 F8(3src_flag_reg_nr, 34, 34, 33, 33)
222 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
223 FF(3src_dst_reg_file,
224 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
225 /* 6: */ 32, 32,
226 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
227 F(3src_saturate, 31, 31)
228 F(3src_debug_control, 30, 30)
229 F(3src_cmpt_control, 29, 29)
230 F(3src_acc_wr_control, 28, 28)
231 F(3src_cond_modifier, 27, 24)
232 F(3src_exec_size, 23, 21)
233 F(3src_pred_inv, 20, 20)
234 F(3src_pred_control, 19, 16)
235 F(3src_thread_control, 15, 14)
236 F(3src_qtr_control, 13, 12)
237 F8(3src_no_dd_check, 11, 11, 10, 10)
238 F8(3src_no_dd_clear, 10, 10, 9, 9)
239 F8(3src_mask_control, 9, 9, 34, 34)
240 F(3src_access_mode, 8, 8)
241 /* Bit 7 is Reserved (for future Opcode expansion) */
242 F(3src_opcode, 6, 0)
243 /** @} */
244
245 /**
246 * Flow control instruction bits:
247 * @{
248 */
249 static inline void
250 brw_inst_set_uip(const struct brw_context *brw,
251 brw_inst *inst, int32_t value)
252 {
253 assert(brw->gen >= 6);
254
255 if (brw->gen >= 8) {
256 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
257 } else {
258 assert(value <= (1 << 16) - 1);
259 assert(value > -(1 << 16));
260 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
261 }
262 }
263
264 static inline int32_t
265 brw_inst_uip(const struct brw_context *brw, brw_inst *inst)
266 {
267 assert(brw->gen >= 6);
268
269 if (brw->gen >= 8) {
270 return brw_inst_bits(inst, 95, 64);
271 } else {
272 return (int16_t)brw_inst_bits(inst, 127, 112);
273 }
274 }
275
276 static inline void
277 brw_inst_set_jip(const struct brw_context *brw,
278 brw_inst *inst, int32_t value)
279 {
280 assert(brw->gen >= 6);
281
282 if (brw->gen >= 8) {
283 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
284 } else {
285 assert(value <= (1 << 16) - 1);
286 assert(value > -(1 << 16));
287 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
288 }
289 }
290
291 static inline int32_t
292 brw_inst_jip(const struct brw_context *brw, brw_inst *inst)
293 {
294 assert(brw->gen >= 6);
295
296 if (brw->gen >= 8) {
297 return brw_inst_bits(inst, 127, 96);
298 } else {
299 return (int16_t)brw_inst_bits(inst, 111, 96);
300 }
301 }
302
303 /** Like FC, but using int16_t to handle negative jump targets. */
304 #define FJ(name, high, low, assertions) \
305 static inline void \
306 brw_inst_set_##name(const struct brw_context *brw, brw_inst *inst, int16_t v) \
307 { \
308 assert(assertions); \
309 assert(v <= (1 << 16) - 1); \
310 assert(v > -(1 << 16)); \
311 (void) brw; \
312 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
313 } \
314 static inline int16_t \
315 brw_inst_##name(const struct brw_context *brw, brw_inst *inst) \
316 { \
317 assert(assertions); \
318 (void) brw; \
319 return brw_inst_bits(inst, high, low); \
320 }
321
322 FJ(gen6_jump_count, 63, 48, brw->gen == 6)
323 FJ(gen4_jump_count, 111, 96, brw->gen < 6)
324 FC(gen4_pop_count, 115, 112, brw->gen < 6)
325 /** @} */
326
327 /**
328 * Fields for SEND messages:
329 * @{
330 */
331 F(eot, 127, 127)
332 FF(mlen,
333 /* 4: */ 119, 116,
334 /* 4.5: */ 119, 116,
335 /* 5: */ 124, 121,
336 /* 6: */ 124, 121,
337 /* 7: */ 124, 121,
338 /* 8: */ 124, 121);
339 FF(rlen,
340 /* 4: */ 115, 112,
341 /* 4.5: */ 115, 112,
342 /* 5: */ 120, 116,
343 /* 6: */ 120, 116,
344 /* 7: */ 120, 116,
345 /* 8: */ 120, 116);
346 FF(header_present,
347 /* 4: doesn't exist */ -1, -1, -1, -1,
348 /* 5: */ 115, 115,
349 /* 6: */ 115, 115,
350 /* 7: */ 115, 115,
351 /* 8: */ 115, 115)
352 FF(function_control,
353 /* 4: */ 111, 96,
354 /* 4.5: */ 111, 96,
355 /* 5: */ 114, 96,
356 /* 6: */ 114, 96,
357 /* 7: */ 114, 96,
358 /* 8: */ 114, 96)
359 FF(sfid,
360 /* 4: */ 123, 120, /* called msg_target */
361 /* 4.5 */ 123, 120,
362 /* 5: */ 95, 92,
363 /* 6: */ 27, 24,
364 /* 7: */ 27, 24,
365 /* 8: */ 27, 24)
366 FC(base_mrf, 27, 24, brw->gen < 6);
367 /** @} */
368
369 /* Message descriptor bits */
370 #define MD(x) (x + 96)
371
372 /**
373 * URB message function control bits:
374 * @{
375 */
376 FF(urb_per_slot_offset,
377 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
378 /* 7: */ MD(16), MD(16),
379 /* 8: */ MD(17), MD(17))
380 FC(urb_complete, MD(15), MD(15), brw->gen < 8)
381 FC(urb_used, MD(14), MD(14), brw->gen < 7)
382 FC(urb_allocate, MD(13), MD(13), brw->gen < 7)
383 FF(urb_swizzle_control,
384 /* 4: */ MD(11), MD(10),
385 /* 4.5: */ MD(11), MD(10),
386 /* 5: */ MD(11), MD(10),
387 /* 6: */ MD(11), MD(10),
388 /* 7: */ MD(14), MD(14),
389 /* 8: */ MD(15), MD(15))
390 FF(urb_global_offset,
391 /* 4: */ MD( 9), MD(4),
392 /* 4.5: */ MD( 9), MD(4),
393 /* 5: */ MD( 9), MD(4),
394 /* 6: */ MD( 9), MD(4),
395 /* 7: */ MD(13), MD(3),
396 /* 8: */ MD(14), MD(4))
397 FF(urb_opcode,
398 /* 4: */ MD( 3), MD(0),
399 /* 4.5: */ MD( 3), MD(0),
400 /* 5: */ MD( 3), MD(0),
401 /* 6: */ MD( 3), MD(0),
402 /* 7: */ MD( 2), MD(0),
403 /* 8: */ MD( 3), MD(0))
404 /** @} */
405
406 /**
407 * Gen4-5 math messages:
408 * @{
409 */
410 FC(math_msg_data_type, MD(7), MD(7), brw->gen < 6)
411 FC(math_msg_saturate, MD(6), MD(6), brw->gen < 6)
412 FC(math_msg_precision, MD(5), MD(5), brw->gen < 6)
413 FC(math_msg_signed_int, MD(4), MD(4), brw->gen < 6)
414 FC(math_msg_function, MD(3), MD(0), brw->gen < 6)
415 /** @} */
416
417 /**
418 * Sampler message function control bits:
419 * @{
420 */
421 FF(sampler_simd_mode,
422 /* 4: doesn't exist */ -1, -1, -1, -1,
423 /* 5: */ MD(17), MD(16),
424 /* 6: */ MD(17), MD(16),
425 /* 7: */ MD(18), MD(17),
426 /* 8: */ MD(18), MD(17))
427 FF(sampler_msg_type,
428 /* 4: */ MD(15), MD(14),
429 /* 4.5: */ MD(15), MD(12),
430 /* 5: */ MD(15), MD(12),
431 /* 6: */ MD(15), MD(12),
432 /* 7: */ MD(16), MD(12),
433 /* 8: */ MD(16), MD(12))
434 FC(sampler_return_format, MD(13), MD(12), brw->gen == 4 && !brw->is_g4x)
435 F(sampler, MD(11), MD(8))
436 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
437 /** @} */
438
439 /**
440 * Data port message function control bits:
441 * @{
442 */
443 FC(dp_category, MD(18), MD(18), brw->gen >= 7)
444
445 /* Gen4-5 store fields in different bits for read/write messages. */
446 FF(dp_read_msg_type,
447 /* 4: */ MD(13), MD(12),
448 /* 4.5: */ MD(13), MD(11),
449 /* 5: */ MD(13), MD(11),
450 /* 6: */ MD(16), MD(13),
451 /* 7: */ MD(17), MD(14),
452 /* 8: */ MD(17), MD(14))
453 FF(dp_write_msg_type,
454 /* 4: */ MD(14), MD(12),
455 /* 4.5: */ MD(14), MD(12),
456 /* 5: */ MD(14), MD(12),
457 /* 6: */ MD(16), MD(13),
458 /* 7: */ MD(17), MD(14),
459 /* 8: */ MD(17), MD(14))
460 FF(dp_read_msg_control,
461 /* 4: */ MD(11), MD( 8),
462 /* 4.5: */ MD(10), MD( 8),
463 /* 5: */ MD(10), MD( 8),
464 /* 6: */ MD(12), MD( 8),
465 /* 7: */ MD(13), MD( 8),
466 /* 8: */ MD(13), MD( 8))
467 FF(dp_write_msg_control,
468 /* 4: */ MD(11), MD( 8),
469 /* 4.5: */ MD(11), MD( 8),
470 /* 5: */ MD(11), MD( 8),
471 /* 6: */ MD(12), MD( 8),
472 /* 7: */ MD(13), MD( 8),
473 /* 8: */ MD(13), MD( 8))
474 FC(dp_read_target_cache, MD(15), MD(14), brw->gen < 6);
475
476 FF(dp_write_commit,
477 /* 4: */ MD(15), MD(15),
478 /* 4.5: */ MD(15), MD(15),
479 /* 5: */ MD(15), MD(15),
480 /* 6: */ MD(17), MD(17),
481 /* 7+: does not exist */ -1, -1, -1, -1)
482
483 /* Gen6+ use the same bit locations for everything. */
484 FF(dp_msg_type,
485 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
486 -1, -1, -1, -1, -1, -1,
487 /* 6: */ MD(16), MD(13),
488 /* 7: */ MD(17), MD(14),
489 /* 8: */ MD(17), MD(14))
490 FF(dp_msg_control,
491 /* 4: */ MD(11), MD( 8),
492 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
493 /* 6: */ MD(12), MD( 8),
494 /* 7: */ MD(13), MD( 8),
495 /* 8: */ MD(13), MD( 8))
496 /** @} */
497
498 /**
499 * Scratch message bits (Gen7+):
500 * @{
501 */
502 FC(scratch_read_write, MD(17), MD(17), brw->gen >= 7) /* 0 = read, 1 = write */
503 FC(scratch_type, MD(16), MD(16), brw->gen >= 7) /* 0 = OWord, 1 = DWord */
504 FC(scratch_invalidate_after_read, MD(15), MD(15), brw->gen >= 7)
505 FC(scratch_block_size, MD(13), MD(12), brw->gen >= 7)
506 FC(scratch_addr_offset, MD(11), MD( 0), brw->gen >= 7)
507 /** @} */
508
509 /**
510 * Render Target message function control bits:
511 * @{
512 */
513 FF(rt_last,
514 /* 4: */ MD(11), MD(11),
515 /* 4.5: */ MD(11), MD(11),
516 /* 5: */ MD(11), MD(11),
517 /* 6: */ MD(12), MD(12),
518 /* 7: */ MD(12), MD(12),
519 /* 8: */ MD(12), MD(12))
520 FC(rt_slot_group, MD(11), MD(11), brw->gen >= 6)
521 F(rt_message_type, MD(10), MD( 8))
522 /** @} */
523
524 /**
525 * Thread Spawn message function control bits:
526 * @{
527 */
528 F(ts_resource_select, MD( 4), MD( 4))
529 F(ts_request_type, MD( 1), MD( 1))
530 F(ts_opcode, MD( 0), MD( 0))
531 /** @} */
532
533 /**
534 * Pixel Interpolator message function control bits:
535 * @{
536 */
537 F(pi_simd_mode, MD(16), MD(16))
538 F(pi_nopersp, MD(14), MD(14))
539 F(pi_message_type, MD(13), MD(12))
540 F(pi_slot_group, MD(11), MD(11))
541 F(pi_message_data, MD(7), MD(0))
542 /** @} */
543
544 /**
545 * Immediates:
546 * @{
547 */
548 static inline int
549 brw_inst_imm_d(const struct brw_context *brw, brw_inst *insn)
550 {
551 (void) brw;
552 return brw_inst_bits(insn, 127, 96);
553 }
554
555 static inline unsigned
556 brw_inst_imm_ud(const struct brw_context *brw, brw_inst *insn)
557 {
558 (void) brw;
559 return brw_inst_bits(insn, 127, 96);
560 }
561
562 static inline float
563 brw_inst_imm_f(const struct brw_context *brw, brw_inst *insn)
564 {
565 fi_type ft;
566 (void) brw;
567 ft.u = brw_inst_bits(insn, 127, 96);
568 return ft.f;
569 }
570
571 static inline void
572 brw_inst_set_imm_d(const struct brw_context *brw,
573 brw_inst *insn, int value)
574 {
575 (void) brw;
576 return brw_inst_set_bits(insn, 127, 96, value);
577 }
578
579 static inline void
580 brw_inst_set_imm_ud(const struct brw_context *brw,
581 brw_inst *insn, unsigned value)
582 {
583 (void) brw;
584 return brw_inst_set_bits(insn, 127, 96, value);
585 }
586
587 static inline void
588 brw_inst_set_imm_f(const struct brw_context *brw,
589 brw_inst *insn, float value)
590 {
591 fi_type ft;
592 (void) brw;
593 ft.f = value;
594 brw_inst_set_bits(insn, 127, 96, ft.u);
595 }
596
597 /** @} */
598
599 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
600 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
601 static inline void \
602 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw, \
603 brw_inst *inst, \
604 unsigned value) \
605 { \
606 assert((value & ~0x3ff) == 0); \
607 if (brw->gen >= 8) { \
608 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
609 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
610 } else { \
611 brw_inst_set_bits(inst, g4_high, g4_low, value); \
612 } \
613 } \
614 static inline unsigned \
615 brw_inst_##reg##_ia1_addr_imm(const struct brw_context *brw, \
616 brw_inst *inst) \
617 { \
618 if (brw->gen >= 8) { \
619 return brw_inst_bits(inst, g8_high, g8_low) | \
620 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
621 } else { \
622 return brw_inst_bits(inst, g4_high, g4_low); \
623 } \
624 }
625
626 /* AddrImm[9:0] for Align1 Indirect Addressing */
627 /* -Gen 4- ----Gen8---- */
628 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
629 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
630 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
631
632 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
633 static inline void \
634 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw, \
635 brw_inst *inst, unsigned value) \
636 { \
637 assert((value & ~0x3ff) == 0); \
638 if (brw->gen >= 8) { \
639 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
640 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
641 } else { \
642 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
643 } \
644 } \
645 static inline unsigned \
646 brw_inst_##reg##_ia16_addr_imm(const struct brw_context *brw, \
647 brw_inst *inst) \
648 { \
649 if (brw->gen >= 8) { \
650 return brw_inst_bits(inst, g8_high, g8_low) | \
651 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
652 } else { \
653 return brw_inst_bits(inst, g4_high, g4_low); \
654 } \
655 }
656
657 /* AddrImm[9:0] for Align16 Indirect Addressing:
658 * Compared to Align1, these are missing the low 4 bits.
659 * -Gen 4- ----Gen8----
660 */
661 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
662 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
663 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
664
665 /**
666 * Fetch a set of contiguous bits from the instruction.
667 *
668 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
669 */
670 static inline uint64_t
671 brw_inst_bits(brw_inst *inst, unsigned high, unsigned low)
672 {
673 /* We assume the field doesn't cross 64-bit boundaries. */
674 const unsigned word = high / 64;
675 assert(word == low / 64);
676
677 high %= 64;
678 low %= 64;
679
680 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
681
682 return (inst->data[word] & mask) >> low;
683 }
684
685 /**
686 * Set bits in the instruction, with proper shifting and masking.
687 *
688 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
689 */
690 static inline void
691 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
692 {
693 const unsigned word = high / 64;
694 assert(word == low / 64);
695
696 high %= 64;
697 low %= 64;
698
699 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
700
701 /* Make sure the supplied value actually fits in the given bitfield. */
702 assert((value & (mask >> low)) == value);
703
704 inst->data[word] = (inst->data[word] & ~mask) | ((value << low) & mask);
705 }
706
707 #undef BRW_IA16_ADDR_IMM
708 #undef BRW_IA1_ADDR_IMM
709 #undef MD
710 #undef F8
711 #undef FF
712 #undef BOUNDS
713 #undef F
714 #undef FC
715
716 typedef struct {
717 uint64_t data;
718 } brw_compact_inst;
719
720 /**
721 * Fetch a set of contiguous bits from the compacted instruction.
722 *
723 * Bits indices range from 0..63.
724 */
725 static inline unsigned
726 brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
727 {
728 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
729
730 return (inst->data & mask) >> low;
731 }
732
733 /**
734 * Set bits in the compacted instruction.
735 *
736 * Bits indices range from 0..63.
737 */
738 static inline void
739 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
740 uint64_t value)
741 {
742 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
743
744 /* Make sure the supplied value actually fits in the given bitfield. */
745 assert((value & (mask >> low)) == value);
746
747 inst->data = (inst->data & ~mask) | ((value << low) & mask);
748 }
749
750 #define F(name, high, low) \
751 static inline void \
752 brw_compact_inst_set_##name(brw_compact_inst *inst, unsigned v) \
753 { \
754 brw_compact_inst_set_bits(inst, high, low, v); \
755 } \
756 \
757 static inline unsigned \
758 brw_compact_inst_##name(brw_compact_inst *inst) \
759 { \
760 return brw_compact_inst_bits(inst, high, low); \
761 }
762
763 F(src1_reg_nr, 63, 56)
764 F(src0_reg_nr, 55, 48)
765 F(dst_reg_nr, 47, 40)
766 F(src1_index, 39, 35)
767 F(src0_index, 34, 30)
768 F(cmpt_control, 29, 29) /* Same location as brw_inst */
769 F(flag_subreg_nr, 28, 28) /* <= Gen6 only */
770 F(cond_modifier, 27, 24) /* Same location as brw_inst */
771 F(acc_wr_control, 23, 23)
772 F(subreg_index, 22, 18)
773 F(datatype_index, 17, 13)
774 F(control_index, 12, 8)
775 F(debug_control, 7, 7)
776 F(opcode, 6, 0) /* Same location as brw_inst */
777
778 /**
779 * (Gen8+) Compacted three-source instructions:
780 * @{
781 */
782 F(3src_src2_reg_nr, 63, 57)
783 F(3src_src1_reg_nr, 56, 50)
784 F(3src_src0_reg_nr, 49, 43)
785 F(3src_src2_subreg_nr, 42, 40)
786 F(3src_src1_subreg_nr, 39, 37)
787 F(3src_src0_subreg_nr, 36, 34)
788 F(3src_src2_rep_ctrl, 33, 33)
789 F(3src_src1_rep_ctrl, 32, 32)
790 F(3src_saturate, 31, 31)
791 F(3src_debug_control, 30, 30)
792 F(3src_cmpt_control, 29, 29)
793 F(3src_src0_rep_ctrl, 28, 28)
794 /* Reserved */
795 F(3src_dst_reg_nr, 18, 12)
796 F(3src_source_index, 11, 10)
797 F(3src_control_index, 9, 8)
798 /* Bit 7 is Reserved (for future Opcode expansion) */
799 F(3src_opcode, 6, 0)
800 /** @} */
801
802 #undef F
803
804 #ifdef __cplusplus
805 }
806 #endif
807
808 #endif