2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
36 #include "brw_context.h"
42 /** Maximum SEND message length */
43 #define BRW_MAX_MSG_LENGTH 15
45 /** First MRF register used by pull loads */
46 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
48 /** First MRF register used by spills */
49 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
51 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
52 typedef struct brw_inst
{
56 static inline uint64_t brw_inst_bits(const brw_inst
*inst
,
57 unsigned high
, unsigned low
);
58 static inline void brw_inst_set_bits(brw_inst
*inst
,
59 unsigned high
, unsigned low
,
62 #define FC(name, high, low, assertions) \
64 brw_inst_set_##name(const struct brw_device_info *devinfo, \
65 brw_inst *inst, uint64_t v) \
69 brw_inst_set_bits(inst, high, low, v); \
71 static inline uint64_t \
72 brw_inst_##name(const struct brw_device_info *devinfo, \
73 const brw_inst *inst) \
77 return brw_inst_bits(inst, high, low); \
80 /* A simple macro for fields which stay in the same place on all generations. */
81 #define F(name, high, low) FC(name, high, low, true)
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
85 if (devinfo->gen >= 8) { \
86 high = hi8; low = lo8; \
87 } else if (devinfo->gen >= 7) { \
88 high = hi7; low = lo7; \
89 } else if (devinfo->gen >= 6) { \
90 high = hi6; low = lo6; \
91 } else if (devinfo->gen >= 5) { \
92 high = hi5; low = lo5; \
93 } else if (devinfo->is_g4x) { \
94 high = hi45; low = lo45; \
96 high = hi4; low = lo4; \
98 assert(((int) high) != -1 && ((int) low) != -1); \
100 /* A general macro for cases where the field has moved to several different
101 * bit locations across generations. GCC appears to combine cases where the
102 * bits are identical, removing some of the inefficiency.
104 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
106 brw_inst_set_##name(const struct brw_device_info *devinfo, \
107 brw_inst *inst, uint64_t value) \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 brw_inst_set_bits(inst, high, low, value); \
112 static inline uint64_t \
113 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
115 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
116 return brw_inst_bits(inst, high, low); \
119 /* A macro for fields which moved as of Gen8+. */
120 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
122 /* 4: */ gen4_high, gen4_low, \
123 /* 4.5: */ gen4_high, gen4_low, \
124 /* 5: */ gen4_high, gen4_low, \
125 /* 6: */ gen4_high, gen4_low, \
126 /* 7: */ gen4_high, gen4_low, \
127 /* 8: */ gen8_high, gen8_low);
129 F(src1_vstride
, 120, 117)
130 F(src1_width
, 116, 114)
131 F(src1_da16_swiz_w
, 115, 114)
132 F(src1_da16_swiz_z
, 113, 112)
133 F(src1_hstride
, 113, 112)
134 F(src1_address_mode
, 111, 111)
135 /** Src1.SrcMod @{ */
136 F(src1_negate
, 110, 110)
137 F(src1_abs
, 109, 109)
139 F8(src1_ia_subreg_nr
, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
140 F(src1_da_reg_nr
, 108, 101)
141 F(src1_da16_subreg_nr
, 100, 100)
142 F(src1_da1_subreg_nr
, 100, 96)
143 F(src1_da16_swiz_y
, 99, 98)
144 F(src1_da16_swiz_x
, 97, 96)
145 F8(src1_reg_type
, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
146 F8(src1_reg_file
, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
147 F(src0_vstride
, 88, 85)
148 F(src0_width
, 84, 82)
149 F(src0_da16_swiz_w
, 83, 82)
150 F(src0_da16_swiz_z
, 81, 80)
151 F(src0_hstride
, 81, 80)
152 F(src0_address_mode
, 79, 79)
153 /** Src0.SrcMod @{ */
154 F(src0_negate
, 78, 78)
157 F8(src0_ia_subreg_nr
, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
158 F(src0_da_reg_nr
, 76, 69)
159 F(src0_da16_subreg_nr
, 68, 68)
160 F(src0_da1_subreg_nr
, 68, 64)
161 F(src0_da16_swiz_y
, 67, 66)
162 F(src0_da16_swiz_x
, 65, 64)
163 F(dst_address_mode
, 63, 63)
164 F(dst_hstride
, 62, 61)
165 F8(dst_ia_subreg_nr
, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
166 F(dst_da_reg_nr
, 60, 53)
167 F(dst_da16_subreg_nr
, 52, 52)
168 F(dst_da1_subreg_nr
, 52, 48)
169 F(da16_writemask
, 51, 48) /* Dst.ChanEn */
170 F8(src0_reg_type
, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
171 F8(src0_reg_file
, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
172 F8(dst_reg_type
, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
173 F8(dst_reg_file
, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
174 F8(mask_control
, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
176 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
179 F8(flag_subreg_nr
, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
181 F(debug_control
, 30, 30)
182 F(cmpt_control
, 29, 29)
183 FC(branch_control
, 28, 28, devinfo
->gen
>= 8)
184 F(acc_wr_control
, 28, 28)
185 F(cond_modifier
, 27, 24)
186 FC(math_function
, 27, 24, devinfo
->gen
>= 6)
189 F(pred_control
, 19, 16)
190 F(thread_control
, 15, 14)
191 F(qtr_control
, 13, 12)
193 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
196 F8(no_dd_check
, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
197 F8(no_dd_clear
, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
199 /* Bit 7 is Reserved (for future Opcode expansion) */
203 * Three-source instructions:
206 F(3src_src2_reg_nr
, 125, 118)
207 F(3src_src2_subreg_nr
, 117, 115) /* Extra discontiguous bit on CHV? */
208 F(3src_src2_swizzle
, 114, 107)
209 F(3src_src2_rep_ctrl
, 106, 106)
210 F(3src_src1_reg_nr
, 104, 97)
211 F(3src_src1_subreg_nr
, 96, 94) /* Extra discontiguous bit on CHV? */
212 F(3src_src1_swizzle
, 93, 86)
213 F(3src_src1_rep_ctrl
, 85, 85)
214 F(3src_src0_reg_nr
, 83, 76)
215 F(3src_src0_subreg_nr
, 75, 73) /* Extra discontiguous bit on CHV? */
216 F(3src_src0_swizzle
, 72, 65)
217 F(3src_src0_rep_ctrl
, 64, 64)
218 F(3src_dst_reg_nr
, 63, 56)
219 F(3src_dst_subreg_nr
, 55, 53)
220 F(3src_dst_writemask
, 52, 49)
221 F8(3src_nib_ctrl
, 47, 47, 11, 11) /* only exists on IVB+ */
222 F8(3src_dst_type
, 45, 44, 48, 46) /* only exists on IVB+ */
223 F8(3src_src_type
, 43, 42, 45, 43)
224 F8(3src_src2_negate
, 41, 41, 42, 42)
225 F8(3src_src2_abs
, 40, 40, 41, 41)
226 F8(3src_src1_negate
, 39, 39, 40, 40)
227 F8(3src_src1_abs
, 38, 38, 39, 39)
228 F8(3src_src0_negate
, 37, 37, 38, 38)
229 F8(3src_src0_abs
, 36, 36, 37, 37)
230 F8(3src_flag_reg_nr
, 34, 34, 33, 33)
231 F8(3src_flag_subreg_nr
, 33, 33, 32, 32)
232 FF(3src_dst_reg_file
,
233 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
235 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
236 F(3src_saturate
, 31, 31)
237 F(3src_debug_control
, 30, 30)
238 F(3src_cmpt_control
, 29, 29)
239 F(3src_acc_wr_control
, 28, 28)
240 F(3src_cond_modifier
, 27, 24)
241 F(3src_exec_size
, 23, 21)
242 F(3src_pred_inv
, 20, 20)
243 F(3src_pred_control
, 19, 16)
244 F(3src_thread_control
, 15, 14)
245 F(3src_qtr_control
, 13, 12)
246 F8(3src_no_dd_check
, 11, 11, 10, 10)
247 F8(3src_no_dd_clear
, 10, 10, 9, 9)
248 F8(3src_mask_control
, 9, 9, 34, 34)
249 F(3src_access_mode
, 8, 8)
250 /* Bit 7 is Reserved (for future Opcode expansion) */
255 * Flow control instruction bits:
259 brw_inst_set_uip(const struct brw_device_info
*devinfo
,
260 brw_inst
*inst
, int32_t value
)
262 assert(devinfo
->gen
>= 6);
264 if (devinfo
->gen
>= 8) {
265 brw_inst_set_bits(inst
, 95, 64, (uint32_t)value
);
267 assert(value
<= (1 << 16) - 1);
268 assert(value
> -(1 << 16));
269 brw_inst_set_bits(inst
, 127, 112, (uint16_t)value
);
273 static inline int32_t
274 brw_inst_uip(const struct brw_device_info
*devinfo
, const brw_inst
*inst
)
276 assert(devinfo
->gen
>= 6);
278 if (devinfo
->gen
>= 8) {
279 return brw_inst_bits(inst
, 95, 64);
281 return (int16_t)brw_inst_bits(inst
, 127, 112);
286 brw_inst_set_jip(const struct brw_device_info
*devinfo
,
287 brw_inst
*inst
, int32_t value
)
289 assert(devinfo
->gen
>= 6);
291 if (devinfo
->gen
>= 8) {
292 brw_inst_set_bits(inst
, 127, 96, (uint32_t)value
);
294 assert(value
<= (1 << 16) - 1);
295 assert(value
> -(1 << 16));
296 brw_inst_set_bits(inst
, 111, 96, (uint16_t)value
);
300 static inline int32_t
301 brw_inst_jip(const struct brw_device_info
*devinfo
, const brw_inst
*inst
)
303 assert(devinfo
->gen
>= 6);
305 if (devinfo
->gen
>= 8) {
306 return brw_inst_bits(inst
, 127, 96);
308 return (int16_t)brw_inst_bits(inst
, 111, 96);
312 /** Like FC, but using int16_t to handle negative jump targets. */
313 #define FJ(name, high, low, assertions) \
315 brw_inst_set_##name(const struct brw_device_info *devinfo, brw_inst *inst, int16_t v) \
317 assert(assertions); \
319 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
321 static inline int16_t \
322 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
324 assert(assertions); \
326 return brw_inst_bits(inst, high, low); \
329 FJ(gen6_jump_count
, 63, 48, devinfo
->gen
== 6)
330 FJ(gen4_jump_count
, 111, 96, devinfo
->gen
< 6)
331 FC(gen4_pop_count
, 115, 112, devinfo
->gen
< 6)
334 /* Message descriptor bits */
335 #define MD(x) ((x) + 96)
338 * Fields for SEND messages:
357 /* 4: doesn't exist */ -1, -1, -1, -1,
362 F(gateway_notify
, MD(16), MD(15))
370 FF(gateway_subfuncid
,
371 /* 4: */ MD(1), MD(0),
372 /* 4.5: */ MD(1), MD(0),
373 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
374 /* 6: */ MD(2), MD(0),
375 /* 7: */ MD(2), MD(0),
376 /* 8: */ MD(2), MD(0))
378 /* 4: */ 123, 120, /* called msg_target */
384 FC(base_mrf
, 27, 24, devinfo
->gen
< 6);
388 * URB message function control bits:
391 FF(urb_per_slot_offset
,
392 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
393 /* 7: */ MD(16), MD(16),
394 /* 8: */ MD(17), MD(17))
395 FC(urb_complete
, MD(15), MD(15), devinfo
->gen
< 8)
396 FC(urb_used
, MD(14), MD(14), devinfo
->gen
< 7)
397 FC(urb_allocate
, MD(13), MD(13), devinfo
->gen
< 7)
398 FF(urb_swizzle_control
,
399 /* 4: */ MD(11), MD(10),
400 /* 4.5: */ MD(11), MD(10),
401 /* 5: */ MD(11), MD(10),
402 /* 6: */ MD(11), MD(10),
403 /* 7: */ MD(14), MD(14),
404 /* 8: */ MD(15), MD(15))
405 FF(urb_global_offset
,
406 /* 4: */ MD( 9), MD(4),
407 /* 4.5: */ MD( 9), MD(4),
408 /* 5: */ MD( 9), MD(4),
409 /* 6: */ MD( 9), MD(4),
410 /* 7: */ MD(13), MD(3),
411 /* 8: */ MD(14), MD(4))
413 /* 4: */ MD( 3), MD(0),
414 /* 4.5: */ MD( 3), MD(0),
415 /* 5: */ MD( 3), MD(0),
416 /* 6: */ MD( 3), MD(0),
417 /* 7: */ MD( 2), MD(0),
418 /* 8: */ MD( 3), MD(0))
422 * Gen4-5 math messages:
425 FC(math_msg_data_type
, MD(7), MD(7), devinfo
->gen
< 6)
426 FC(math_msg_saturate
, MD(6), MD(6), devinfo
->gen
< 6)
427 FC(math_msg_precision
, MD(5), MD(5), devinfo
->gen
< 6)
428 FC(math_msg_signed_int
, MD(4), MD(4), devinfo
->gen
< 6)
429 FC(math_msg_function
, MD(3), MD(0), devinfo
->gen
< 6)
433 * Sampler message function control bits:
436 FF(sampler_simd_mode
,
437 /* 4: doesn't exist */ -1, -1, -1, -1,
438 /* 5: */ MD(17), MD(16),
439 /* 6: */ MD(17), MD(16),
440 /* 7: */ MD(18), MD(17),
441 /* 8: */ MD(18), MD(17))
443 /* 4: */ MD(15), MD(14),
444 /* 4.5: */ MD(15), MD(12),
445 /* 5: */ MD(15), MD(12),
446 /* 6: */ MD(15), MD(12),
447 /* 7: */ MD(16), MD(12),
448 /* 8: */ MD(16), MD(12))
449 FC(sampler_return_format
, MD(13), MD(12), devinfo
->gen
== 4 && !devinfo
->is_g4x
)
450 F(sampler
, MD(11), MD(8))
451 F(binding_table_index
, MD( 7), MD(0)) /* also used by other messages */
455 * Data port message function control bits:
458 FC(dp_category
, MD(18), MD(18), devinfo
->gen
>= 7)
460 /* Gen4-5 store fields in different bits for read/write messages. */
462 /* 4: */ MD(13), MD(12),
463 /* 4.5: */ MD(13), MD(11),
464 /* 5: */ MD(13), MD(11),
465 /* 6: */ MD(16), MD(13),
466 /* 7: */ MD(17), MD(14),
467 /* 8: */ MD(17), MD(14))
468 FF(dp_write_msg_type
,
469 /* 4: */ MD(14), MD(12),
470 /* 4.5: */ MD(14), MD(12),
471 /* 5: */ MD(14), MD(12),
472 /* 6: */ MD(16), MD(13),
473 /* 7: */ MD(17), MD(14),
474 /* 8: */ MD(17), MD(14))
475 FF(dp_read_msg_control
,
476 /* 4: */ MD(11), MD( 8),
477 /* 4.5: */ MD(10), MD( 8),
478 /* 5: */ MD(10), MD( 8),
479 /* 6: */ MD(12), MD( 8),
480 /* 7: */ MD(13), MD( 8),
481 /* 8: */ MD(13), MD( 8))
482 FF(dp_write_msg_control
,
483 /* 4: */ MD(11), MD( 8),
484 /* 4.5: */ MD(11), MD( 8),
485 /* 5: */ MD(11), MD( 8),
486 /* 6: */ MD(12), MD( 8),
487 /* 7: */ MD(13), MD( 8),
488 /* 8: */ MD(13), MD( 8))
489 FC(dp_read_target_cache
, MD(15), MD(14), devinfo
->gen
< 6);
492 /* 4: */ MD(15), MD(15),
493 /* 4.5: */ MD(15), MD(15),
494 /* 5: */ MD(15), MD(15),
495 /* 6: */ MD(17), MD(17),
496 /* 7+: does not exist */ -1, -1, -1, -1)
498 /* Gen6+ use the same bit locations for everything. */
500 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
501 -1, -1, -1, -1, -1, -1,
502 /* 6: */ MD(16), MD(13),
503 /* 7: */ MD(17), MD(14),
504 /* 8: */ MD(17), MD(14))
506 /* 4: */ MD(11), MD( 8),
507 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
508 /* 6: */ MD(12), MD( 8),
509 /* 7: */ MD(13), MD( 8),
510 /* 8: */ MD(13), MD( 8))
514 * Scratch message bits (Gen7+):
517 FC(scratch_read_write
, MD(17), MD(17), devinfo
->gen
>= 7) /* 0 = read, 1 = write */
518 FC(scratch_type
, MD(16), MD(16), devinfo
->gen
>= 7) /* 0 = OWord, 1 = DWord */
519 FC(scratch_invalidate_after_read
, MD(15), MD(15), devinfo
->gen
>= 7)
520 FC(scratch_block_size
, MD(13), MD(12), devinfo
->gen
>= 7)
521 FC(scratch_addr_offset
, MD(11), MD( 0), devinfo
->gen
>= 7)
525 * Render Target message function control bits:
529 /* 4: */ MD(11), MD(11),
530 /* 4.5: */ MD(11), MD(11),
531 /* 5: */ MD(11), MD(11),
532 /* 6: */ MD(12), MD(12),
533 /* 7: */ MD(12), MD(12),
534 /* 8: */ MD(12), MD(12))
535 FC(rt_slot_group
, MD(11), MD(11), devinfo
->gen
>= 6)
536 F(rt_message_type
, MD(10), MD( 8))
540 * Thread Spawn message function control bits:
543 F(ts_resource_select
, MD( 4), MD( 4))
544 F(ts_request_type
, MD( 1), MD( 1))
545 F(ts_opcode
, MD( 0), MD( 0))
549 * Pixel Interpolator message function control bits:
552 F(pi_simd_mode
, MD(16), MD(16))
553 F(pi_nopersp
, MD(14), MD(14))
554 F(pi_message_type
, MD(13), MD(12))
555 F(pi_slot_group
, MD(11), MD(11))
556 F(pi_message_data
, MD(7), MD(0))
564 brw_inst_imm_d(const struct brw_device_info
*devinfo
, const brw_inst
*insn
)
567 return brw_inst_bits(insn
, 127, 96);
570 static inline unsigned
571 brw_inst_imm_ud(const struct brw_device_info
*devinfo
, const brw_inst
*insn
)
574 return brw_inst_bits(insn
, 127, 96);
578 brw_inst_imm_f(const struct brw_device_info
*devinfo
, const brw_inst
*insn
)
582 ft
.u
= brw_inst_bits(insn
, 127, 96);
587 brw_inst_set_imm_d(const struct brw_device_info
*devinfo
,
588 brw_inst
*insn
, int value
)
591 return brw_inst_set_bits(insn
, 127, 96, value
);
595 brw_inst_set_imm_ud(const struct brw_device_info
*devinfo
,
596 brw_inst
*insn
, unsigned value
)
599 return brw_inst_set_bits(insn
, 127, 96, value
);
603 brw_inst_set_imm_f(const struct brw_device_info
*devinfo
,
604 brw_inst
*insn
, float value
)
609 brw_inst_set_bits(insn
, 127, 96, ft
.u
);
614 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
615 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
617 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
621 assert((value & ~0x3ff) == 0); \
622 if (devinfo->gen >= 8) { \
623 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
624 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
626 brw_inst_set_bits(inst, g4_high, g4_low, value); \
629 static inline unsigned \
630 brw_inst_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
631 const brw_inst *inst) \
633 if (devinfo->gen >= 8) { \
634 return brw_inst_bits(inst, g8_high, g8_low) | \
635 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
637 return brw_inst_bits(inst, g4_high, g4_low); \
641 /* AddrImm[9:0] for Align1 Indirect Addressing */
642 /* -Gen 4- ----Gen8---- */
643 BRW_IA1_ADDR_IMM(src1
, 105, 96, 121, 104, 96)
644 BRW_IA1_ADDR_IMM(src0
, 73, 64, 95, 72, 64)
645 BRW_IA1_ADDR_IMM(dst
, 57, 48, 47, 56, 48)
647 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
649 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
650 brw_inst *inst, unsigned value) \
652 assert((value & ~0x3ff) == 0); \
653 if (devinfo->gen >= 8) { \
654 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
655 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
657 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
660 static inline unsigned \
661 brw_inst_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
662 const brw_inst *inst) \
664 if (devinfo->gen >= 8) { \
665 return brw_inst_bits(inst, g8_high, g8_low) | \
666 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
668 return brw_inst_bits(inst, g4_high, g4_low); \
672 /* AddrImm[9:0] for Align16 Indirect Addressing:
673 * Compared to Align1, these are missing the low 4 bits.
674 * -Gen 4- ----Gen8----
676 BRW_IA16_ADDR_IMM(src1
, 105, 96, 121, 104, 100)
677 BRW_IA16_ADDR_IMM(src0
, 73, 64, 95, 72, 68)
678 BRW_IA16_ADDR_IMM(dst
, 57, 52, 47, 56, 52)
681 * Fetch a set of contiguous bits from the instruction.
683 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
685 static inline uint64_t
686 brw_inst_bits(const brw_inst
*inst
, unsigned high
, unsigned low
)
688 /* We assume the field doesn't cross 64-bit boundaries. */
689 const unsigned word
= high
/ 64;
690 assert(word
== low
/ 64);
695 const uint64_t mask
= (1ull << (high
- low
+ 1)) - 1;
697 return (inst
->data
[word
] >> low
) & mask
;
701 * Set bits in the instruction, with proper shifting and masking.
703 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
706 brw_inst_set_bits(brw_inst
*inst
, unsigned high
, unsigned low
, uint64_t value
)
708 const unsigned word
= high
/ 64;
709 assert(word
== low
/ 64);
714 const uint64_t mask
= ((1ull << (high
- low
+ 1)) - 1) << low
;
716 /* Make sure the supplied value actually fits in the given bitfield. */
717 assert((value
& (mask
>> low
)) == value
);
719 inst
->data
[word
] = (inst
->data
[word
] & ~mask
) | (value
<< low
);
722 #undef BRW_IA16_ADDR_IMM
723 #undef BRW_IA1_ADDR_IMM
736 * Fetch a set of contiguous bits from the compacted instruction.
738 * Bits indices range from 0..63.
740 static inline unsigned
741 brw_compact_inst_bits(brw_compact_inst
*inst
, unsigned high
, unsigned low
)
743 const uint64_t mask
= (1ull << (high
- low
+ 1)) - 1;
745 return (inst
->data
>> low
) & mask
;
749 * Set bits in the compacted instruction.
751 * Bits indices range from 0..63.
754 brw_compact_inst_set_bits(brw_compact_inst
*inst
, unsigned high
, unsigned low
,
757 const uint64_t mask
= ((1ull << (high
- low
+ 1)) - 1) << low
;
759 /* Make sure the supplied value actually fits in the given bitfield. */
760 assert((value
& (mask
>> low
)) == value
);
762 inst
->data
= (inst
->data
& ~mask
) | (value
<< low
);
765 #define F(name, high, low) \
767 brw_compact_inst_set_##name(brw_compact_inst *inst, unsigned v) \
769 brw_compact_inst_set_bits(inst, high, low, v); \
772 static inline unsigned \
773 brw_compact_inst_##name(brw_compact_inst *inst) \
775 return brw_compact_inst_bits(inst, high, low); \
778 F(src1_reg_nr
, 63, 56)
779 F(src0_reg_nr
, 55, 48)
780 F(dst_reg_nr
, 47, 40)
781 F(src1_index
, 39, 35)
782 F(src0_index
, 34, 30)
783 F(cmpt_control
, 29, 29) /* Same location as brw_inst */
784 F(flag_subreg_nr
, 28, 28) /* <= Gen6 only */
785 F(cond_modifier
, 27, 24) /* Same location as brw_inst */
786 F(acc_wr_control
, 23, 23)
787 F(subreg_index
, 22, 18)
788 F(datatype_index
, 17, 13)
789 F(control_index
, 12, 8)
790 F(debug_control
, 7, 7)
791 F(opcode
, 6, 0) /* Same location as brw_inst */
794 * (Gen8+) Compacted three-source instructions:
797 F(3src_src2_reg_nr
, 63, 57)
798 F(3src_src1_reg_nr
, 56, 50)
799 F(3src_src0_reg_nr
, 49, 43)
800 F(3src_src2_subreg_nr
, 42, 40)
801 F(3src_src1_subreg_nr
, 39, 37)
802 F(3src_src0_subreg_nr
, 36, 34)
803 F(3src_src2_rep_ctrl
, 33, 33)
804 F(3src_src1_rep_ctrl
, 32, 32)
805 F(3src_saturate
, 31, 31)
806 F(3src_debug_control
, 30, 30)
807 F(3src_cmpt_control
, 29, 29)
808 F(3src_src0_rep_ctrl
, 28, 28)
810 F(3src_dst_reg_nr
, 18, 12)
811 F(3src_source_index
, 11, 10)
812 F(3src_control_index
, 9, 8)
813 /* Bit 7 is Reserved (for future Opcode expansion) */