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i965: Introduce a new brw_compact_inst API.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
43 typedef struct brw_inst {
44 uint64_t data[2];
45 } brw_inst;
46
47 static inline uint64_t brw_inst_bits(brw_inst *inst,
48 unsigned high, unsigned low);
49 static inline void brw_inst_set_bits(brw_inst *inst,
50 unsigned high, unsigned low,
51 uint64_t value);
52
53 #define FC(name, high, low, assertions) \
54 static inline void \
55 brw_inst_set_##name(const struct brw_context *brw, \
56 brw_inst *inst, uint64_t v) \
57 { \
58 assert(assertions); \
59 brw_inst_set_bits(inst, high, low, v); \
60 } \
61 static inline uint64_t \
62 brw_inst_##name(const struct brw_context *brw, \
63 brw_inst *inst) \
64 { \
65 assert(assertions); \
66 return brw_inst_bits(inst, high, low); \
67 }
68
69 /* A simple macro for fields which stay in the same place on all generations. */
70 #define F(name, high, low) FC(name, high, low, true)
71
72 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
73 unsigned high, low; \
74 if (brw->gen >= 8) { \
75 high = hi8; low = lo8; \
76 } else if (brw->gen >= 7) { \
77 high = hi7; low = lo7; \
78 } else if (brw->gen >= 6) { \
79 high = hi6; low = lo6; \
80 } else if (brw->gen >= 5) { \
81 high = hi5; low = lo5; \
82 } else if (brw->is_g4x) { \
83 high = hi45; low = lo45; \
84 } else { \
85 high = hi4; low = lo4; \
86 } \
87 assert(((int) high) != -1 && ((int) low) != -1); \
88
89 /* A general macro for cases where the field has moved to several different
90 * bit locations across generations. GCC appears to combine cases where the
91 * bits are identical, removing some of the inefficiency.
92 */
93 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
94 static inline void \
95 brw_inst_set_##name(const struct brw_context *brw, \
96 brw_inst *inst, uint64_t value) \
97 { \
98 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
99 brw_inst_set_bits(inst, high, low, value); \
100 } \
101 static inline uint64_t \
102 brw_inst_##name(const struct brw_context *brw, brw_inst *inst) \
103 { \
104 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
105 return brw_inst_bits(inst, high, low); \
106 }
107
108 /* A macro for fields which moved as of Gen8+. */
109 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
110 FF(name, \
111 /* 4: */ gen4_high, gen4_low, \
112 /* 4.5: */ gen4_high, gen4_low, \
113 /* 5: */ gen4_high, gen4_low, \
114 /* 6: */ gen4_high, gen4_low, \
115 /* 7: */ gen4_high, gen4_low, \
116 /* 8: */ gen8_high, gen8_low);
117
118 F(src1_vstride, 120, 117)
119 F(src1_width, 116, 114)
120 F(src1_da16_swiz_w, 115, 114)
121 F(src1_da16_swiz_z, 113, 112)
122 F(src1_hstride, 113, 112)
123 F(src1_address_mode, 111, 111)
124 /** Src1.SrcMod @{ */
125 F(src1_negate, 110, 110)
126 F(src1_abs, 109, 109)
127 /** @} */
128 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
129 F(src1_da_reg_nr, 108, 101)
130 F(src1_da16_subreg_nr, 100, 100)
131 F(src1_da1_subreg_nr, 100, 96)
132 F(src1_da16_swiz_y, 99, 98)
133 F(src1_da16_swiz_x, 97, 96)
134 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
135 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
136 F(src0_vstride, 88, 85)
137 F(src0_width, 84, 82)
138 F(src0_da16_swiz_w, 83, 82)
139 F(src0_da16_swiz_z, 81, 80)
140 F(src0_hstride, 81, 80)
141 F(src0_address_mode, 79, 79)
142 /** Src0.SrcMod @{ */
143 F(src0_negate, 78, 78)
144 F(src0_abs, 77, 77)
145 /** @} */
146 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
147 F(src0_da_reg_nr, 76, 69)
148 F(src0_da16_subreg_nr, 68, 68)
149 F(src0_da1_subreg_nr, 68, 64)
150 F(src0_da16_swiz_y, 67, 66)
151 F(src0_da16_swiz_x, 65, 64)
152 F(dst_address_mode, 63, 63)
153 F(dst_hstride, 62, 61)
154 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
155 F(dst_da_reg_nr, 60, 53)
156 F(dst_da16_subreg_nr, 52, 52)
157 F(dst_da1_subreg_nr, 52, 48)
158 F(da16_writemask, 51, 48) /* Dst.ChanEn */
159 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
160 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
161 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
162 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
163 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
164 FF(flag_reg_nr,
165 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
166 /* 7: */ 90, 90,
167 /* 8: */ 33, 33)
168 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
169 F(saturate, 31, 31)
170 FC(branch_control, 30, 30, brw->gen >= 8)
171 F(debug_control, 30, 30)
172 F(cmpt_control, 29, 29)
173 F(acc_wr_control, 28, 28)
174 F(cond_modifier, 27, 24)
175 FC(math_function, 27, 24, brw->gen >= 6)
176 F(exec_size, 23, 21)
177 F(pred_inv, 20, 20)
178 F(pred_control, 19, 16)
179 F(thread_control, 15, 14)
180 F(qtr_control, 13, 12)
181 FF(nib_control,
182 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
183 /* 7: */ 47, 47,
184 /* 8: */ 11, 11)
185 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
186 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
187 F(access_mode, 8, 8)
188 /* Bit 7 is Reserved (for future Opcode expansion) */
189 F(opcode, 6, 0)
190
191 /**
192 * Three-source instructions:
193 * @{
194 */
195 F(3src_src2_reg_nr, 125, 118)
196 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
197 F(3src_src2_swizzle, 114, 107)
198 F(3src_src2_rep_ctrl, 106, 106)
199 F(3src_src1_reg_nr, 104, 97)
200 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
201 F(3src_src1_swizzle, 93, 86)
202 F(3src_src1_rep_ctrl, 85, 85)
203 F(3src_src0_reg_nr, 83, 76)
204 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
205 F(3src_src0_swizzle, 72, 65)
206 F(3src_src0_rep_ctrl, 64, 64)
207 F(3src_dst_reg_nr, 63, 56)
208 F(3src_dst_subreg_nr, 55, 53)
209 F(3src_dst_writemask, 52, 49)
210 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
211 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
212 F8(3src_src_type, 43, 42, 45, 43)
213 F8(3src_src2_negate, 41, 41, 42, 42)
214 F8(3src_src2_abs, 40, 40, 41, 41)
215 F8(3src_src1_negate, 39, 39, 40, 40)
216 F8(3src_src1_abs, 38, 38, 39, 39)
217 F8(3src_src0_negate, 37, 37, 38, 38)
218 F8(3src_src0_abs, 36, 36, 37, 37)
219 F8(3src_flag_reg_nr, 34, 34, 33, 33)
220 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
221 FF(3src_dst_reg_file,
222 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
223 /* 6: */ 32, 32,
224 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
225 F(3src_saturate, 31, 31)
226 F(3src_debug_control, 30, 30)
227 F(3src_cmpt_control, 29, 29)
228 F(3src_acc_wr_control, 28, 28)
229 F(3src_cond_modifier, 27, 24)
230 F(3src_exec_size, 23, 21)
231 F(3src_pred_inv, 20, 20)
232 F(3src_pred_control, 19, 16)
233 F(3src_thread_control, 15, 14)
234 F(3src_qtr_control, 13, 12)
235 F8(3src_no_dd_check, 11, 11, 10, 10)
236 F8(3src_no_dd_clear, 10, 10, 9, 9)
237 F8(3src_mask_control, 9, 9, 34, 34)
238 F(3src_access_mode, 8, 8)
239 /* Bit 7 is Reserved (for future Opcode expansion) */
240 F(3src_opcode, 6, 0)
241 /** @} */
242
243 /**
244 * Flow control instruction bits:
245 * @{
246 */
247 static inline void
248 brw_inst_set_uip(const struct brw_context *brw,
249 brw_inst *inst, int32_t value)
250 {
251 assert(brw->gen >= 6);
252
253 if (brw->gen >= 8) {
254 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
255 } else {
256 assert(value <= (1 << 16) - 1);
257 assert(value > -(1 << 16));
258 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
259 }
260 }
261
262 static inline int32_t
263 brw_inst_uip(const struct brw_context *brw, brw_inst *inst)
264 {
265 assert(brw->gen >= 6);
266
267 if (brw->gen >= 8) {
268 return brw_inst_bits(inst, 95, 64);
269 } else {
270 return (int16_t)brw_inst_bits(inst, 127, 112);
271 }
272 }
273
274 static inline void
275 brw_inst_set_jip(const struct brw_context *brw,
276 brw_inst *inst, int32_t value)
277 {
278 assert(brw->gen >= 6);
279
280 if (brw->gen >= 8) {
281 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
282 } else {
283 assert(value <= (1 << 16) - 1);
284 assert(value > -(1 << 16));
285 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
286 }
287 }
288
289 static inline int32_t
290 brw_inst_jip(const struct brw_context *brw, brw_inst *inst)
291 {
292 assert(brw->gen >= 6);
293
294 if (brw->gen >= 8) {
295 return brw_inst_bits(inst, 127, 96);
296 } else {
297 return (int16_t)brw_inst_bits(inst, 111, 96);
298 }
299 }
300
301 /** Like FC, but using int16_t to handle negative jump targets. */
302 #define FJ(name, high, low, assertions) \
303 static inline void \
304 brw_inst_set_##name(const struct brw_context *brw, brw_inst *inst, int16_t v) \
305 { \
306 assert(assertions); \
307 assert(v <= (1 << 16) - 1); \
308 assert(v > -(1 << 16)); \
309 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
310 } \
311 static inline int16_t \
312 brw_inst_##name(const struct brw_context *brw, brw_inst *inst) \
313 { \
314 assert(assertions); \
315 return brw_inst_bits(inst, high, low); \
316 }
317
318 FJ(gen6_jump_count, 63, 48, brw->gen == 6)
319 FJ(gen4_jump_count, 111, 96, brw->gen < 6)
320 FC(gen4_pop_count, 115, 112, brw->gen < 6)
321 /** @} */
322
323 /**
324 * Fields for SEND messages:
325 * @{
326 */
327 F(eot, 127, 127)
328 FF(mlen,
329 /* 4: */ 119, 116,
330 /* 4.5: */ 119, 116,
331 /* 5: */ 124, 121,
332 /* 6: */ 124, 121,
333 /* 7: */ 124, 121,
334 /* 8: */ 124, 121);
335 FF(rlen,
336 /* 4: */ 115, 112,
337 /* 4.5: */ 115, 112,
338 /* 5: */ 120, 116,
339 /* 6: */ 120, 116,
340 /* 7: */ 120, 116,
341 /* 8: */ 120, 116);
342 FF(header_present,
343 /* 4: doesn't exist */ -1, -1, -1, -1,
344 /* 5: */ 115, 115,
345 /* 6: */ 115, 115,
346 /* 7: */ 115, 115,
347 /* 8: */ 115, 115)
348 FF(function_control,
349 /* 4: */ 111, 96,
350 /* 4.5: */ 111, 96,
351 /* 5: */ 114, 96,
352 /* 6: */ 114, 96,
353 /* 7: */ 114, 96,
354 /* 8: */ 114, 96)
355 FF(sfid,
356 /* 4: */ 123, 120, /* called msg_target */
357 /* 4.5 */ 123, 120,
358 /* 5: */ 95, 92,
359 /* 6: */ 27, 24,
360 /* 7: */ 27, 24,
361 /* 8: */ 27, 24)
362 FC(base_mrf, 27, 24, brw->gen < 6);
363 /** @} */
364
365 /* Message descriptor bits */
366 #define MD(x) (x + 96)
367
368 /**
369 * URB message function control bits:
370 * @{
371 */
372 FF(urb_per_slot_offset,
373 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
374 /* 7: */ MD(16), MD(16),
375 /* 8: */ MD(17), MD(17))
376 FC(urb_complete, MD(15), MD(15), brw->gen < 8)
377 FC(urb_used, MD(14), MD(14), brw->gen < 7)
378 FC(urb_allocate, MD(13), MD(13), brw->gen < 7)
379 FF(urb_swizzle_control,
380 /* 4: */ MD(11), MD(10),
381 /* 4.5: */ MD(11), MD(10),
382 /* 5: */ MD(11), MD(10),
383 /* 6: */ MD(11), MD(10),
384 /* 7: */ MD(14), MD(14),
385 /* 8: */ MD(15), MD(15))
386 FF(urb_global_offset,
387 /* 4: */ MD( 9), MD(4),
388 /* 4.5: */ MD( 9), MD(4),
389 /* 5: */ MD( 9), MD(4),
390 /* 6: */ MD( 9), MD(4),
391 /* 7: */ MD(13), MD(3),
392 /* 8: */ MD(14), MD(4))
393 FF(urb_opcode,
394 /* 4: */ MD( 3), MD(0),
395 /* 4.5: */ MD( 3), MD(0),
396 /* 5: */ MD( 3), MD(0),
397 /* 6: */ MD( 3), MD(0),
398 /* 7: */ MD( 2), MD(0),
399 /* 8: */ MD( 3), MD(0))
400 /** @} */
401
402 /**
403 * Gen4-5 math messages:
404 * @{
405 */
406 FC(math_msg_data_type, MD(7), MD(7), brw->gen < 6)
407 FC(math_msg_saturate, MD(6), MD(6), brw->gen < 6)
408 FC(math_msg_precision, MD(5), MD(5), brw->gen < 6)
409 FC(math_msg_signed_int, MD(4), MD(4), brw->gen < 6)
410 FC(math_msg_function, MD(3), MD(0), brw->gen < 6)
411 /** @} */
412
413 /**
414 * Sampler message function control bits:
415 * @{
416 */
417 FF(sampler_simd_mode,
418 /* 4: doesn't exist */ -1, -1, -1, -1,
419 /* 5: */ MD(17), MD(16),
420 /* 6: */ MD(17), MD(16),
421 /* 7: */ MD(18), MD(17),
422 /* 8: */ MD(18), MD(17))
423 FF(sampler_msg_type,
424 /* 4: */ MD(15), MD(14),
425 /* 4.5: */ MD(15), MD(12),
426 /* 5: */ MD(15), MD(12),
427 /* 6: */ MD(15), MD(12),
428 /* 7: */ MD(16), MD(12),
429 /* 8: */ MD(16), MD(12))
430 FC(sampler_return_format, MD(13), MD(12), brw->gen == 4 && !brw->is_g4x)
431 F(sampler, MD(11), MD(8))
432 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
433 /** @} */
434
435 /**
436 * Data port message function control bits:
437 * @{
438 */
439 FC(dp_category, MD(18), MD(18), brw->gen >= 7)
440
441 /* Gen4-5 store fields in different bits for read/write messages. */
442 FF(dp_read_msg_type,
443 /* 4: */ MD(13), MD(12),
444 /* 4.5: */ MD(13), MD(11),
445 /* 5: */ MD(13), MD(11),
446 /* 6: */ MD(16), MD(13),
447 /* 7: */ MD(17), MD(14),
448 /* 8: */ MD(17), MD(14))
449 FF(dp_write_msg_type,
450 /* 4: */ MD(14), MD(12),
451 /* 4.5: */ MD(14), MD(12),
452 /* 5: */ MD(14), MD(12),
453 /* 6: */ MD(16), MD(13),
454 /* 7: */ MD(17), MD(14),
455 /* 8: */ MD(17), MD(14))
456 FF(dp_read_msg_control,
457 /* 4: */ MD(11), MD( 8),
458 /* 4.5: */ MD(10), MD( 8),
459 /* 5: */ MD(10), MD( 8),
460 /* 6: */ MD(12), MD( 8),
461 /* 7: */ MD(13), MD( 8),
462 /* 8: */ MD(13), MD( 8))
463 FF(dp_write_msg_control,
464 /* 4: */ MD(11), MD( 8),
465 /* 4.5: */ MD(11), MD( 8),
466 /* 5: */ MD(11), MD( 8),
467 /* 6: */ MD(12), MD( 8),
468 /* 7: */ MD(13), MD( 8),
469 /* 8: */ MD(13), MD( 8))
470 FC(dp_read_target_cache, MD(15), MD(14), brw->gen < 6);
471
472 FF(dp_write_commit,
473 /* 4: */ MD(15), MD(15),
474 /* 4.5: */ MD(15), MD(15),
475 /* 5: */ MD(15), MD(15),
476 /* 6: */ MD(17), MD(17),
477 /* 7+: does not exist */ -1, -1, -1, -1)
478
479 /* Gen6+ use the same bit locations for everything. */
480 FF(dp_msg_type,
481 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
482 -1, -1, -1, -1, -1, -1,
483 /* 6: */ MD(16), MD(13),
484 /* 7: */ MD(17), MD(14),
485 /* 8: */ MD(17), MD(14))
486 FF(dp_msg_control,
487 /* 4: */ MD(11), MD( 8),
488 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
489 /* 6: */ MD(12), MD( 8),
490 /* 7: */ MD(13), MD( 8),
491 /* 8: */ MD(13), MD( 8))
492 /** @} */
493
494 /**
495 * Scratch message bits (Gen7+):
496 * @{
497 */
498 FC(scratch_read_write, MD(17), MD(17), brw->gen >= 7) /* 0 = read, 1 = write */
499 FC(scratch_type, MD(16), MD(16), brw->gen >= 7) /* 0 = OWord, 1 = DWord */
500 FC(scratch_invalidate_after_read, MD(15), MD(15), brw->gen >= 7)
501 FC(scratch_block_size, MD(13), MD(12), brw->gen >= 7)
502 FC(scratch_addr_offset, MD(11), MD( 0), brw->gen >= 7)
503 /** @} */
504
505 /**
506 * Render Target message function control bits:
507 * @{
508 */
509 FF(rt_last,
510 /* 4: */ MD(11), MD(11),
511 /* 4.5: */ MD(11), MD(11),
512 /* 5: */ MD(11), MD(11),
513 /* 6: */ MD(12), MD(12),
514 /* 7: */ MD(12), MD(12),
515 /* 8: */ MD(12), MD(12))
516 FC(rt_slot_group, MD(11), MD(11), brw->gen >= 6)
517 F(rt_message_type, MD(10), MD( 8))
518 /** @} */
519
520 /**
521 * Thread Spawn message function control bits:
522 * @{
523 */
524 F(ts_resource_select, MD( 4), MD( 4))
525 F(ts_request_type, MD( 1), MD( 1))
526 F(ts_opcode, MD( 0), MD( 0))
527 /** @} */
528
529 /**
530 * Immediates:
531 * @{
532 */
533 static inline int
534 brw_inst_imm_d(const struct brw_context *brw, brw_inst *insn)
535 {
536 return brw_inst_bits(insn, 127, 96);
537 }
538
539 static inline unsigned
540 brw_inst_imm_ud(const struct brw_context *brw, brw_inst *insn)
541 {
542 return brw_inst_bits(insn, 127, 96);
543 }
544
545 static inline float
546 brw_inst_imm_f(const struct brw_context *brw, brw_inst *insn)
547 {
548 fi_type ft;
549 ft.u = brw_inst_bits(insn, 127, 96);
550 return ft.f;
551 }
552
553 static inline void
554 brw_inst_set_imm_d(const struct brw_context *brw,
555 brw_inst *insn, int value)
556 {
557 return brw_inst_set_bits(insn, 127, 96, value);
558 }
559
560 static inline void
561 brw_inst_set_imm_ud(const struct brw_context *brw,
562 brw_inst *insn, unsigned value)
563 {
564 return brw_inst_set_bits(insn, 127, 96, value);
565 }
566
567 static inline void
568 brw_inst_set_imm_f(const struct brw_context *brw,
569 brw_inst *insn, float value)
570 {
571 fi_type ft;
572 ft.f = value;
573 brw_inst_set_bits(insn, 127, 96, ft.u);
574 }
575
576 /** @} */
577
578 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
579 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
580 static inline void \
581 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw, \
582 brw_inst *inst, \
583 unsigned value) \
584 { \
585 assert((value & ~0x3ff) == 0); \
586 if (brw->gen >= 8) { \
587 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
588 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
589 } else { \
590 brw_inst_set_bits(inst, g4_high, g4_low, value); \
591 } \
592 } \
593 static inline unsigned \
594 brw_inst_##reg##_ia1_addr_imm(const struct brw_context *brw, \
595 brw_inst *inst) \
596 { \
597 if (brw->gen >= 8) { \
598 return brw_inst_bits(inst, g8_high, g8_low) | \
599 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
600 } else { \
601 return brw_inst_bits(inst, g4_high, g4_low); \
602 } \
603 }
604
605 /* AddrImm[9:0] for Align1 Indirect Addressing */
606 /* -Gen 4- ----Gen8---- */
607 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
608 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
609 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
610
611 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
612 static inline void \
613 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw, \
614 brw_inst *inst, unsigned value) \
615 { \
616 assert((value & ~0x3ff) == 0); \
617 if (brw->gen >= 8) { \
618 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
619 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
620 } else { \
621 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
622 } \
623 } \
624 static inline unsigned \
625 brw_inst_##reg##_ia16_addr_imm(const struct brw_context *brw, \
626 brw_inst *inst) \
627 { \
628 if (brw->gen >= 8) { \
629 return brw_inst_bits(inst, g8_high, g8_low) | \
630 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
631 } else { \
632 return brw_inst_bits(inst, g4_high, g4_low); \
633 } \
634 }
635
636 /* AddrImm[9:0] for Align16 Indirect Addressing:
637 * Compared to Align1, these are missing the low 4 bits.
638 * -Gen 4- ----Gen8----
639 */
640 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
641 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
642 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
643
644 /**
645 * Fetch a set of contiguous bits from the instruction.
646 *
647 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
648 */
649 static inline uint64_t
650 brw_inst_bits(brw_inst *inst, unsigned high, unsigned low)
651 {
652 /* We assume the field doesn't cross 64-bit boundaries. */
653 const unsigned word = high / 64;
654 assert(word == low / 64);
655
656 high %= 64;
657 low %= 64;
658
659 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
660
661 return (inst->data[word] & mask) >> low;
662 }
663
664 /**
665 * Set bits in the instruction, with proper shifting and masking.
666 *
667 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
668 */
669 static inline void
670 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
671 {
672 const unsigned word = high / 64;
673 assert(word == low / 64);
674
675 high %= 64;
676 low %= 64;
677
678 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
679
680 /* Make sure the supplied value actually fits in the given bitfield. */
681 assert((value & (mask >> low)) == value);
682
683 inst->data[word] = (inst->data[word] & ~mask) | ((value << low) & mask);
684 }
685
686 #undef BRW_IA16_ADDR_IMM
687 #undef BRW_IA1_ADDR_IMM
688 #undef MD
689 #undef F8
690 #undef FF
691 #undef BOUNDS
692 #undef F
693 #undef FC
694
695 typedef struct {
696 uint64_t data;
697 } brw_compact_inst;
698
699 /**
700 * Fetch a set of contiguous bits from the compacted instruction.
701 *
702 * Bits indices range from 0..63.
703 */
704 static inline unsigned
705 brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
706 {
707 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
708
709 return (inst->data & mask) >> low;
710 }
711
712 /**
713 * Set bits in the compacted instruction.
714 *
715 * Bits indices range from 0..63.
716 */
717 static inline void
718 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
719 uint64_t value)
720 {
721 const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
722
723 /* Make sure the supplied value actually fits in the given bitfield. */
724 assert((value & (mask >> low)) == value);
725
726 inst->data = (inst->data & ~mask) | ((value << low) & mask);
727 }
728
729 #define F(name, high, low) \
730 static inline void \
731 brw_compact_inst_set_##name(struct brw_compact_instruction *insn, unsigned v) \
732 { \
733 brw_compact_inst *inst = (brw_compact_inst *)insn; \
734 brw_compact_inst_set_bits(inst, high, low, v); \
735 } \
736 \
737 static inline unsigned \
738 brw_compact_inst_##name(struct brw_compact_instruction *insn) \
739 { \
740 brw_compact_inst *inst = (brw_compact_inst *)insn; \
741 return brw_compact_inst_bits(inst, high, low); \
742 }
743
744 F(src1_reg_nr, 63, 56)
745 F(src0_reg_nr, 55, 48)
746 F(dst_reg_nr, 47, 40)
747 F(src1_index, 39, 35)
748 F(src0_index, 34, 30)
749 F(cmpt_control, 29, 29) /* Same location as brw_inst */
750 F(flag_subreg_nr, 28, 28) /* <= Gen6 only */
751 F(cond_modifier, 27, 24) /* Same location as brw_inst */
752 F(acc_wr_control, 23, 23)
753 F(subreg_index, 22, 18)
754 F(datatype_index, 17, 13)
755 F(control_index, 12, 8)
756 F(debug_control, 7, 7)
757 F(opcode, 6, 0) /* Same location as brw_inst */
758
759 /**
760 * (Gen8+) Compacted three-source instructions:
761 * @{
762 */
763 F(3src_src2_reg_nr, 63, 57)
764 F(3src_src1_reg_nr, 56, 50)
765 F(3src_src0_reg_nr, 49, 43)
766 F(3src_src2_subreg_nr, 42, 40)
767 F(3src_src1_subreg_nr, 39, 37)
768 F(3src_src0_subreg_nr, 36, 34)
769 F(3src_src2_rep_ctrl, 33, 33)
770 F(3src_src1_rep_ctrl, 32, 32)
771 F(3src_saturate, 31, 31)
772 F(3src_debug_control, 30, 30)
773 F(3src_cmpt_control, 29, 29)
774 F(3src_src0_rep_ctrl, 28, 28)
775 /* Reserved */
776 F(3src_dst_reg_nr, 18, 12)
777 F(3src_source_index, 11, 10)
778 F(3src_control_index, 9, 8)
779 /* Bit 7 is Reserved (for future Opcode expansion) */
780 F(3src_opcode, 6, 0)
781 /** @} */
782
783 #undef F
784
785 #ifdef __cplusplus
786 }
787 #endif
788
789 #endif