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28 #include "brw_shader.h"
32 class fs_reg
: public backend_reg
{
34 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
39 explicit fs_reg(float f
);
40 explicit fs_reg(int32_t i
);
41 explicit fs_reg(uint32_t u
);
42 explicit fs_reg(uint8_t vf
[4]);
43 explicit fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
);
44 fs_reg(struct brw_reg fixed_hw_reg
);
45 fs_reg(enum register_file file
, int reg
);
46 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
);
48 bool equals(const fs_reg
&r
) const;
49 bool is_contiguous() const;
52 * Return the size in bytes of a single logical component of the
53 * register assuming the given execution width.
55 unsigned component_size(unsigned width
) const;
57 /** Smear a channel of the reg to all channels. */
58 fs_reg
&set_smear(unsigned subreg
);
61 * Offset in bytes from the start of the register. Values up to a
62 * backend_reg::reg_offset unit are valid.
68 /** Register region horizontal stride */
75 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
76 reg
.negate
= !reg
.negate
;
81 retype(fs_reg reg
, enum brw_reg_type type
)
83 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
88 byte_offset(fs_reg reg
, unsigned delta
)
95 reg
.reg_offset
+= delta
/ 32;
98 reg
.reg
+= delta
/ 32;
103 reg
.subreg_offset
+= delta
% 32;
108 horiz_offset(fs_reg reg
, unsigned delta
)
114 /* These only have a single component that is implicitly splatted. A
115 * horizontal offset should be a harmless no-op.
121 return byte_offset(reg
, delta
* reg
.stride
* type_sz(reg
.type
));
129 component(fs_reg reg
, unsigned idx
)
131 assert(reg
.subreg_offset
== 0);
132 reg
.subreg_offset
= idx
* type_sz(reg
.type
);
138 is_uniform(const fs_reg
®
)
140 return (reg
.stride
== 0 || reg
.is_null()) &&
141 (!reg
.reladdr
|| is_uniform(*reg
.reladdr
));
145 * Get either of the 8-component halves of a 16-component register.
147 * Note: this also works if \c reg represents a SIMD16 pair of registers.
150 half(fs_reg reg
, unsigned idx
)
162 return horiz_offset(reg
, 8 * idx
);
167 unreachable("Cannot take half of this register type");
172 static const fs_reg reg_undef
;
174 class fs_inst
: public backend_instruction
{
175 fs_inst
&operator=(const fs_inst
&);
177 void init(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
178 const fs_reg
*src
, unsigned sources
);
181 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
184 fs_inst(enum opcode opcode
, uint8_t exec_size
);
185 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
);
186 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
188 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
189 const fs_reg
&src0
, const fs_reg
&src1
);
190 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
191 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
);
192 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
193 const fs_reg src
[], unsigned sources
);
194 fs_inst(const fs_inst
&that
);
197 void resize_sources(uint8_t num_sources
);
199 bool equals(fs_inst
*inst
) const;
200 bool overwrites_reg(const fs_reg
®
) const;
201 bool is_send_from_grf() const;
202 bool is_partial_write() const;
203 bool is_copy_payload(const brw::simple_allocator
&grf_alloc
) const;
204 unsigned components_read(unsigned i
) const;
205 int regs_read(int arg
) const;
206 bool can_do_source_mods(const struct brw_device_info
*devinfo
);
207 bool has_side_effects() const;
209 bool reads_flag() const;
210 bool writes_flag() const;
215 uint8_t sources
; /**< Number of fs_reg sources. */
218 * Execution size of the instruction. This is used by the generator to
219 * generate the correct binary for the given fs_inst. Current valid
220 * values are 1, 8, 16.
225 bool force_sechalf
:1;
226 bool pi_noperspective
:1; /**< Pixel interpolator noperspective flag */
230 * Set second-half quarter control on \p inst.
232 static inline fs_inst
*
233 set_sechalf(fs_inst
*inst
)
235 inst
->force_sechalf
= true;
240 * Make the execution of \p inst dependent on the evaluation of a possibly
241 * inverted predicate.
243 static inline fs_inst
*
244 set_predicate_inv(enum brw_predicate pred
, bool inverse
,
247 inst
->predicate
= pred
;
248 inst
->predicate_inverse
= inverse
;
253 * Make the execution of \p inst dependent on the evaluation of a predicate.
255 static inline fs_inst
*
256 set_predicate(enum brw_predicate pred
, fs_inst
*inst
)
258 return set_predicate_inv(pred
, false, inst
);
262 * Write the result of evaluating the condition given by \p mod to a flag
265 static inline fs_inst
*
266 set_condmod(enum brw_conditional_mod mod
, fs_inst
*inst
)
268 inst
->conditional_mod
= mod
;
273 * Clamp the result of \p inst to the saturation range of its destination
276 static inline fs_inst
*
277 set_saturate(bool saturate
, fs_inst
*inst
)
279 inst
->saturate
= saturate
;